1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2015 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16 #ifdef CONFIG_MCC_MODE
17 #define _HAL_MCC_C_
18
19 #include <drv_types.h> /* PADAPTER */
20 #include <rtw_mcc.h> /* mcc structure */
21 #include <hal_data.h> /* HAL_DATA */
22 #include <rtw_pwrctrl.h> /* power control */
23
24 /* use for AP/GO + STA/GC case */
25 #define MCC_DURATION_IDX 0 /* druration for station side */
26 #define MCC_TSF_SYNC_OFFSET_IDX 1
27 #define MCC_START_TIME_OFFSET_IDX 2
28 #define MCC_INTERVAL_IDX 3
29 #define MCC_GUARD_OFFSET0_IDX 4
30 #define MCC_GUARD_OFFSET1_IDX 5
31 #define MCC_STOP_THRESHOLD 6
32 #define TU 1024 /* 1 TU equals 1024 microseconds */
33 /* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
34 u8 mcc_switch_channel_policy_table[][7]={
35 {20, 50, 40, 100, 0, 0, 30},
36 {80, 50, 10, 100, 0, 0, 30},
37 {36, 50, 32, 100, 0, 0, 30},
38 {30, 50, 35, 100, 0, 0, 30},
39 };
40
41 const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
42
dump_iqk_val_table(PADAPTER padapter)43 static void dump_iqk_val_table(PADAPTER padapter)
44 {
45 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
46 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
47 struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
48 u8 total_rf_path = hal_spec->rf_reg_path_num;
49 u8 rf_path_idx = 0;
50 u8 backup_chan_idx = 0;
51 u8 backup_reg_idx = 0;
52
53 #ifdef CONFIG_MCC_MODE_V2
54 #else
55
56 RTW_INFO("=============dump IQK backup table================\n");
57 for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
58 for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
59 for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
60 RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
61 , iqk_reg_backup[backup_chan_idx].central_chnl
62 , iqk_reg_backup[backup_chan_idx].bw_mode
63 , rf_path_idx
64 , backup_reg_idx
65 , iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
66 );
67 }
68 }
69 }
70 RTW_INFO("=============================================\n");
71
72 #endif
73 }
74
rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter,u8 * ie,u32 * ie_len)75 static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
76 {
77 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
78 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
79 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
80 u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
81 u32 p2p_noa_attr_len = 0;
82 u8 noa_desc_num = 1;
83 u8 opp_ps = 0; /* Disable OppPS */
84 u8 noa_count = 255;
85 u32 noa_duration;
86 u32 noa_interval;
87 u8 noa_index = 0;
88 u8 mcc_policy_idx = 0;
89
90 mcc_policy_idx = pmccobjpriv->policy_index;
91 noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
92 noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
93
94 /* P2P OUI(4 bytes) */
95 _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
96 p2p_noa_attr_len = p2p_noa_attr_len + 4;
97
98 /* attrute ID(1 byte) */
99 p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
100 p2p_noa_attr_len = p2p_noa_attr_len + 1;
101
102 /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
103 RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
104 p2p_noa_attr_len = p2p_noa_attr_len + 2;
105
106 /* Index (1 byte) */
107 p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
108 p2p_noa_attr_len = p2p_noa_attr_len + 1;
109
110 /* CTWindow and OppPS Parameters (1 byte) */
111 p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
112 p2p_noa_attr_len = p2p_noa_attr_len+ 1;
113
114 /* NoA Count (1 byte) */
115 p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
116 p2p_noa_attr_len = p2p_noa_attr_len + 1;
117
118 /* NoA Duration (4 bytes) unit: microseconds */
119 RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
120 p2p_noa_attr_len = p2p_noa_attr_len + 4;
121
122 /* NoA Interval (4 bytes) unit: microseconds */
123 RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
124 p2p_noa_attr_len = p2p_noa_attr_len + 4;
125
126 /* NoA Start Time (4 bytes) unit: microseconds */
127 RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
128 if (0)
129 RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
130 , noa_index
131 , p2p_noa_attr_ie[p2p_noa_attr_len]
132 , p2p_noa_attr_ie[p2p_noa_attr_len + 1]
133 , p2p_noa_attr_ie[p2p_noa_attr_len + 2]
134 , p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
135
136 p2p_noa_attr_len = p2p_noa_attr_len + 4;
137 rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
138 }
139
140
141 /**
142 * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
143 * @padapter: the adapter to be update go p2p ie
144 */
rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)145 static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
146 {
147 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
148 struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
149 u8 *pos = NULL;
150
151
152 /* no noa attribute, build it */
153 if (pmccadapriv->p2p_go_noa_ie_len == 0)
154 rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
155 else {
156 /* has noa attribut, modify it */
157 u32 noa_duration = 0;
158
159 /* update index */
160 pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
161 /* 0~255 */
162 (*pos) = ((*pos) + 1) % 256;
163 if (0)
164 RTW_INFO("indxe:%d\n", (*pos));
165
166
167 /* update duration */
168 noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
169 pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
170 RTW_PUT_LE32(pos, noa_duration);
171
172 /* update start time */
173 pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
174 RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
175 if (0)
176 RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
177 , ((u8*)(pos))[0]
178 , ((u8*)(pos))[1]
179 , ((u8*)(pos))[2]
180 , ((u8*)(pos))[3]);
181
182 }
183
184 if (0) {
185 RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
186 RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
187 }
188 update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
189 }
190
191 /**
192 * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
193 * @padapter: the adapter to be update go p2p ie
194 */
rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)195 static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
196 {
197 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
198 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
199
200 /* chech has noa ie or not */
201 if (pmccadapriv->p2p_go_noa_ie_len == 0)
202 return;
203
204 pmccadapriv->p2p_go_noa_ie_len = 0;
205 update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
206 }
207
208 /* restore IQK value for all interface */
rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)209 void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
210 {
211 u8 take_care_iqk = _FALSE;
212 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
213 _adapter *iface = NULL;
214 struct mcc_adapter_priv *mccadapriv = NULL;
215 u8 i = 0;
216
217 rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
218 if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
219 for (i = 0; i < dvobj->iface_nums; i++) {
220 iface = dvobj->padapters[i];
221 if (iface == NULL)
222 continue;
223
224 mccadapriv = &iface->mcc_adapterpriv;
225 if (mccadapriv->role == MCC_ROLE_MAX)
226 continue;
227
228 rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
229 }
230 }
231
232 if (0)
233 dump_iqk_val_table(padapter);
234 }
235
rtw_hal_check_mcc_status(PADAPTER padapter,u8 mcc_status)236 u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
237 {
238 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
239
240 if (pmccobjpriv->mcc_status & (mcc_status))
241 return _TRUE;
242 else
243 return _FALSE;
244 }
245
rtw_hal_set_mcc_status(PADAPTER padapter,u8 mcc_status)246 void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)
247 {
248 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
249
250 pmccobjpriv->mcc_status |= (mcc_status);
251 }
252
rtw_hal_clear_mcc_status(PADAPTER padapter,u8 mcc_status)253 void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
254 {
255 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
256
257 pmccobjpriv->mcc_status &= (~mcc_status);
258 }
259
rtw_hal_mcc_update_policy_table(PADAPTER adapter)260 static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
261 {
262 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
263 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
264 u8 mcc_duration = mccobjpriv->duration;
265 s8 mcc_policy_idx = mccobjpriv->policy_index;
266 u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
267 u8 new_mcc_duration_time = 0;
268 u8 new_starttime_offset = 0;
269
270 /* convert % to ms */
271 new_mcc_duration_time = mcc_duration * interval / 100;
272
273 /* start time offset = (interval - duration time)/2 */
274 new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
275
276 /* update modified parameters */
277 mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
278 = new_mcc_duration_time;
279
280 mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
281 = new_starttime_offset;
282
283
284 }
285
rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)286 static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
287 {
288 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
289 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
290 struct registry_priv *registry_par = &padapter->registrypriv;
291 u8 mcc_duration = 0;
292 s8 mcc_policy_idx = 0;
293
294 mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
295 mcc_duration = mccobjpriv->duration;
296
297 if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
298 mccobjpriv->policy_index = 0;
299 RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
300 mcc_policy_idx, mccobjpriv->policy_index);
301 } else
302 mccobjpriv->policy_index = mcc_policy_idx;
303
304 /* convert % to time */
305 if (mcc_duration != 0)
306 rtw_hal_mcc_update_policy_table(padapter);
307
308 RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
309 , mccobjpriv->policy_index
310 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
311 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
312 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
313 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
314 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
315 , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
316
317 }
318
rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter)319 static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter)
320 {
321 struct registry_priv *preg = &padapter->registrypriv;
322 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
323 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
324
325 switch (pmccadapriv->role) {
326 case MCC_ROLE_STA:
327 case MCC_ROLE_GC:
328 switch (pmlmeext->cur_bwmode) {
329 case CHANNEL_WIDTH_20:
330 /*
331 * target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)
332 * = target tx tp(Mbits/sec) * 128 * duration(ms)
333 * note:
334 * target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes
335 * duration(ms) / 1024 ==> msec to sec
336 */
337 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
338 break;
339 case CHANNEL_WIDTH_40:
340 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
341 break;
342 case CHANNEL_WIDTH_80:
343 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
344 break;
345 case CHANNEL_WIDTH_160:
346 case CHANNEL_WIDTH_80_80:
347 RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
348 , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
349 break;
350 }
351 break;
352 case MCC_ROLE_AP:
353 case MCC_ROLE_GO:
354 switch (pmlmeext->cur_bwmode) {
355 case CHANNEL_WIDTH_20:
356 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
357 break;
358 case CHANNEL_WIDTH_40:
359 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
360 break;
361 case CHANNEL_WIDTH_80:
362 pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
363 break;
364 case CHANNEL_WIDTH_160:
365 case CHANNEL_WIDTH_80_80:
366 RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
367 , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
368 break;
369 }
370 break;
371 default:
372 RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
373 , FUNC_ADPT_ARG(padapter), pmccadapriv->role);
374 break;
375 }
376 }
377
378 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
mcc_cfg_phdym_rf_ch(_adapter * adapter)379 static void mcc_cfg_phdym_rf_ch (_adapter *adapter)
380 {
381 struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
382 struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
383 HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
384 struct dm_struct *dm = &hal->odmpriv;
385 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
386 u8 order = 0;
387
388 set_channel_bwmode(adapter, mlmeext->cur_channel, mlmeext->cur_ch_offset, mlmeext->cur_bwmode);
389 order = mccadapriv->order;
390 mcc_dm->mcc_rf_ch[order] = phy_query_rf_reg(adapter, RF_PATH_A, 0x18, 0x03ff);
391 }
392
mcc_cfg_phdym_update_macid(_adapter * adapter,u8 add,u8 mac_id)393 static void mcc_cfg_phdym_update_macid (_adapter *adapter, u8 add, u8 mac_id)
394 {
395 struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
396 struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
397 HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
398 struct dm_struct *dm = &hal->odmpriv;
399 struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
400 u8 order = 0, i = 0;
401
402 order = mccadapriv->order;
403 if (add) {
404 for (i = 0; i < NUM_STA; i++) {
405 if (mcc_dm->sta_macid[order][i] == 0xff) {
406 mcc_dm->sta_macid[order][i] = mac_id;
407 break;
408 }
409 }
410 } else {
411 for (i = 0; i < NUM_STA; i++) {
412 if (mcc_dm->sta_macid[order][i] == mac_id) {
413 mcc_dm->sta_macid[order][i] = 0xff;
414 break;
415 }
416 }
417 }
418
419
420 }
421
mcc_cfg_phdym_start(_adapter * adapter,u8 start)422 static void mcc_cfg_phdym_start(_adapter *adapter, u8 start)
423 {
424 struct dvobj_priv *dvobj;
425 struct mcc_obj_priv *mccobjpriv;
426 HAL_DATA_TYPE *hal;
427 struct dm_struct *dm;
428 struct _phydm_mcc_dm_ *mcc_dm;
429 u8 rfk_forbidden = _TRUE;
430 u8 i = 0, j = 0;
431
432 dvobj = adapter_to_dvobj(adapter);
433 mccobjpriv = adapter_to_mccobjpriv(adapter);
434 hal = GET_HAL_DATA(adapter);
435 dm = &hal->odmpriv;
436 mcc_dm = &dm->mcc_dm;
437
438 if (start) {
439 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
440 mcc_dm->mcc_status = mccobjpriv->mcc_phydm_offload;
441 #endif
442
443 rfk_forbidden = _TRUE;
444 halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
445 } else {
446 rfk_forbidden = _FALSE;
447 halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
448
449 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
450 for(i = 0; i < MAX_MCC_NUM; i ++) {
451 for(j = 0; j < NUM_STA; j ++) {
452 if (mcc_dm->sta_macid[i][j] != 0xff)
453 /* clear all used value for mcc stop */
454 /* do nothing for mcc start due to phydm will init to 0xff */
455 mcc_dm->sta_macid[i][j] = 0xff;
456 }
457 mcc_dm->mcc_rf_ch[i] = 0xff;
458 }
459 mcc_dm->mcc_status = 0;
460 #endif
461 }
462 }
463
mcc_cfg_phdym_dump(_adapter * adapter,void * sel)464 static void mcc_cfg_phdym_dump(_adapter *adapter, void *sel)
465 {
466 HAL_DATA_TYPE *hal;
467 struct dm_struct *dm;
468 struct _phydm_mcc_dm_ *mcc_dm;
469 u8 rfk_forbidden = _TRUE;
470 u8 i = 0, j = 0;
471
472
473 hal = GET_HAL_DATA(adapter);
474 dm = &hal->odmpriv;
475 mcc_dm = &dm->mcc_dm;
476
477 rfk_forbidden = halrf_cmn_info_get(dm, HALRF_CMNINFO_RFK_FORBIDDEN);
478 RTW_PRINT_SEL(sel, "dump mcc dm info\n");
479 RTW_PRINT_SEL(sel, "mcc_status=%d\n", mcc_dm->mcc_status);
480 RTW_PRINT_SEL(sel, "rfk_forbidden=%d\n", rfk_forbidden);
481 for(i = 0; i < MAX_MCC_NUM; i ++) {
482
483 if (mcc_dm->mcc_rf_ch[i] != 0xff)
484 RTW_PRINT_SEL(sel, "mcc_dm->mcc_rf_ch[%d] = 0x%02x\n", i, mcc_dm->mcc_rf_ch[i]);
485
486 for(j = 0; j < NUM_STA; j ++) {
487 if (mcc_dm->sta_macid[i][j] != 0xff)
488 RTW_PRINT_SEL(sel, "mcc_dm->sta_macid[%d][%d] = %d\n", i, j, mcc_dm->sta_macid[i][j]);
489 }
490 }
491 }
492
mcc_cfg_phdym_offload(_adapter * adapter,u8 enable)493 static void mcc_cfg_phdym_offload(_adapter *adapter, u8 enable)
494 {
495 struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
496 _adapter *iface = NULL;
497 struct mcc_adapter_priv *mccadapriv = NULL;
498 HAL_DATA_TYPE *hal = NULL;
499 struct dm_struct *dm = NULL;
500 struct _phydm_mcc_dm_ *mcc_dm = NULL;
501 struct sta_priv *stapriv = NULL;
502 struct sta_info *sta = NULL;
503 struct wlan_network *cur_network = NULL;
504 _irqL irqL;
505 _list *head = NULL, *list = NULL;
506 u8 i = 0;
507
508
509 hal = GET_HAL_DATA(adapter);
510 dm = &hal->odmpriv;
511 mcc_dm = &dm->mcc_dm;
512
513 /* due to phydm will rst related date, driver must set related data */
514 if (enable) {
515 for (i = 0; i < MAX_MCC_NUM; i++) {
516 iface = mccobjpriv->iface[i];
517 if (!iface)
518 continue;
519 stapriv = &iface->stapriv;
520 mccadapriv = &iface->mcc_adapterpriv;
521 switch (mccadapriv->role) {
522 case MCC_ROLE_STA:
523 case MCC_ROLE_GC:
524 cur_network = &iface->mlmepriv.cur_network;
525 sta = rtw_get_stainfo(stapriv, cur_network->network.MacAddress);
526 if (sta)
527 mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
528 break;
529 case MCC_ROLE_AP:
530 case MCC_ROLE_GO:
531 _enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
532
533 head = &stapriv->asoc_list;
534 list = get_next(head);
535
536 while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
537 sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
538 list = get_next(list);
539 mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
540 }
541
542 _exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
543 break;
544 default:
545 RTW_INFO("Unknown role\n");
546 rtw_warn_on(1);
547 break;
548 }
549
550 }
551 }
552
553 mcc_dm->mcc_status = enable;
554 }
555
rtw_hal_mcc_cfg_phydm(_adapter * adapter,enum mcc_cfg_phydm_ops ops,void * data)556 static void rtw_hal_mcc_cfg_phydm (_adapter *adapter, enum mcc_cfg_phydm_ops ops, void *data)
557 {
558 switch (ops) {
559 case MCC_CFG_PHYDM_OFFLOAD:
560 mcc_cfg_phdym_offload(adapter, *(u8 *)data);
561 break;
562 case MCC_CFG_PHYDM_RF_CH:
563 mcc_cfg_phdym_rf_ch(adapter);
564 break;
565 case MCC_CFG_PHYDM_ADD_CLIENT:
566 mcc_cfg_phdym_update_macid(adapter, _TRUE, *(u8 *)data);
567 break;
568 case MCC_CFG_PHYDM_REMOVE_CLIENT:
569 mcc_cfg_phdym_update_macid(adapter, _FALSE, *(u8 *)data);
570 break;
571 case MCC_CFG_PHYDM_START:
572 mcc_cfg_phdym_start(adapter, _TRUE);
573 break;
574 case MCC_CFG_PHYDM_STOP:
575 mcc_cfg_phdym_start(adapter, _FALSE);
576 break;
577 case MCC_CFG_PHYDM_DUMP:
578 mcc_cfg_phdym_dump(adapter, data);
579 break;
580 case MCC_CFG_PHYDM_MAX:
581 default:
582 RTW_ERR("[MCC] rtw_hal_mcc_cfg_phydm ops error (%d)\n", ops);
583 break;
584
585 }
586 }
587 #endif
588
rtw_hal_config_mcc_role_setting(PADAPTER padapter,u8 order)589 static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
590 {
591 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
592 struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
593 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
594 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
595 struct wlan_network *cur_network = &(pmlmepriv->cur_network);
596 struct sta_priv *pstapriv = &padapter->stapriv;
597 struct sta_info *psta = NULL;
598 struct registry_priv *preg = &padapter->registrypriv;
599 _irqL irqL;
600 _list *phead =NULL, *plist = NULL;
601 u8 policy_index = 0;
602 u8 mcc_duration = 0;
603 u8 mcc_interval = 0;
604 u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);
605 u8 ap_num = DEV_AP_NUM(pdvobjpriv);
606
607 policy_index = pmccobjpriv->policy_index;
608 mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
609 - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
610 - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
611 mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
612
613 if (starting_ap_num == 0 && ap_num == 0) {
614 pmccadapriv->order = order;
615
616 if (pmccadapriv->order == 0) {
617 /* setting is smiliar to GO/AP */
618 /* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
619 pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
620 } else if (pmccadapriv->order == 1) {
621 /* pmccadapriv->mcc_duration = mcc_duration; */
622 pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
623 } else {
624 RTW_INFO("[MCC] not support >= 3 interface\n");
625 rtw_warn_on(1);
626 }
627
628 rtw_hal_mcc_assign_tx_threshold(padapter);
629
630 psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
631 if (psta) {
632 /* combine AP/GO macid and mgmt queue macid to bitmap */
633 pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
634 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
635 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
636 #endif
637 } else {
638 RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
639 rtw_warn_on(1);
640 }
641 } else {
642 /* GO/AP is 1nd order GC/STA is 2nd order */
643 switch (pmccadapriv->role) {
644 case MCC_ROLE_STA:
645 case MCC_ROLE_GC:
646 pmccadapriv->order = 1;
647 pmccadapriv->mcc_duration = mcc_duration;
648
649 rtw_hal_mcc_assign_tx_threshold(padapter);
650 /* assign used mac to avoid affecting RA */
651 pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
652
653 psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
654 if (psta) {
655 /* combine AP/GO macid and mgmt queue macid to bitmap */
656 pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
657 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
658 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
659 #endif
660 } else {
661 RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
662 rtw_warn_on(1);
663 }
664 break;
665 case MCC_ROLE_AP:
666 case MCC_ROLE_GO:
667 pmccadapriv->order = 0;
668 /* total druation value equals interval */
669 pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
670 pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
671
672 rtw_hal_mcc_assign_tx_threshold(padapter);
673
674 _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
675
676 phead = &pstapriv->asoc_list;
677 plist = get_next(phead);
678 pmccadapriv->mcc_macid_bitmap = 0;
679
680 while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
681 psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
682 plist = get_next(plist);
683 pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
684 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
685 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
686 #endif
687 }
688
689 _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
690
691 psta = rtw_get_bcmc_stainfo(padapter);
692
693 if (psta != NULL)
694 pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
695 else {
696 pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
697 RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
698 , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
699 }
700
701 /* combine client macid and mgmt queue macid to bitmap */
702 pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
703 break;
704 default:
705 RTW_INFO("Unknown role\n");
706 rtw_warn_on(1);
707 break;
708 }
709
710 }
711
712 /* setting Null data parameters */
713 if (pmccadapriv->role == MCC_ROLE_STA) {
714 pmccadapriv->null_early = 3;
715 pmccadapriv->null_rty_num= 5;
716 } else if (pmccadapriv->role == MCC_ROLE_GC) {
717 pmccadapriv->null_early = 2;
718 pmccadapriv->null_rty_num= 5;
719 } else {
720 pmccadapriv->null_early = 0;
721 pmccadapriv->null_rty_num= 0;
722 }
723
724 RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
725 RTW_INFO("order:%d\n", pmccadapriv->order);
726 RTW_INFO("role:%d\n", pmccadapriv->role);
727 RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
728 RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
729 RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
730 RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
731 RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
732 RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
733 RTW_INFO("**********************************\n");
734
735 pmccobjpriv->iface[pmccadapriv->order] = padapter;
736 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
737 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_RF_CH, NULL);
738 #endif
739
740 }
741
rtw_hal_mcc_rqt_tsf(PADAPTER padapter,u64 * out_tsf)742 static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)
743 {
744 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
745 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
746 PADAPTER order0_iface = NULL;
747 PADAPTER order1_iface = NULL;
748 struct submit_ctx *tsf_req_sctx = NULL;
749 enum _hw_port tsfx = MAX_HW_PORT;
750 enum _hw_port tsfy = MAX_HW_PORT;
751 u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
752
753 _enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
754
755 order0_iface = mccobjpriv->iface[0];
756 order1_iface = mccobjpriv->iface[1];
757
758 tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
759 rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);
760 mccobjpriv->mcc_tsf_req_sctx_order = 0;
761 tsfx = rtw_hal_get_port(order0_iface);
762 tsfy = rtw_hal_get_port(order1_iface);
763
764 SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);
765 SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);
766
767 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
768
769 if (!rtw_sctx_wait(tsf_req_sctx, __func__))
770 RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
771
772 if (tsf_req_sctx->status == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {
773 out_tsf[0] = order0_iface->mcc_adapterpriv.tsf;
774 out_tsf[1] = order1_iface->mcc_adapterpriv.tsf;
775 }
776
777
778 _exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
779 }
780
rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter,u8 case_num,u32 tsfdiff,s8 * upper_bound_0,s8 * lower_bound_0,s8 * upper_bound_1,s8 * lower_bound_1)781 static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
782 u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
783 {
784 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
785 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
786 u8 duration_0 = 0, duration_1 = 0;
787 s8 final_upper_bound = 0, final_lower_bound = 0;
788 u8 intersection = _FALSE;
789 u8 min_start_time = 5;
790 u8 max_start_time = 95;
791
792 duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
793 duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
794
795 switch(case_num) {
796 case 1:
797 *upper_bound_0 = tsfdiff;
798 *lower_bound_0 = tsfdiff - duration_1;
799 *upper_bound_1 = 150 - duration_1;
800 *lower_bound_1= 0;
801 break;
802 case 2:
803 *upper_bound_0 = tsfdiff + 100;
804 *lower_bound_0 = tsfdiff + 100 - duration_1;
805 *upper_bound_1 = 150 - duration_1;
806 *lower_bound_1= 0;
807 break;
808 case 3:
809 *upper_bound_0 = tsfdiff + 50;
810 *lower_bound_0 = tsfdiff + 50 - duration_1;
811 *upper_bound_1 = 150 - duration_1;
812 *lower_bound_1= 0;
813 break;
814 case 4:
815 *upper_bound_0 = tsfdiff;
816 *lower_bound_0 = tsfdiff - duration_1;
817 *upper_bound_1 = 150 - duration_1;
818 *lower_bound_1= 0;
819 break;
820 case 5:
821 *upper_bound_0 = 200 - tsfdiff;
822 *lower_bound_0 = 200 - tsfdiff - duration_1;
823 *upper_bound_1 = 150 - duration_1;
824 *lower_bound_1= 0;
825 break;
826 case 6:
827 *upper_bound_0 = tsfdiff - 50;
828 *lower_bound_0 = tsfdiff - 50 - duration_1;
829 *upper_bound_1 = 150 - duration_1;
830 *lower_bound_1= 0;
831 break;
832 default:
833 RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
834 }
835
836
837 /* check Intersection or not */
838 if ((*lower_bound_1 >= *upper_bound_0) ||
839 (*lower_bound_0 >= *upper_bound_1))
840 intersection = _FALSE;
841 else
842 intersection = _TRUE;
843
844 if (intersection) {
845 if (*upper_bound_0 > *upper_bound_1)
846 final_upper_bound = *upper_bound_1;
847 else
848 final_upper_bound = *upper_bound_0;
849
850 if (*lower_bound_0 > *lower_bound_1)
851 final_lower_bound = *lower_bound_0;
852 else
853 final_lower_bound = *lower_bound_1;
854
855 mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
856
857 /* check start time less than 5ms, request by Pablo@SD1 */
858 if (mccobjpriv->start_time <= min_start_time) {
859 mccobjpriv->start_time = 6;
860 if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
861 intersection = _FALSE;
862 goto exit;
863 }
864 }
865
866 /* check start time less than 95ms */
867 if (mccobjpriv->start_time >= max_start_time) {
868 mccobjpriv->start_time = 90;
869 if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
870 intersection = _FALSE;
871 goto exit;
872 }
873 }
874 }
875
876 exit:
877 return intersection;
878 }
879
rtw_hal_mcc_decide_duration(PADAPTER padapter)880 static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
881 {
882 struct registry_priv *registry_par = &padapter->registrypriv;
883 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
884 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
885 struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
886 _adapter *iface = NULL, *iface_order0 = NULL, *iface_order1 = NULL;
887 u8 duration = 0, i = 0, duration_time;
888 u8 mcc_interval = 150;
889
890 iface_order0 = mccobjpriv->iface[0];
891 iface_order1 = mccobjpriv->iface[1];
892 mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
893 mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
894
895 if (mccobjpriv->duration == 0) {
896 /* default */
897 duration = 30;/*(%)*/
898 RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
899 __FUNCTION__, duration);
900 } else {
901 duration = mccobjpriv->duration;/*(%)*/
902 RTW_INFO("%s: mccobjpriv->duration=%d\n",
903 __FUNCTION__, duration);
904 }
905
906 mccobjpriv->interval = mcc_interval;
907 mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
908 /* convert % to ms, for primary adapter */
909 duration_time = mccobjpriv->interval * duration / 100;
910
911 for (i = 0; i < dvobj->iface_nums; i++) {
912 iface = dvobj->padapters[i];
913
914 if (!iface)
915 continue;
916
917 mccadapriv = &iface->mcc_adapterpriv;
918 if (mccadapriv->role == MCC_ROLE_MAX)
919 continue;
920
921 if (is_primary_adapter(iface))
922 mccadapriv->mcc_duration = duration_time;
923 else
924 mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
925 }
926
927 RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
928 RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
929 }
930
rtw_hal_mcc_update_timing_parameters(PADAPTER padapter,u8 force_update)931 static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
932 {
933 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
934 u8 need_update = _FALSE;
935 u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
936 u8 ap_num = DEV_AP_NUM(dvobj);
937
938
939 /* for STA+STA, modify policy table */
940 if (starting_ap_num == 0 && ap_num == 0) {
941 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
942 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
943 struct mcc_adapter_priv *pmccadapriv = NULL;
944 _adapter *iface = NULL;
945 u64 tsf[MAX_MCC_NUM] = {0};
946 u64 tsf0 = 0, tsf1 = 0;
947 u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
948 s8 upper_bound_0 = 0, lower_bound_0 = 0;
949 s8 upper_bound_1 = 0, lower_bound_1 = 0;
950 u8 valid = _FALSE;
951 u8 case_num = 1;
952 u8 i = 0;
953
954 /* query TSF */
955 rtw_hal_mcc_rqt_tsf(padapter, tsf);
956
957 /* selecet policy table according TSF diff */
958 tsf0 = tsf[0];
959 beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
960 tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
961
962 tsf1 = tsf[1];
963 beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
964 tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
965
966 if (tsf0 > tsf1)
967 tsfdiff = tsf0- tsf1;
968 else
969 tsfdiff = (tsf0 + beaconperiod_0 * TU) - tsf1;
970
971 /* convert to ms */
972 tsfdiff = (tsfdiff / TU);
973
974 /* force update*/
975 if (force_update) {
976 RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
977 pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
978 RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
979 RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
980 __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
981 pmccobjpriv->last_tsfdiff = tsfdiff;
982 need_update = _TRUE;
983 } else {
984 if (pmccobjpriv->last_tsfdiff > tsfdiff) {
985 /* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
986 if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
987 RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
988 pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
989 RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
990 RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
991 __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
992
993 pmccobjpriv->last_tsfdiff = tsfdiff;
994 need_update = _TRUE;
995 } else {
996 need_update = _FALSE;
997 }
998 } else if (tsfdiff > pmccobjpriv->last_tsfdiff){
999 /* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
1000 if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
1001 RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
1002 pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
1003 RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
1004 RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
1005 __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
1006
1007 pmccobjpriv->last_tsfdiff = tsfdiff;
1008 need_update = _TRUE;
1009 } else {
1010 need_update = _FALSE;
1011 }
1012 } else {
1013 need_update = _FALSE;
1014 }
1015 }
1016
1017 if (need_update == _FALSE)
1018 goto exit;
1019
1020 rtw_hal_mcc_decide_duration(padapter);
1021
1022 if (tsfdiff <= 50) {
1023
1024 /* RX TBTT 0 */
1025 case_num = 1;
1026 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1027 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1028
1029 if (valid)
1030 goto valid_result;
1031
1032 /* RX TBTT 1 */
1033 case_num = 2;
1034 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1035 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1036
1037 if (valid)
1038 goto valid_result;
1039
1040 /* RX TBTT 2 */
1041 case_num = 3;
1042 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1043 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1044
1045 if (valid)
1046 goto valid_result;
1047
1048 if (valid == _FALSE) {
1049 RTW_INFO("[MCC] do not find fit start time\n");
1050 RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
1051 tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
1052
1053 }
1054
1055 } else {
1056
1057 /* RX TBTT 0 */
1058 case_num = 4;
1059 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1060 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1061
1062 if (valid)
1063 goto valid_result;
1064
1065
1066 /* RX TBTT 1 */
1067 case_num = 5;
1068 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1069 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1070
1071 if (valid)
1072 goto valid_result;
1073
1074
1075 /* RX TBTT 2 */
1076 case_num = 6;
1077 valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
1078 &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
1079
1080 if (valid)
1081 goto valid_result;
1082
1083 if (valid == _FALSE) {
1084 RTW_INFO("[MCC] do not find fit start time\n");
1085 RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
1086 tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
1087 }
1088 }
1089
1090
1091
1092 valid_result:
1093 RTW_INFO("********************\n");
1094 RTW_INFO("%s: case_num:%d, start time:%d\n",
1095 __func__, case_num, pmccobjpriv->start_time);
1096 RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
1097 __func__, upper_bound_0, lower_bound_0);
1098 RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
1099 __func__, upper_bound_1, lower_bound_1);
1100
1101 for (i = 0; i < dvobj->iface_nums; i++) {
1102 iface = dvobj->padapters[i];
1103 if (iface == NULL)
1104 continue;
1105
1106 pmccadapriv = &iface->mcc_adapterpriv;
1107 pmccadapriv = &iface->mcc_adapterpriv;
1108 if (pmccadapriv->role == MCC_ROLE_MAX)
1109 continue;
1110 #if 0
1111 if (pmccadapriv->order == 0) {
1112 pmccadapriv->mcc_duration = mcc_duration;
1113 } else if (pmccadapriv->order == 1) {
1114 pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
1115 } else {
1116 RTW_INFO("[MCC] not support >= 3 interface\n");
1117 rtw_warn_on(1);
1118 }
1119 #endif
1120 RTW_INFO("********************\n");
1121 RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
1122 FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
1123 RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
1124 FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
1125 RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
1126 FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
1127 RTW_INFO("********************\n");
1128 }
1129
1130 }
1131 exit:
1132 return need_update;
1133 }
1134
rtw_hal_decide_mcc_role(PADAPTER padapter)1135 static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
1136 {
1137 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1138 _adapter *iface = NULL;
1139 struct mcc_adapter_priv *pmccadapriv = NULL;
1140 struct wifidirect_info *pwdinfo = NULL;
1141 struct mlme_priv *pmlmepriv = NULL;
1142 u8 ret = _SUCCESS, i = 0;
1143 u8 order = 1;
1144
1145 for (i = 0; i < dvobj->iface_nums; i++) {
1146 iface = dvobj->padapters[i];
1147 if (iface == NULL)
1148 continue;
1149
1150 pmccadapriv = &iface->mcc_adapterpriv;
1151 pwdinfo = &iface->wdinfo;
1152
1153 if (MLME_IS_GO(iface))
1154 pmccadapriv->role = MCC_ROLE_GO;
1155 else if (MLME_IS_AP(iface))
1156 pmccadapriv->role = MCC_ROLE_AP;
1157 else if (MLME_IS_GC(iface))
1158 pmccadapriv->role = MCC_ROLE_GC;
1159 else if (MLME_IS_STA(iface)) {
1160 if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))
1161 pmccadapriv->role = MCC_ROLE_STA;
1162 else {
1163 /* bypass non-linked/non-linking interface */
1164 RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n",
1165 FUNC_ADPT_ARG(iface), MLME_STATE(iface));
1166 continue;
1167 }
1168 } else {
1169 /* bypass non-linked/non-linking interface */
1170 RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n",
1171 FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));
1172 continue;
1173 }
1174
1175 if (padapter == iface) {
1176 /* current adapter is order 0 */
1177 rtw_hal_config_mcc_role_setting(iface, 0);
1178 } else {
1179 rtw_hal_config_mcc_role_setting(iface, order);
1180 order ++;
1181 }
1182 }
1183
1184 rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
1185
1186 return ret;
1187 }
1188
rtw_hal_construct_CTS(PADAPTER padapter,u8 * pframe,u32 * pLength)1189 static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
1190 {
1191 u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1192
1193 /* frame type, length = 1*/
1194 set_frame_sub_type(pframe, WIFI_RTS);
1195
1196 /* frame control flag, length = 1 */
1197 *(pframe + 1) = 0;
1198
1199 /* frame duration, length = 2 */
1200 *(pframe + 2) = 0x00;
1201 *(pframe + 3) = 0x78;
1202
1203 /* frame recvaddr, length = 6 */
1204 _rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
1205 _rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
1206 _rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
1207 *pLength = 22;
1208 }
1209
1210 /* avoid wrong information for power limit */
rtw_hal_mcc_upadate_chnl_bw(_adapter * padapter,u8 ch,u8 ch_offset,u8 bw,u8 print)1211 void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
1212 {
1213
1214 u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1215 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1216 PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
1217 u8 cch_160, cch_80, cch_40, cch_20;
1218
1219 center_ch = rtw_get_center_ch(ch, bw, ch_offset);
1220
1221 if (bw == CHANNEL_WIDTH_80) {
1222 if (center_ch > ch)
1223 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
1224 else if (center_ch < ch)
1225 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
1226 else
1227 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1228 }
1229
1230 /* set Channel */
1231 /* saved channel/bw info */
1232 rtw_set_oper_ch(padapter, ch);
1233 rtw_set_oper_bw(padapter, bw);
1234 rtw_set_oper_choffset(padapter, ch_offset);
1235
1236 cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
1237 cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
1238 cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
1239
1240 if (cch_80 != 0)
1241 cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
1242 if (cch_40 != 0)
1243 cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
1244
1245
1246 hal->cch_80 = cch_80;
1247 hal->cch_40 = cch_40;
1248 hal->cch_20 = cch_20;
1249 hal->current_channel = center_ch;
1250 hal->CurrentCenterFrequencyIndex1 = center_ch;
1251 hal->current_channel_bw = bw;
1252 hal->nCur40MhzPrimeSC = ch_offset;
1253 hal->nCur80MhzPrimeSC = chnl_offset80;
1254 hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
1255
1256 if (print) {
1257 RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
1258 , FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
1259 , ch_offset, chnl_offset80
1260 , hal->cch_80, hal->cch_40, hal->cch_20
1261 , band_str(hal->current_band_type));
1262 }
1263 }
1264
rtw_hal_dl_mcc_fw_rsvd_page(_adapter * adapter,u8 * pframe,u16 * index,u8 tx_desc,u32 page_size,u8 * total_page_num,RSVDPAGE_LOC * rsvd_page_loc,u8 * page_num)1265 u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
1266 u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
1267 {
1268 u32 len = 0;
1269 _adapter *iface = NULL;
1270 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1271 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
1272 struct mlme_ext_info *pmlmeinfo = NULL;
1273 struct mlme_ext_priv *pmlmeext = NULL;
1274 struct hal_com_data *hal = GET_HAL_DATA(adapter);
1275 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1276 struct mcc_adapter_priv *mccadapriv = NULL;
1277 #if defined(CONFIG_RTL8822C)
1278 struct dm_struct *phydm = adapter_to_phydm(adapter);
1279 struct txagc_table_8822c tab;
1280 u8 agc_buff[2][NUM_RATE_AC_2SS]; /* tatol 0x40 rate index for PATH A/B */
1281 #endif
1282
1283 u8 ret = _SUCCESS, i = 0, j =0, order = 0, CurtPktPageNum = 0;
1284 u8 *start = NULL;
1285 u8 path = RF_PATH_A;
1286
1287 if (page_num) {
1288 #ifdef CONFIG_MCC_MODE_V2
1289 if (!hal->RegIQKFWOffload)
1290 RTW_WARN("[MCC] must enable FW IQK for New IC\n");
1291 #endif /* CONFIG_MCC_MODE_V2 */
1292 *total_page_num += (2 * MAX_MCC_NUM+ 1);
1293 RTW_INFO("[MCC] allocate mcc rsvd page num = %d\n", *total_page_num);
1294 goto exit;
1295 }
1296
1297 /* check proccess mcc start setting */
1298 if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
1299 ret = _FAIL;
1300 goto exit;
1301 }
1302
1303 for (i = 0; i < dvobj->iface_nums; i++) {
1304 iface = dvobj->padapters[i];
1305 if (iface == NULL)
1306 continue;
1307
1308 mccadapriv = &iface->mcc_adapterpriv;
1309 if (mccadapriv->role == MCC_ROLE_MAX)
1310 continue;
1311
1312 order = mccadapriv->order;
1313 pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;
1314
1315 switch (mccadapriv->role) {
1316 case MCC_ROLE_STA:
1317 case MCC_ROLE_GC:
1318 /* Build NULL DATA */
1319 RTW_INFO("LocNull(order:%d): %d\n"
1320 , order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
1321 len = 0;
1322
1323 rtw_hal_construct_NullFunctionData(iface
1324 , &pframe[*index], &len, _FALSE, 0, 0, _FALSE);
1325 rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
1326 len, _FALSE, _FALSE, _FALSE);
1327
1328 CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
1329 *total_page_num += CurtPktPageNum;
1330 *index += (CurtPktPageNum * page_size);
1331 RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
1332 break;
1333 case MCC_ROLE_AP:
1334 /* Bulid CTS */
1335 RTW_INFO("LocCTS(order:%d): %d\n"
1336 , order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
1337
1338 len = 0;
1339 rtw_hal_construct_CTS(iface, &pframe[*index], &len);
1340 rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
1341 len, _FALSE, _FALSE, _FALSE);
1342
1343 CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
1344 *total_page_num += CurtPktPageNum;
1345 *index += (CurtPktPageNum * page_size);
1346 RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
1347 break;
1348 case MCC_ROLE_GO:
1349 /* To DO */
1350 break;
1351 default:
1352 RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
1353 , FUNC_ADPT_ARG(iface), mccadapriv->role);
1354 break;
1355 }
1356 }
1357
1358 for (i = 0; i < MAX_MCC_NUM; i++) {
1359 u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
1360 BAND_TYPE band = BAND_MAX;
1361 u8 power_index = 0;
1362 u8 rate_array_sz = 0;
1363 u8 *rates = NULL;
1364 u8 rate = 0;
1365 u8 shift = 0;
1366 u32 power_index_4bytes = 0;
1367 u8 total_rate = 0;
1368 u8 *total_rate_offset = NULL;
1369
1370 iface = pmccobjpriv->iface[i];
1371 pmlmeext = &iface->mlmeextpriv;
1372 ch = pmlmeext->cur_channel;
1373 bw = pmlmeext->cur_bwmode;
1374 bw_offset = pmlmeext->cur_ch_offset;
1375 center_ch = rtw_get_center_ch(ch, bw, bw_offset);
1376 band = center_ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
1377 rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
1378
1379 start = &pframe[*index - tx_desc];
1380 _rtw_memset(start, 0, page_size);
1381 pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
1382 RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
1383 ADPT_ARG(iface), mccadapriv->order,
1384 i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
1385
1386 total_rate_offset = start;
1387 #if !defined(CONFIG_RTL8822C)
1388 for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
1389 total_rate = 0;
1390 /* PATH A for 0~63 byte, PATH B for 64~127 byte*/
1391 if (path == RF_PATH_A)
1392 start = total_rate_offset + 1;
1393 else if (path == RF_PATH_B)
1394 start = total_rate_offset + 64;
1395 else {
1396 RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
1397 break;
1398 }
1399
1400 /* CCK */
1401 if (ch <= 14) {
1402 rate_array_sz = rates_by_sections[CCK].rate_num;
1403 rates = rates_by_sections[CCK].rates;
1404 for (j = 0; j < rate_array_sz; ++j) {
1405 power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
1406 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1407
1408 shift = rate % 4;
1409 if (shift == 0) {
1410 *start = rate;
1411 start++;
1412 total_rate++;
1413
1414 #ifdef DBG_PWR_IDX_RSVD_PAGE
1415 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1416 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1417 center_ch, MGN_RATE_STR(rates[j]), power_index);
1418 #endif
1419 }
1420
1421 *start = power_index;
1422 start++;
1423
1424 #ifdef DBG_PWR_IDX_RSVD_PAGE
1425 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1426 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1427 center_ch, MGN_RATE_STR(rates[j]), power_index);
1428
1429
1430 shift = rate % 4;
1431 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1432 if (shift == 3) {
1433 rate = rate - 3;
1434 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1435 power_index_4bytes = 0;
1436 total_rate++;
1437 }
1438 #endif
1439
1440 }
1441 }
1442
1443 /* OFDM */
1444 rate_array_sz = rates_by_sections[OFDM].rate_num;
1445 rates = rates_by_sections[OFDM].rates;
1446 for (j = 0; j < rate_array_sz; ++j) {
1447 power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
1448 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1449
1450 shift = rate % 4;
1451 if (shift == 0) {
1452 *start = rate;
1453 start++;
1454 total_rate++;
1455
1456 #ifdef DBG_PWR_IDX_RSVD_PAGE
1457 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1458 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1459 center_ch, MGN_RATE_STR(rates[j]), power_index);
1460 #endif
1461
1462 }
1463
1464 *start = power_index;
1465 start++;
1466
1467 #ifdef DBG_PWR_IDX_RSVD_PAGE
1468 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1469 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1470 center_ch, MGN_RATE_STR(rates[j]), power_index);
1471
1472 shift = rate % 4;
1473 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1474 if (shift == 3) {
1475 rate = rate - 3;
1476 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1477 power_index_4bytes = 0;
1478 total_rate++;
1479 }
1480 #endif
1481 }
1482
1483 /* HT_MCS0_MCS7 */
1484 rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
1485 rates = rates_by_sections[HT_MCS0_MCS7].rates;
1486 for (j = 0; j < rate_array_sz; ++j) {
1487 power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
1488 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1489
1490 shift = rate % 4;
1491 if (shift == 0) {
1492 *start = rate;
1493 start++;
1494 total_rate++;
1495
1496 #ifdef DBG_PWR_IDX_RSVD_PAGE
1497 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1498 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1499 center_ch, MGN_RATE_STR(rates[j]), power_index);
1500 #endif
1501
1502 }
1503
1504 *start = power_index;
1505 start++;
1506
1507 #ifdef DBG_PWR_IDX_RSVD_PAGE
1508 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1509 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1510 center_ch, MGN_RATE_STR(rates[j]), power_index);
1511
1512 shift = rate % 4;
1513 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1514 if (shift == 3) {
1515 rate = rate - 3;
1516 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1517 power_index_4bytes = 0;
1518 total_rate++;
1519 }
1520 #endif
1521 }
1522
1523 /* HT_MCS8_MCS15 */
1524 rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
1525 rates = rates_by_sections[HT_MCS8_MCS15].rates;
1526 for (j = 0; j < rate_array_sz; ++j) {
1527 power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
1528 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1529
1530 shift = rate % 4;
1531 if (shift == 0) {
1532 *start = rate;
1533 start++;
1534 total_rate++;
1535
1536 #ifdef DBG_PWR_IDX_RSVD_PAGE
1537 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1538 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1539 center_ch, MGN_RATE_STR(rates[j]), power_index);
1540 #endif
1541 }
1542
1543 *start = power_index;
1544 start++;
1545
1546 #ifdef DBG_PWR_IDX_RSVD_PAGE
1547 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1548 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1549 center_ch, MGN_RATE_STR(rates[j]), power_index);
1550
1551 shift = rate % 4;
1552 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1553 if (shift == 3) {
1554 rate = rate - 3;
1555 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1556 power_index_4bytes = 0;
1557 total_rate++;
1558 }
1559 #endif
1560 }
1561
1562 /* VHT_1SSMCS0_1SSMCS9 */
1563 rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
1564 rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
1565 for (j = 0; j < rate_array_sz; ++j) {
1566 power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
1567 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1568
1569 shift = rate % 4;
1570 if (shift == 0) {
1571 *start = rate;
1572 start++;
1573 total_rate++;
1574 #ifdef DBG_PWR_IDX_RSVD_PAGE
1575 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
1576 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1577 center_ch, MGN_RATE_STR(rates[j]), power_index);
1578 #endif
1579 }
1580 *start = power_index;
1581 start++;
1582 #ifdef DBG_PWR_IDX_RSVD_PAGE
1583 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1584 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1585 center_ch, MGN_RATE_STR(rates[j]), power_index);
1586
1587 shift = rate % 4;
1588 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1589 if (shift == 3) {
1590 rate = rate - 3;
1591 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1592 power_index_4bytes = 0;
1593 total_rate++;
1594 }
1595 #endif
1596 }
1597
1598 /* VHT_2SSMCS0_2SSMCS9 */
1599 rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
1600 rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
1601 for (j = 0; j < rate_array_sz; ++j) {
1602 power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
1603 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1604
1605 shift = rate % 4;
1606 if (shift == 0) {
1607 *start = rate;
1608 start++;
1609 total_rate++;
1610 #ifdef DBG_PWR_IDX_RSVD_PAGE
1611 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1612 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1613 center_ch, MGN_RATE_STR(rates[j]), power_index);
1614 #endif
1615 }
1616 *start = power_index;
1617 start++;
1618 #ifdef DBG_PWR_IDX_RSVD_PAGE
1619 RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
1620 ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
1621 center_ch, MGN_RATE_STR(rates[j]), power_index);
1622
1623 shift = rate % 4;
1624 power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
1625 if (shift == 3) {
1626 rate = rate - 3;
1627 RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
1628 power_index_4bytes = 0;
1629 total_rate++;
1630 }
1631 #endif
1632 }
1633
1634 }
1635 /* total rate store in offset 0 */
1636 *total_rate_offset = total_rate;
1637
1638 #ifdef DBG_PWR_IDX_RSVD_PAGE
1639 RTW_INFO("total_rate=%d\n", total_rate);
1640 RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
1641 RTW_INFO_DUMP("\n", total_rate_offset, 128);
1642 RTW_INFO(" ==================================================\n");
1643 #endif
1644
1645 CurtPktPageNum = 1;
1646 *total_page_num += CurtPktPageNum;
1647 *index += (CurtPktPageNum * page_size);
1648 RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
1649 #else /* 8822C */
1650 for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
1651 /* CCK */
1652 if (ch <= 14) {
1653 rate_array_sz = rates_by_sections[CCK].rate_num;
1654 rates = rates_by_sections[CCK].rates;
1655 for (j = 0; j < rate_array_sz; ++j) {
1656 power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
1657 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1658 agc_buff[path][rate] = power_index;
1659 }
1660 }
1661
1662 /* OFDM */
1663 rate_array_sz = rates_by_sections[OFDM].rate_num;
1664 rates = rates_by_sections[OFDM].rates;
1665 for (j = 0; j < rate_array_sz; ++j) {
1666 power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
1667 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1668 agc_buff[path][rate] = power_index;
1669 }
1670 /* HT */
1671 rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
1672 rates = rates_by_sections[HT_MCS0_MCS7].rates;
1673 for (j = 0; j < rate_array_sz; ++j) {
1674 power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
1675 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1676 agc_buff[path][rate] = power_index;
1677 }
1678
1679 rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
1680 rates = rates_by_sections[HT_MCS8_MCS15].rates;
1681 for (j = 0; j < rate_array_sz; ++j) {
1682 power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
1683 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1684 agc_buff[path][rate] = power_index;
1685 }
1686 /* VHT */
1687 rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
1688 rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
1689 for (j = 0; j < rate_array_sz; ++j) {
1690 power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
1691 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1692 agc_buff[path][rate] = power_index;
1693 }
1694
1695 rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
1696 rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
1697 for (j = 0; j < rate_array_sz; ++j) {
1698 power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
1699 rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
1700 agc_buff[path][rate] = power_index;
1701 }
1702 }
1703 phydm_get_txagc_ref_and_diff_8822c(phydm, agc_buff, NUM_RATE_AC_2SS, &tab);
1704 *start = tab.ref_pow_cck[0];
1705 start++;
1706 *start = tab.ref_pow_cck[1];
1707 start++;
1708 *start = tab.ref_pow_ofdm[0];
1709 start++;
1710 *start = tab.ref_pow_ofdm[1];
1711 start++;
1712 _rtw_memcpy(start, tab.diff_t, sizeof(tab.diff_t));
1713 CurtPktPageNum = 1;
1714 *total_page_num += CurtPktPageNum;
1715 *index += (CurtPktPageNum * page_size);
1716 RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
1717 #ifdef DBG_PWR_IDX_RSVD_PAGE
1718 if (1) {
1719 u8 path_idx;
1720 for (path_idx = 0; path_idx < 2; path_idx++) {
1721 for (j = 0; j < NUM_RATE_AC_2SS; j++)
1722 RTW_INFO("agc_buff[%d][%d]=%x\n", i, j, agc_buff[i][j]);
1723 }
1724 RTW_INFO("tab->ref_pow_cck[0]=%x\n", tab.ref_pow_cck[0]);
1725 RTW_INFO("tab->ref_pow_cck[1]=%x\n", tab.ref_pow_cck[1]);
1726 RTW_INFO("tab->ref_pow_ofdm[0]=%x\n", tab.ref_pow_ofdm[0]);
1727 RTW_INFO("tab->ref_pow_ofdm[1]=%x\n", tab.ref_pow_ofdm[1]);
1728 RTW_INFO_DUMP("diff_t ", tab.diff_t, NUM_RATE_AC_2SS);
1729 RTW_INFO_DUMP("tab ", (u8 *)&tab, sizeof(tab));
1730 }
1731 #endif
1732
1733 #endif
1734 }
1735
1736 exit:
1737 return ret;
1738 }
1739
1740 /*
1741 * 1. Download MCC rsvd page
1742 * 2. Re-Download beacon after download rsvd page
1743 */
rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)1744 static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
1745 {
1746 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1747 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
1748 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1749 PADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);
1750 PADAPTER iface = NULL;
1751 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
1752 u8 mstatus = RT_MEDIA_CONNECT, i = 0;
1753
1754 RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
1755
1756 rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
1757
1758 /* Re-Download beacon */
1759 for (i = 0; i < MAX_MCC_NUM; i++) {
1760 iface = pmccobjpriv->iface[i];
1761 if (iface == NULL)
1762 continue;
1763
1764 pmccadapriv = &iface->mcc_adapterpriv;
1765
1766 if (pmccadapriv->role == MCC_ROLE_AP
1767 || pmccadapriv->role == MCC_ROLE_GO) {
1768 tx_beacon_hdl(iface, NULL);
1769 }
1770 }
1771 }
1772
rtw_hal_set_mcc_rsvdpage_cmd(_adapter * padapter)1773 static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
1774 {
1775 u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
1776 _adapter *iface = NULL;
1777 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
1778 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1779 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
1780
1781 SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
1782 SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal_spec->rf_reg_path_num);
1783 for (order = 0; order < MAX_MCC_NUM; order++) {
1784 iface = pmccobjpriv->iface[i];
1785
1786 SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
1787 SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
1788 }
1789
1790 #ifdef CONFIG_MCC_MODE_DEBUG
1791 RTW_INFO("=========================\n");
1792 RTW_INFO("MCC RSVD PAGE LOC:\n");
1793 for (i = 0; i < H2C_MCC_LOCATION_LEN; i++)
1794 pr_dbg("0x%x ", cmd[i]);
1795 pr_dbg("\n");
1796 RTW_INFO("=========================\n");
1797 #endif /* CONFIG_MCC_MODE_DEBUG */
1798
1799 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
1800 }
1801
rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)1802 static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
1803 {
1804 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
1805 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
1806 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1807 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
1808 u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
1809 u8 fw_eable = 1;
1810 u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
1811 u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
1812 u8 ap_num = DEV_AP_NUM(dvobj);
1813
1814 if (starting_ap_num == 0 && ap_num == 0)
1815 /* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
1816 fw_eable = 0;
1817 else
1818 /* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
1819 fw_eable = 1;
1820
1821 if (fw_eable == 1) {
1822 PADAPTER order0_iface = NULL;
1823 PADAPTER order1_iface = NULL;
1824 u8 policy_idx = mccobjpriv->policy_index;
1825 u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
1826 u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
1827 u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
1828 u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
1829 u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
1830 enum _hw_port tsf_bsae_port = MAX_HW_PORT;
1831 enum _hw_port tsf_sync_port = MAX_HW_PORT;
1832 order0_iface = mccobjpriv->iface[0];
1833 order1_iface = mccobjpriv->iface[1];
1834
1835 tsf_bsae_port = rtw_hal_get_port(order1_iface);
1836 tsf_sync_port = rtw_hal_get_port(order0_iface);
1837
1838 /* FW set enable */
1839 SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
1840 /* TSF Sync offset */
1841 SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
1842 /* start time offset */
1843 SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
1844 /* interval */
1845 SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
1846 /* Early time to inform driver by C2H before switch channel */
1847 SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
1848 /* Port0 sync from Port1, not support multi-port */
1849 SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
1850 SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
1851 } else {
1852 /* start time offset */
1853 SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);
1854 /* interval */
1855 SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);
1856 /* Early time to inform driver by C2H before switch channel */
1857 SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
1858 }
1859
1860 #ifdef CONFIG_MCC_MODE_DEBUG
1861 {
1862 u8 i = 0;
1863
1864 RTW_INFO("=========================\n");
1865 RTW_INFO("NoA:\n");
1866 for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
1867 pr_dbg("0x%x ", cmd[i]);
1868 pr_dbg("\n");
1869 RTW_INFO("=========================\n");
1870 }
1871 #endif /* CONFIG_MCC_MODE_DEBUG */
1872
1873 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
1874 }
1875
1876 #ifndef CONFIG_MCC_MODE_V2
rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)1877 static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
1878 {
1879 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1880 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
1881 struct mcc_adapter_priv *pmccadapriv = NULL;
1882 _adapter *iface = NULL;
1883 u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
1884 u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
1885 u8 total_rf_path = GET_HAL_SPEC(padapter)->rf_reg_path_num;
1886 u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
1887
1888 /* by order, last order & last_rf_path_index must set ready bit = 1 */
1889 for (i = 0; i < MAX_MCC_NUM; i++) {
1890 iface = pmccobjpriv->iface[i];
1891 if (iface == NULL)
1892 continue;
1893
1894 pmccadapriv = &iface->mcc_adapterpriv;
1895 order = pmccadapriv->order;
1896
1897 for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
1898
1899 _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
1900 TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0] */
1901 TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0] */
1902 RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0] */
1903 RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0] */
1904
1905 /* ready or not */
1906 if (order == last_order && rf_path_idx == last_rf_path_index)
1907 bready = 1;
1908 else
1909 bready = 0;
1910
1911 SET_H2CCMD_MCC_IQK_READY(cmd, bready);
1912 SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
1913 SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
1914
1915 /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
1916 SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
1917 /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
1918 SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
1919 /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
1920 SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
1921 /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
1922 SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
1923
1924
1925 /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
1926 SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
1927 /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
1928 SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
1929 /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
1930 SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
1931 /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
1932 SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
1933
1934 #ifdef CONFIG_MCC_MODE_DEBUG
1935 RTW_INFO("=========================\n");
1936 RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
1937 RTW_INFO("TX_X: 0x%02x\n", TX_X);
1938 RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
1939 RTW_INFO("RX_X: 0x%02x\n", RX_X);
1940 RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
1941 RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
1942 RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
1943 RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
1944 RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
1945 RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
1946 RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
1947 RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
1948 RTW_INFO("=========================\n");
1949 #endif /* CONFIG_MCC_MODE_DEBUG */
1950
1951 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
1952 }
1953 }
1954 }
1955 #endif
1956
1957
rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)1958 static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
1959 {
1960 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1961 struct mcc_adapter_priv *pmccadapriv = NULL;
1962 _adapter *iface = NULL;
1963 u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;
1964 u16 bitmap = 0;
1965
1966 for (i = 0; i < dvobj->iface_nums; i++) {
1967 iface = dvobj->padapters[i];
1968 if (iface == NULL)
1969 continue;
1970
1971 pmccadapriv = &iface->mcc_adapterpriv;
1972 if (pmccadapriv->role == MCC_ROLE_MAX)
1973 continue;
1974
1975 order = pmccadapriv->order;
1976 bitmap = pmccadapriv->mcc_macid_bitmap;
1977
1978 if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
1979 RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
1980 , FUNC_ADPT_ARG(padapter), order);
1981 continue;
1982 }
1983 SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
1984 SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));
1985 }
1986
1987 #ifdef CONFIG_MCC_MODE_DEBUG
1988 RTW_INFO("=========================\n");
1989 RTW_INFO("MACID BITMAP: ");
1990 for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
1991 printk("0x%x ", cmd[i]);
1992 printk("\n");
1993 RTW_INFO("=========================\n");
1994 #endif /* CONFIG_MCC_MODE_DEBUG */
1995 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
1996 }
1997
1998 #ifdef CONFIG_MCC_MODE_V2
get_pri_ch_idx_by_adapter(u8 center_ch,u8 channel,u8 bw,u8 ch_offset40)1999 static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
2000 {
2001 u8 pri_ch_idx = 0, chnl_offset80 = 0;
2002
2003 if (bw == CHANNEL_WIDTH_80) {
2004 if (center_ch > channel)
2005 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
2006 else if (center_ch < channel)
2007 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
2008 else
2009 chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2010 }
2011
2012 if (bw == CHANNEL_WIDTH_80) {
2013 /* primary channel is at lower subband of 80MHz & 40MHz */
2014 if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
2015 pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
2016 /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
2017 else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
2018 pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2019 /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
2020 else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
2021 pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2022 /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
2023 else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
2024 pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
2025 else {
2026 if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
2027 pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
2028 else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
2029 pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
2030 else
2031 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
2032 }
2033 } else if (bw == CHANNEL_WIDTH_40) {
2034 /* primary channel is at upper subband of 40MHz */
2035 if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
2036 pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2037 /* primary channel is at lower subband of 40MHz */
2038 else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
2039 pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2040 else
2041 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
2042 }
2043
2044 return pri_ch_idx;
2045 }
2046
rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter,u8 stop)2047 static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
2048 {
2049 u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
2050 u8 order = 0, totalnum = 0;
2051 u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
2052 u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
2053 u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
2054 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2055 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
2056 struct mcc_adapter_priv *mccadapriv = NULL;
2057 struct mlme_ext_priv *pmlmeext = NULL;
2058 struct mlme_ext_info *pmlmeinfo = NULL;
2059 _adapter *iface = NULL;
2060
2061 RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
2062
2063 for (i = 0; i < MAX_MCC_NUM; i++) {
2064 iface = pmccobjpriv->iface[i];
2065 if (iface == NULL)
2066 continue;
2067
2068 if (stop) {
2069 if (iface != padapter)
2070 continue;
2071 }
2072
2073 mccadapriv = &iface->mcc_adapterpriv;
2074 order = mccadapriv->order;
2075
2076 if (!stop)
2077 totalnum = MAX_MCC_NUM;
2078 else
2079 totalnum = 0xff; /* 0xff means stop */
2080
2081 pmlmeext = &iface->mlmeextpriv;
2082 center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
2083 pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
2084 bw = pmlmeext->cur_bwmode;
2085 duration = mccadapriv->mcc_duration;
2086 role = mccadapriv->role;
2087
2088 incurch = _FALSE;
2089 dis_sw_retry = _TRUE;
2090
2091 /* STA/GC TX NULL data to inform AP/GC for ps mode */
2092 switch (role) {
2093 case MCC_ROLE_GO:
2094 case MCC_ROLE_AP:
2095 distxnull = MCC_DISABLE_TX_NULL;
2096 break;
2097 case MCC_ROLE_GC:
2098 set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
2099 distxnull = MCC_ENABLE_TX_NULL;
2100 break;
2101 case MCC_ROLE_STA:
2102 distxnull = MCC_ENABLE_TX_NULL;
2103 break;
2104 }
2105
2106 null_early_time = mccadapriv->null_early;
2107
2108 c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
2109 tsfx = rtw_hal_get_port(iface);
2110 update_parm = 0;
2111
2112 SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
2113 SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
2114 SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
2115 SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
2116 SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
2117 SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
2118 SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
2119 SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
2120 SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
2121 SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
2122 SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
2123 SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
2124 SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
2125 SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
2126
2127 #ifdef CONFIG_MCC_MODE_DEBUG
2128 RTW_INFO("=========================\n");
2129 RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
2130 RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
2131 RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
2132 RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
2133 RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
2134 RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
2135 RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
2136 RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
2137 RTW_INFO("=========================\n");
2138 #endif /* CONFIG_MCC_MODE_DEBUG */
2139
2140 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
2141 }
2142 }
2143
2144 #else
rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter,u8 stop)2145 static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
2146 {
2147 u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
2148 u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
2149 u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
2150 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2151 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
2152 struct mcc_adapter_priv *mccadapriv = NULL;
2153 struct mlme_ext_priv *pmlmeext = NULL;
2154 struct mlme_ext_info *pmlmeinfo = NULL;
2155 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
2156 _adapter *iface = NULL;
2157
2158 RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
2159
2160 for (i = 0; i < MAX_MCC_NUM; i++) {
2161 iface = pmccobjpriv->iface[i];
2162 if (iface == NULL)
2163 continue;
2164
2165 if (stop) {
2166 if (iface != padapter)
2167 continue;
2168 }
2169
2170 mccadapriv = &iface->mcc_adapterpriv;
2171 order = mccadapriv->order;
2172
2173 if (!stop)
2174 totalnum = MAX_MCC_NUM;
2175 else
2176 totalnum = 0xff; /* 0xff means stop */
2177
2178 pmlmeext = &iface->mlmeextpriv;
2179 chidx = pmlmeext->cur_channel;
2180 bw = pmlmeext->cur_bwmode;
2181 bw40sc = pmlmeext->cur_ch_offset;
2182
2183 /* decide 80 band width offset */
2184 if (bw == CHANNEL_WIDTH_80) {
2185 u8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);
2186
2187 if (center_ch > chidx)
2188 bw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;
2189 else if (center_ch < chidx)
2190 bw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;
2191 else
2192 bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2193 } else
2194 bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2195
2196 duration = mccadapriv->mcc_duration;
2197 role = mccadapriv->role;
2198
2199 incurch = _FALSE;
2200
2201 if (IS_HARDWARE_TYPE_8812(padapter))
2202 rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
2203 else
2204 rfetype = 0;
2205
2206 /* STA/GC TX NULL data to inform AP/GC for ps mode */
2207 switch (role) {
2208 case MCC_ROLE_GO:
2209 case MCC_ROLE_AP:
2210 distxnull = MCC_DISABLE_TX_NULL;
2211 break;
2212 case MCC_ROLE_GC:
2213 case MCC_ROLE_STA:
2214 distxnull = MCC_ENABLE_TX_NULL;
2215 break;
2216 }
2217
2218 c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
2219 chscan = MCC_CHIDX;
2220
2221 SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
2222 SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
2223 SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
2224 SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
2225 SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
2226 SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
2227 SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
2228 SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
2229 SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
2230 SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
2231 SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
2232 SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
2233 SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
2234
2235 #ifdef CONFIG_MCC_MODE_DEBUG
2236 RTW_INFO("=========================\n");
2237 RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
2238 RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
2239 RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
2240 RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
2241 RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
2242 RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
2243 RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
2244 RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
2245 RTW_INFO("=========================\n");
2246 #endif /* CONFIG_MCC_MODE_DEBUG */
2247
2248 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
2249 }
2250 }
2251 #endif
2252
rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter,u8 stop)2253 static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
2254 {
2255 #ifdef CONFIG_MCC_MODE_V2
2256 /* new cmd 0x17 */
2257 rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
2258 #else
2259 /* old cmd 0x18 */
2260 rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
2261 #endif
2262 }
2263
check_mcc_support(PADAPTER adapter)2264 static u8 check_mcc_support(PADAPTER adapter)
2265 {
2266 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
2267 u8 sta_linked_num = DEV_STA_LD_NUM(dvobj);
2268 u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
2269 u8 ap_num = DEV_AP_NUM(dvobj);
2270 u8 ret = _FAIL;
2271
2272 RTW_INFO("[MCC] sta_linked_num=%d, starting_ap_num=%d,ap_num=%d\n",
2273 sta_linked_num, starting_ap_num, ap_num);
2274
2275 /* case for sta + sta case */
2276 if (sta_linked_num == MAX_MCC_NUM) {
2277 ret = _SUCCESS;
2278 goto exit;
2279 }
2280
2281 /* case for starting AP + linked sta */
2282 if ((starting_ap_num + sta_linked_num) == MAX_MCC_NUM) {
2283 ret = _SUCCESS;
2284 goto exit;
2285 }
2286
2287 /* case for started AP + linked sta */
2288 if ((ap_num + sta_linked_num) == MAX_MCC_NUM) {
2289 ret = _SUCCESS;
2290 goto exit;
2291 }
2292
2293 exit:
2294 return ret;
2295 }
2296
rtw_hal_mcc_start_prehdl(PADAPTER padapter)2297 static void rtw_hal_mcc_start_prehdl(PADAPTER padapter)
2298 {
2299 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2300 _adapter *iface = NULL;
2301 struct mcc_adapter_priv *mccadapriv = NULL;
2302 u8 i = 1;
2303
2304 for (i = 0; i < dvobj->iface_nums; i++) {
2305 iface = dvobj->padapters[i];
2306 if (iface == NULL)
2307 continue;
2308
2309 mccadapriv = &iface->mcc_adapterpriv;
2310 mccadapriv->role = MCC_ROLE_MAX;
2311 }
2312
2313 #ifdef CONFIG_RTL8822C
2314 if (IS_HARDWARE_TYPE_8822C(padapter)) {
2315 HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
2316 struct dm_struct *dm = &hal->odmpriv;
2317
2318 odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, hal->bFWReady);
2319 }
2320 #endif
2321 }
2322
rtw_hal_set_mcc_start_setting(PADAPTER padapter,u8 status)2323 static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
2324 {
2325 u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
2326 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2327 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
2328
2329 if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
2330 rtw_warn_on(1);
2331 RTW_INFO("PS mode is not active before start mcc, force exit ps mode\n");
2332 LeaveAllPowerSaveModeDirect(padapter);
2333 }
2334
2335 if (check_mcc_support(padapter) == _FAIL) {
2336 ret = _FAIL;
2337 goto exit;
2338 }
2339
2340 rtw_hal_mcc_start_prehdl(padapter);
2341
2342 /* configure mcc switch channel setting */
2343 rtw_hal_config_mcc_switch_channel_setting(padapter);
2344
2345 if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
2346 ret = _FAIL;
2347 goto exit;
2348 }
2349
2350 /* set mcc status to indicate process mcc start setting */
2351 rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);
2352
2353 /* only download rsvd page for connect */
2354 if (status == MCC_SETCMD_STATUS_START_CONNECT) {
2355 /* download mcc rsvd page */
2356 rtw_hal_set_fw_mcc_rsvd_page(padapter);
2357 rtw_hal_set_mcc_rsvdpage_cmd(padapter);
2358 }
2359
2360 /* configure time setting */
2361 rtw_hal_set_mcc_time_setting_cmd(padapter);
2362
2363 #ifndef CONFIG_MCC_MODE_V2
2364 /* IQK value offload */
2365 rtw_hal_set_mcc_IQK_offload_cmd(padapter);
2366 #endif
2367
2368 /* set mac id to fw */
2369 rtw_hal_set_mcc_macid_cmd(padapter);
2370 #ifdef CONFIG_HW_P0_TSF_SYNC
2371 if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {
2372 /* disable tsf auto sync */
2373 RTW_INFO("[MCC] disable HW TSF sync\n");
2374 rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
2375 } else {
2376 RTW_INFO("[MCC] already disable HW TSF sync\n");
2377 }
2378 #endif
2379 /* set mcc parameter */
2380 rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
2381
2382 exit:
2383 return ret;
2384 }
2385
rtw_hal_set_mcc_stop_setting(PADAPTER padapter,u8 status)2386 static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
2387 {
2388 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2389 struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;
2390 _adapter *iface = NULL;
2391 struct mcc_adapter_priv *mccadapriv = NULL;
2392 u8 i = 0;
2393 /*
2394 * when adapter disconnect, stop mcc mod
2395 * total=0xf means stop mcc mode
2396 */
2397
2398 switch (status) {
2399 default:
2400 /* let fw switch to other interface channel */
2401 for (i = 0; i < MAX_MCC_NUM; i++) {
2402 iface = mccobjpriv->iface[i];
2403 if (iface == NULL)
2404 continue;
2405
2406 mccadapriv = &iface->mcc_adapterpriv;
2407
2408 /* use other interface to set cmd */
2409 if (iface != padapter) {
2410 rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
2411 break;
2412 }
2413 }
2414 break;
2415 }
2416 }
2417
rtw_hal_mcc_status_hdl(PADAPTER padapter,u8 status)2418 static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
2419 {
2420 switch (status) {
2421 case MCC_SETCMD_STATUS_STOP_DISCONNECT:
2422 rtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
2423 break;
2424 case MCC_SETCMD_STATUS_STOP_SCAN_START:
2425 rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);
2426 rtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);
2427 break;
2428
2429 case MCC_SETCMD_STATUS_START_CONNECT:
2430 case MCC_SETCMD_STATUS_START_SCAN_DONE:
2431 rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
2432 break;
2433 default:
2434 RTW_INFO(FUNC_ADPT_FMT" error status(%d)\n", FUNC_ADPT_ARG(padapter), status);
2435 break;
2436 }
2437 }
2438
rtw_hal_mcc_stop_posthdl(PADAPTER padapter)2439 static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
2440 {
2441 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2442 struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
2443 struct mcc_adapter_priv *mccadapriv = NULL;
2444 _adapter *iface = NULL;
2445 PHAL_DATA_TYPE hal;
2446 u8 i = 0;
2447 u8 enable_rx_bar = _FALSE;
2448
2449 hal = GET_HAL_DATA(padapter);
2450
2451 for (i = 0; i < MAX_MCC_NUM; i++) {
2452 iface = mccobjpriv->iface[i];
2453 if (iface == NULL)
2454 continue;
2455
2456 /* release network queue */
2457 rtw_netif_wake_queue(iface->pnetdev);
2458 mccadapriv = &iface->mcc_adapterpriv;
2459 mccadapriv->mcc_tx_bytes_from_kernel = 0;
2460 mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
2461 mccadapriv->mcc_tx_bytes_to_port = 0;
2462
2463 if (mccadapriv->role == MCC_ROLE_GO)
2464 rtw_hal_mcc_remove_go_p2p_ie(iface);
2465
2466 #ifdef CONFIG_TDLS
2467 if (MLME_IS_STA(iface)) {
2468 if (mccadapriv->backup_tdls_en) {
2469 rtw_enable_tdls_func(iface);
2470 RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
2471 mccadapriv->backup_tdls_en = _FALSE;
2472 }
2473 }
2474 #endif /* CONFIG_TDLS */
2475
2476 mccadapriv->role = MCC_ROLE_MAX;
2477 mccobjpriv->iface[i] = NULL;
2478 }
2479
2480 /* force switch channel */
2481 hal->current_channel = 0;
2482 hal->current_channel_bw = CHANNEL_WIDTH_MAX;
2483 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
2484 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_STOP, NULL);
2485 #endif
2486
2487 #ifdef CONFIG_RTL8822C
2488 if (IS_HARDWARE_TYPE_8822C(padapter)) {
2489 HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
2490 struct dm_struct *dm = &hal->odmpriv;
2491
2492 odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, _FALSE);
2493 }
2494 #endif
2495 }
2496
rtw_hal_mcc_start_posthdl(PADAPTER padapter)2497 static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
2498 {
2499 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2500 struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
2501 struct mcc_adapter_priv *mccadapriv = NULL;
2502 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
2503 _adapter *iface = NULL;
2504 u8 i = 0, order = 0;
2505 u8 enable_rx_bar = _TRUE;
2506
2507 for (i = 0; i < MAX_MCC_NUM; i++) {
2508 iface = mccobjpriv->iface[i];
2509 if (iface == NULL)
2510 continue;
2511
2512 mccadapriv = &iface->mcc_adapterpriv;
2513 if (mccadapriv->role == MCC_ROLE_MAX)
2514 continue;
2515
2516 mccadapriv->mcc_tx_bytes_from_kernel = 0;
2517 mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
2518 mccadapriv->mcc_tx_bytes_to_port = 0;
2519
2520 #ifdef CONFIG_TDLS
2521 if (MLME_IS_STA(iface)) {
2522 if (rtw_is_tdls_enabled(iface)) {
2523 mccadapriv->backup_tdls_en = _TRUE;
2524 rtw_disable_tdls_func(iface, _TRUE);
2525 RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
2526 }
2527 }
2528 #endif /* CONFIG_TDLS */
2529 }
2530 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
2531 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_START, NULL);
2532 #endif
2533 }
2534
2535 /*
2536 * rtw_hal_set_mcc_setting - set mcc setting
2537 * @padapter: currnet padapter to stop/start MCC
2538 * @stop: stop mcc or not
2539 * @return val: 1 for SUCCESS, 0 for fail
2540 */
rtw_hal_set_mcc_setting(PADAPTER padapter,u8 status)2541 static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
2542 {
2543 u8 ret = _FAIL;
2544 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
2545 u8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;
2546 systime start_time = rtw_get_current_time();
2547
2548 RTW_INFO("===> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
2549
2550 rtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);
2551 pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
2552
2553 if (stop == _FALSE) {
2554 /* handle mcc start */
2555 if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
2556 goto exit;
2557
2558 /* wait for C2H */
2559 if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
2560 RTW_INFO(FUNC_ADPT_FMT": wait for mcc start C2H time out\n", FUNC_ADPT_ARG(padapter));
2561 else
2562 ret = _SUCCESS;
2563
2564 if (ret == _SUCCESS) {
2565 RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
2566 rtw_hal_mcc_status_hdl(padapter, status);
2567 rtw_hal_mcc_start_posthdl(padapter);
2568 }
2569 } else {
2570
2571 /* set mcc status to indicate process mcc start setting */
2572 rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);
2573
2574 /* handle mcc stop */
2575 rtw_hal_set_mcc_stop_setting(padapter, status);
2576
2577 /* wait for C2H */
2578 if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
2579 RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
2580 else {
2581 ret = _SUCCESS;
2582 rtw_hal_mcc_status_hdl(padapter, status);
2583 rtw_hal_mcc_stop_posthdl(padapter);
2584 }
2585 }
2586
2587 exit:
2588 /* clear mcc status */
2589 rtw_hal_clear_mcc_status(padapter
2590 , MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
2591
2592 RTW_INFO(FUNC_ADPT_FMT" in %dms <===\n"
2593 , FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));
2594 return ret;
2595 }
2596
2597 /**
2598 * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case
2599 * @cur_iface: fw stay channel setting of this iface
2600 * @next_iface: fw will swich channel setting of this iface
2601 */
rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface,PADAPTER next_iface)2602 static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)
2603 {
2604 u8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;
2605 u8 next_bw = next_iface->mlmeextpriv.cur_bwmode;
2606
2607 /* for both interface are VHT80, doesn't limit_traffic according to iperf results */
2608 if (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {
2609 cur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
2610 next_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
2611 }
2612 }
2613
2614
2615 /**
2616 * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl
2617 */
rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)2618 static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
2619 {
2620 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
2621 struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
2622 struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
2623 _adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
2624 struct registry_priv *preg = &padapter->registrypriv;
2625 u8 cur_op_ch = pdvobjpriv->oper_channel;
2626 u8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;
2627 static u8 cnt = 1;
2628 u32 single_tx_cri = preg->rtw_mcc_single_tx_cri;
2629
2630 for (i = 0; i < iface_num; i++) {
2631 iface = pdvobjpriv->padapters[i];
2632 if (iface == NULL)
2633 continue;
2634
2635 if (cur_op_ch == iface->mlmeextpriv.cur_channel) {
2636 cur_iface = iface;
2637 cur_mccadapriv = &cur_iface->mcc_adapterpriv;
2638 cur_order = cur_mccadapriv->order;
2639 next_order = (cur_order + 1) % iface_num;
2640 next_iface = pmccobjpriv->iface[next_order];
2641 next_mccadapriv = &next_iface->mcc_adapterpriv;
2642 break;
2643 }
2644 }
2645
2646 if (cur_iface == NULL || next_iface == NULL) {
2647 RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
2648 rtw_warn_on(1);
2649 return;
2650 }
2651
2652 /* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
2653 if (cnt == 2) {
2654 cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
2655 - cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
2656 cur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;
2657
2658 next_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel
2659 - next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
2660 next_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;
2661
2662 cnt = 1;
2663 } else
2664 cnt = 2;
2665
2666 /* check single TX or cuncurrnet TX */
2667 if (next_mccadapriv->mcc_tp < single_tx_cri) {
2668 /* single TX, does not stop */
2669 cur_mccadapriv->mcc_tx_stop = _FALSE;
2670 cur_mccadapriv->mcc_tp_limit = _FALSE;
2671 } else {
2672 /* concurrent TX, stop */
2673 cur_mccadapriv->mcc_tx_stop = _TRUE;
2674 cur_mccadapriv->mcc_tp_limit = _TRUE;
2675 }
2676
2677 if (cur_mccadapriv->mcc_tp < single_tx_cri) {
2678 next_mccadapriv->mcc_tx_stop = _FALSE;
2679 next_mccadapriv->mcc_tp_limit = _FALSE;
2680 } else {
2681 next_mccadapriv->mcc_tx_stop = _FALSE;
2682 next_mccadapriv->mcc_tp_limit = _TRUE;
2683 next_mccadapriv->mcc_tx_bytes_to_port = 0;
2684 }
2685
2686 /* stop current iface kernel queue or not */
2687 if (cur_mccadapriv->mcc_tx_stop)
2688 rtw_netif_stop_queue(cur_iface->pnetdev);
2689 else
2690 rtw_netif_wake_queue(cur_iface->pnetdev);
2691
2692 /* stop next iface kernel queue or not */
2693 if (next_mccadapriv->mcc_tx_stop)
2694 rtw_netif_stop_queue(next_iface->pnetdev);
2695 else
2696 rtw_netif_wake_queue(next_iface->pnetdev);
2697
2698 /* start xmit tasklet */
2699 rtw_os_xmit_schedule(next_iface);
2700
2701 rtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);
2702
2703 if (0) {
2704 RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
2705 cur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);
2706 dump_os_queue(0, cur_iface);
2707 RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
2708 next_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);
2709 dump_os_queue(0, next_iface);
2710 }
2711 }
2712
rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter,u8 buflen,u8 * tmpBuf)2713 static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
2714 {
2715 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
2716 struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
2717 struct mcc_adapter_priv *pmccadapriv = NULL;
2718 PADAPTER iface = NULL;
2719 u8 i = 0;
2720 u8 policy_idx = pmccobjpriv->policy_index;
2721 u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
2722 u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
2723
2724 for (i = 0; i < pdvobjpriv->iface_nums; i++) {
2725 iface = pdvobjpriv->padapters[i];
2726 if (iface == NULL)
2727 continue;
2728
2729 pmccadapriv = &iface->mcc_adapterpriv;
2730 if (pmccadapriv->role == MCC_ROLE_MAX)
2731 continue;
2732
2733 /* GO & channel match */
2734 if (pmccadapriv->role == MCC_ROLE_GO) {
2735 /* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
2736 pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
2737
2738 if (0) {
2739 RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
2740 RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
2741 RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
2742 , FUNC_ADPT_ARG(iface)
2743 , tmpBuf[2]
2744 , tmpBuf[3]
2745 , tmpBuf[4]
2746 , tmpBuf[5]
2747 ,pmccadapriv->noa_start_time);
2748 }
2749
2750 rtw_hal_mcc_update_go_p2p_ie(iface);
2751
2752 break;
2753 }
2754 }
2755
2756 }
2757
mcc_get_reg_hdl(PADAPTER adapter,const u8 * val)2758 static u8 mcc_get_reg_hdl(PADAPTER adapter, const u8 *val)
2759 {
2760 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
2761 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
2762 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
2763 _adapter *cur_iface = NULL;
2764 u8 ret = _SUCCESS;
2765 u8 cur_order = 0;
2766 #ifdef CONFIG_RTL8822C
2767 u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0x1d70};
2768 #else
2769 u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0xc50,0xe50};
2770 #endif
2771 u16 dbg_rf_reg[DBG_MCC_RF_REG_NUM] = {0x18};
2772 u8 i;
2773 u32 reg_val;
2774 u8 path = 0, path_nums = 0;
2775
2776 if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
2777 ret = _FAIL;
2778 goto exit;
2779 }
2780
2781 if (!val)
2782 cur_order = 0xff;
2783 else
2784 cur_order = *val;
2785
2786 if (cur_order >= MAX_MCC_NUM && cur_order != 0xff) {
2787 RTW_ERR("%s: cur_order=%d\n", __func__, cur_order);
2788 ret = _FAIL;
2789 goto exit;
2790 }
2791
2792 path_nums = hal_spec->rf_reg_path_num;
2793 if (cur_order == 0xff)
2794 cur_iface = adapter;
2795 else
2796 cur_iface = mccobjpriv->iface[cur_order];
2797
2798 if (!cur_iface) {
2799 RTW_ERR("%s: cur_iface = NULL, cur_order=%d\n", __func__, cur_order);
2800 ret = _FAIL;
2801 goto exit;
2802 }
2803
2804 _enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
2805 if (!RTW_CANNOT_IO(adapter)) {
2806 /* RTW_INFO("=================================\n");
2807 RTW_INFO(ADPT_FMT": cur_order:%d\n", ADPT_ARG(cur_iface), cur_order); */
2808
2809 for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
2810 reg_val = rtw_read32(adapter, dbg_reg[i]);
2811 mccobjpriv->dbg_reg[i] = dbg_reg[i];
2812 mccobjpriv->dbg_reg_val[i] = reg_val;
2813 /* RTW_PRINT("REG_%X:0x%08x\n", dbg_reg[i], reg_val); */
2814 }
2815 for (i = 0; i < ARRAY_SIZE(dbg_rf_reg); i++) {
2816 for (path = 0; path < path_nums; path++) {
2817 reg_val = rtw_hal_read_rfreg(adapter, path, dbg_rf_reg[i], 0xffffffff);
2818 /* RTW_PRINT("RF_PATH_%d_REG_%X:0x%08x\n",
2819 path, dbg_rf_reg[i], reg_val); */
2820 mccobjpriv->dbg_rf_reg[i] = dbg_rf_reg[i];
2821 mccobjpriv->dbg_rf_reg_val[i][path] = reg_val;
2822 }
2823 }
2824 }
2825 _exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
2826
2827 exit:
2828 return ret;
2829 }
2830
mcc_get_reg_cmd(_adapter * adapter,u8 cur_order)2831 static u8 mcc_get_reg_cmd(_adapter *adapter, u8 cur_order)
2832 {
2833 struct cmd_obj *cmdobj;
2834 struct drvextra_cmd_parm *pdrvextra_cmd_parm;
2835 struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
2836 u8 *mcc_cur_order = NULL;
2837 u8 res = _SUCCESS;
2838
2839
2840 cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
2841 if (cmdobj == NULL) {
2842 res = _FAIL;
2843 goto exit;
2844 }
2845
2846 pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
2847 if (pdrvextra_cmd_parm == NULL) {
2848 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
2849 res = _FAIL;
2850 goto exit;
2851 }
2852
2853 mcc_cur_order = rtw_zmalloc(sizeof(u8));
2854 if (mcc_cur_order == NULL) {
2855 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
2856 rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
2857 res = _FAIL;
2858 goto exit;
2859 }
2860
2861 pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
2862 pdrvextra_cmd_parm->type = MCC_GET_DBG_REG_WK_CID;
2863 pdrvextra_cmd_parm->size = 1;
2864 pdrvextra_cmd_parm->pbuf = mcc_cur_order;
2865
2866 _rtw_memcpy(mcc_cur_order, &cur_order, 1);
2867
2868 init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
2869 res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
2870
2871 exit:
2872 return res;
2873 }
2874
rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter,u8 buflen,u8 * tmpBuf)2875 static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
2876 {
2877 struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);
2878 struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
2879 struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
2880 struct mcc_adapter_priv *mccadapriv = NULL;
2881 _adapter *iface = NULL;
2882 u8 order = 0;
2883
2884 order = mccobjpriv->mcc_tsf_req_sctx_order;
2885 iface = mccobjpriv->iface[order];
2886 mccadapriv = &iface->mcc_adapterpriv;
2887 mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
2888
2889
2890 if (0)
2891 RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);
2892
2893 if (mccadapriv->order == (MAX_MCC_NUM - 1))
2894 rtw_sctx_done(&mcc_tsf_req_sctx);
2895 else
2896 mccobjpriv->mcc_tsf_req_sctx_order ++;
2897
2898 }
2899
2900 /**
2901 * rtw_hal_mcc_c2h_handler - mcc c2h handler
2902 */
rtw_hal_mcc_c2h_handler(PADAPTER padapter,u8 buflen,u8 * tmpBuf)2903 void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
2904 {
2905 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
2906 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
2907 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
2908 struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
2909 _adapter *cur_adapter = NULL;
2910 u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
2911 _irqL irqL;
2912
2913 /* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
2914 /* To avoid reg is set, but driver recive c2h to set wrong oper_channel */
2915 if (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {
2916 RTW_INFO(FUNC_ADPT_FMT" MCC alread stops return\n", FUNC_ADPT_ARG(padapter));
2917 return;
2918 }
2919
2920 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2921 pmccobjpriv->mcc_c2h_status = tmpBuf[0];
2922 pmccobjpriv->current_order = tmpBuf[1];
2923 cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
2924 cur_ch = cur_adapter->mlmeextpriv.cur_channel;
2925 cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
2926 cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
2927 rtw_set_oper_ch(cur_adapter, cur_ch);
2928 rtw_set_oper_bw(cur_adapter, cur_bw);
2929 rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
2930 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2931
2932 if (0)
2933 RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
2934
2935 switch (pmccobjpriv->mcc_c2h_status) {
2936 case MCC_RPT_SUCCESS:
2937 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2938 pmccobjpriv->cur_mcc_success_cnt++;
2939 rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
2940 mcc_get_reg_cmd(padapter, pmccobjpriv->current_order);
2941 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2942 break;
2943 case MCC_RPT_TXNULL_FAIL:
2944 RTW_INFO("[MCC] TXNULL FAIL\n");
2945 break;
2946 case MCC_RPT_STOPMCC:
2947 RTW_INFO("[MCC] MCC stop\n");
2948 pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
2949 rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
2950 rtw_sctx_done(&mcc_sctx);
2951 break;
2952 case MCC_RPT_READY:
2953 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2954 /* initialize counter & time */
2955 pmccobjpriv->mcc_launch_time = rtw_get_current_time();
2956 pmccobjpriv->mcc_c2h_status = MCC_RPT_READY;
2957 pmccobjpriv->cur_mcc_success_cnt = 0;
2958 pmccobjpriv->prev_mcc_success_cnt = 0;
2959 pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
2960 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2961
2962 RTW_INFO("[MCC] MCC ready\n");
2963 rtw_sctx_done(&mcc_sctx);
2964 break;
2965 case MCC_RPT_SWICH_CHANNEL_NOTIFY:
2966 rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
2967 break;
2968 case MCC_RPT_UPDATE_NOA_START_TIME:
2969 rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
2970 break;
2971 case MCC_RPT_TSF:
2972 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2973 rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
2974 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
2975 break;
2976 default:
2977 /* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
2978 break;
2979 }
2980 }
2981
rtw_hal_mcc_update_parameter(PADAPTER padapter,u8 force_update)2982 void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
2983 {
2984 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
2985 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
2986 u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
2987 u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
2988 u8 ap_num = DEV_AP_NUM(dvobj);
2989
2990 if (ap_num == 0) {
2991 u8 need_update = _FALSE;
2992 u8 start_time_offset = 0, interval = 0, duration = 0;
2993
2994 need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
2995
2996 if (need_update == _FALSE)
2997 return;
2998
2999 start_time_offset = mccobjpriv->start_time;
3000 interval = mccobjpriv->interval;
3001 duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
3002
3003 SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
3004 SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
3005 SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
3006 SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
3007 SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
3008 } else {
3009 PADAPTER order0_iface = NULL;
3010 PADAPTER order1_iface = NULL;
3011 u8 policy_idx = mccobjpriv->policy_index;
3012 u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
3013 u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
3014 u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
3015 u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
3016 u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
3017 u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
3018 u8 order0_duration = 0;
3019 u8 i = 0;
3020 enum _hw_port tsf_bsae_port = MAX_HW_PORT;
3021 enum _hw_port tsf_sync_port = MAX_HW_PORT;
3022
3023 RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
3024
3025 order0_iface = mccobjpriv->iface[0];
3026 order1_iface = mccobjpriv->iface[1];
3027
3028 /* GO/AP is order 0, GC/STA is order 1 */
3029 order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;
3030 order0_iface->mcc_adapterpriv.mcc_duration = duration;
3031
3032 tsf_bsae_port = rtw_hal_get_port(order1_iface);
3033 tsf_sync_port = rtw_hal_get_port(order0_iface);
3034
3035 /* update IE */
3036 for (i = 0; i < dvobj->iface_nums; i++) {
3037 PADAPTER iface = NULL;
3038 struct mcc_adapter_priv *mccadapriv = NULL;
3039
3040 iface = dvobj->padapters[i];
3041 if (iface == NULL)
3042 continue;
3043
3044 mccadapriv = &iface->mcc_adapterpriv;
3045 if (mccadapriv->role == MCC_ROLE_MAX)
3046 continue;
3047
3048 if (mccadapriv->role == MCC_ROLE_GO)
3049 rtw_hal_mcc_update_go_p2p_ie(iface);
3050 }
3051
3052 /* update H2C cmd */
3053 /* FW set enable */
3054 SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
3055 /* TSF Sync offset */
3056 SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
3057 /* start time offset */
3058 SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
3059 /* interval */
3060 SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
3061 /* Early time to inform driver by C2H before switch channel */
3062 SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
3063 /* Port0 sync from Port1, not support multi-port */
3064 SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
3065 SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
3066 SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
3067 SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
3068 }
3069
3070 rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
3071 }
3072
3073 /**
3074 * rtw_hal_mcc_sw_status_check - check mcc swich channel status
3075 * @padapter: primary adapter
3076 */
rtw_hal_mcc_sw_status_check(PADAPTER padapter)3077 void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
3078 {
3079 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3080 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
3081 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
3082 struct mcc_adapter_priv *mccadapriv = NULL;
3083 _adapter *iface = NULL;
3084 u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
3085 u8 policy_idx = pmccobjpriv->policy_index;
3086 u8 noa_enable = _FALSE;
3087 u8 i = 0;
3088 _irqL irqL;
3089 u8 ap_num = DEV_AP_NUM(dvobj);
3090
3091 /* #define MCC_RESTART 1 */
3092
3093 if (!MCC_EN(padapter))
3094 return;
3095
3096 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3097
3098 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3099
3100 /* check noa enable or not */
3101 for (i = 0; i < dvobj->iface_nums; i++) {
3102 iface = dvobj->padapters[i];
3103 if (iface == NULL)
3104 continue;
3105
3106 mccadapriv = &iface->mcc_adapterpriv;
3107 if (mccadapriv->role == MCC_ROLE_MAX)
3108 continue;
3109
3110 if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
3111 noa_enable = _TRUE;
3112 break;
3113 }
3114 }
3115
3116 if (!noa_enable && ap_num == 0)
3117 rtw_hal_mcc_update_parameter(padapter, _FALSE);
3118
3119 threshold = pmccobjpriv->mcc_stop_threshold;
3120
3121 if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
3122 rtw_warn_on(1);
3123 RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
3124 LeaveAllPowerSaveModeDirect(padapter);
3125 }
3126
3127 if (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {
3128 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
3129
3130 cur_cnt = pmccobjpriv->cur_mcc_success_cnt;
3131 prev_cnt = pmccobjpriv->prev_mcc_success_cnt;
3132 if (cur_cnt < prev_cnt)
3133 diff_cnt = (cur_cnt + 255) - prev_cnt;
3134 else
3135 diff_cnt = cur_cnt - prev_cnt;
3136
3137 if (diff_cnt < threshold) {
3138 pmccobjpriv->mcc_tolerance_time--;
3139 RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
3140 __func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
3141 } else
3142 pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
3143
3144 pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
3145
3146 if (pmccobjpriv->mcc_tolerance_time != 0)
3147 check_ret = _SUCCESS;
3148
3149 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
3150
3151 if (check_ret != _SUCCESS) {
3152 RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
3153 /* restart MCC */
3154 #ifdef MCC_RESTART
3155 rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
3156 rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
3157 #endif /* MCC_RESTART */
3158 }
3159 } else {
3160 _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
3161 pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
3162 _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
3163 }
3164
3165 }
3166 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3167 }
3168
3169 /**
3170 * rtw_hal_mcc_change_scan_flag - change scan flag under mcc
3171 *
3172 * MCC mode under sitesurvey goto AP channel to tx bcn & data
3173 * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)
3174 *
3175 * @padapter: the adapter to be change scan flag
3176 * @ch: pointer to rerurn ch
3177 * @bw: pointer to rerurn bw
3178 * @offset: pointer to rerurn offset
3179 */
rtw_hal_mcc_change_scan_flag(PADAPTER padapter,u8 * ch,u8 * bw,u8 * offset)3180 u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
3181 {
3182 u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;
3183 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3184 struct mcc_adapter_priv *mccadapriv = NULL;
3185 struct mlme_ext_priv *mlmeext = NULL;
3186 _adapter *iface = NULL;
3187
3188 if (!MCC_EN(padapter))
3189 goto exit;
3190
3191 if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
3192 goto exit;
3193
3194 /* disable PS_ANNC & TX_RESUME for all interface */
3195 /* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */
3196 mlmeext = &padapter->mlmeextpriv;
3197
3198 flags = mlmeext_scan_backop_flags(mlmeext);
3199 if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))
3200 flags &= ~SS_BACKOP_PS_ANNC;
3201
3202 if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))
3203 flags &= ~SS_BACKOP_TX_RESUME;
3204
3205 mlmeext_assign_scan_backop_flags(mlmeext, flags);
3206
3207 for (i = 0; i < dvobj->iface_nums; i++) {
3208 iface = dvobj->padapters[i];
3209 if (!iface)
3210 continue;
3211
3212 mlmeext = &iface->mlmeextpriv;
3213
3214 if (MLME_IS_GO(iface) || MLME_IS_AP(iface))
3215 back_op = _TRUE;
3216 else if (MLME_IS_GC(iface) && (iface != padapter))
3217 /* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */
3218 back_op = _TRUE;
3219 else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))
3220 /* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect */
3221 back_op = _TRUE;
3222 else {
3223 /* bypass non-linked/non-linking interface/scan interface */
3224 continue;
3225 }
3226
3227 if (back_op) {
3228 *ch = mlmeext->cur_channel;
3229 *bw = mlmeext->cur_bwmode;
3230 *offset = mlmeext->cur_ch_offset;
3231 need_ch_setting_union = _FALSE;
3232 }
3233 }
3234 exit:
3235 return need_ch_setting_union;
3236 }
3237
3238 /**
3239 * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not
3240 * @padapter: the adapter to be record tx bytes
3241 * @len: data len
3242 */
rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter,u32 len)3243 inline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)
3244 {
3245 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
3246
3247 if (MCC_EN(padapter)) {
3248 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3249 pmccadapriv->mcc_tx_bytes_from_kernel += len;
3250 if (0)
3251 RTW_INFO("%s(order:%d): mcc tx bytes from kernel:%lld\n"
3252 , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);
3253 }
3254 }
3255 }
3256
3257 /**
3258 * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl
3259 * @padapter: the adapter to be record tx bytes
3260 * @len: data len
3261 */
rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter,u32 len)3262 inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
3263 {
3264 if (MCC_EN(padapter)) {
3265 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3266 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
3267
3268 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3269 pmccadapriv->mcc_tx_bytes_to_port += len;
3270 if (0)
3271 RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
3272 , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
3273 , pmccadapriv->mcc_target_tx_bytes_to_port);
3274 }
3275 }
3276 }
3277
3278 /**
3279 * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not
3280 * @padapter: the adapter to be stopped
3281 */
rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)3282 inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
3283 {
3284 if (MCC_EN(padapter)) {
3285 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3286 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
3287
3288 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3289 if (pmccadapriv->mcc_tp_limit) {
3290 if (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {
3291 pmccadapriv->mcc_tx_stop = _TRUE;
3292 rtw_netif_stop_queue(padapter->pnetdev);
3293 return _TRUE;
3294 }
3295 }
3296 }
3297 }
3298
3299 return _FALSE;
3300 }
3301
rtw_hal_mcc_assign_scan_flag(PADAPTER padapter,u8 scan_done)3302 static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
3303 {
3304 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3305 struct mcc_adapter_priv *mccadapriv = NULL;
3306 _adapter *iface = NULL;
3307 struct mlme_ext_priv *pmlmeext = NULL;
3308 u8 i = 0, flags;
3309
3310 if (!MCC_EN(padapter))
3311 return;
3312
3313 for (i = 0; i < dvobj->iface_nums; i++) {
3314 iface = dvobj->padapters[i];
3315 if (iface == NULL)
3316 continue;
3317
3318 mccadapriv = &iface->mcc_adapterpriv;
3319 if (mccadapriv->role == MCC_ROLE_MAX)
3320 continue;
3321
3322 pmlmeext = &iface->mlmeextpriv;
3323 if (is_client_associated_to_ap(iface)) {
3324 flags = mlmeext_scan_backop_flags_sta(pmlmeext);
3325 if (scan_done) {
3326 if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
3327 flags &= ~SS_BACKOP_EN;
3328 mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
3329 }
3330 } else {
3331 if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
3332 flags |= SS_BACKOP_EN;
3333 mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
3334 }
3335 }
3336
3337 }
3338 }
3339 }
3340
3341 /**
3342 * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
3343 * @padapter: the adapter to be setted
3344 * @ch_setting_changed: softap channel setting to be changed or not
3345 */
rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)3346 u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
3347 {
3348 u8 ret = _FAIL;
3349
3350 if (MCC_EN(padapter)) {
3351 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3352
3353 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3354 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
3355 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3356 ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_SCAN_START);
3357 rtw_hal_mcc_assign_scan_flag(padapter, 0);
3358 }
3359 }
3360 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3361 }
3362
3363 return ret;
3364 }
3365
3366 /**
3367 * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete
3368 * @padapter: the adapter to be setted
3369 * @ch_setting_changed: softap channel setting to be changed or not
3370 */
rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)3371 u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
3372 {
3373 u8 ret = _FAIL;
3374
3375 if (MCC_EN(padapter)) {
3376 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3377
3378 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3379
3380 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
3381 rtw_hal_mcc_assign_scan_flag(padapter, 1);
3382 ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE);
3383 }
3384 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3385 }
3386
3387 return ret;
3388 }
3389
3390
3391 /**
3392 * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start
3393 * @padapter: the adapter to be setted
3394 * @chbw_grouped: channel bw offset can not be allowed or not
3395 */
rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter,u8 chbw_allow)3396 u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
3397 {
3398 u8 ret = _FAIL;
3399
3400 if (MCC_EN(padapter)) {
3401 /* channel bw offset can not be allowed, start MCC */
3402 if (chbw_allow == _FALSE) {
3403 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3404
3405 rtw_hal_mcc_restore_iqk_val(padapter);
3406 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3407 ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
3408 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3409 }
3410 }
3411
3412 return ret;
3413 }
3414
3415 /**
3416 * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)
3417 * @padapter: the adapter to be setted
3418 */
rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)3419 u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)
3420 {
3421 u8 ret = _FAIL;
3422
3423 if (MCC_EN(padapter)) {
3424 struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
3425
3426 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3427 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
3428 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
3429 ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
3430 }
3431 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3432 }
3433
3434 return ret;
3435 }
3436
3437 /**
3438 * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done
3439 * @padapter: the adapter to be checked
3440 */
rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)3441 u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
3442 {
3443 u8 ret = _FAIL;
3444
3445 if (MCC_EN(padapter)) {
3446 struct mi_state mstate;
3447
3448 rtw_mi_status_no_self(padapter, &mstate);
3449
3450 if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
3451 bool chbw_allow = _TRUE;
3452 u8 u_ch, u_offset, u_bw;
3453 struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
3454 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3455
3456 if (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {
3457 dump_adapters_status(RTW_DBGDUMP , dvobj);
3458 rtw_warn_on(1);
3459 }
3460
3461 RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
3462 , FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
3463
3464 /* chbw_allow? */
3465 chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
3466 , cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
3467 , u_ch, u_bw, u_offset);
3468
3469 RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
3470 , FUNC_ADPT_ARG(padapter), chbw_allow);
3471
3472 /* if chbw_allow = false, start MCC setting */
3473 if (chbw_allow == _FALSE) {
3474 struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
3475
3476 rtw_hal_mcc_restore_iqk_val(padapter);
3477 _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3478 ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
3479 _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
3480 }
3481 }
3482 }
3483
3484 return ret;
3485 }
3486
3487 /**
3488 * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join
3489 * @padapter: the adapter to be checked
3490 * @ch: pointer to rerurn ch
3491 * @bw: pointer to rerurn bw
3492 * @offset: pointer to rerurn offset
3493 * @chbw_allow: allow to use adapter's channel setting
3494 */
rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter,u8 * ch,u8 * bw,u8 * offset,u8 chbw_allow)3495 u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)
3496 {
3497 u8 ret = _FAIL;
3498
3499 /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */
3500 if (MCC_EN(padapter)) {
3501 /* restore union channel related setting to current channel related setting */
3502 if (chbw_allow == _FALSE) {
3503 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
3504
3505 /* issue null data to other interface connected to AP */
3506 rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
3507
3508 *ch = pmlmeext->cur_channel;
3509 *bw = pmlmeext->cur_bwmode;
3510 *offset = pmlmeext->cur_ch_offset;
3511
3512 RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
3513 , FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
3514 , *ch, *bw, *offset);
3515 ret = _SUCCESS;
3516 }
3517 }
3518
3519 return ret;
3520 }
3521
rtw_hal_mcc_dump_noa_content(void * sel,PADAPTER padapter)3522 static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
3523 {
3524 struct mcc_adapter_priv *pmccadapriv = NULL;
3525 u8 *pos = NULL;
3526 pmccadapriv = &padapter->mcc_adapterpriv;
3527 /* last position for NoA attribute */
3528 pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
3529
3530
3531 RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
3532 RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
3533 RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
3534 RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
3535 RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
3536 RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
3537 }
3538
mcc_dump_dbg_reg(void * sel,_adapter * adapter)3539 static void mcc_dump_dbg_reg(void *sel, _adapter *adapter)
3540 {
3541 struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
3542 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3543 u8 i,j;
3544 _irqL irqL;
3545
3546 _enter_critical_bh(&mccobjpriv->mcc_lock, &irqL);
3547 RTW_PRINT_SEL(sel, "current order=%d\n", mccobjpriv->current_order);
3548 _exit_critical_bh(&mccobjpriv->mcc_lock, &irqL);
3549
3550 _enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
3551 for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_reg); i++)
3552 RTW_PRINT_SEL(sel, "REG_0x%X:0x%08x\n", mccobjpriv->dbg_reg[i], mccobjpriv->dbg_reg_val[i]);
3553
3554 for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_rf_reg); i++) {
3555 for (j = 0; j < hal_spec->rf_reg_path_num; j++)
3556 RTW_PRINT_SEL(sel, "RF_PATH_%d_REG_0x%X:0x%08x\n",
3557 j, mccobjpriv->dbg_rf_reg[i], mccobjpriv->dbg_rf_reg_val[i][j]);
3558 }
3559 _exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
3560 }
3561
3562
rtw_hal_dump_mcc_info(void * sel,struct dvobj_priv * dvobj)3563 void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
3564 {
3565 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
3566 struct mcc_adapter_priv *mccadapriv = NULL;
3567 _adapter *iface = NULL, *pri_adapter = NULL;
3568 struct registry_priv *regpriv = NULL;
3569 HAL_DATA_TYPE *hal = NULL;
3570 u8 i = 0, j = 0;
3571 u64 tsf[MAX_MCC_NUM] = {0};
3572
3573 /* regpriv is common for all adapter */
3574 pri_adapter = dvobj_get_primary_adapter(dvobj);
3575 hal = GET_HAL_DATA(pri_adapter);
3576
3577 RTW_PRINT_SEL(sel, "**********************************************\n");
3578 RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(pri_adapter));
3579 RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
3580 ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);
3581 RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable");
3582 RTW_PRINT_SEL(sel, "phydm offload:%s\n", mccobjpriv->mcc_phydm_offload ? "enable":"disable");
3583
3584 if (rtw_hal_check_mcc_status(pri_adapter, MCC_STATUS_DOING_MCC)) {
3585 rtw_hal_mcc_rqt_tsf(pri_adapter, tsf);
3586
3587 for (i = 0; i < MAX_MCC_NUM; i++) {
3588 iface = mccobjpriv->iface[i];
3589 if (!iface)
3590 continue;
3591
3592 regpriv = &iface->registrypriv;
3593 mccadapriv = &iface->mcc_adapterpriv;
3594
3595 if (mccadapriv) {
3596 u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
3597
3598 RTW_PRINT_SEL(sel, "adapter mcc info:\n");
3599 RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
3600 RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order);
3601 RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration);
3602 RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port);
3603 RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp);
3604 RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid);
3605 RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap);
3606 RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
3607 RTW_PRINT_SEL(sel, "registry data:\n");
3608 RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
3609 RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
3610 RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
3611 RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_sta_bw20_target_tx_tp);
3612 RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
3613 RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
3614 RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
3615 RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]);
3616 if (MLME_IS_GO(iface))
3617 rtw_hal_mcc_dump_noa_content(sel, iface);
3618 RTW_PRINT_SEL(sel, "**********************************************\n");
3619 }
3620 }
3621
3622 mcc_dump_dbg_reg(sel, pri_adapter);
3623 }
3624
3625 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
3626 RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
3627 rtw_hal_mcc_cfg_phydm(pri_adapter, MCC_CFG_PHYDM_DUMP, sel);
3628 RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
3629 #endif
3630
3631 RTW_PRINT_SEL(sel, "------------------------------------------\n");
3632 RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index);
3633 RTW_PRINT_SEL(sel, "------------------------------------------\n");
3634 RTW_PRINT_SEL(sel, "define data:\n");
3635 RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
3636 RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
3637 RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", MCC_AP_BW80_TARGET_TX_TP);
3638 RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", MCC_STA_BW20_TARGET_TX_TP);
3639 RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M):%d Mbps\n", MCC_STA_BW40_TARGET_TX_TP);
3640 RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", MCC_STA_BW80_TARGET_TX_TP);
3641 RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", MCC_SINGLE_TX_CRITERIA);
3642 RTW_PRINT_SEL(sel, "------------------------------------------\n");
3643 }
3644
update_mcc_mgntframe_attrib(_adapter * padapter,struct pkt_attrib * pattrib)3645 inline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
3646 {
3647 if (MCC_EN(padapter)) {
3648 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
3649 /* use QSLT_MGNT to check mgnt queue or bcn queue */
3650 if (pattrib->qsel == QSLT_MGNT) {
3651 pattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;
3652 pattrib->qsel = QSLT_VO;
3653 }
3654 }
3655 }
3656 }
3657
rtw_hal_mcc_link_status_chk(_adapter * padapter,const char * msg)3658 inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
3659 {
3660 u8 ret = _TRUE, i = 0;
3661 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3662 _adapter *iface;
3663 struct mlme_ext_priv *mlmeext;
3664
3665 if (MCC_EN(padapter)) {
3666 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
3667 for (i = 0; i < dvobj->iface_nums; i++) {
3668 iface = dvobj->padapters[i];
3669 mlmeext = &iface->mlmeextpriv;
3670 if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
3671 #ifdef DBG_EXPIRATION_CHK
3672 RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
3673 #endif
3674 ret = _FALSE;
3675 goto exit;
3676 }
3677 }
3678 }
3679 }
3680
3681 exit:
3682 return ret;
3683 }
3684
rtw_hal_mcc_issue_null_data(_adapter * padapter,u8 chbw_allow,u8 ps_mode)3685 void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
3686 {
3687 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3688 _adapter *iface = NULL;
3689 systime start = rtw_get_current_time();
3690 u8 i = 0;
3691
3692 if (!MCC_EN(padapter))
3693 return;
3694
3695 if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
3696 return;
3697
3698 if (chbw_allow == _TRUE)
3699 return;
3700
3701 for (i = 0; i < dvobj->iface_nums; i++) {
3702 iface = dvobj->padapters[i];
3703 /* issue null data to inform ap station will leave */
3704 if (is_client_associated_to_ap(iface)) {
3705 struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
3706 struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
3707 u8 ch = mlmeext->cur_channel;
3708 u8 bw = mlmeext->cur_bwmode;
3709 u8 offset = mlmeext->cur_ch_offset;
3710 struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
3711
3712 if (!sta)
3713 continue;
3714
3715 set_channel_bwmode(iface, ch, offset, bw);
3716
3717 if (ps_mode)
3718 rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
3719 else
3720 rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
3721
3722 issue_nulldata(iface, NULL, ps_mode, 3, 50);
3723 }
3724 }
3725 RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
3726 }
3727
rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter,u8 * pframe,u32 * len)3728 u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
3729 {
3730 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
3731
3732 if (!MCC_EN(padapter))
3733 return pframe;
3734
3735 if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
3736 return pframe;
3737
3738 if (pmccadapriv->p2p_go_noa_ie_len == 0)
3739 return pframe;
3740
3741 _rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
3742 *len = *len + pmccadapriv->p2p_go_noa_ie_len;
3743
3744 return pframe + pmccadapriv->p2p_go_noa_ie_len;
3745 }
3746
rtw_hal_dump_mcc_policy_table(void * sel)3747 void rtw_hal_dump_mcc_policy_table(void *sel)
3748 {
3749 u8 idx = 0;
3750 RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
3751
3752 for (idx = 0; idx < mcc_max_policy_num; idx ++) {
3753 RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
3754 , mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
3755 , mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
3756 , mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
3757 , mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
3758 , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
3759 , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
3760 }
3761 }
3762
rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter,int mac_id,u8 add)3763 void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
3764 {
3765 struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
3766
3767 if (!MCC_EN(padapter))
3768 return;
3769
3770 if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
3771 return;
3772
3773 if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
3774 return;
3775
3776 if (mac_id < 0) {
3777 RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
3778 return;
3779 }
3780
3781 RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
3782 , ADPT_ARG(padapter), add ? "add" : "clear"
3783 , mac_id, pmccadapriv->mcc_macid_bitmap);
3784
3785 if (add) {
3786 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
3787 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &mac_id);
3788 #endif
3789 pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
3790 } else {
3791 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
3792 rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_REMOVE_CLIENT, &mac_id);
3793 #endif
3794 pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
3795 }
3796 rtw_hal_set_mcc_macid_cmd(padapter);
3797 }
3798
rtw_hal_mcc_process_noa(PADAPTER padapter)3799 void rtw_hal_mcc_process_noa(PADAPTER padapter)
3800 {
3801 struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
3802 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3803 struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
3804
3805 if (!MCC_EN(padapter))
3806 return;
3807
3808 if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
3809 return;
3810
3811 if (!MLME_IS_GC(padapter))
3812 return;
3813
3814 switch(pwdinfo->p2p_ps_mode) {
3815 case P2P_PS_NONE:
3816 RTW_INFO("[MCC] Disable NoA under MCC\n");
3817 rtw_hal_mcc_update_parameter(padapter, _TRUE);
3818 break;
3819 case P2P_PS_NOA:
3820 RTW_INFO("[MCC] Enable NoA under MCC\n");
3821 break;
3822 default:
3823 break;
3824
3825 }
3826 }
3827
rtw_hal_mcc_parameter_init(PADAPTER padapter)3828 void rtw_hal_mcc_parameter_init(PADAPTER padapter)
3829 {
3830 if (!padapter->registrypriv.en_mcc)
3831 return;
3832
3833 if (is_primary_adapter(padapter)) {
3834 SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
3835 SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
3836 SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
3837 SET_MCC_PHYDM_OFFLOAD(padapter, padapter->registrypriv.rtw_mcc_phydm_offload);
3838 }
3839 }
3840
3841
set_mcc_duration_hdl(PADAPTER adapter,const u8 * val)3842 static u8 set_mcc_duration_hdl(PADAPTER adapter, const u8 *val)
3843 {
3844 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
3845 struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
3846 _adapter *iface = NULL;
3847 u8 duration = 50;
3848 u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
3849 enum mcc_duration_setting type;
3850
3851 if (!mccobjpriv->enable_runtime_duration)
3852 goto exit;
3853
3854 #ifdef CONFIG_P2P_PS
3855 /* check noa enable or not */
3856 for (i = 0; i < dvobj->iface_nums; i++) {
3857 iface = dvobj->padapters[i];
3858 if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
3859 noa_enable = _TRUE;
3860 break;
3861 }
3862 }
3863 #endif /* CONFIG_P2P_PS */
3864
3865 type = val[0];
3866 duration = val[1];
3867
3868 if (type == MCC_DURATION_MAPPING) {
3869 switch (duration) {
3870 /* 0 = fair scheduling */
3871 case 0:
3872 mccobjpriv->duration= 40;
3873 mccobjpriv->policy_index = 2;
3874 mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
3875 break;
3876 /* 1 = favor STA */
3877 case 1:
3878 mccobjpriv->duration= 70;
3879 mccobjpriv->policy_index = 1;
3880 mccobjpriv->mchan_sched_mode = MCC_FAVOR_STA;
3881 break;
3882 /* 2 = favor P2P*/
3883 case 2:
3884 default:
3885 mccobjpriv->duration= 30;
3886 mccobjpriv->policy_index = 0;
3887 mccobjpriv->mchan_sched_mode = MCC_FAVOR_P2P;
3888 break;
3889 }
3890 } else {
3891 mccobjpriv->duration = duration;
3892 rtw_hal_mcc_update_policy_table(adapter);
3893 }
3894
3895 /* only update sw parameter under MCC
3896 it will be force update during */
3897 if (noa_enable)
3898 goto exit;
3899
3900 if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
3901 rtw_hal_mcc_update_parameter(adapter, _TRUE);
3902 exit:
3903 return ret;
3904 }
3905
rtw_set_mcc_duration_cmd(_adapter * adapter,u8 type,u8 val)3906 u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
3907 {
3908 struct cmd_obj *cmdobj;
3909 struct drvextra_cmd_parm *pdrvextra_cmd_parm;
3910 struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
3911 u8 *buf = NULL;
3912 u8 sz = 2;
3913 u8 res = _SUCCESS;
3914
3915
3916 cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
3917 if (cmdobj == NULL) {
3918 res = _FAIL;
3919 goto exit;
3920 }
3921
3922 pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
3923 if (pdrvextra_cmd_parm == NULL) {
3924 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
3925 res = _FAIL;
3926 goto exit;
3927 }
3928
3929 buf = rtw_zmalloc(sizeof(u8) * sz);
3930 if (buf == NULL) {
3931 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
3932 rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
3933 res = _FAIL;
3934 goto exit;
3935 }
3936
3937 pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
3938 pdrvextra_cmd_parm->type = MCC_SET_DURATION_WK_CID;
3939 pdrvextra_cmd_parm->size = sz;
3940 pdrvextra_cmd_parm->pbuf = buf;
3941
3942 _rtw_memcpy(buf, &type, 1);
3943 _rtw_memcpy(buf + 1, &val, 1);
3944
3945 init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
3946 res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
3947
3948 exit:
3949 return res;
3950 }
3951
3952 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
mcc_phydm_offload_enable_hdl(_adapter * adapter,const u8 * val)3953 static u8 mcc_phydm_offload_enable_hdl(_adapter *adapter, const u8 *val)
3954 {
3955 struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
3956 u8 ret = _SUCCESS;
3957 u8 enable = *val;
3958
3959 /*only modify driver parameter during non-mcc status */
3960 if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
3961 mccobjpriv->mcc_phydm_offload = enable;
3962 } else {
3963 /*modify both driver & phydm parameter during mcc status */
3964 mccobjpriv->mcc_phydm_offload = enable;
3965 rtw_hal_mcc_cfg_phydm(adapter, MCC_CFG_PHYDM_OFFLOAD, &mccobjpriv->mcc_phydm_offload);
3966 }
3967
3968 RTW_INFO("[MCC] phydm offload enable hdl(%d)\n", mccobjpriv->mcc_phydm_offload);
3969
3970 return ret;
3971 }
3972
rtw_set_mcc_phydm_offload_enable_cmd(_adapter * adapter,u8 enable,u8 enqueue)3973 u8 rtw_set_mcc_phydm_offload_enable_cmd(_adapter *adapter, u8 enable, u8 enqueue)
3974 {
3975 u8 res = _SUCCESS;
3976
3977 if (enqueue) {
3978 struct cmd_obj *cmdobj;
3979 struct drvextra_cmd_parm *pdrvextra_cmd_parm;
3980 struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
3981 u8 *mcc_phydm_offload_enable = NULL;
3982
3983
3984 cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
3985 if (cmdobj == NULL) {
3986 res = _FAIL;
3987 goto exit;
3988 }
3989
3990 pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
3991 if (pdrvextra_cmd_parm == NULL) {
3992 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
3993 res = _FAIL;
3994 goto exit;
3995 }
3996
3997 mcc_phydm_offload_enable = rtw_zmalloc(sizeof(u8));
3998 if (mcc_phydm_offload_enable == NULL) {
3999 rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
4000 rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
4001 res = _FAIL;
4002 goto exit;
4003 }
4004
4005 pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
4006 pdrvextra_cmd_parm->type = MCC_SET_PHYDM_OFFLOAD_WK_CID;
4007 pdrvextra_cmd_parm->size = 1;
4008 pdrvextra_cmd_parm->pbuf = mcc_phydm_offload_enable;
4009
4010 _rtw_memcpy(mcc_phydm_offload_enable, &enable, 1);
4011 init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
4012 res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
4013 } else {
4014 mcc_phydm_offload_enable_hdl(adapter, &enable);
4015 }
4016
4017 exit:
4018 return res;
4019 }
4020 #endif
4021
rtw_mcc_cmd_hdl(_adapter * adapter,u8 type,const u8 * val)4022 u8 rtw_mcc_cmd_hdl(_adapter *adapter, u8 type, const u8 *val)
4023 {
4024 struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
4025 u8 ret = _SUCCESS;
4026
4027 switch (type) {
4028 case MCC_SET_DURATION_WK_CID:
4029 set_mcc_duration_hdl(adapter, val);
4030 break;
4031 case MCC_GET_DBG_REG_WK_CID:
4032 mcc_get_reg_hdl(adapter, val);
4033 break;
4034 #ifdef CONFIG_MCC_PHYDM_OFFLOAD
4035 case MCC_SET_PHYDM_OFFLOAD_WK_CID:
4036 mcc_phydm_offload_enable_hdl(adapter, val);
4037 break;
4038 #endif
4039 default:
4040 RTW_ERR("[MCC] rtw_mcc_cmd_hdl fail(%d)\n", type);
4041 break;
4042 }
4043
4044
4045
4046 return ret;
4047 }
4048
4049 #endif /* CONFIG_MCC_MODE */
4050