1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2015 - 2019 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef _HAL_HALMAC_H_ 17 #define _HAL_HALMAC_H_ 18 19 #include <drv_types.h> /* adapter_to_dvobj(), struct intf_hdl and etc. */ 20 #include <hal_data.h> /* struct hal_spec_t */ 21 #include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */ 22 23 /* HALMAC Definition for Driver */ 24 #define RTW_HALMAC_H2C_MAX_SIZE 8 25 #define RTW_HALMAC_BA_SSN_RPT_SIZE 4 26 27 #define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) 28 #define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac)) 29 #define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) 30 31 /* for H2C cmd */ 32 #define MAX_H2C_BOX_NUMS 4 33 #define MESSAGE_BOX_SIZE 4 34 #define EX_MESSAGE_BOX_SIZE 4 35 36 typedef enum _RTW_HALMAC_MODE { 37 RTW_HALMAC_MODE_NORMAL, 38 RTW_HALMAC_MODE_WIFI_TEST, 39 } RTW_HALMAC_MODE; 40 41 union rtw_phy_para_data { 42 struct _mac { 43 u32 value; /* value to be set in bit mask(msk) */ 44 u32 msk; /* bit mask */ 45 u16 offset; /* address */ 46 u8 msk_en; /* 0/1 for msk invalid/valid */ 47 u8 size; /* Unit is bytes, and value should be 1/2/4 */ 48 } mac; 49 struct _bb { 50 u32 value; 51 u32 msk; 52 u16 offset; 53 u8 msk_en; 54 u8 size; 55 } bb; 56 struct _rf { 57 u32 value; 58 u32 msk; 59 u8 offset; 60 u8 msk_en; 61 /* 62 * 0: path A 63 * 1: path B 64 * 2: path C 65 * 3: path D 66 */ 67 u8 path; 68 } rf; 69 struct _delay { 70 /* 71 * 0: microsecond (us) 72 * 1: millisecond (ms) 73 */ 74 u8 unit; 75 u16 value; 76 } delay; 77 }; 78 79 struct rtw_phy_parameter { 80 /* 81 * 0: MAC register 82 * 1: BB register 83 * 2: RF register 84 * 3: Delay 85 * 0xFF: Latest(End) command 86 */ 87 u8 cmd; 88 union rtw_phy_para_data data; 89 }; 90 91 struct rtw_halmac_bcn_ctrl { 92 u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */ 93 u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */ 94 u8 tsf_update:1; /* Update TSF when beacon or probe response */ 95 u8 enable_bcn:1; /* Enable beacon related functions */ 96 u8 rxbcn_rpt:1; /* Enable RXBCNOK report */ 97 u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */ 98 u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */ 99 }; 100 101 extern struct halmac_platform_api rtw_halmac_platform_api; 102 103 /* HALMAC API for Driver(HAL) */ 104 u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); 105 u16 rtw_halmac_read16(struct intf_hdl *, u32 addr); 106 u32 rtw_halmac_read32(struct intf_hdl *, u32 addr); 107 void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); 108 #ifdef CONFIG_SDIO_INDIRECT_ACCESS 109 u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); 110 u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); 111 u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); 112 #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ 113 int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); 114 int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); 115 int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); 116 117 /* Software Information */ 118 void rtw_halmac_get_version(char *str, u32 len); 119 120 /* Software setting before Initialization */ 121 int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable); 122 123 /* Software Initialization */ 124 int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api); 125 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 126 127 /* Get operations */ 128 int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue); 129 int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size); 130 int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size); 131 int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy); 132 int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size); 133 int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size); 134 int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size); 135 int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz); 136 int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size); 137 int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size); 138 int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size); 139 int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size); 140 int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); 141 int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); 142 int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 143 int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type); 144 int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 145 /*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/ 146 147 /* Set operations */ 148 int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info); 149 int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size); 150 int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 151 int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 152 int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 153 int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type); 154 int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport); 155 int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space); 156 int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 157 int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid); 158 int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw); 159 int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); 160 int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable); 161 162 /* Functions */ 163 int rtw_halmac_poweron(struct dvobj_priv *); 164 int rtw_halmac_poweroff(struct dvobj_priv *); 165 int rtw_halmac_init_hal(struct dvobj_priv *); 166 int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); 167 int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); 168 int rtw_halmac_deinit_hal(struct dvobj_priv *); 169 int rtw_halmac_self_verify(struct dvobj_priv *); 170 int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout); 171 int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); 172 int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); 173 int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); 174 int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem); 175 int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); 176 int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); 177 int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); 178 179 /* eFuse */ 180 int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); 181 int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); 182 int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 183 int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 184 int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 185 int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); 186 int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 187 int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 188 int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 189 int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 190 191 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 192 int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 193 194 int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); 195 int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); 196 197 /* Specific function APIs*/ 198 int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); 199 int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); 200 int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); 201 int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); 202 int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz); 203 int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para); 204 int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode); 205 void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on); 206 int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable); 207 #ifdef CONFIG_PNO_SUPPORT 208 int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable); 209 #endif 210 211 #ifdef CONFIG_SDIO_HCI 212 int rtw_halmac_query_tx_page_num(struct dvobj_priv *); 213 int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page); 214 u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size); 215 int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size); 216 u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq); 217 int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format); 218 #endif /* CONFIG_SDIO_HCI */ 219 220 #ifdef CONFIG_USB_HCI 221 u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); 222 int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num); 223 u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); 224 #endif /* CONFIG_USB_HCI */ 225 226 #ifdef CONFIG_SUPPORT_TRX_SHARED 227 void dump_trx_share_mode(void *sel, _adapter *adapter); 228 #endif 229 230 #ifdef CONFIG_BEAMFORMING 231 #ifdef RTW_BEAMFORMING_VERSION_2 232 int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, 233 u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr); 234 int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d); 235 236 int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role, 237 enum halmac_data_rate rate); 238 int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role); 239 240 int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, 241 u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54); 242 243 int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, 244 u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, 245 u32 *given_gid_tab, u32 *given_user_pos); 246 #define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \ 247 rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos) 248 249 #endif /* RTW_BEAMFORMING_VERSION_2 */ 250 #endif /* CONFIG_BEAMFORMING */ 251 252 #endif /* _HAL_HALMAC_H_ */ 253