1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2014 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #include <drv_types.h>
18 #include <hal_data.h>
19
20 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)21 enum odm_board_type boardType(u8 InterfaceSel)
22 {
23 enum odm_board_type board = ODM_BOARD_DEFAULT;
24
25 #ifdef CONFIG_PCI_HCI
26 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
27 switch (pcie) {
28 case INTF_SEL0_SOLO_MINICARD:
29 board |= ODM_BOARD_MINICARD;
30 break;
31 case INTF_SEL1_BT_COMBO_MINICARD:
32 board |= ODM_BOARD_BT;
33 board |= ODM_BOARD_MINICARD;
34 break;
35 default:
36 board = ODM_BOARD_DEFAULT;
37 break;
38 }
39
40 #elif defined(CONFIG_USB_HCI)
41 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
42 switch (usb) {
43 case INTF_SEL1_USB_High_Power:
44 board |= ODM_BOARD_EXT_LNA;
45 board |= ODM_BOARD_EXT_PA;
46 break;
47 case INTF_SEL2_MINICARD:
48 board |= ODM_BOARD_MINICARD;
49 break;
50 case INTF_SEL4_USB_Combo:
51 board |= ODM_BOARD_BT;
52 break;
53 case INTF_SEL5_USB_Combo_MF:
54 board |= ODM_BOARD_BT;
55 break;
56 case INTF_SEL0_USB:
57 case INTF_SEL3_USB_Solo:
58 default:
59 board = ODM_BOARD_DEFAULT;
60 break;
61 }
62
63 #endif
64 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
65
66 return board;
67 }
68
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)69 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
70 {
71 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
72 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
73
74 if (hal->RegIQKFWOffload) {
75 rtw_sctx_init(&hal->iqk_sctx, 0);
76 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
77 } else
78 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
79
80 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
81
82 if (rtw_mi_check_status(adapter, MI_LINKED)) {
83 #ifdef CONFIG_LPS
84 LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
85 #endif
86 halrf_iqk_trigger(p_dm_odm, _FALSE);
87 }
88 }
89
90 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)91 void rtw_phydm_iqk_trigger(_adapter *adapter)
92 {
93 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
94 u8 clear = _TRUE;
95 u8 segment = _FALSE;
96 u8 rfk_forbidden = _FALSE;
97
98 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
99 #if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)
100 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
101 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
102 #else
103 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
104 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
105 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
106 #endif
107 }
108 #endif
109
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)110 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
111 {
112 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
113
114 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
115 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
116 #else
117 halrf_iqk_trigger(p_dm_odm, recovery);
118 #endif
119 }
rtw_phydm_lck_trigger(_adapter * adapter)120 void rtw_phydm_lck_trigger(_adapter *adapter)
121 {
122 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
123
124 halrf_lck_trigger(p_dm_odm);
125 }
126 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)127 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
128 {
129 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
130
131 rtw_ps_deny(adapter, PS_DENY_IOCTL);
132 LeaveAllPowerSaveModeDirect(adapter);
133
134 rtw_phydm_ability_backup(adapter);
135 rtw_phydm_func_disable_all(adapter);
136
137 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
138
139 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
140 rtw_phydm_ability_restore(adapter);
141
142 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
143 }
144
rtw_hal_lck_test(_adapter * adapter)145 void rtw_hal_lck_test(_adapter *adapter)
146 {
147 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
148
149 rtw_ps_deny(adapter, PS_DENY_IOCTL);
150 LeaveAllPowerSaveModeDirect(adapter);
151
152 rtw_phydm_ability_backup(adapter);
153 rtw_phydm_func_disable_all(adapter);
154
155 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
156
157 rtw_phydm_lck_trigger(adapter);
158
159 rtw_phydm_ability_restore(adapter);
160 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
161 }
162 #endif
163
164 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)165 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
166 {
167 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
168
169 if (adapter->registrypriv.fw_param_init)
170 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
171 else
172 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
173
174 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
175 }
176 #endif
177
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)178 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
179 {
180 struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
181 _adapter *adapter = p_dm->adapter;
182 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
183 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
184
185 if (p_sta) {
186 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
187 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
188 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
189 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
190
191 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
192 }
193 }
194
195 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
rtw_phydm_fill_desc_dpt(void * dm,u8 * desc,u8 dpt_lv)196 void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
197 {
198 struct dm_struct *p_dm = (struct dm_struct *)dm;
199 _adapter *adapter = p_dm->adapter;
200
201 switch (rtw_get_chip_type(adapter)) {
202 /*
203 #ifdef CONFIG_RTL8188F
204 case RTL8188F:
205 break;
206 #endif
207
208 #ifdef CONFIG_RTL8723B
209 case RTL8723B :
210 break;
211 #endif
212
213 #ifdef CONFIG_RTL8703B
214 case RTL8703B :
215 break;
216 #endif
217
218 #ifdef CONFIG_RTL8812A
219 case RTL8812 :
220 break;
221 #endif
222
223 #ifdef CONFIG_RTL8821A
224 case RTL8821:
225 break;
226 #endif
227
228 #ifdef CONFIG_RTL8814A
229 case RTL8814A :
230 break;
231 #endif
232
233 #ifdef CONFIG_RTL8192F
234 case RTL8192F :
235 break;
236 #endif
237 */
238 /*
239 #ifdef CONFIG_RTL8192E
240 case RTL8192E :
241 SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
242 break;
243 #endif
244 */
245 #ifdef CONFIG_RTL8822B
246 case RTL8822B :
247 SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
248 break;
249 #endif
250
251 #ifdef CONFIG_RTL8821C
252 case RTL8821C :
253 SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
254 break;
255 #endif
256
257 default :
258 RTW_ERR("%s IC not support dynamic tx power\n", __func__);
259 break;
260 }
261 }
rtw_phydm_set_dyntxpwr(_adapter * adapter,u8 * desc,u8 mac_id)262 void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
263 {
264 struct dm_struct *dm = adapter_to_phydm(adapter);
265
266 odm_set_dyntxpwr(dm, desc, mac_id);
267 }
268 #endif
269
270 #ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(_adapter * adapter,u8 state)271 void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
272 {
273 struct registry_priv *pregistrypriv = &adapter->registrypriv;
274 struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
275 struct dm_struct *dm = adapter_to_phydm(adapter);
276 u8 tdma_dig_en;
277
278 switch (state) {
279 case TDMADIG_INIT:
280 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
281 phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
282 break;
283 case TDMADIG_NON_INIT:
284 if(pregistrypriv->tdmadig_dynamic) {
285 if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
286 tdma_dig_en = 0;
287 else
288 tdma_dig_en = pregistrypriv->tdmadig_en;
289 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
290 }
291 break;
292 default:
293 break;
294
295 }
296 }
297 #endif/*CONFIG_TDMADIG*/
rtw_phydm_ops_func_init(struct dm_struct * p_phydm)298 void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
299 {
300 struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
301
302 p_ra_t->record_ra_info = record_ra_info;
303 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
304 p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
305 #endif
306 }
rtw_phydm_priv_init(_adapter * adapter)307 void rtw_phydm_priv_init(_adapter *adapter)
308 {
309 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
310 struct dm_struct *phydm = &(hal->odmpriv);
311
312 phydm->adapter = adapter;
313 odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
314 }
315
Init_ODM_ComInfo(_adapter * adapter)316 void Init_ODM_ComInfo(_adapter *adapter)
317 {
318 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
319 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
320 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
321 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
322 int i;
323
324 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
325 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
326 rtw_odm_init_ic_type(adapter);
327
328 if (rtw_get_intf_type(adapter) == RTW_GSPI)
329 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
330 else
331 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
332
333 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
334
335 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
336
337 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
338
339 #ifdef CONFIG_ADVANCE_OTA
340 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
341 #endif
342 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
343
344 {
345 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
346 u8 odm_board_type = ODM_BOARD_DEFAULT;
347
348 if (pHalData->ExternalLNA_2G != 0) {
349 odm_board_type |= ODM_BOARD_EXT_LNA;
350 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
351 }
352 if (pHalData->external_lna_5g != 0) {
353 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
354 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
355 }
356 if (pHalData->ExternalPA_2G != 0) {
357 odm_board_type |= ODM_BOARD_EXT_PA;
358 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
359 }
360 if (pHalData->external_pa_5g != 0) {
361 odm_board_type |= ODM_BOARD_EXT_PA_5G;
362 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
363 }
364 if (pHalData->EEPROMBluetoothCoexist)
365 odm_board_type |= ODM_BOARD_BT;
366
367 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
368 /* 1 ============== End of BoardType ============== */
369 }
370
371 rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
372
373 #ifdef CONFIG_DFS_MASTER
374 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter_to_rfctl(adapter)->dfs_region_domain);
375 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
376 #endif
377
378 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
379 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
380 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
381 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
382
383 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
384 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
385
386 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
387
388 /*Add by YuChen for kfree init*/
389 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
390 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
391
392 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
393 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
394 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
395
396 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
397 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
398 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
399
400 /* waiting for PhyDMV034 support*/
401 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
402 /*Add by YuChen for adaptivity init*/
403 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
404 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
405 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
406 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
407
408 /*halrf info init*/
409 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
410 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
411 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
412
413 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
414 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
415
416 #ifdef CONFIG_IQK_PA_OFF
417 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
418 #endif
419 rtw_hal_update_iqk_fw_offload_cap(adapter);
420 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
421 rtw_hal_update_param_init_fw_offload_cap(adapter);
422 #endif
423
424 /* Pointer reference */
425 /*Antenna diversity relative parameters*/
426 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
427 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
428
429 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
430 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
431 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
432
433 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
434 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
435
436 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
437 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
438 #ifdef CONFIG_NARROWBAND_SUPPORTING
439 if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
440 || (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
441 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
442 }
443 else
444 #endif
445 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
446 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
447 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
448
449 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
450 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
451 /*Add by Yuchen for phydm beamforming*/
452 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
453 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
454 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
455 #ifdef CONFIG_RTL8723B
456 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
457 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
458 #endif /*CONFIG_RTL8723B*/
459 #ifdef CONFIG_USB_HCI
460 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
461 #endif
462
463 #ifdef CONFIG_DYNAMIC_SOML
464 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
465 #endif
466 #ifdef CONFIG_RTW_PATH_DIV
467 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
468 #endif
469 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
470
471 /*halrf info hook*/
472 /* waiting for PhyDMV034 support*/
473 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
474 #ifdef CONFIG_MP_INCLUDED
475 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
476 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
477 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
478 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
479 #endif/*CONFIG_MP_INCLUDED*/
480 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
481 phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
482
483 rtw_phydm_ops_func_init(pDM_Odm);
484 phydm_dm_early_init(pDM_Odm);
485 /* TODO */
486 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
487 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
488 }
489
490
491 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
492 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
493 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
494 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
495
496 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
497 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
498 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
499 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
500
501 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
502 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
503 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
504 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
505
506
507 struct turbo_edca_setting{
508 u32 edca_ul; /* uplink, tx */
509 u32 edca_dl; /* downlink, rx */
510 };
511
512 #define TURBO_EDCA_ENT(UL, DL) {UL, DL}
513
514 #if 0
515 #define TURBO_EDCA_MODE_NUM 18
516 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
517 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
518 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
519 TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
520
521 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
522 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
523 TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
524
525 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
526 TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
527 TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
528
529 TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
530 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
531 TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
532
533 TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
534 TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
535 TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
536
537 TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
538
539 TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
540
541 TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
542 };
543 #else
544 #define TURBO_EDCA_MODE_NUM 8
545 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
546 /* { UL, DL } */
547 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
548
549 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
550
551 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
552
553 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
554
555 TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
556
557 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
558
559 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
560
561 TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
562 };
563 #endif
564
rtw_hal_turbo_edca(_adapter * adapter)565 void rtw_hal_turbo_edca(_adapter *adapter)
566 {
567 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
568 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
569 struct recv_priv *precvpriv = &(adapter->recvpriv);
570 struct registry_priv *pregpriv = &adapter->registrypriv;
571 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
572 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
573
574 /* Parameter suggested by Scott */
575 #if 0
576 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
577 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
578 #endif
579 u32 EDCA_BE_UL = 0x5ea42b;
580 u32 EDCA_BE_DL = 0x00a42b;
581 u8 ic_type = rtw_get_chip_type(adapter);
582
583 u8 iot_peer = 0;
584 u8 wireless_mode = 0xFF; /* invalid value */
585 u8 traffic_index;
586 u32 edca_param;
587 u64 cur_tx_bytes = 0;
588 u64 cur_rx_bytes = 0;
589 u8 bbtchange = _TRUE;
590 u8 is_bias_on_rx = _FALSE;
591 u8 is_linked = _FALSE;
592 u8 interface_type;
593
594 if (hal_data->dis_turboedca == 1)
595 return;
596
597 if (rtw_mi_check_status(adapter, MI_ASSOC))
598 is_linked = _TRUE;
599
600 if (is_linked != _TRUE) {
601 precvpriv->is_any_non_be_pkts = _FALSE;
602 return;
603 }
604
605 if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
606 precvpriv->is_any_non_be_pkts = _FALSE;
607 return;
608 }
609
610 interface_type = rtw_get_intf_type(adapter);
611 wireless_mode = pmlmeext->cur_wireless_mode;
612
613 iot_peer = pmlmeinfo->assoc_AP_vendor;
614
615 if (iot_peer >= HT_IOT_PEER_MAX) {
616 precvpriv->is_any_non_be_pkts = _FALSE;
617 return;
618 }
619
620 if (ic_type == RTL8188E) {
621 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
622 is_bias_on_rx = _TRUE;
623 }
624
625 /* Check if the status needs to be changed. */
626 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
627 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
628 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
629
630 /* traffic, TX or RX */
631 if (is_bias_on_rx) {
632 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
633 /* Uplink TP is present. */
634 traffic_index = UP_LINK;
635 } else {
636 /* Balance TP is present. */
637 traffic_index = DOWN_LINK;
638 }
639 } else {
640 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
641 /* Downlink TP is present. */
642 traffic_index = DOWN_LINK;
643 } else {
644 /* Balance TP is present. */
645 traffic_index = UP_LINK;
646 }
647 }
648 #if 0
649 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
650 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
651 #endif
652 {
653 if (interface_type == RTW_PCIE) {
654 EDCA_BE_UL = 0x6ea42b;
655 EDCA_BE_DL = 0x6ea42b;
656 }
657
658 /* 92D txop can't be set to 0x3e for cisco1250 */
659 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
660 EDCA_BE_DL = edca_setting_DL[iot_peer];
661 EDCA_BE_UL = edca_setting_UL[iot_peer];
662 }
663 /* merge from 92s_92c_merge temp*/
664 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
665 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
666 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
667 EDCA_BE_DL = 0xa630;
668 else if (iot_peer == HT_IOT_PEER_MARVELL) {
669 EDCA_BE_DL = edca_setting_DL[iot_peer];
670 EDCA_BE_UL = edca_setting_UL[iot_peer];
671 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
672 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
673 /* Suggested by SD3 Wilson for ASUS TP issue.*/
674 EDCA_BE_DL = edca_setting_DL[iot_peer];
675 }
676
677 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
678 EDCA_BE_UL = 0x5ea42b;
679 EDCA_BE_DL = 0x5ea42b;
680
681 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
682 }
683
684 if (interface_type == RTW_PCIE &&
685 ((ic_type == RTL8822B)
686 || (ic_type == RTL8822C)
687 || (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
688 EDCA_BE_UL = 0x6ea42b;
689 EDCA_BE_DL = 0x6ea42b;
690 }
691
692 if ((ic_type == RTL8822B)
693 && (interface_type == RTW_SDIO))
694 EDCA_BE_DL = 0x00431c;
695
696 #ifdef CONFIG_RTW_TPT_MODE
697 if ( dvobj->tpt_mode > 0 ) {
698 EDCA_BE_UL = dvobj->edca_be_ul;
699 EDCA_BE_DL = dvobj->edca_be_dl;
700 }
701 #endif /* CONFIG_RTW_TPT_MODE */
702
703 /* keep this condition at last check */
704 if (hal_data->dis_turboedca == 2) {
705
706 if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
707
708 struct turbo_edca_setting param;
709
710 param = rtw_turbo_edca[hal_data->edca_param_mode];
711
712 EDCA_BE_UL = param.edca_ul;
713 EDCA_BE_DL = param.edca_dl;
714
715 } else {
716
717 EDCA_BE_UL = hal_data->edca_param_mode;
718 EDCA_BE_DL = hal_data->edca_param_mode;
719 }
720 }
721
722 if (traffic_index == DOWN_LINK)
723 edca_param = EDCA_BE_DL;
724 else
725 edca_param = EDCA_BE_UL;
726
727 #ifdef CONFIG_EXTEND_LOWRATE_TXOP
728 #define TXOP_CCK1M 0x01A6
729 #define TXOP_CCK2M 0x00E6
730 #define TXOP_CCK5M 0x006B
731 #define TXOP_OFD6M 0x0066
732 #define TXOP_MCS6M 0x0061
733 {
734 struct sta_info *psta;
735 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
736 u8 mac_id, role, current_rate_id;
737
738 /* search all used & connect2AP macid */
739 for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
740 if (rtw_macid_is_used(macid_ctl, mac_id)) {
741 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
742 if (role != H2C_MSR_ROLE_AP)
743 continue;
744
745 psta = macid_ctl->sta[mac_id];
746 current_rate_id = rtw_get_current_tx_rate(adapter, psta);
747 /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
748 switch (current_rate_id) {
749 case DESC_RATE1M:
750 edca_param &= 0x0000FFFF;
751 edca_param |= (TXOP_CCK1M<<16);
752 break;
753 case DESC_RATE2M:
754 edca_param &= 0x0000FFFF;
755 edca_param |= (TXOP_CCK2M<<16);
756 break;
757 case DESC_RATE5_5M:
758 edca_param &= 0x0000FFFF;
759 edca_param |= (TXOP_CCK5M<<16);
760 break;
761 case DESC_RATE6M:
762 edca_param &= 0x0000FFFF;
763 edca_param |= (TXOP_OFD6M<<16);
764 break;
765 case DESC_RATEMCS0:
766 edca_param &= 0x0000FFFF;
767 edca_param |= (TXOP_MCS6M<<16);
768 break;
769 default:
770 break;
771 }
772 }
773 }
774 }
775 #endif /* CONFIG_EXTEND_LOWRATE_TXOP */
776
777 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
778 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
779 #endif
780
781 if ( edca_param != hal_data->ac_param_be) {
782
783 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
784
785 RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
786 }
787
788 hal_data->prv_traffic_idx = traffic_index;
789 }
790
791 hal_data->is_turbo_edca = _TRUE;
792 } else {
793 /* */
794 /* Turn Off EDCA turbo here. */
795 /* Restore original EDCA according to the declaration of AP. */
796 /* */
797 if (hal_data->is_turbo_edca) {
798 edca_param = hal_data->ac_param_be;
799 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
800 hal_data->is_turbo_edca = _FALSE;
801 }
802 }
803
804 }
805
rtw_dm_get_min_rssi(_adapter * adapter)806 s8 rtw_dm_get_min_rssi(_adapter *adapter)
807 {
808 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
809 struct sta_info *sta;
810 s8 min_rssi = 127, rssi;
811 int i;
812
813 for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
814 sta = macid_ctl->sta[i];
815 if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
816 || is_broadcast_mac_addr(sta->cmn.mac_addr))
817 continue;
818 rssi = sta->cmn.rssi_stat.rssi;
819 if (rssi >= 0 && min_rssi > rssi)
820 min_rssi = rssi;
821 }
822
823 return min_rssi == 127 ? 0 : min_rssi;
824 }
825
rtw_phydm_get_min_rssi(_adapter * adapter)826 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
827 {
828 struct dm_struct *phydm = adapter_to_phydm(adapter);
829 s8 rssi_min = 0;
830
831 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
832 return rssi_min;
833 }
834
rtw_phydm_get_cur_igi(_adapter * adapter)835 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
836 {
837 struct dm_struct *phydm = adapter_to_phydm(adapter);
838 u8 cur_igi = 0;
839
840 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
841 return cur_igi;
842 }
843
rtw_phydm_get_edcca_flag(_adapter * adapter)844 bool rtw_phydm_get_edcca_flag(_adapter *adapter)
845 {
846 struct dm_struct *phydm = adapter_to_phydm(adapter);
847 bool cur_edcca_flag = 0;
848
849 cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
850 return cur_edcca_flag;
851 }
852
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)853 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
854 {
855 struct dm_struct *phydm = adapter_to_phydm(adapter);
856
857 if (cnt == FA_OFDM)
858 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
859 else if (cnt == FA_CCK)
860 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
861 else if (cnt == FA_TOTAL)
862 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
863 else if (cnt == CCA_OFDM)
864 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
865 else if (cnt == CCA_CCK)
866 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
867 else if (cnt == CCA_ALL)
868 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
869 else if (cnt == CRC32_OK_VHT)
870 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
871 else if (cnt == CRC32_OK_HT)
872 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
873 else if (cnt == CRC32_OK_LEGACY)
874 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
875 else if (cnt == CRC32_OK_CCK)
876 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
877 else if (cnt == CRC32_ERROR_VHT)
878 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
879 else if (cnt == CRC32_ERROR_HT)
880 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
881 else if (cnt == CRC32_ERROR_LEGACY)
882 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
883 else if (cnt == CRC32_ERROR_CCK)
884 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
885 else
886 return 0;
887 }
888
rtw_phydm_is_iqk_in_progress(_adapter * adapter)889 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
890 {
891 u8 rts = _FALSE;
892 struct dm_struct *podmpriv = adapter_to_phydm(adapter);
893
894 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
895 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
896 RTW_ERR("IQK InProgress\n");
897 rts = _TRUE;
898 }
899 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
900
901 return rts;
902 }
903
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)904 void SetHalODMVar(
905 PADAPTER Adapter,
906 HAL_ODM_VARIABLE eVariable,
907 void *pValue1,
908 BOOLEAN bSet)
909 {
910 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
911 /* _irqL irqL; */
912 switch (eVariable) {
913 case HAL_ODM_STA_INFO: {
914 struct sta_info *psta = (struct sta_info *)pValue1;
915
916 if (bSet) {
917 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
918 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
919 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
920 } else {
921 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
922 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
923 psta->cmn.dm_ctrl = 0;
924 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
925
926 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
927 }
928 }
929 break;
930 case HAL_ODM_P2P_STATE:
931 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
932 break;
933 case HAL_ODM_WIFI_DISPLAY_STATE:
934 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
935 break;
936 case HAL_ODM_REGULATION:
937 /* used to auto enable/disable adaptivity by SD7 */
938 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
939 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
940 break;
941 case HAL_ODM_INITIAL_GAIN: {
942 u8 rx_gain = *((u8 *)(pValue1));
943 /*printk("rx_gain:%x\n",rx_gain);*/
944 if (rx_gain == 0xff) {/*restore rx gain*/
945 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
946 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
947 } else {
948 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
949 /*odm_write_dig(podmpriv,rx_gain);*/
950 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
951 }
952 }
953 break;
954 case HAL_ODM_RX_INFO_DUMP: {
955 u8 cur_igi = 0;
956 s8 rssi_min;
957 void *sel;
958
959 sel = pValue1;
960 cur_igi = rtw_phydm_get_cur_igi(Adapter);
961 rssi_min = rtw_phydm_get_min_rssi(Adapter);
962
963 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
964 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
965 , podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
966 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
967 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
968 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
969 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
970
971 if (podmpriv->is_linked) {
972 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
973 if (IS_HARDWARE_TYPE_8814A(Adapter))
974 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
975 podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
976 else
977 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
978 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
979 rtw_dump_raw_rssi_info(Adapter, sel);
980 #endif
981 }
982 }
983 break;
984 case HAL_ODM_RX_Dframe_INFO: {
985 void *sel;
986
987 sel = pValue1;
988
989 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
990 #ifdef DBG_RX_DFRAME_RAW_DATA
991 rtw_dump_rx_dframe_info(Adapter, sel);
992 #endif
993 }
994 break;
995
996 #ifdef CONFIG_ANTENNA_DIVERSITY
997 case HAL_ODM_ANTDIV_SELECT: {
998 u8 antenna = (*(u8 *)pValue1);
999 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1000 /*switch antenna*/
1001 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
1002 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
1003
1004 }
1005 break;
1006 #endif
1007
1008 default:
1009 break;
1010 }
1011 }
1012
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1013 void GetHalODMVar(
1014 PADAPTER Adapter,
1015 HAL_ODM_VARIABLE eVariable,
1016 void *pValue1,
1017 void *pValue2)
1018 {
1019 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
1020
1021 switch (eVariable) {
1022 #ifdef CONFIG_ANTENNA_DIVERSITY
1023 case HAL_ODM_ANTDIV_SELECT: {
1024 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
1025 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
1026 }
1027 break;
1028 #endif
1029 case HAL_ODM_INITIAL_GAIN:
1030 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
1031 break;
1032 default:
1033 break;
1034 }
1035 }
1036
1037 #ifdef RTW_HALMAC
1038 #include "../hal_halmac.h"
1039 #endif
1040
1041 enum hal_status
rtw_phydm_fw_iqk(struct dm_struct * p_dm_odm,u8 clear,u8 segment)1042 rtw_phydm_fw_iqk(
1043 struct dm_struct *p_dm_odm,
1044 u8 clear,
1045 u8 segment
1046 )
1047 {
1048 #ifdef RTW_HALMAC
1049 struct _ADAPTER *adapter = p_dm_odm->adapter;
1050
1051 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
1052 return HAL_STATUS_SUCCESS;
1053 #endif
1054 return HAL_STATUS_FAILURE;
1055 }
1056
1057 enum hal_status
rtw_phydm_cfg_phy_para(struct dm_struct * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)1058 rtw_phydm_cfg_phy_para(
1059 struct dm_struct *p_dm_odm,
1060 enum phydm_halmac_param config_type,
1061 u32 offset,
1062 u32 data,
1063 u32 mask,
1064 enum rf_path e_rf_path,
1065 u32 delay_time)
1066 {
1067 #ifdef RTW_HALMAC
1068 struct _ADAPTER *adapter = p_dm_odm->adapter;
1069 struct rtw_phy_parameter para;
1070
1071 switch (config_type) {
1072 case PHYDM_HALMAC_CMD_MAC_W8:
1073 para.cmd = 0; /* MAC register */
1074 para.data.mac.offset = offset;
1075 para.data.mac.value = data;
1076 para.data.mac.msk = mask;
1077 para.data.mac.msk_en = (mask) ? 1 : 0;
1078 para.data.mac.size = 1;
1079 break;
1080 case PHYDM_HALMAC_CMD_MAC_W16:
1081 para.cmd = 0; /* MAC register */
1082 para.data.mac.offset = offset;
1083 para.data.mac.value = data;
1084 para.data.mac.msk = mask;
1085 para.data.mac.msk_en = (mask) ? 1 : 0;
1086 para.data.mac.size = 2;
1087 break;
1088 case PHYDM_HALMAC_CMD_MAC_W32:
1089 para.cmd = 0; /* MAC register */
1090 para.data.mac.offset = offset;
1091 para.data.mac.value = data;
1092 para.data.mac.msk = mask;
1093 para.data.mac.msk_en = (mask) ? 1 : 0;
1094 para.data.mac.size = 4;
1095 break;
1096 case PHYDM_HALMAC_CMD_BB_W8:
1097 para.cmd = 1; /* BB register */
1098 para.data.bb.offset = offset;
1099 para.data.bb.value = data;
1100 para.data.bb.msk = mask;
1101 para.data.bb.msk_en = (mask) ? 1 : 0;
1102 para.data.bb.size = 1;
1103 break;
1104 case PHYDM_HALMAC_CMD_BB_W16:
1105 para.cmd = 1; /* BB register */
1106 para.data.bb.offset = offset;
1107 para.data.bb.value = data;
1108 para.data.bb.msk = mask;
1109 para.data.bb.msk_en = (mask) ? 1 : 0;
1110 para.data.bb.size = 2;
1111 break;
1112 case PHYDM_HALMAC_CMD_BB_W32:
1113 para.cmd = 1; /* BB register */
1114 para.data.bb.offset = offset;
1115 para.data.bb.value = data;
1116 para.data.bb.msk = mask;
1117 para.data.bb.msk_en = (mask) ? 1 : 0;
1118 para.data.bb.size = 4;
1119 break;
1120 case PHYDM_HALMAC_CMD_RF_W:
1121 para.cmd = 2; /* RF register */
1122 para.data.rf.offset = offset;
1123 para.data.rf.value = data;
1124 para.data.rf.msk = mask;
1125 para.data.rf.msk_en = (mask) ? 1 : 0;
1126 if (e_rf_path == RF_PATH_A)
1127 para.data.rf.path = 0;
1128 else if (e_rf_path == RF_PATH_B)
1129 para.data.rf.path = 1;
1130 else if (e_rf_path == RF_PATH_C)
1131 para.data.rf.path = 2;
1132 else if (e_rf_path == RF_PATH_D)
1133 para.data.rf.path = 3;
1134 else
1135 para.data.rf.path = 0;
1136 break;
1137 case PHYDM_HALMAC_CMD_DELAY_US:
1138 para.cmd = 3; /* Delay */
1139 para.data.delay.unit = 0; /* microsecond */
1140 para.data.delay.value = delay_time;
1141 break;
1142 case PHYDM_HALMAC_CMD_DELAY_MS:
1143 para.cmd = 3; /* Delay */
1144 para.data.delay.unit = 1; /* millisecond */
1145 para.data.delay.value = delay_time;
1146 break;
1147 case PHYDM_HALMAC_CMD_END:
1148 para.cmd = 0xFF; /* End command */
1149 break;
1150 default:
1151 return HAL_STATUS_FAILURE;
1152 }
1153
1154 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
1155 return HAL_STATUS_FAILURE;
1156 #endif /*RTW_HALMAC*/
1157 return HAL_STATUS_SUCCESS;
1158 }
1159
1160
1161 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)1162 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
1163 {
1164 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1165 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1166 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1167 struct sta_priv *pstapriv = &adapter->stapriv;
1168 struct sta_info *psta = NULL;
1169 bool is_linked = _FALSE;
1170
1171 if (!rtw_is_hw_init_completed(adapter))
1172 return;
1173
1174 if (rtw_mi_check_status(adapter, MI_ASSOC))
1175 is_linked = _TRUE;
1176
1177 if (is_linked == _FALSE)
1178 return;
1179
1180 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1181 if (psta == NULL)
1182 return;
1183
1184 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
1185
1186 phydm_watchdog_lps_32k(&pHalData->odmpriv);
1187
1188 #ifdef CONFIG_LPS_PG
1189 if (pwrpriv->lps_level == LPS_PG) {
1190 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
1191 RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n",
1192 FUNC_ADPT_ARG(adapter));
1193 }
1194 #endif /* CONFIG_LPS_PG */
1195 }
1196
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)1197 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
1198 {
1199 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1200 struct sta_priv *pstapriv = &adapter->stapriv;
1201 u8 cur_igi = 0;
1202 s8 min_rssi = 0;
1203
1204 if (!rtw_is_hw_init_completed(adapter))
1205 return;
1206
1207 cur_igi = rtw_phydm_get_cur_igi(adapter);
1208 min_rssi = rtw_dm_get_min_rssi(adapter);
1209 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
1210
1211 if (min_rssi <= 0)
1212 return;
1213
1214 if ((cur_igi > min_rssi + 5) ||
1215 (cur_igi < min_rssi - 5)) {
1216 #ifdef CONFIG_LPS
1217 rtw_dm_in_lps_wk_cmd(adapter);
1218 #endif
1219 }
1220 }
1221 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1222
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)1223 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
1224 {
1225 struct ra_sta_info *ra_info;
1226 u8 curr_sgi = _FALSE;
1227 u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
1228
1229 if (!psta)
1230 return;
1231 RTW_PRINT_SEL(sel, "\n");
1232 RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
1233 psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
1234
1235 if (is_client_associated_to_ap(psta->padapter))
1236 RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
1237 rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
1238
1239 ra_info = &psta->cmn.ra_info;
1240 curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
1241 RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
1242 , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
1243 , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
1244 );
1245
1246 if (0) {
1247 RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
1248 , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
1249 , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
1250 );
1251 RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
1252 , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
1253 , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
1254 );
1255 RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
1256 , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
1257 , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
1258 );
1259 RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
1260 , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
1261 , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
1262 );
1263 }
1264
1265 _RTW_PRINT_SEL(sel, "RTW: [TP] ");
1266 tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
1267 rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
1268 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1269
1270 if (tx_tp_mbips)
1271 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1272 else
1273 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
1274
1275 if (rx_tp_mbips)
1276 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1277 else
1278 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
1279
1280 if (bi_tp_mbips)
1281 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1282 else
1283 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1284
1285
1286 _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
1287 tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
1288 rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
1289 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1290 if (tx_tp_mbips)
1291 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1292 else
1293 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
1294
1295 if (rx_tp_mbips)
1296 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1297 else
1298 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
1299
1300 if (bi_tp_mbips)
1301 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1302 else
1303 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1304
1305 #if 0
1306 RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
1307 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
1308 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
1309 #endif
1310 }
1311
dump_sta_info(void * sel,struct sta_info * psta)1312 void dump_sta_info(void *sel, struct sta_info *psta)
1313 {
1314 struct ra_sta_info *ra_info;
1315 u8 curr_tx_sgi = _FALSE;
1316 u8 curr_tx_rate = 0;
1317
1318 if (!psta)
1319 return;
1320
1321 ra_info = &psta->cmn.ra_info;
1322
1323 RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
1324 MAC_ARG(psta->cmn.mac_addr));
1325 RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
1326 RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
1327 RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
1328 RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
1329 RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
1330 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
1331 RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
1332 RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
1333 RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
1334 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
1335 RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
1336 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
1337 RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
1338 RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
1339
1340 curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
1341 curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
1342 RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
1343 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
1344 RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
1345 RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
1346 RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
1347 }
1348
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)1349 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
1350 {
1351 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1352 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1353 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
1354
1355 if (psta == NULL) {
1356 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
1357 rtw_warn_on(1);
1358 return;
1359 }
1360
1361 if (psta->cmn.mac_id >= macid_ctl->num)
1362 return;
1363
1364 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
1365 dump_sta_info(RTW_DBGDUMP, psta);
1366 }
1367
init_phydm_info(_adapter * adapter)1368 static void init_phydm_info(_adapter *adapter)
1369 {
1370 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1371 struct dm_struct *phydm = &(hal_data->odmpriv);
1372
1373 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
1374 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
1375 }
1376
1377 #ifdef CONFIG_CTRL_TXSS_BY_TP
rtw_phydm_trx_cfg(_adapter * adapter,bool tx_1ss)1378 void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
1379 {
1380 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1381 enum bb_path txpath = BB_PATH_AB;
1382 enum bb_path rxpath = BB_PATH_AB;
1383 /*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
1384 enum bb_path txpath_1ss = BB_PATH_A;
1385
1386 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1387 txpath = (tx_1ss) ? BB_PATH_A : txpath;
1388
1389 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
1390 RTW_ERR("%s failed\n", __func__);
1391 }
1392 #endif
1393
1394
1395 /*
1396 * trx_mode init - 8822B / 8822C / 8192F
1397 * 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
1398 * Path-diversity - 8822B / 8822C / 8192F
1399 * PHYDM API - phydm_api_trx_mode
1400 */
rtw_phydm_config_trx_path(_adapter * adapter)1401 static u8 rtw_phydm_config_trx_path(_adapter *adapter)
1402 {
1403 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1404 enum bb_path txpath;
1405 enum bb_path rxpath;
1406 int i;
1407 u8 rst = _FAIL;
1408
1409 rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1410 if (!txpath) {
1411 RTW_ERR("%s tx_path_bmp is empty\n", __func__);
1412 rtw_warn_on(1);
1413 goto exit;
1414 }
1415 if (!rxpath) {
1416 RTW_ERR("%s rx_path_bmp is empty\n", __func__);
1417 rtw_warn_on(1);
1418 goto exit;
1419 }
1420
1421 tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
1422 , GET_HAL_TX_PATH_BMP(adapter));
1423
1424 #if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
1425 {
1426 enum bb_path txpath_1ss;
1427
1428 if (txpath == BB_PATH_AB) {
1429 switch (hal_data->max_tx_cnt) {
1430 case 2:
1431 #ifdef CONFIG_RTW_TX_NPATH_EN
1432 if (adapter->registrypriv.tx_npath == 1)
1433 txpath_1ss = BB_PATH_AB;
1434 else
1435 #endif
1436 #ifdef CONFIG_RTW_PATH_DIV
1437 if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
1438 txpath_1ss = BB_PATH_AUTO;
1439 else
1440 #endif
1441 txpath_1ss = BB_PATH_A;
1442 break;
1443 case 1:
1444 #ifdef CONFIG_RTW_PATH_DIV
1445 if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
1446 txpath = txpath_1ss = BB_PATH_AUTO;
1447 else
1448 #endif
1449 txpath = txpath_1ss = BB_PATH_A;
1450 break;
1451 default:
1452 RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
1453 , hal_data->max_tx_cnt);
1454 rtw_warn_on(1);
1455 goto exit;
1456 }
1457 } else
1458 txpath_1ss = txpath;
1459
1460 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
1461 RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
1462 , txpath, rxpath, txpath_1ss);
1463 rtw_warn_on(1);
1464 goto exit;
1465 }
1466
1467 if (hal_data->txpath_nss[0] != txpath_1ss) {
1468 hal_data->txpath_nss[0] = txpath_1ss;
1469 if (txpath_1ss == BB_PATH_AUTO)
1470 hal_data->txpath_num_nss[0] = 1;
1471 else {
1472 hal_data->txpath_num_nss[0] = 0;
1473 for (i = 0; i < RF_PATH_MAX; i++) {
1474 if (txpath_1ss & BIT(i))
1475 hal_data->txpath_num_nss[0]++;
1476 }
1477 }
1478 }
1479 }
1480 #elif defined(CONFIG_RTL8814B)
1481 {
1482 if (config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath) == FALSE) {
1483 RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
1484 , txpath, rxpath);
1485 rtw_warn_on(1);
1486 goto exit;
1487 }
1488
1489 /* 8814B is always full-TX */
1490 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1491 }
1492 #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
1493 {
1494 #ifdef CONFIG_RTW_TX_NPATH_EN
1495 if (adapter->registrypriv.tx_npath == 1) {
1496 phydm_tx_2path(adapter_to_phydm(adapter));
1497 tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
1498 }
1499 #endif
1500 }
1501 #endif
1502
1503 hal_data->txpath = txpath;
1504 hal_data->rxpath = rxpath;
1505 dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
1506 rst = _SUCCESS;
1507
1508 exit:
1509 return rst;
1510 }
1511
rtw_phydm_init(_adapter * adapter)1512 void rtw_phydm_init(_adapter *adapter)
1513 {
1514 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1515 struct dm_struct *phydm = &(hal_data->odmpriv);
1516
1517 rtw_phydm_config_trx_path(adapter);
1518 init_phydm_info(adapter);
1519 hal_data->phydm_init_result = odm_dm_init(phydm);
1520
1521 #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
1522 phydm_pathb_q_matrix_rotate_en(phydm);
1523 #endif
1524 }
1525
rtw_phydm_set_crystal_cap(_adapter * adapter,u8 crystal_cap)1526 bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
1527 {
1528 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1529 struct dm_struct *phydm = &(hal_data->odmpriv);
1530
1531 return phydm_set_crystal_cap_reg(phydm, crystal_cap);
1532 }
1533
1534 #ifdef CONFIG_LPS_PG
1535 /*
1536 static void _lps_pg_state_update(_adapter *adapter)
1537 {
1538 u8 is_in_lpspg = _FALSE;
1539 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1540 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1541 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1542 struct sta_priv *pstapriv = &adapter->stapriv;
1543 struct sta_info *psta = NULL;
1544
1545 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1546 is_in_lpspg = _TRUE;
1547 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1548
1549 if (psta)
1550 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1551 }
1552 */
rtw_phydm_lps_pg_hdl(_adapter * adapter,struct sta_info * sta,bool in_lpspg)1553 void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
1554 {
1555 struct dm_struct *phydm = adapter_to_phydm(adapter);
1556 /*u8 rate_id;*/
1557
1558 if(sta == NULL) {
1559 RTW_ERR("%s sta is null\n", __func__);
1560 rtw_warn_on(1);
1561 return;
1562 }
1563
1564 if (in_lpspg) {
1565 sta->cmn.ra_info.disable_ra = _TRUE;
1566 sta->cmn.ra_info.disable_pt = _TRUE;
1567 /*TODO : DRV fix tx rate*/
1568 /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
1569 } else {
1570 sta->cmn.ra_info.disable_ra = _FALSE;
1571 sta->cmn.ra_info.disable_pt = _FALSE;
1572 }
1573
1574 rtw_phydm_ra_registed(adapter, sta);
1575 }
1576 #endif
1577
1578 /*#define DBG_PHYDM_STATE_CHK*/
1579
1580
_rtw_phydm_rfk_condition_check(_adapter * adapter,u8 is_scaning,u8 ifs_linked)1581 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
1582 {
1583 u8 rfk_allowed = _TRUE;
1584
1585 #ifdef CONFIG_SKIP_RFK_IN_DM
1586 rfk_allowed = _FALSE;
1587 if (0)
1588 RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
1589 return rfk_allowed;
1590 #endif
1591
1592 #ifdef CONFIG_MCC_MODE
1593 /*not in MCC State*/
1594 if (MCC_EN(adapter) &&
1595 rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
1596 rfk_allowed = _FALSE;
1597 if (0)
1598 RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
1599 return rfk_allowed;
1600 }
1601 #endif
1602
1603 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1604
1605 #endif
1606
1607 if (ifs_linked) {
1608 if (is_scaning) {
1609 rfk_allowed = _FALSE;
1610 RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
1611 }
1612 else {
1613 rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
1614 if (rfk_allowed == _FALSE)
1615 RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
1616 }
1617 }
1618
1619 return rfk_allowed;
1620 }
1621
1622 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter,u8 ifs_linked)1623 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
1624 {
1625 u8 iqk_sgt = _FALSE;
1626
1627 #if 0
1628 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1629 if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
1630 rst = _TRUE;
1631 #else
1632 if (ifs_linked)
1633 iqk_sgt = _TRUE;
1634 #endif
1635 return iqk_sgt;
1636 }
1637 #endif
1638
1639 /*check the tx low rate while unlinked to any AP;for pwr tracking */
_rtw_phydm_pwr_tracking_rate_check(_adapter * adapter)1640 static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
1641 {
1642 int i;
1643 _adapter *iface;
1644 u8 if_tx_rate = 0xFF;
1645 u8 tx_rate = 0xFF;
1646 struct mlme_ext_priv *pmlmeext = NULL;
1647 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1648 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1649 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
1650
1651 for (i = 0; i < dvobj->iface_nums; i++) {
1652 iface = dvobj->padapters[i];
1653 pmlmeext = &(iface->mlmeextpriv);
1654 if ((iface) && rtw_is_adapter_up(iface)) {
1655 #ifdef CONFIG_P2P
1656 if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
1657 if_tx_rate = IEEE80211_OFDM_RATE_6MB;
1658 else
1659 #endif
1660 if_tx_rate = pmlmeext->tx_rate;
1661
1662 if (if_tx_rate < tx_rate) {
1663 /*5G limit ofdm rate*/
1664 if (pHalData->current_channel > 14) {
1665 if (!IS_CCK_RATE(if_tx_rate))
1666 tx_rate = if_tx_rate;
1667 } else {
1668 tx_rate = if_tx_rate;
1669 }
1670 }
1671 RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
1672 }
1673 }
1674
1675 /*suggest by RF James,unlinked setting ofdm rate*/
1676 if (tx_rate == 0xFF)
1677 tx_rate = IEEE80211_OFDM_RATE_6MB;
1678
1679 RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
1680 return tx_rate;
1681 }
1682
1683 #ifdef CONFIG_DYNAMIC_SOML
rtw_dyn_soml_byte_update(_adapter * adapter,u8 data_rate,u32 size)1684 void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
1685 {
1686 struct dm_struct *phydm = adapter_to_phydm(adapter);
1687
1688 phydm_soml_bytes_acq(phydm, data_rate, size);
1689 }
1690
rtw_dyn_soml_para_set(_adapter * adapter,u8 train_num,u8 intvl,u8 period,u8 delay)1691 void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
1692 u8 period, u8 delay)
1693 {
1694 struct dm_struct *phydm = adapter_to_phydm(adapter);
1695
1696 phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
1697 RTW_INFO("%s.\n", __func__);
1698 }
1699
rtw_dyn_soml_config(_adapter * adapter)1700 void rtw_dyn_soml_config(_adapter *adapter)
1701 {
1702 RTW_INFO("%s.\n", __func__);
1703
1704 if (adapter->registrypriv.dyn_soml_en == 1) {
1705 /* Must after phydm_adaptive_soml_init() */
1706 rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
1707 RTW_INFO("dyn_soml_en = 1\n");
1708 } else {
1709 if (adapter->registrypriv.dyn_soml_en == 2) {
1710 rtw_dyn_soml_para_set(adapter,
1711 adapter->registrypriv.dyn_soml_train_num,
1712 adapter->registrypriv.dyn_soml_interval,
1713 adapter->registrypriv.dyn_soml_period,
1714 adapter->registrypriv.dyn_soml_delay);
1715 RTW_INFO("dyn_soml_en = 2\n");
1716 RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
1717 adapter->registrypriv.dyn_soml_train_num,
1718 adapter->registrypriv.dyn_soml_interval,
1719 adapter->registrypriv.dyn_soml_period,
1720 adapter->registrypriv.dyn_soml_delay);
1721 } else if (adapter->registrypriv.dyn_soml_en == 0) {
1722 RTW_INFO("dyn_soml_en = 0\n");
1723 } else
1724 RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
1725 adapter->registrypriv.dyn_soml_en);
1726 }
1727 }
1728 #endif
1729
rtw_phydm_set_rrsr(_adapter * adapter,u32 rrsr_value,bool write_rrsr)1730 void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
1731 {
1732 struct dm_struct *phydm = adapter_to_phydm(adapter);
1733 u32 temp_rrsr =0xFFFFFFFF;
1734
1735 if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
1736 temp_rrsr = adapter->registrypriv.set_rrsr_value;
1737 else
1738 temp_rrsr = rrsr_value;
1739
1740 odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
1741 if(write_rrsr)
1742 phydm_rrsr_set_register(phydm, temp_rrsr);
1743 }
rtw_phydm_dyn_rrsr_en(_adapter * adapter,bool en_rrsr)1744 void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
1745 {
1746 struct dm_struct *phydm = adapter_to_phydm(adapter);
1747
1748 phydm_rrsr_en(phydm, en_rrsr);
1749 }
rtw_phydm_read_efuse(_adapter * adapter)1750 void rtw_phydm_read_efuse(_adapter *adapter)
1751 {
1752 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1753 struct dm_struct *phydm = &(hal_data->odmpriv);
1754
1755 /*PHYDM API - thermal trim*/
1756 phydm_get_thermal_trim_offset(phydm);
1757 /*PHYDM API - power trim*/
1758 phydm_get_power_trim_offset(phydm);
1759 }
1760
1761 #ifdef CONFIG_LPS_PWR_TRACKING
rtw_phydm_pwr_tracking_directly(_adapter * adapter)1762 void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
1763 {
1764 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1765 u8 rfk_forbidden = _TRUE;
1766 u8 is_linked = _FALSE;
1767
1768 if (rtw_mi_check_status(adapter, MI_ASSOC))
1769 is_linked = _TRUE;
1770
1771 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
1772 halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1773
1774 odm_txpowertracking_direct_ce(&hal_data->odmpriv);
1775 }
1776 #endif
1777
rtw_phydm_watchdog(_adapter * adapter,bool in_lps)1778 void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
1779 {
1780 u8 bLinked = _FALSE;
1781 u8 bsta_state = _FALSE;
1782 u8 bBtDisabled = _TRUE;
1783 u8 rfk_forbidden = _FALSE;
1784 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1785 u8 segment_iqk = _FALSE;
1786 #endif
1787 u8 tx_unlinked_low_rate = 0xFF;
1788 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1789
1790 if (!rtw_is_hw_init_completed(adapter)) {
1791 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1792 return;
1793 }
1794 if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
1795 pHalData->bScanInProcess = _TRUE;
1796 else
1797 pHalData->bScanInProcess = _FALSE;
1798
1799 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1800 bLinked = _TRUE;
1801 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1802 bsta_state = _TRUE;
1803 }
1804
1805 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1806 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1807
1808 #ifdef CONFIG_BT_COEXIST
1809 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1810 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1811 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1812 #else
1813 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
1814 #endif /* CONFIG_BT_COEXIST */
1815
1816 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
1817 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1818
1819 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1820 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
1821 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1822 #endif
1823 #ifdef DBG_PHYDM_STATE_CHK
1824 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1825 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1826 #endif
1827
1828 if (bLinked == _FALSE) {
1829 tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
1830 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
1831 }
1832
1833 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1834 #ifdef DBG_PHYDM_STATE_CHK
1835 RTW_ERR("Not stay in union band, skip phydm\n");
1836 #endif
1837 goto _exit;
1838 }*/
1839
1840 #ifdef CONFIG_TDMADIG
1841 rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
1842 #endif/*CONFIG_TDMADIG*/
1843
1844 if (in_lps)
1845 phydm_watchdog_lps(&pHalData->odmpriv);
1846 else
1847 phydm_watchdog(&pHalData->odmpriv);
1848
1849 #ifdef CONFIG_RTW_ACS
1850 rtw_acs_update_current_info(adapter);
1851 #endif
1852
1853 return;
1854 }
1855
1856
1857