1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8188FPHYREG_H__ 16 #define __INC_HAL8188FPHYREG_H__ 17 18 /*--------------------------Define Parameters-------------------------------*/ 19 20 /* ************************************************************ 21 * Regsiter offset definition 22 * ************************************************************ */ 23 24 /* 25 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 26 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 27 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 28 * 3. RF register 0x00-2E 29 * 4. Bit Mask for BB/RF register 30 * 5. Other defintion for BB/RF R/W 31 * */ 32 33 34 /* 35 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 36 * 1. Page1(0x100) 37 * */ 38 #define rPMAC_Reset 0x100 39 #define rPMAC_TxStart 0x104 40 #define rPMAC_TxLegacySIG 0x108 41 #define rPMAC_TxHTSIG1 0x10c 42 #define rPMAC_TxHTSIG2 0x110 43 #define rPMAC_PHYDebug 0x114 44 #define rPMAC_TxPacketNum 0x118 45 #define rPMAC_TxIdle 0x11c 46 #define rPMAC_TxMACHeader0 0x120 47 #define rPMAC_TxMACHeader1 0x124 48 #define rPMAC_TxMACHeader2 0x128 49 #define rPMAC_TxMACHeader3 0x12c 50 #define rPMAC_TxMACHeader4 0x130 51 #define rPMAC_TxMACHeader5 0x134 52 #define rPMAC_TxDataType 0x138 53 #define rPMAC_TxRandomSeed 0x13c 54 #define rPMAC_CCKPLCPPreamble 0x140 55 #define rPMAC_CCKPLCPHeader 0x144 56 #define rPMAC_CCKCRC16 0x148 57 #define rPMAC_OFDMRxCRC32OK 0x170 58 #define rPMAC_OFDMRxCRC32Er 0x174 59 #define rPMAC_OFDMRxParityEr 0x178 60 #define rPMAC_OFDMRxCRC8Er 0x17c 61 #define rPMAC_CCKCRxRC16Er 0x180 62 #define rPMAC_CCKCRxRC32Er 0x184 63 #define rPMAC_CCKCRxRC32OK 0x188 64 #define rPMAC_TxStatus 0x18c 65 66 /* 67 * 2. Page2(0x200) 68 * 69 * The following two definition are only used for USB interface. */ 70 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 71 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 72 73 /* 74 * 3. Page8(0x800) 75 * */ 76 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 77 78 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 79 #define rFPGA0_PSDFunction 0x808 80 81 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 82 83 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 84 #define rFPGA0_RFTiming2 0x814 85 86 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 87 #define rFPGA0_XA_HSSIParameter2 0x824 88 #define rFPGA0_XB_HSSIParameter1 0x828 89 #define rFPGA0_XB_HSSIParameter2 0x82c 90 #define rTxAGC_B_Rate18_06 0x830 91 #define rTxAGC_B_Rate54_24 0x834 92 #define rTxAGC_B_CCK1_55_Mcs32 0x838 93 #define rTxAGC_B_Mcs03_Mcs00 0x83c 94 95 #define rTxAGC_B_Mcs07_Mcs04 0x848 96 #define rTxAGC_B_Mcs11_Mcs08 0x84c 97 98 #define rFPGA0_XA_LSSIParameter 0x840 99 #define rFPGA0_XB_LSSIParameter 0x844 100 101 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 102 #define rFPGA0_RFSleepUpParameter 0x854 103 104 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 105 #define rFPGA0_XCD_SwitchControl 0x85c 106 107 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 108 #define rFPGA0_XB_RFInterfaceOE 0x864 109 110 #define rTxAGC_B_Mcs15_Mcs12 0x868 111 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 112 113 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 114 #define rFPGA0_XCD_RFInterfaceSW 0x874 115 116 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 117 #define rFPGA0_XCD_RFParameter 0x87c 118 119 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 120 #define rFPGA0_AnalogParameter2 0x884 121 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 122 #define rFPGA0_AnalogParameter4 0x88c 123 124 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 125 #define rFPGA0_XB_LSSIReadBack 0x8a4 126 #define rFPGA0_XC_LSSIReadBack 0x8a8 127 #define rFPGA0_XD_LSSIReadBack 0x8ac 128 129 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 130 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 131 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 132 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 133 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 134 135 /* 136 * 4. Page9(0x900) 137 * */ 138 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 139 140 #define rFPGA1_TxBlock 0x904 /* Useless now */ 141 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 142 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 143 #define rS0S1_PathSwitch 0x948 144 145 /* 146 * 5. PageA(0xA00) 147 * 148 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 149 #define rCCK0_System 0xa00 150 151 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 152 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 153 154 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 155 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 156 157 #define rCCK0_RxHP 0xa14 158 159 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 160 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 161 162 #define rCCK0_TxFilter1 0xa20 163 #define rCCK0_TxFilter2 0xa24 164 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 165 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 166 #define rCCK0_TRSSIReport 0xa50 167 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 168 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 169 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c 170 * 171 * PageB(0xB00) 172 * */ 173 #define rPdp_AntA 0xb00 174 #define rPdp_AntA_4 0xb04 175 #define rConfig_Pmpd_AntA 0xb28 176 #define rConfig_AntA 0xb68 177 #define rConfig_AntB 0xb6c 178 #define rPdp_AntB 0xb70 179 #define rPdp_AntB_4 0xb74 180 #define rConfig_Pmpd_AntB 0xb98 181 #define rAPK 0xbd8 182 183 /* 184 * 6. PageC(0xC00) 185 * */ 186 #define rOFDM0_LSTF 0xc00 187 188 #define rOFDM0_TRxPathEnable 0xc04 189 #define rOFDM0_TRMuxPar 0xc08 190 #define rOFDM0_TRSWIsolation 0xc0c 191 192 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 193 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 194 #define rOFDM0_XBRxAFE 0xc18 195 #define rOFDM0_XBRxIQImbalance 0xc1c 196 #define rOFDM0_XCRxAFE 0xc20 197 #define rOFDM0_XCRxIQImbalance 0xc24 198 #define rOFDM0_XDRxAFE 0xc28 199 #define rOFDM0_XDRxIQImbalance 0xc2c 200 201 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 202 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 203 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 204 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 205 206 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 207 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 208 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 209 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 210 211 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 212 #define rOFDM0_XAAGCCore2 0xc54 213 #define rOFDM0_XBAGCCore1 0xc58 214 #define rOFDM0_XBAGCCore2 0xc5c 215 #define rOFDM0_XCAGCCore1 0xc60 216 #define rOFDM0_XCAGCCore2 0xc64 217 #define rOFDM0_XDAGCCore1 0xc68 218 #define rOFDM0_XDAGCCore2 0xc6c 219 220 #define rOFDM0_AGCParameter1 0xc70 221 #define rOFDM0_AGCParameter2 0xc74 222 #define rOFDM0_AGCRSSITable 0xc78 223 #define rOFDM0_HTSTFAGC 0xc7c 224 225 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 226 #define rOFDM0_XATxAFE 0xc84 227 #define rOFDM0_XBTxIQImbalance 0xc88 228 #define rOFDM0_XBTxAFE 0xc8c 229 #define rOFDM0_XCTxIQImbalance 0xc90 230 #define rOFDM0_XCTxAFE 0xc94 231 #define rOFDM0_XDTxIQImbalance 0xc98 232 #define rOFDM0_XDTxAFE 0xc9c 233 234 #define rOFDM0_RxIQExtAnta 0xca0 235 #define rOFDM0_TxCoeff1 0xca4 236 #define rOFDM0_TxCoeff2 0xca8 237 #define rOFDM0_TxCoeff3 0xcac 238 #define rOFDM0_TxCoeff4 0xcb0 239 #define rOFDM0_TxCoeff5 0xcb4 240 #define rOFDM0_TxCoeff6 0xcb8 241 #define rOFDM0_RxHPParameter 0xce0 242 #define rOFDM0_TxPseudoNoiseWgt 0xce4 243 #define rOFDM0_FrameSync 0xcf0 244 #define rOFDM0_DFSReport 0xcf4 245 246 /* 247 * 7. PageD(0xD00) 248 * */ 249 #define rOFDM1_LSTF 0xd00 250 #define rOFDM1_TRxPathEnable 0xd04 251 252 #define rOFDM1_CFO 0xd08 /* No setting now */ 253 #define rOFDM1_CSI1 0xd10 254 #define rOFDM1_SBD 0xd14 255 #define rOFDM1_CSI2 0xd18 256 #define rOFDM1_CFOTracking 0xd2c 257 #define rOFDM1_TRxMesaure1 0xd34 258 #define rOFDM1_IntfDet 0xd3c 259 #define rOFDM1_PseudoNoiseStateAB 0xd50 260 #define rOFDM1_PseudoNoiseStateCD 0xd54 261 #define rOFDM1_RxPseudoNoiseWgt 0xd58 262 263 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 264 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 265 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 266 267 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 268 #define rOFDM_ShortCFOCD 0xdb0 269 #define rOFDM_LongCFOAB 0xdb4 270 #define rOFDM_LongCFOCD 0xdb8 271 #define rOFDM_TailCFOAB 0xdbc 272 #define rOFDM_TailCFOCD 0xdc0 273 #define rOFDM_PWMeasure1 0xdc4 274 #define rOFDM_PWMeasure2 0xdc8 275 #define rOFDM_BWReport 0xdcc 276 #define rOFDM_AGCReport 0xdd0 277 #define rOFDM_RxSNR 0xdd4 278 #define rOFDM_RxEVMCSI 0xdd8 279 #define rOFDM_SIGReport 0xddc 280 281 282 /* 283 * 8. PageE(0xE00) 284 * */ 285 #define rTxAGC_A_Rate18_06 0xe00 286 #define rTxAGC_A_Rate54_24 0xe04 287 #define rTxAGC_A_CCK1_Mcs32 0xe08 288 #define rTxAGC_A_Mcs03_Mcs00 0xe10 289 #define rTxAGC_A_Mcs07_Mcs04 0xe14 290 #define rTxAGC_A_Mcs11_Mcs08 0xe18 291 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 292 293 #define rFPGA0_IQK 0xe28 294 #define rTx_IQK_Tone_A 0xe30 295 #define rRx_IQK_Tone_A 0xe34 296 #define rTx_IQK_PI_A 0xe38 297 #define rRx_IQK_PI_A 0xe3c 298 299 #define rTx_IQK 0xe40 300 #define rRx_IQK 0xe44 301 #define rIQK_AGC_Pts 0xe48 302 #define rIQK_AGC_Rsp 0xe4c 303 #define rTx_IQK_Tone_B 0xe50 304 #define rRx_IQK_Tone_B 0xe54 305 #define rTx_IQK_PI_B 0xe58 306 #define rRx_IQK_PI_B 0xe5c 307 #define rIQK_AGC_Cont 0xe60 308 309 #define rBlue_Tooth 0xe6c 310 #define rRx_Wait_CCA 0xe70 311 #define rTx_CCK_RFON 0xe74 312 #define rTx_CCK_BBON 0xe78 313 #define rTx_OFDM_RFON 0xe7c 314 #define rTx_OFDM_BBON 0xe80 315 #define rTx_To_Rx 0xe84 316 #define rTx_To_Tx 0xe88 317 #define rRx_CCK 0xe8c 318 319 #define rTx_Power_Before_IQK_A 0xe94 320 #define rTx_Power_After_IQK_A 0xe9c 321 322 #define rRx_Power_Before_IQK_A 0xea0 323 #define rRx_Power_Before_IQK_A_2 0xea4 324 #define rRx_Power_After_IQK_A 0xea8 325 #define rRx_Power_After_IQK_A_2 0xeac 326 327 #define rTx_Power_Before_IQK_B 0xeb4 328 #define rTx_Power_After_IQK_B 0xebc 329 330 #define rRx_Power_Before_IQK_B 0xec0 331 #define rRx_Power_Before_IQK_B_2 0xec4 332 #define rRx_Power_After_IQK_B 0xec8 333 #define rRx_Power_After_IQK_B_2 0xecc 334 335 #define rRx_OFDM 0xed0 336 #define rRx_Wait_RIFS 0xed4 337 #define rRx_TO_Rx 0xed8 338 #define rStandby 0xedc 339 #define rSleep 0xee0 340 #define rPMPD_ANAEN 0xeec 341 342 /* 343 * 7. RF Register 0x00-0x2E (RF 8256) 344 * RF-0222D 0x00-3F 345 * 346 * Zebra1 */ 347 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 348 #define rZebra1_TRxEnable1 0x1 349 #define rZebra1_TRxEnable2 0x2 350 #define rZebra1_AGC 0x4 351 #define rZebra1_ChargePump 0x5 352 #define rZebra1_Channel 0x7 /* RF channel switch */ 353 354 /* #endif */ 355 #define rZebra1_TxGain 0x8 /* Useless now */ 356 #define rZebra1_TxLPF 0x9 357 #define rZebra1_RxLPF 0xb 358 #define rZebra1_RxHPFCorner 0xc 359 360 /* Zebra4 */ 361 #define rGlobalCtrl 0 /* Useless now */ 362 #define rRTL8256_TxLPF 19 363 #define rRTL8256_RxLPF 11 364 365 /* RTL8258 */ 366 #define rRTL8258_TxLPF 0x11 /* Useless now */ 367 #define rRTL8258_RxLPF 0x13 368 #define rRTL8258_RSSILPF 0xa 369 370 /* 371 * RL6052 Register definition 372 * */ 373 #define RF_AC 0x00 /* */ 374 375 #define RF_IQADJ_G1 0x01 /* */ 376 #define RF_IQADJ_G2 0x02 /* */ 377 #define RF_BS_PA_APSET_G1_G4 0x03 378 #define RF_BS_PA_APSET_G5_G8 0x04 379 #define RF_POW_TRSW 0x05 /* */ 380 381 #define RF_GAIN_RX 0x06 /* */ 382 #define RF_GAIN_TX 0x07 /* */ 383 384 #define RF_TXM_IDAC 0x08 /* */ 385 #define RF_IPA_G 0x09 /* */ 386 #define RF_TXBIAS_G 0x0A 387 #define RF_TXPA_AG 0x0B 388 #define RF_IPA_A 0x0C /* */ 389 #define RF_TXBIAS_A 0x0D 390 #define RF_BS_PA_APSET_G9_G11 0x0E 391 #define RF_BS_IQGEN 0x0F /* */ 392 393 #define RF_MODE1 0x10 /* */ 394 #define RF_MODE2 0x11 /* */ 395 396 #define RF_RX_AGC_HP 0x12 /* */ 397 #define RF_TX_AGC 0x13 /* */ 398 #define RF_BIAS 0x14 /* */ 399 #define RF_IPA 0x15 /* */ 400 #define RF_TXBIAS 0x16 401 #define RF_POW_ABILITY 0x17 /* */ 402 #define RF_MODE_AG 0x18 /* */ 403 #define rRfChannel 0x18 /* RF channel and BW switch */ 404 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 405 #define RF_TOP 0x19 /* */ 406 407 #define RF_RX_G1 0x1A /* */ 408 #define RF_RX_G2 0x1B /* */ 409 410 #define RF_RX_BB2 0x1C /* */ 411 #define RF_RX_BB1 0x1D /* */ 412 413 #define RF_RCK1 0x1E /* */ 414 #define RF_RCK2 0x1F /* */ 415 416 #define RF_TX_G1 0x20 /* */ 417 #define RF_TX_G2 0x21 /* */ 418 #define RF_TX_G3 0x22 /* */ 419 420 #define RF_TX_BB1 0x23 /* */ 421 422 #define RF_T_METER 0x24 /* */ 423 424 #define RF_SYN_G1 0x25 /* RF TX Power control */ 425 #define RF_SYN_G2 0x26 /* RF TX Power control */ 426 #define RF_SYN_G3 0x27 /* RF TX Power control */ 427 #define RF_SYN_G4 0x28 /* RF TX Power control */ 428 #define RF_SYN_G5 0x29 /* RF TX Power control */ 429 #define RF_SYN_G6 0x2A /* RF TX Power control */ 430 #define RF_SYN_G7 0x2B /* RF TX Power control */ 431 #define RF_SYN_G8 0x2C /* RF TX Power control */ 432 433 #define RF_RCK_OS 0x30 /* RF TX PA control */ 434 435 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 436 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 437 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 438 #define RF_TX_BIAS_A 0x35 439 #define RF_TX_BIAS_D 0x36 440 #define RF_LOBF_9 0x38 441 #define RF_RXRF_A3 0x3C /* */ 442 #define RF_TRSW 0x3F 443 444 #define RF_TXRF_A2 0x41 445 #define RF_TXPA_G4 0x46 446 #define RF_TXPA_A4 0x4B 447 #define RF_0x52 0x52 448 #define RF_RXG_MIX_SWBW 0x87 449 #define RF_DBG_LP_RX2 0xDF 450 #define RF_WE_LUT 0xEF 451 #define RF_S0S1 0xB0 452 453 #define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0)) 454 455 /* 456 * Bit Mask 457 * 458 * 1. Page1(0x100) */ 459 #define bBBResetB 0x100 /* Useless now? */ 460 #define bGlobalResetB 0x200 461 #define bOFDMTxStart 0x4 462 #define bCCKTxStart 0x8 463 #define bCRC32Debug 0x100 464 #define bPMACLoopback 0x10 465 #define bTxLSIG 0xffffff 466 #define bOFDMTxRate 0xf 467 #define bOFDMTxReserved 0x10 468 #define bOFDMTxLength 0x1ffe0 469 #define bOFDMTxParity 0x20000 470 #define bTxHTSIG1 0xffffff 471 #define bTxHTMCSRate 0x7f 472 #define bTxHTBW 0x80 473 #define bTxHTLength 0xffff00 474 #define bTxHTSIG2 0xffffff 475 #define bTxHTSmoothing 0x1 476 #define bTxHTSounding 0x2 477 #define bTxHTReserved 0x4 478 #define bTxHTAggreation 0x8 479 #define bTxHTSTBC 0x30 480 #define bTxHTAdvanceCoding 0x40 481 #define bTxHTShortGI 0x80 482 #define bTxHTNumberHT_LTF 0x300 483 #define bTxHTCRC8 0x3fc00 484 #define bCounterReset 0x10000 485 #define bNumOfOFDMTx 0xffff 486 #define bNumOfCCKTx 0xffff0000 487 #define bTxIdleInterval 0xffff 488 #define bOFDMService 0xffff0000 489 #define bTxMACHeader 0xffffffff 490 #define bTxDataInit 0xff 491 #define bTxHTMode 0x100 492 #define bTxDataType 0x30000 493 #define bTxRandomSeed 0xffffffff 494 #define bCCKTxPreamble 0x1 495 #define bCCKTxSFD 0xffff0000 496 #define bCCKTxSIG 0xff 497 #define bCCKTxService 0xff00 498 #define bCCKLengthExt 0x8000 499 #define bCCKTxLength 0xffff0000 500 #define bCCKTxCRC16 0xffff 501 #define bCCKTxStatus 0x1 502 #define bOFDMTxStatus 0x2 503 504 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 505 506 /* 2. Page8(0x800) */ 507 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 508 #define bJapanMode 0x2 509 #define bCCKTxSC 0x30 510 #define bCCKEn 0x1000000 511 #define bOFDMEn 0x2000000 512 513 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 514 #define bOFDMTxDACPhase 0x40000 515 #define bXATxAGC 0x3f 516 517 #define bAntennaSelect 0x0300 518 519 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 520 #define bXCTxAGC 0xf000 521 #define bXDTxAGC 0xf0000 522 523 #define bPAStart 0xf0000000 /* Useless now */ 524 #define bTRStart 0x00f00000 525 #define bRFStart 0x0000f000 526 #define bBBStart 0x000000f0 527 #define bBBCCKStart 0x0000000f 528 #define bPAEnd 0xf /* Reg0x814 */ 529 #define bTREnd 0x0f000000 530 #define bRFEnd 0x000f0000 531 #define bCCAMask 0x000000f0 /* T2R */ 532 #define bR2RCCAMask 0x00000f00 533 #define bHSSI_R2TDelay 0xf8000000 534 #define bHSSI_T2RDelay 0xf80000 535 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 536 #define bIGFromCCK 0x200 537 #define bAGCAddress 0x3f 538 #define bRxHPTx 0x7000 539 #define bRxHPT2R 0x38000 540 #define bRxHPCCKIni 0xc0000 541 #define bAGCTxCode 0xc00000 542 #define bAGCRxCode 0x300000 543 544 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 545 #define b3WireAddressLength 0x400 546 547 #define b3WireRFPowerDown 0x1 /* Useless now 548 * #define bHWSISelect 0x8 */ 549 #define b5GPAPEPolarity 0x40000000 550 #define b2GPAPEPolarity 0x80000000 551 #define bRFSW_TxDefaultAnt 0x3 552 #define bRFSW_TxOptionAnt 0x30 553 #define bRFSW_RxDefaultAnt 0x300 554 #define bRFSW_RxOptionAnt 0x3000 555 #define bRFSI_3WireData 0x1 556 #define bRFSI_3WireClock 0x2 557 #define bRFSI_3WireLoad 0x4 558 #define bRFSI_3WireRW 0x8 559 #define bRFSI_3Wire 0xf 560 561 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 562 563 #define bRFSI_TRSW 0x20 /* Useless now */ 564 #define bRFSI_TRSWB 0x40 565 #define bRFSI_ANTSW 0x100 566 #define bRFSI_ANTSWB 0x200 567 #define bRFSI_PAPE 0x400 568 #define bRFSI_PAPE5G 0x800 569 #define bBandSelect 0x1 570 #define bHTSIG2_GI 0x80 571 #define bHTSIG2_Smoothing 0x01 572 #define bHTSIG2_Sounding 0x02 573 #define bHTSIG2_Aggreaton 0x08 574 #define bHTSIG2_STBC 0x30 575 #define bHTSIG2_AdvCoding 0x40 576 #define bHTSIG2_NumOfHTLTF 0x300 577 #define bHTSIG2_CRC8 0x3fc 578 #define bHTSIG1_MCS 0x7f 579 #define bHTSIG1_BandWidth 0x80 580 #define bHTSIG1_HTLength 0xffff 581 #define bLSIG_Rate 0xf 582 #define bLSIG_Reserved 0x10 583 #define bLSIG_Length 0x1fffe 584 #define bLSIG_Parity 0x20 585 #define bCCKRxPhase 0x4 586 587 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 588 589 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 590 591 #define bLSSIReadBackData 0xfffff /* T65 RF */ 592 593 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 594 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 595 #define bRegulator0Standby 0x1 596 #define bRegulatorPLLStandby 0x2 597 #define bRegulator1Standby 0x4 598 #define bPLLPowerUp 0x8 599 #define bDPLLPowerUp 0x10 600 #define bDA10PowerUp 0x20 601 #define bAD7PowerUp 0x200 602 #define bDA6PowerUp 0x2000 603 #define bXtalPowerUp 0x4000 604 #define b40MDClkPowerUP 0x8000 605 #define bDA6DebugMode 0x20000 606 #define bDA6Swing 0x380000 607 608 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 609 610 #define b80MClkDelay 0x18000000 /* Useless */ 611 #define bAFEWatchDogEnable 0x20000000 612 613 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 614 #define bXtalCap23 0x3 615 #define bXtalCap92x 0x0f000000 616 #define bXtalCap 0x0f000000 617 618 #define bIntDifClkEnable 0x400 /* Useless */ 619 #define bExtSigClkEnable 0x800 620 #define bBandgapMbiasPowerUp 0x10000 621 #define bAD11SHGain 0xc0000 622 #define bAD11InputRange 0x700000 623 #define bAD11OPCurrent 0x3800000 624 #define bIPathLoopback 0x4000000 625 #define bQPathLoopback 0x8000000 626 #define bAFELoopback 0x10000000 627 #define bDA10Swing 0x7e0 628 #define bDA10Reverse 0x800 629 #define bDAClkSource 0x1000 630 #define bAD7InputRange 0x6000 631 #define bAD7Gain 0x38000 632 #define bAD7OutputCMMode 0x40000 633 #define bAD7InputCMMode 0x380000 634 #define bAD7Current 0xc00000 635 #define bRegulatorAdjust 0x7000000 636 #define bAD11PowerUpAtTx 0x1 637 #define bDA10PSAtTx 0x10 638 #define bAD11PowerUpAtRx 0x100 639 #define bDA10PSAtRx 0x1000 640 #define bCCKRxAGCFormat 0x200 641 #define bPSDFFTSamplepPoint 0xc000 642 #define bPSDAverageNum 0x3000 643 #define bIQPathControl 0xc00 644 #define bPSDFreq 0x3ff 645 #define bPSDAntennaPath 0x30 646 #define bPSDIQSwitch 0x40 647 #define bPSDRxTrigger 0x400000 648 #define bPSDTxTrigger 0x80000000 649 #define bPSDSineToneScale 0x7f000000 650 #define bPSDReport 0xffff 651 652 /* 3. Page9(0x900) */ 653 #define bOFDMTxSC 0x30000000 /* Useless */ 654 #define bCCKTxOn 0x1 655 #define bOFDMTxOn 0x2 656 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 657 #define bDebugItem 0xff /* reset debug page and LWord */ 658 #define bAntL 0x10 659 #define bAntNonHT 0x100 660 #define bAntHT1 0x1000 661 #define bAntHT2 0x10000 662 #define bAntHT1S1 0x100000 663 #define bAntNonHTS1 0x1000000 664 665 /* 4. PageA(0xA00) */ 666 #define bCCKBBMode 0x3 /* Useless */ 667 #define bCCKTxPowerSaving 0x80 668 #define bCCKRxPowerSaving 0x40 669 670 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 671 672 #define bCCKScramble 0x8 /* Useless */ 673 #define bCCKAntDiversity 0x8000 674 #define bCCKCarrierRecovery 0x4000 675 #define bCCKTxRate 0x3000 676 #define bCCKDCCancel 0x0800 677 #define bCCKISICancel 0x0400 678 #define bCCKMatchFilter 0x0200 679 #define bCCKEqualizer 0x0100 680 #define bCCKPreambleDetect 0x800000 681 #define bCCKFastFalseCCA 0x400000 682 #define bCCKChEstStart 0x300000 683 #define bCCKCCACount 0x080000 684 #define bCCKcs_lim 0x070000 685 #define bCCKBistMode 0x80000000 686 #define bCCKCCAMask 0x40000000 687 #define bCCKTxDACPhase 0x4 688 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 689 #define bCCKr_cp_mode0 0x0100 690 #define bCCKTxDCOffset 0xf0 691 #define bCCKRxDCOffset 0xf 692 #define bCCKCCAMode 0xc000 693 #define bCCKFalseCS_lim 0x3f00 694 #define bCCKCS_ratio 0xc00000 695 #define bCCKCorgBit_sel 0x300000 696 #define bCCKPD_lim 0x0f0000 697 #define bCCKNewCCA 0x80000000 698 #define bCCKRxHPofIG 0x8000 699 #define bCCKRxIG 0x7f00 700 #define bCCKLNAPolarity 0x800000 701 #define bCCKRx1stGain 0x7f0000 702 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 703 #define bCCKRxAGCSatLevel 0x1f000000 704 #define bCCKRxAGCSatCount 0xe0 705 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 706 #define bCCKFixedRxAGC 0x8000 707 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 708 #define bCCKAntennaPolarity 0x2000 709 #define bCCKTxFilterType 0x0c00 710 #define bCCKRxAGCReportType 0x0300 711 #define bCCKRxDAGCEn 0x80000000 712 #define bCCKRxDAGCPeriod 0x20000000 713 #define bCCKRxDAGCSatLevel 0x1f000000 714 #define bCCKTimingRecovery 0x800000 715 #define bCCKTxC0 0x3f0000 716 #define bCCKTxC1 0x3f000000 717 #define bCCKTxC2 0x3f 718 #define bCCKTxC3 0x3f00 719 #define bCCKTxC4 0x3f0000 720 #define bCCKTxC5 0x3f000000 721 #define bCCKTxC6 0x3f 722 #define bCCKTxC7 0x3f00 723 #define bCCKDebugPort 0xff0000 724 #define bCCKDACDebug 0x0f000000 725 #define bCCKFalseAlarmEnable 0x8000 726 #define bCCKFalseAlarmRead 0x4000 727 #define bCCKTRSSI 0x7f 728 #define bCCKRxAGCReport 0xfe 729 #define bCCKRxReport_AntSel 0x80000000 730 #define bCCKRxReport_MFOff 0x40000000 731 #define bCCKRxRxReport_SQLoss 0x20000000 732 #define bCCKRxReport_Pktloss 0x10000000 733 #define bCCKRxReport_Lockedbit 0x08000000 734 #define bCCKRxReport_RateError 0x04000000 735 #define bCCKRxReport_RxRate 0x03000000 736 #define bCCKRxFACounterLower 0xff 737 #define bCCKRxFACounterUpper 0xff000000 738 #define bCCKRxHPAGCStart 0xe000 739 #define bCCKRxHPAGCFinal 0x1c00 740 #define bCCKRxFalseAlarmEnable 0x8000 741 #define bCCKFACounterFreeze 0x4000 742 #define bCCKTxPathSel 0x10000000 743 #define bCCKDefaultRxPath 0xc000000 744 #define bCCKOptionRxPath 0x3000000 745 746 /* 5. PageC(0xC00) */ 747 #define bNumOfSTF 0x3 /* Useless */ 748 #define bShift_L 0xc0 749 #define bGI_TH 0xc 750 #define bRxPathA 0x1 751 #define bRxPathB 0x2 752 #define bRxPathC 0x4 753 #define bRxPathD 0x8 754 #define bTxPathA 0x1 755 #define bTxPathB 0x2 756 #define bTxPathC 0x4 757 #define bTxPathD 0x8 758 #define bTRSSIFreq 0x200 759 #define bADCBackoff 0x3000 760 #define bDFIRBackoff 0xc000 761 #define bTRSSILatchPhase 0x10000 762 #define bRxIDCOffset 0xff 763 #define bRxQDCOffset 0xff00 764 #define bRxDFIRMode 0x1800000 765 #define bRxDCNFType 0xe000000 766 #define bRXIQImb_A 0x3ff 767 #define bRXIQImb_B 0xfc00 768 #define bRXIQImb_C 0x3f0000 769 #define bRXIQImb_D 0xffc00000 770 #define bDC_dc_Notch 0x60000 771 #define bRxNBINotch 0x1f000000 772 #define bPD_TH 0xf 773 #define bPD_TH_Opt2 0xc000 774 #define bPWED_TH 0x700 775 #define bIfMF_Win_L 0x800 776 #define bPD_Option 0x1000 777 #define bMF_Win_L 0xe000 778 #define bBW_Search_L 0x30000 779 #define bwin_enh_L 0xc0000 780 #define bBW_TH 0x700000 781 #define bED_TH2 0x3800000 782 #define bBW_option 0x4000000 783 #define bRatio_TH 0x18000000 784 #define bWindow_L 0xe0000000 785 #define bSBD_Option 0x1 786 #define bFrame_TH 0x1c 787 #define bFS_Option 0x60 788 #define bDC_Slope_check 0x80 789 #define bFGuard_Counter_DC_L 0xe00 790 #define bFrame_Weight_Short 0x7000 791 #define bSub_Tune 0xe00000 792 #define bFrame_DC_Length 0xe000000 793 #define bSBD_start_offset 0x30000000 794 #define bFrame_TH_2 0x7 795 #define bFrame_GI2_TH 0x38 796 #define bGI2_Sync_en 0x40 797 #define bSarch_Short_Early 0x300 798 #define bSarch_Short_Late 0xc00 799 #define bSarch_GI2_Late 0x70000 800 #define bCFOAntSum 0x1 801 #define bCFOAcc 0x2 802 #define bCFOStartOffset 0xc 803 #define bCFOLookBack 0x70 804 #define bCFOSumWeight 0x80 805 #define bDAGCEnable 0x10000 806 #define bTXIQImb_A 0x3ff 807 #define bTXIQImb_B 0xfc00 808 #define bTXIQImb_C 0x3f0000 809 #define bTXIQImb_D 0xffc00000 810 #define bTxIDCOffset 0xff 811 #define bTxQDCOffset 0xff00 812 #define bTxDFIRMode 0x10000 813 #define bTxPesudoNoiseOn 0x4000000 814 #define bTxPesudoNoise_A 0xff 815 #define bTxPesudoNoise_B 0xff00 816 #define bTxPesudoNoise_C 0xff0000 817 #define bTxPesudoNoise_D 0xff000000 818 #define bCCADropOption 0x20000 819 #define bCCADropThres 0xfff00000 820 #define bEDCCA_H 0xf 821 #define bEDCCA_L 0xf0 822 #define bLambda_ED 0x300 823 #define bRxInitialGain 0x7f 824 #define bRxAntDivEn 0x80 825 #define bRxAGCAddressForLNA 0x7f00 826 #define bRxHighPowerFlow 0x8000 827 #define bRxAGCFreezeThres 0xc0000 828 #define bRxFreezeStep_AGC1 0x300000 829 #define bRxFreezeStep_AGC2 0xc00000 830 #define bRxFreezeStep_AGC3 0x3000000 831 #define bRxFreezeStep_AGC0 0xc000000 832 #define bRxRssi_Cmp_En 0x10000000 833 #define bRxQuickAGCEn 0x20000000 834 #define bRxAGCFreezeThresMode 0x40000000 835 #define bRxOverFlowCheckType 0x80000000 836 #define bRxAGCShift 0x7f 837 #define bTRSW_Tri_Only 0x80 838 #define bPowerThres 0x300 839 #define bRxAGCEn 0x1 840 #define bRxAGCTogetherEn 0x2 841 #define bRxAGCMin 0x4 842 #define bRxHP_Ini 0x7 843 #define bRxHP_TRLNA 0x70 844 #define bRxHP_RSSI 0x700 845 #define bRxHP_BBP1 0x7000 846 #define bRxHP_BBP2 0x70000 847 #define bRxHP_BBP3 0x700000 848 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 849 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 850 #define bRxSettle_TRSW 0x7 851 #define bRxSettle_LNA 0x38 852 #define bRxSettle_RSSI 0x1c0 853 #define bRxSettle_BBP 0xe00 854 #define bRxSettle_RxHP 0x7000 855 #define bRxSettle_AntSW_RSSI 0x38000 856 #define bRxSettle_AntSW 0xc0000 857 #define bRxProcessTime_DAGC 0x300000 858 #define bRxSettle_HSSI 0x400000 859 #define bRxProcessTime_BBPPW 0x800000 860 #define bRxAntennaPowerShift 0x3000000 861 #define bRSSITableSelect 0xc000000 862 #define bRxHP_Final 0x7000000 863 #define bRxHTSettle_BBP 0x7 864 #define bRxHTSettle_HSSI 0x8 865 #define bRxHTSettle_RxHP 0x70 866 #define bRxHTSettle_BBPPW 0x80 867 #define bRxHTSettle_Idle 0x300 868 #define bRxHTSettle_Reserved 0x1c00 869 #define bRxHTRxHPEn 0x8000 870 #define bRxHTAGCFreezeThres 0x30000 871 #define bRxHTAGCTogetherEn 0x40000 872 #define bRxHTAGCMin 0x80000 873 #define bRxHTAGCEn 0x100000 874 #define bRxHTDAGCEn 0x200000 875 #define bRxHTRxHP_BBP 0x1c00000 876 #define bRxHTRxHP_Final 0xe0000000 877 #define bRxPWRatioTH 0x3 878 #define bRxPWRatioEn 0x4 879 #define bRxMFHold 0x3800 880 #define bRxPD_Delay_TH1 0x38 881 #define bRxPD_Delay_TH2 0x1c0 882 #define bRxPD_DC_COUNT_MAX 0x600 883 /* #define bRxMF_Hold 0x3800 */ 884 #define bRxPD_Delay_TH 0x8000 885 #define bRxProcess_Delay 0xf0000 886 #define bRxSearchrange_GI2_Early 0x700000 887 #define bRxFrame_Guard_Counter_L 0x3800000 888 #define bRxSGI_Guard_L 0xc000000 889 #define bRxSGI_Search_L 0x30000000 890 #define bRxSGI_TH 0xc0000000 891 #define bDFSCnt0 0xff 892 #define bDFSCnt1 0xff00 893 #define bDFSFlag 0xf0000 894 #define bMFWeightSum 0x300000 895 #define bMinIdxTH 0x7f000000 896 #define bDAFormat 0x40000 897 #define bTxChEmuEnable 0x01000000 898 #define bTRSWIsolation_A 0x7f 899 #define bTRSWIsolation_B 0x7f00 900 #define bTRSWIsolation_C 0x7f0000 901 #define bTRSWIsolation_D 0x7f000000 902 #define bExtLNAGain 0x7c00 903 904 /* 6. PageE(0xE00) */ 905 #define bSTBCEn 0x4 /* Useless */ 906 #define bAntennaMapping 0x10 907 #define bNss 0x20 908 #define bCFOAntSumD 0x200 909 #define bPHYCounterReset 0x8000000 910 #define bCFOReportGet 0x4000000 911 #define bOFDMContinueTx 0x10000000 912 #define bOFDMSingleCarrier 0x20000000 913 #define bOFDMSingleTone 0x40000000 914 /* #define bRxPath1 0x01 */ 915 /* #define bRxPath2 0x02 */ 916 /* #define bRxPath3 0x04 */ 917 /* #define bRxPath4 0x08 */ 918 /* #define bTxPath1 0x10 */ 919 /* #define bTxPath2 0x20 */ 920 #define bHTDetect 0x100 921 #define bCFOEn 0x10000 922 #define bCFOValue 0xfff00000 923 #define bSigTone_Re 0x3f 924 #define bSigTone_Im 0x7f00 925 #define bCounter_CCA 0xffff 926 #define bCounter_ParityFail 0xffff0000 927 #define bCounter_RateIllegal 0xffff 928 #define bCounter_CRC8Fail 0xffff0000 929 #define bCounter_MCSNoSupport 0xffff 930 #define bCounter_FastSync 0xffff 931 #define bShortCFO 0xfff 932 #define bShortCFOTLength 12 /* total */ 933 #define bShortCFOFLength 11 /* fraction */ 934 #define bLongCFO 0x7ff 935 #define bLongCFOTLength 11 936 #define bLongCFOFLength 11 937 #define bTailCFO 0x1fff 938 #define bTailCFOTLength 13 939 #define bTailCFOFLength 12 940 #define bmax_en_pwdB 0xffff 941 #define bCC_power_dB 0xffff0000 942 #define bnoise_pwdB 0xffff 943 #define bPowerMeasTLength 10 944 #define bPowerMeasFLength 3 945 #define bRx_HT_BW 0x1 946 #define bRxSC 0x6 947 #define bRx_HT 0x8 948 #define bNB_intf_det_on 0x1 949 #define bIntf_win_len_cfg 0x30 950 #define bNB_Intf_TH_cfg 0x1c0 951 #define bRFGain 0x3f 952 #define bTableSel 0x40 953 #define bTRSW 0x80 954 #define bRxSNR_A 0xff 955 #define bRxSNR_B 0xff00 956 #define bRxSNR_C 0xff0000 957 #define bRxSNR_D 0xff000000 958 #define bSNREVMTLength 8 959 #define bSNREVMFLength 1 960 #define bCSI1st 0xff 961 #define bCSI2nd 0xff00 962 #define bRxEVM1st 0xff0000 963 #define bRxEVM2nd 0xff000000 964 #define bSIGEVM 0xff 965 #define bPWDB 0xff00 966 #define bSGIEN 0x10000 967 968 #define bSFactorQAM1 0xf /* Useless */ 969 #define bSFactorQAM2 0xf0 970 #define bSFactorQAM3 0xf00 971 #define bSFactorQAM4 0xf000 972 #define bSFactorQAM5 0xf0000 973 #define bSFactorQAM6 0xf0000 974 #define bSFactorQAM7 0xf00000 975 #define bSFactorQAM8 0xf000000 976 #define bSFactorQAM9 0xf0000000 977 #define bCSIScheme 0x100000 978 979 #define bNoiseLvlTopSet 0x3 /* Useless */ 980 #define bChSmooth 0x4 981 #define bChSmoothCfg1 0x38 982 #define bChSmoothCfg2 0x1c0 983 #define bChSmoothCfg3 0xe00 984 #define bChSmoothCfg4 0x7000 985 #define bMRCMode 0x800000 986 #define bTHEVMCfg 0x7000000 987 988 #define bLoopFitType 0x1 /* Useless */ 989 #define bUpdCFO 0x40 990 #define bUpdCFOOffData 0x80 991 #define bAdvUpdCFO 0x100 992 #define bAdvTimeCtrl 0x800 993 #define bUpdClko 0x1000 994 #define bFC 0x6000 995 #define bTrackingMode 0x8000 996 #define bPhCmpEnable 0x10000 997 #define bUpdClkoLTF 0x20000 998 #define bComChCFO 0x40000 999 #define bCSIEstiMode 0x80000 1000 #define bAdvUpdEqz 0x100000 1001 #define bUChCfg 0x7000000 1002 #define bUpdEqz 0x8000000 1003 1004 /* Rx Pseduo noise */ 1005 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1006 #define bRxPesudoNoise_A 0xff 1007 #define bRxPesudoNoise_B 0xff00 1008 #define bRxPesudoNoise_C 0xff0000 1009 #define bRxPesudoNoise_D 0xff000000 1010 #define bPesudoNoiseState_A 0xffff 1011 #define bPesudoNoiseState_B 0xffff0000 1012 #define bPesudoNoiseState_C 0xffff 1013 #define bPesudoNoiseState_D 0xffff0000 1014 1015 /* 7. RF Register 1016 * Zebra1 */ 1017 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1018 #define bZebra1_TRxControl 0xc00 1019 #define bZebra1_TRxGainSetting 0x07f 1020 #define bZebra1_RxCorner 0xc00 1021 #define bZebra1_TxChargePump 0x38 1022 #define bZebra1_RxChargePump 0x7 1023 #define bZebra1_ChannelNum 0xf80 1024 #define bZebra1_TxLPFBW 0x400 1025 #define bZebra1_RxLPFBW 0x600 1026 1027 /* Zebra4 */ 1028 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1029 #define bRTL8256RegModeCtrl0 0x40 1030 #define bRTL8256_TxLPFBW 0x18 1031 #define bRTL8256_RxLPFBW 0x600 1032 1033 /* RTL8258 */ 1034 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1035 #define bRTL8258_RxLPFBW 0xc00 1036 #define bRTL8258_RSSILPFBW 0xc0 1037 1038 1039 /* 1040 * Other Definition 1041 * */ 1042 1043 /* byte endable for sb_write */ 1044 #define bByte0 0x1 /* Useless */ 1045 #define bByte1 0x2 1046 #define bByte2 0x4 1047 #define bByte3 0x8 1048 #define bWord0 0x3 1049 #define bWord1 0xc 1050 #define bDWord 0xf 1051 1052 /* for PutRegsetting & GetRegSetting BitMask */ 1053 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1054 #define bMaskByte1 0xff00 1055 #define bMaskByte2 0xff0000 1056 #define bMaskByte3 0xff000000 1057 #define bMaskHWord 0xffff0000 1058 #define bMaskLWord 0x0000ffff 1059 #define bMaskDWord 0xffffffff 1060 #define bMaskH3Bytes 0xffffff00 1061 #define bMask12Bits 0xfff 1062 #define bMaskH4Bits 0xf0000000 1063 #define bMaskOFDM_D 0xffc00000 1064 #define bMaskCCK 0x3f3f3f3f 1065 1066 1067 #define bEnable 0x1 /* Useless */ 1068 #define bDisable 0x0 1069 1070 #define LeftAntenna 0x0 /* Useless */ 1071 #define RightAntenna 0x1 1072 1073 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1074 #define tUpdateRxCounter 100 /* 100ms */ 1075 1076 #define rateCCK 0 /* Useless */ 1077 #define rateOFDM 1 1078 #define rateHT 2 1079 1080 /* define Register-End */ 1081 #define bPMAC_End 0x1ff /* Useless */ 1082 #define bFPGAPHY0_End 0x8ff 1083 #define bFPGAPHY1_End 0x9ff 1084 #define bCCKPHY0_End 0xaff 1085 #define bOFDMPHY0_End 0xcff 1086 #define bOFDMPHY1_End 0xdff 1087 1088 /* define max debug item in each debug page 1089 * #define bMaxItem_FPGA_PHY0 0x9 1090 * #define bMaxItem_FPGA_PHY1 0x3 1091 * #define bMaxItem_PHY_11B 0x16 1092 * #define bMaxItem_OFDM_PHY0 0x29 1093 * #define bMaxItem_OFDM_PHY1 0x0 */ 1094 1095 #define bPMACControl 0x0 /* Useless */ 1096 #define bWMACControl 0x1 1097 #define bWNICControl 0x2 1098 1099 #define PathA 0x0 /* Useless */ 1100 #define PathB 0x1 1101 #define PathC 0x2 1102 #define PathD 0x3 1103 1104 /*--------------------------Define Parameters-------------------------------*/ 1105 1106 1107 /* BB Register Definition 1108 * 1109 * 4. Page9(0x900) 1110 * */ 1111 #define rDPDT_control 0x92c 1112 #define rfe_ctrl_anta_src 0x930 1113 #define rS0S1_PathSwitch 0x948 1114 #define BBrx_DFIR 0x954 1115 #define AGC_table_select 0xb2c 1116 1117 /* 1118 * PageB(0xB00) 1119 * */ 1120 #define rPdp_AntA 0xb00 1121 #define rPdp_AntA_4 0xb04 1122 #define rPdp_AntA_8 0xb08 1123 #define rPdp_AntA_C 0xb0c 1124 #define rPdp_AntA_10 0xb10 1125 #define rPdp_AntA_14 0xb14 1126 #define rPdp_AntA_18 0xb18 1127 #define rPdp_AntA_1C 0xb1c 1128 #define rPdp_AntA_20 0xb20 1129 #define rPdp_AntA_24 0xb24 1130 1131 #define rConfig_Pmpd_AntA 0xb28 1132 #define rConfig_ram64x16 0xb2c 1133 1134 #define rBndA 0xb30 1135 #define rHssiPar 0xb34 1136 1137 #define rConfig_AntA 0xb68 1138 #define rConfig_AntB 0xb6c 1139 1140 #define rPdp_AntB 0xb70 1141 #define rPdp_AntB_4 0xb74 1142 #define rPdp_AntB_8 0xb78 1143 #define rPdp_AntB_C 0xb7c 1144 #define rPdp_AntB_10 0xb80 1145 #define rPdp_AntB_14 0xb84 1146 #define rPdp_AntB_18 0xb88 1147 #define rPdp_AntB_1C 0xb8c 1148 #define rPdp_AntB_20 0xb90 1149 #define rPdp_AntB_24 0xb94 1150 1151 #define rConfig_Pmpd_AntB 0xb98 1152 1153 #define rBndB 0xba0 1154 1155 #define rAPK 0xbd8 1156 #define rPm_Rx0_AntA 0xbdc 1157 #define rPm_Rx1_AntA 0xbe0 1158 #define rPm_Rx2_AntA 0xbe4 1159 #define rPm_Rx3_AntA 0xbe8 1160 #define rPm_Rx0_AntB 0xbec 1161 #define rPm_Rx1_AntB 0xbf0 1162 #define rPm_Rx2_AntB 0xbf4 1163 #define rPm_Rx3_AntB 0xbf8 1164 1165 #endif 1166