1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8710B
46 #include <rtl8710b_hal.h>
47 #endif
48 #ifdef CONFIG_RTL8188F
49 #include <rtl8188f_hal.h>
50 #endif
51 #ifdef CONFIG_RTL8188GTV
52 #include <rtl8188gtv_hal.h>
53 #endif
54 #ifdef CONFIG_RTL8192F
55 #include <rtl8192f_hal.h>
56 #endif
57 #endif /* !RTW_HALMAC */
58
59
MgntQuery_NssTxRate(u16 Rate)60 u8 MgntQuery_NssTxRate(u16 Rate)
61 {
62 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
63
64 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
65 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
66 NssNum = RF_2TX;
67 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
68 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
69 NssNum = RF_3TX;
70 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
71 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
72 NssNum = RF_4TX;
73 else
74 NssNum = RF_1TX;
75
76 return NssNum;
77 }
78
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)79 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
80 {
81 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
82 u8 ChannelToSw = pMptCtx->MptChannelToSw;
83 u32 ulRateIdx = pMptCtx->mpt_rate_index;
84 u32 ulbandwidth = pMptCtx->MptBandWidth;
85
86 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
87 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
88 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
89 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
90 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
91
92 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
98 }
99 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
100 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 } else {
104 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
105 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 }
107 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
108 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
109 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
110 }
111 }
112
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)113 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
114 {
115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
116 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
117
118
119 if (!netif_running(padapter->pnetdev)) {
120 return _FAIL;
121 }
122
123 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
124 return _FAIL;
125 }
126 if (enable)
127 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
128 else
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
130
131 return _SUCCESS;
132 }
133
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)134 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
137 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
138
139
140 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
141 }
142
143
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)144 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
145 {
146 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
147 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
148 u8 i;
149 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
150 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
151 u8 u1Channel = pHalData->current_channel;
152 u32 ulRateIdx = pMptCtx->mpt_rate_index;
153 u8 DataRate = 0xFF;
154
155 /* Do not modify CCK TX filter parameters for 8822B*/
156 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
157 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
158 return;
159
160 DataRate = mpt_to_mgnt_rate(ulRateIdx);
161
162 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
163 pHalData->bCCKinCH14 = TRUE;
164 else
165 pHalData->bCCKinCH14 = FALSE;
166
167 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
168 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
169 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
170 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
171 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
172
173 } else {
174 /* Normal setting for 8703B, just recover to the default setting. */
175 /* This hardcore values reference from the parameter which BB team gave. */
176 for (i = 0 ; i < 2 ; ++i)
177 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
178
179 }
180 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
181 /* 2.4G CCK TX DFIR */
182 /* 2016.01.20 Suggest from RS BB mingzhi*/
183 if (u1Channel == 14) {
184 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
185 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
186 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
187 } else {
188 for (i = 0 ; i < 3 ; ++i) {
189 phy_set_bb_reg(Adapter,
190 pHalData->RegForRecover[i].offset,
191 bMaskDWord,
192 pHalData->RegForRecover[i].value);
193 }
194 }
195 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
196 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
197 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
198 CCKSwingIndex = 20; /* default index */
199
200 if (!pHalData->bCCKinCH14) {
201 /* Readback the current bb cck swing value and compare with the table to */
202 /* get the current swing index */
203 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
204 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
205 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
206 CCKSwingIndex = i;
207 break;
208 }
209 }
210 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
211 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
212 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
213 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
214 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
215 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
216 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
217 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
218 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
219 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
220 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
221 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
222 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
223 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
224 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
225 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
226 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
227 } else {
228 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
229 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
230 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
231 CCKSwingIndex = i;
232 break;
233 }
234 }
235 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
236 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
237 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
238 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
239 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
240 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
241 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
242 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
243 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
244 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
245 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
246 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
247 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
248 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
249 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
250 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
252 }
253 } else {
254
255 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
257
258 if (!pHalData->bCCKinCH14) {
259 /* Readback the current bb cck swing value and compare with the table to */
260 /* get the current swing index */
261 for (i = 0; i < CCK_TABLE_SIZE; i++) {
262 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264 CCKSwingIndex = i;
265 break;
266 }
267 }
268
269 /*Write 0xa22 0xa23*/
270 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272
273
274 /*Write 0xa24 ~ 0xa27*/
275 TempVal2 = 0;
276 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
277 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280
281 /*Write 0xa28 0xa29*/
282 TempVal3 = 0;
283 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285 } else {
286 for (i = 0; i < CCK_TABLE_SIZE; i++) {
287 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289 CCKSwingIndex = i;
290 break;
291 }
292 }
293
294 /*Write 0xa22 0xa23*/
295 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297
298 /*Write 0xa24 ~ 0xa27*/
299 TempVal2 = 0;
300 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304
305 /*Write 0xa28 0xa29*/
306 TempVal3 = 0;
307 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309 }
310
311 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314 }
315
316 }
317
hal_mpt_SetChannel(PADAPTER pAdapter)318 void hal_mpt_SetChannel(PADAPTER pAdapter)
319 {
320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
321 struct mp_priv *pmp = &pAdapter->mppriv;
322 u8 channel = pmp->channel;
323 u8 bandwidth = pmp->bandwidth;
324
325 hal_mpt_SwitchRfSetting(pAdapter);
326
327 pHalData->bSwChnl = _TRUE;
328 pHalData->bSetChnlBW = _TRUE;
329
330 if (bandwidth == 2) {
331 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332 } else if (bandwidth == 1) {
333 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334 } else
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336
337 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338 rtw_btcoex_wifionly_scan_notify(pAdapter);
339
340 }
341
342 /*
343 * Notice
344 * Switch bandwitdth may change center frequency(channel)
345 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)346 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347 {
348 struct mp_priv *pmp = &pAdapter->mppriv;
349 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
350
351 u8 channel = pmp->channel;
352 u8 bandwidth = pmp->bandwidth;
353
354 pHalData->bSwChnl = _TRUE;
355 pHalData->bSetChnlBW = _TRUE;
356
357 if (bandwidth == 2) {
358 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359 } else if (bandwidth == 1) {
360 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361 } else
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363
364 hal_mpt_SwitchRfSetting(pAdapter);
365 rtw_btcoex_wifionly_scan_notify(pAdapter);
366
367 }
368
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)369 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370 {
371 switch (Rate) {
372 case MPT_CCK: {
373 u32 TxAGC = 0, pwr = 0;
374
375 pwr = pTxPower[RF_PATH_A];
376 if (pwr < 0x3f) {
377 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380 }
381 pwr = pTxPower[RF_PATH_B];
382 if (pwr < 0x3f) {
383 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386 }
387 }
388 break;
389
390 case MPT_OFDM_AND_HT: {
391 u32 TxAGC = 0;
392 u8 pwr = 0;
393
394 pwr = pTxPower[0];
395 if (pwr < 0x3f) {
396 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404 }
405 TxAGC = 0;
406 pwr = pTxPower[1];
407 if (pwr < 0x3f) {
408 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416 }
417 }
418 break;
419
420 default:
421 break;
422 }
423 RTW_INFO("<===mpt_SetTxPower_Old()\n");
424 }
425
426 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)427 mpt_SetTxPower(
428 PADAPTER pAdapter,
429 MPT_TXPWR_DEF Rate,
430 u8 *pTxPower
431 )
432 {
433 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
434
435 u8 path = 0 , i = 0, MaxRate = MGN_6M;
436 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437 u8 tx_nss = 2;
438
439 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter)) {
440 EndPath = RF_PATH_D;
441 tx_nss = 4;
442 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
443 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
444 EndPath = RF_PATH_A;
445 tx_nss = 1;
446 }
447
448 switch (Rate) {
449 case MPT_CCK: {
450 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
451
452 for (path = StartPath; path <= EndPath; path++)
453 for (i = 0; i < sizeof(rate); ++i)
454 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
455 }
456 break;
457 case MPT_OFDM: {
458 u8 rate[] = {
459 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
460 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
461 };
462
463 for (path = StartPath; path <= EndPath; path++)
464 for (i = 0; i < sizeof(rate); ++i)
465 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
466 }
467 break;
468 case MPT_HT: {
469 u8 rate[] = {
470 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
471 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
472 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
473 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
474 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
475 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
476 MGN_MCS30, MGN_MCS31,
477 };
478 if (tx_nss == 4)
479 MaxRate = MGN_MCS31;
480 else if (tx_nss == 3)
481 MaxRate = MGN_MCS23;
482 else if (tx_nss == 2)
483 MaxRate = MGN_MCS15;
484 else
485 MaxRate = MGN_MCS7;
486
487 for (path = StartPath; path <= EndPath; path++) {
488 for (i = 0; i < sizeof(rate); ++i) {
489 if (rate[i] > MaxRate)
490 break;
491 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
492 }
493 }
494 }
495 break;
496 case MPT_VHT: {
497 u8 rate[] = {
498 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
499 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
500 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
501 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
502 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
503 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
504 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
505 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
506 };
507 if (tx_nss == 4)
508 MaxRate = MGN_VHT4SS_MCS9;
509 else if (tx_nss == 3)
510 MaxRate = MGN_VHT3SS_MCS9;
511 else if (tx_nss == 2)
512 MaxRate = MGN_VHT2SS_MCS9;
513 else
514 MaxRate = MGN_VHT1SS_MCS9;
515
516 for (path = StartPath; path <= EndPath; path++) {
517 for (i = 0; i < sizeof(rate); ++i) {
518 if (rate[i] > MaxRate)
519 break;
520 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
521 }
522 }
523 }
524 break;
525 default:
526 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
527 break;
528 }
529 }
530
hal_mpt_SetTxPower(PADAPTER pAdapter)531 void hal_mpt_SetTxPower(PADAPTER pAdapter)
532 {
533 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
534 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
535 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
536
537 if (pHalData->rf_chip < RF_CHIP_MAX) {
538 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
539 IS_HARDWARE_TYPE_8723B(pAdapter) ||
540 IS_HARDWARE_TYPE_8192E(pAdapter) ||
541 IS_HARDWARE_TYPE_8703B(pAdapter) ||
542 IS_HARDWARE_TYPE_8188F(pAdapter) ||
543 IS_HARDWARE_TYPE_8188GTV(pAdapter)
544 ) {
545
546 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
547
548 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
549 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
550
551 } else {
552
553 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
554 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
555 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
556 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
557 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
558 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
559 }
560 }
561
562 rtw_hal_set_txpwr_done(pAdapter);
563 } else
564 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
565
566 odm_clear_txpowertracking_state(pDM_Odm);
567 }
568
hal_mpt_SetDataRate(PADAPTER pAdapter)569 void hal_mpt_SetDataRate(PADAPTER pAdapter)
570 {
571 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
572 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
573 u32 DataRate;
574
575 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
576
577 hal_mpt_SwitchRfSetting(pAdapter);
578
579 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
580 #ifdef CONFIG_RTL8723B
581 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
582 if (IS_CCK_RATE(DataRate)) {
583 if (pMptCtx->mpt_rf_path == RF_PATH_A)
584 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
585 else
586 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
587 } else {
588 if (pMptCtx->mpt_rf_path == RF_PATH_A)
589 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
590 else
591 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
592 }
593 }
594
595 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
596 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
597 if (pMptCtx->mpt_rf_path == RF_PATH_A)
598 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
599 else
600 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
601 }
602 #endif
603 }
604
605 #define RF_PATH_AB 22
606
607 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)608 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
609 {
610 u8 Path;
611 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
612
613 for (Path = 0; Path <= RF_PATH_D; Path++) {
614 switch (Path) {
615 case RF_PATH_B:
616 IGReg = rB_IGI_Jaguar;
617 break;
618 case RF_PATH_C:
619 IGReg = rC_IGI_Jaguar2;
620 break;
621 case RF_PATH_D:
622 IGReg = rD_IGI_Jaguar2;
623 break;
624 default:
625 IGReg = rA_IGI_Jaguar;
626 break;
627 }
628
629 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
630 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
631 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
632 }
633 }
634
mpt_SetRFPath_8814A(PADAPTER pAdapter)635 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
636 {
637
638 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
639 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
640 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
641 R_ANTENNA_SELECT_CCK *p_cck_txrx;
642 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
643 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
644 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
645
646 u32 ulAntennaTx = pHalData->antenna_tx_path;
647 u32 ulAntennaRx = pHalData->AntennaRxPath;
648 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
649
650 if (NssforRate == RF_3TX) {
651 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
652
653 switch (ulAntennaTx) {
654 case ANTENNA_BCD:
655 pMptCtx->mpt_rf_path = RF_PATH_BCD;
656 /*pHalData->ValidTxPath = 0x0e;*/
657 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
658 break;
659
660 case ANTENNA_ABC:
661 default:
662 pMptCtx->mpt_rf_path = RF_PATH_ABC;
663 /*pHalData->ValidTxPath = 0x0d;*/
664 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
665 break;
666 }
667
668 } else { /*/if(NssforRate == RF_1TX)*/
669 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
670 switch (ulAntennaTx) {
671 case ANTENNA_BCD:
672 pMptCtx->mpt_rf_path = RF_PATH_BCD;
673 /*pHalData->ValidTxPath = 0x0e;*/
674 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
675 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
676 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
677 break;
678
679 case ANTENNA_BC:
680 pMptCtx->mpt_rf_path = RF_PATH_BC;
681 /*pHalData->ValidTxPath = 0x06;*/
682 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
683 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
684 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
685 break;
686 case ANTENNA_B:
687 pMptCtx->mpt_rf_path = RF_PATH_B;
688 /*pHalData->ValidTxPath = 0x02;*/
689 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
690 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
691 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
692 break;
693
694 case ANTENNA_C:
695 pMptCtx->mpt_rf_path = RF_PATH_C;
696 /*pHalData->ValidTxPath = 0x04;*/
697 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
698 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
699 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
700 break;
701
702 case ANTENNA_D:
703 pMptCtx->mpt_rf_path = RF_PATH_D;
704 /*pHalData->ValidTxPath = 0x08;*/
705 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
706 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
707 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
708 break;
709
710 case ANTENNA_A:
711 default:
712 pMptCtx->mpt_rf_path = RF_PATH_A;
713 /*pHalData->ValidTxPath = 0x01;*/
714 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
715 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
716 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
717 break;
718 }
719 }
720
721 switch (ulAntennaRx) {
722 case ANTENNA_A:
723 /*pHalData->ValidRxPath = 0x01;*/
724 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
725 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
726 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
727 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
728 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
729 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
730 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
731 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
732 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
733 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
734 /*/ CCA related PD_delay_th*/
735 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
736 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
737 break;
738
739 case ANTENNA_B:
740 /*pHalData->ValidRxPath = 0x02;*/
741 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
742 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
743 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
744 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
745 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
746 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
747 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
748 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
749 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
750 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
751 /*/ CCA related PD_delay_th*/
752 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
753 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
754 break;
755
756 case ANTENNA_C:
757 /*pHalData->ValidRxPath = 0x04;*/
758 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
759 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
760 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
761 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
762 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
763 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
764 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
765 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
766 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
767 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
768 /*/ CCA related PD_delay_th*/
769 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
770 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
771 break;
772
773 case ANTENNA_D:
774 /*pHalData->ValidRxPath = 0x08;*/
775 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
776 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
777 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
778 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
779 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
780 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
781 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
782 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
783 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
784 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
785 /*/ CCA related PD_delay_th*/
786 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
787 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
788 break;
789
790 case ANTENNA_BC:
791 /*pHalData->ValidRxPath = 0x06;*/
792 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
793 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
794 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
795 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
796 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
797 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
798 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
799 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
800 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
801 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
802 /*/ CCA related PD_delay_th*/
803 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
804 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
805 break;
806
807 case ANTENNA_CD:
808 /*pHalData->ValidRxPath = 0x0C;*/
809 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
810 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
811 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
812 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
813 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
814 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
815 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
816 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
817 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
818 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
819 /*/ CCA related PD_delay_th*/
820 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
821 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
822 break;
823
824 case ANTENNA_BCD:
825 /*pHalData->ValidRxPath = 0x0e;*/
826 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
827 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
828 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
829 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
830 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
831 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
832 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
833 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
834 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
835 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
836 /*/ CCA related PD_delay_th*/
837 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
838 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
839 break;
840
841 case ANTENNA_ABCD:
842 /*pHalData->ValidRxPath = 0x0f;*/
843 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
844 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
845 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
846 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
847 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
848 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
849 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
850 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
851 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
852 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
853 /*/ CCA related PD_delay_th*/
854 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
855 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
856 break;
857
858 default:
859 break;
860 }
861
862 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
863
864 mpt_ToggleIG_8814A(pAdapter);
865 }
866
867 #endif /* CONFIG_RTL8814A */
868 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) \
869 || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
870 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)871 mpt_SetSingleTone_8814A(
872 PADAPTER pAdapter,
873 BOOLEAN bSingleTone,
874 BOOLEAN bEnPMacTx)
875 {
876
877 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
878 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
879 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
880
881 if (bSingleTone) {
882 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
883 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
884 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
885 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
886
887 switch (pMptCtx->mpt_rf_path) {
888 case RF_PATH_A:
889 case RF_PATH_B:
890 case RF_PATH_C:
891 case RF_PATH_D:
892 StartPath = pMptCtx->mpt_rf_path;
893 EndPath = pMptCtx->mpt_rf_path;
894 break;
895 case RF_PATH_AB:
896 EndPath = RF_PATH_B;
897 break;
898 case RF_PATH_BC:
899 StartPath = RF_PATH_B;
900 EndPath = RF_PATH_C;
901 break;
902 case RF_PATH_ABC:
903 EndPath = RF_PATH_C;
904 break;
905 case RF_PATH_BCD:
906 StartPath = RF_PATH_B;
907 EndPath = RF_PATH_D;
908 break;
909 case RF_PATH_ABCD:
910 EndPath = RF_PATH_D;
911 break;
912 }
913
914 if (bEnPMacTx == FALSE) {
915 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
916 issue_nulldata(pAdapter, NULL, 1, 3, 500);
917 }
918
919 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
920
921 for (path = StartPath; path <= EndPath; path++) {
922 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
923 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
924
925 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
926 }
927
928 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
929 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
930 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
931 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
932 } else {
933 switch (pMptCtx->mpt_rf_path) {
934 case RF_PATH_A:
935 case RF_PATH_B:
936 case RF_PATH_C:
937 case RF_PATH_D:
938 StartPath = pMptCtx->mpt_rf_path;
939 EndPath = pMptCtx->mpt_rf_path;
940 break;
941 case RF_PATH_AB:
942 EndPath = RF_PATH_B;
943 break;
944 case RF_PATH_BC:
945 StartPath = RF_PATH_B;
946 EndPath = RF_PATH_C;
947 break;
948 case RF_PATH_ABC:
949 EndPath = RF_PATH_C;
950 break;
951 case RF_PATH_BCD:
952 StartPath = RF_PATH_B;
953 EndPath = RF_PATH_D;
954 break;
955 case RF_PATH_ABCD:
956 EndPath = RF_PATH_D;
957 break;
958 }
959 for (path = StartPath; path <= EndPath; path++)
960 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
961
962 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
963
964 if (bEnPMacTx == FALSE) {
965 if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
966 #ifdef PHYDM_MP_SUPPORT
967 phydm_stop_ofdm_cont_tx(pAdapter);
968 pMptCtx->bCckContTx = FALSE;
969 pMptCtx->bOfdmContTx = FALSE;
970 #endif
971 } else
972 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
973 }
974
975 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
976 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
977 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
978 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
979 }
980 }
981
982 #endif
983
984 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)985 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
986 {
987 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
988 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
989 struct mp_priv *pmp = &pAdapter->mppriv;
990 u8 channel = pmp->channel;
991 u8 bandwidth = pmp->bandwidth;
992 u8 eLNA_2g = pHalData->ExternalLNA_2G;
993 u32 ulAntennaTx, ulAntennaRx;
994 u32 reg0xC50 = 0;
995
996 ulAntennaTx = pHalData->antenna_tx_path;
997 ulAntennaRx = pHalData->AntennaRxPath;
998
999 switch (ulAntennaTx) {
1000 case ANTENNA_A:
1001 pMptCtx->mpt_rf_path = RF_PATH_A;
1002 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
1003 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1004 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1005 break;
1006 case ANTENNA_B:
1007 pMptCtx->mpt_rf_path = RF_PATH_B;
1008 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
1009 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1010 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1011 break;
1012 case ANTENNA_AB:
1013 pMptCtx->mpt_rf_path = RF_PATH_AB;
1014 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1015 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1016 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1017 break;
1018 default:
1019 pMptCtx->mpt_rf_path = RF_PATH_AB;
1020 RTW_INFO("Unknown Tx antenna.\n");
1021 break;
1022 }
1023
1024 switch (ulAntennaRx) {
1025 case ANTENNA_A:
1026 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1027 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1028 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1029 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1030
1031 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1032 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1033 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1034 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1035
1036 /* set PWED_TH for BB Yn user guide R29 */
1037 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1038 if (channel <= 14) { /* 2.4G */
1039 if (bandwidth == CHANNEL_WIDTH_20
1040 && eLNA_2g == 0) {
1041 /* 0x830[3:1]=3'b010 */
1042 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1043 } else
1044 /* 0x830[3:1]=3'b100 */
1045 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1046 } else
1047 /* 0x830[3:1]=3'b100 for 5G */
1048 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1049 }
1050 break;
1051 case ANTENNA_B:
1052 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1053 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1054 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1055 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1056
1057 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1058 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1059 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1060 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1061
1062 /* set PWED_TH for BB Yn user guide R29 */
1063 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1064 if (channel <= 14) {
1065 if (bandwidth == CHANNEL_WIDTH_20
1066 && eLNA_2g == 0) {
1067 /* 0x830[3:1]=3'b010 */
1068 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1069 } else
1070 /* 0x830[3:1]=3'b100 */
1071 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1072 } else
1073 /* 0x830[3:1]=3'b100 for 5G */
1074 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1075 }
1076 break;
1077 case ANTENNA_AB:
1078 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1079 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1080 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1081 /* set PWED_TH for BB Yn user guide R29 */
1082 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1083 break;
1084 default:
1085 RTW_INFO("Unknown Rx antenna.\n");
1086 break;
1087 }
1088
1089 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1090 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1091 /* WiFi */
1092 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1093 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1094 } else {
1095 /* BT */
1096 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1097 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1098 }
1099 }
1100 }
1101 #endif
1102
1103 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1104 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1105 {
1106 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1107 u32 ulAntennaTx, ulAntennaRx;
1108 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1109 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1110 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1111 u8 i;
1112
1113 ulAntennaTx = pHalData->antenna_tx_path;
1114 ulAntennaRx = pHalData->AntennaRxPath;
1115
1116 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1117 RTW_INFO("This RF chip ID is not supported\n");
1118 return;
1119 }
1120
1121 switch (pAdapter->mppriv.antenna_tx) {
1122 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1123 pMptCtx->mpt_rf_path = RF_PATH_A;
1124 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1125 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1126
1127 for (i = 0; i < 3; ++i) {
1128 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1129 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1130
1131 if (offset != 0) {
1132 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1133 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1134 }
1135 }
1136 for (i = 0; i < 2; ++i) {
1137 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1138 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1139
1140 if (offset != 0) {
1141 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1142 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1143 }
1144 }
1145 }
1146 break;
1147 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1148 u32 offset;
1149 u32 data;
1150
1151 pMptCtx->mpt_rf_path = RF_PATH_B;
1152 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1153 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1154
1155 for (i = 0; i < 3; ++i) {
1156 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1157 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1158 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1159 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1160 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1161 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1162 }
1163 }
1164 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1165 for (i = 0; i < 2; ++i) {
1166 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1167 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1168 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1169 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1170 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1171 }
1172 }
1173 }
1174 break;
1175 default:
1176 pMptCtx->mpt_rf_path = RF_PATH_AB;
1177 break;
1178 }
1179 }
1180 #endif
1181
1182 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1183 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1184 {
1185 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1186 u32 ulAntennaTx, ulAntennaRx;
1187 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1188 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1189 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1190 u8 i;
1191
1192 ulAntennaTx = pHalData->antenna_tx_path;
1193 ulAntennaRx = pHalData->AntennaRxPath;
1194
1195 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1196 RTW_INFO("This RF chip ID is not supported\n");
1197 return;
1198 }
1199
1200 switch (pAdapter->mppriv.antenna_tx) {
1201 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1202 pMptCtx->mpt_rf_path = RF_PATH_A;
1203 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1204 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1205
1206 for (i = 0; i < 3; ++i) {
1207 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1208 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1209
1210 if (offset != 0) {
1211 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1212 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1213 }
1214
1215 }
1216 for (i = 0; i < 2; ++i) {
1217 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1218 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1219
1220 if (offset != 0) {
1221 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1222 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1223 }
1224 }
1225 }
1226 break;
1227 case ANTENNA_B: { /* Actually path S0 (BT)*/
1228 pMptCtx->mpt_rf_path = RF_PATH_B;
1229 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1230 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1231
1232 for (i = 0; i < 3; ++i) {
1233 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1234 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1235
1236 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1237 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1238 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1239 }
1240 }
1241 for (i = 0; i < 2; ++i) {
1242 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1243 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1244
1245 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1246 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1247 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1248 }
1249 }
1250 }
1251 break;
1252 default:
1253 pMptCtx->mpt_rf_path = RF_PATH_AB;
1254 break;
1255 }
1256
1257 }
1258 #endif
1259
1260 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1261 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1262 {
1263 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1264 u8 p = 0, i = 0;
1265 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1266 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1267 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1268 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1269
1270 ulAntennaTx = pHalData->antenna_tx_path;
1271 ulAntennaRx = pHalData->AntennaRxPath;
1272
1273 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1274 RTW_INFO("This RF chip ID is not supported\n");
1275 return;
1276 }
1277
1278 switch (pAdapter->mppriv.antenna_tx) {
1279 /* Actually path S1 (Wi-Fi) */
1280 case ANTENNA_A: {
1281 pMptCtx->mpt_rf_path = RF_PATH_A;
1282 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1283 }
1284 break;
1285 /* Actually path S0 (BT) */
1286 case ANTENNA_B: {
1287 pMptCtx->mpt_rf_path = RF_PATH_B;
1288 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1289
1290 }
1291 break;
1292 default:
1293 pMptCtx->mpt_rf_path = RF_PATH_AB;
1294 break;
1295 }
1296 }
1297 #endif
1298
mpt_SetRFPath_819X(PADAPTER pAdapter)1299 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1300 {
1301 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1302 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1303 u32 ulAntennaTx, ulAntennaRx;
1304 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1305 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1306 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1307 u8 chgTx = 0, chgRx = 0;
1308 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1309
1310 ulAntennaTx = pHalData->antenna_tx_path;
1311 ulAntennaRx = pHalData->AntennaRxPath;
1312
1313 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1314 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1315
1316 p_ofdm_tx->r_ant_ht1 = 0x1;
1317 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1318 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1319
1320 switch (ulAntennaTx) {
1321 case ANTENNA_A:
1322 p_ofdm_tx->r_tx_antenna = 0x1;
1323 r_ofdm_tx_en_val = 0x1;
1324 p_ofdm_tx->r_ant_l = 0x1;
1325 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1326 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1327 p_cck_txrx->r_ccktx_enable = 0x8;
1328 chgTx = 1;
1329 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1330 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1331 {
1332 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1333 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1334 r_ofdm_tx_en_val = 0x3;
1335 /*/ Power save*/
1336 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1337 /*/ We need to close RFB by SW control*/
1338 if (pHalData->rf_type == RF_2T2R) {
1339 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1340 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1341 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1342 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1343 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1344 }
1345 }
1346 pMptCtx->mpt_rf_path = RF_PATH_A;
1347 break;
1348 case ANTENNA_B:
1349 p_ofdm_tx->r_tx_antenna = 0x2;
1350 r_ofdm_tx_en_val = 0x2;
1351 p_ofdm_tx->r_ant_l = 0x2;
1352 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1353 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1354 p_cck_txrx->r_ccktx_enable = 0x4;
1355 chgTx = 1;
1356 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1357 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1358 {
1359 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1360 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1361
1362 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1363 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1364 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1365 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1366 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1367 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1368 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1369 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1370 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1371 }
1372 }
1373 pMptCtx->mpt_rf_path = RF_PATH_B;
1374 break;
1375 case ANTENNA_AB:/*/ For 8192S*/
1376 p_ofdm_tx->r_tx_antenna = 0x3;
1377 r_ofdm_tx_en_val = 0x3;
1378 p_ofdm_tx->r_ant_l = 0x3;
1379 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1380 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1381 p_cck_txrx->r_ccktx_enable = 0xC;
1382 chgTx = 1;
1383 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1384 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1385 {
1386 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1387 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1388 /* Disable Power save*/
1389 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1390 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1391 if (pHalData->rf_type == RF_2T2R) {
1392 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1393
1394 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1395 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1396 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1397 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1398 }
1399 }
1400 pMptCtx->mpt_rf_path = RF_PATH_AB;
1401 break;
1402 default:
1403 break;
1404 }
1405 #if 0
1406 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1407 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1408 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1409 #endif
1410 switch (ulAntennaRx) {
1411 case ANTENNA_A:
1412 r_rx_antenna_ofdm = 0x1; /* A*/
1413 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1414 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1415 chgRx = 1;
1416 break;
1417 case ANTENNA_B:
1418 r_rx_antenna_ofdm = 0x2; /*/ B*/
1419 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1420 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1421 chgRx = 1;
1422 break;
1423 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1424 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1425 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1426 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1427 chgRx = 1;
1428 break;
1429 default:
1430 break;
1431 }
1432
1433
1434 if (chgTx && chgRx) {
1435 switch (pHalData->rf_chip) {
1436 case RF_8225:
1437 case RF_8256:
1438 case RF_6052:
1439 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1440 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1441 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1442 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1443 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1444 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1445 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1446 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1447 }
1448 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1449 break;
1450
1451 default:
1452 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1453 break;
1454 }
1455 }
1456 } /* MPT_ProSetRFPath */
1457
1458 #ifdef CONFIG_RTL8192F
1459
mpt_set_rfpath_8192f(PADAPTER pAdapter)1460 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1461 {
1462 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1463 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1464
1465 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1466 u8 NssforRate, odmNssforRate;
1467 u32 ulAntennaTx, ulAntennaRx;
1468 enum bb_path RxAntToPhyDm;
1469 enum bb_path TxAntToPhyDm;
1470
1471 ulAntennaTx = pHalData->antenna_tx_path;
1472 ulAntennaRx = pHalData->AntennaRxPath;
1473 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1474
1475 if (pHalData->rf_chip >= RF_TYPE_MAX)
1476 RTW_INFO("This RF chip ID is not supported\n");
1477
1478 switch (ulAntennaTx) {
1479 case ANTENNA_A:
1480 pMptCtx->mpt_rf_path = RF_PATH_A;
1481 TxAntToPhyDm = BB_PATH_A;
1482 break;
1483 case ANTENNA_B:
1484 pMptCtx->mpt_rf_path = RF_PATH_B;
1485 TxAntToPhyDm = BB_PATH_B;
1486 break;
1487 case ANTENNA_AB:
1488 pMptCtx->mpt_rf_path = RF_PATH_AB;
1489 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1490 break;
1491 default:
1492 pMptCtx->mpt_rf_path = RF_PATH_AB;
1493 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1494 break;
1495 }
1496
1497 switch (ulAntennaRx) {
1498 case ANTENNA_A:
1499 RxAntToPhyDm = BB_PATH_A;
1500 break;
1501 case ANTENNA_B:
1502 RxAntToPhyDm = BB_PATH_B;
1503 break;
1504 case ANTENNA_AB:
1505 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1506 break;
1507 default:
1508 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1509 break;
1510 }
1511
1512 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1513
1514 }
1515
1516 #endif
1517
hal_mpt_SetAntenna(PADAPTER pAdapter)1518 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1519 {
1520 PHAL_DATA_TYPE hal;
1521 ANTENNA_PATH anttx;
1522 enum bb_path bb_tx = 0;
1523
1524
1525 hal = GET_HAL_DATA(pAdapter);
1526 anttx = hal->antenna_tx_path;
1527
1528 switch (anttx) {
1529 case ANTENNA_A:
1530 bb_tx = BB_PATH_A;
1531 break;
1532 case ANTENNA_B:
1533 bb_tx = BB_PATH_B;
1534 break;
1535 case ANTENNA_C:
1536 bb_tx = BB_PATH_C;
1537 break;
1538 case ANTENNA_D:
1539 bb_tx = BB_PATH_D;
1540 break;
1541 case ANTENNA_AB:
1542 bb_tx = BB_PATH_AB;
1543 break;
1544 case ANTENNA_AC:
1545 bb_tx = BB_PATH_AC;
1546 break;
1547 case ANTENNA_AD:
1548 bb_tx = BB_PATH_AD;
1549 break;
1550 case ANTENNA_BC:
1551 bb_tx = BB_PATH_BC;
1552 break;
1553 case ANTENNA_BD:
1554 bb_tx = BB_PATH_BD;
1555 break;
1556 case ANTENNA_CD:
1557 bb_tx = BB_PATH_CD;
1558 break;
1559 case ANTENNA_ABC:
1560 bb_tx = BB_PATH_ABC;
1561 break;
1562 case ANTENNA_BCD:
1563 bb_tx = BB_PATH_BCD;
1564 break;
1565 case ANTENNA_ABD:
1566 bb_tx = BB_PATH_ABD;
1567 break;
1568 case ANTENNA_ACD:
1569 bb_tx = BB_PATH_ACD;
1570 break;
1571 case ANTENNA_ABCD:
1572 bb_tx = BB_PATH_ABCD;
1573 break;
1574 default:
1575 bb_tx = BB_PATH_A;
1576 break;
1577 }
1578 tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
1579 RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
1580
1581 #ifdef CONFIG_RTL8822C
1582 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1583 rtl8822c_mp_config_rfpath(pAdapter);
1584 return;
1585 }
1586 #endif
1587 #ifdef CONFIG_RTL8814A
1588 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1589 mpt_SetRFPath_8814A(pAdapter);
1590 return;
1591 }
1592 #endif
1593 #ifdef CONFIG_RTL8822B
1594 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1595 rtl8822b_mp_config_rfpath(pAdapter);
1596 return;
1597 }
1598 #endif
1599 #ifdef CONFIG_RTL8821C
1600 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1601 rtl8821c_mp_config_rfpath(pAdapter);
1602 return;
1603 }
1604 #endif
1605 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1606 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1607 mpt_SetRFPath_8812A(pAdapter);
1608 return;
1609 }
1610 #endif
1611 #ifdef CONFIG_RTL8723B
1612 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1613 mpt_SetRFPath_8723B(pAdapter);
1614 return;
1615 }
1616 #endif
1617
1618 #ifdef CONFIG_RTL8703B
1619 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1620 mpt_SetRFPath_8703B(pAdapter);
1621 return;
1622 }
1623 #endif
1624
1625 #ifdef CONFIG_RTL8723D
1626 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1627 mpt_SetRFPath_8723D(pAdapter);
1628 return;
1629 }
1630 #endif
1631
1632 #ifdef CONFIG_RTL8192F
1633 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1634 mpt_set_rfpath_8192f(pAdapter);
1635 return;
1636 }
1637 #endif
1638
1639 #ifdef CONFIG_RTL8814B
1640 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1641 rtl8814b_mp_config_rfpath(pAdapter);
1642 return;
1643 }
1644 #endif
1645
1646 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1647 mpt_SetRFPath_8821B(pAdapter);
1648 Prepare for 8822B
1649 else if (IS_HARDWARE_TYPE_8822B(Context))
1650 mpt_SetRFPath_8822B(Context);
1651 */
1652 mpt_SetRFPath_819X(pAdapter);
1653 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1654 }
1655
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1656 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1657 {
1658 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1659
1660 if (!netif_running(pAdapter->pnetdev)) {
1661 return _FAIL;
1662 }
1663
1664
1665 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1666 return _FAIL;
1667 }
1668
1669 target_ther &= 0xff;
1670
1671 pHalData->eeprom_thermal_meter = target_ther;
1672
1673 return _SUCCESS;
1674 }
1675
1676
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1677 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1678 {
1679 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1680 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1681 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1682 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1683 } else
1684 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1685
1686 }
1687
1688
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1689 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1690
1691 {
1692 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1693
1694 u32 ThermalValue = 0;
1695 s32 thermal_value_temp = 0;
1696 s8 thermal_offset = 0;
1697 u32 thermal_reg_mask = 0;
1698
1699 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1700 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1701 else
1702 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1703
1704 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1705
1706 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1707
1708 thermal_value_temp = ThermalValue + thermal_offset;
1709
1710 if (thermal_value_temp > 63)
1711 ThermalValue = 63;
1712 else if (thermal_value_temp < 0)
1713 ThermalValue = 0;
1714 else
1715 ThermalValue = thermal_value_temp;
1716
1717 return (u8)ThermalValue;
1718 }
1719
1720
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1721 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1722 {
1723 #if 0
1724 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1725 rtw_msleep_os(1000);
1726 fw_cmd_data(pAdapter, value, 1);
1727 *value &= 0xFF;
1728 #else
1729 hal_mpt_TriggerRFThermalMeter(pAdapter);
1730 rtw_msleep_os(1000);
1731 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1732 #endif
1733
1734 }
1735
1736
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1737 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1738 {
1739 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1740
1741 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1742
1743 if (bStart) {/*/ Start Single Carrier.*/
1744 /*/ Start Single Carrier.*/
1745 /*/ 1. if OFDM block on?*/
1746 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1747 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1748
1749 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1750 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1751
1752 /*/ 3. turn on scramble setting*/
1753 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1754
1755 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1756 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1757 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1758 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1759 else
1760 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1761 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1762
1763 } else {
1764 /*/ Stop Single Carrier.*/
1765 /*/ Stop Single Carrier.*/
1766 /*/ Turn off all test modes.*/
1767 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1768 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1769 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1770 else
1771 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1772 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1773
1774 rtw_msleep_os(10);
1775 /*/BB Reset*/
1776 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1777 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1778 }
1779 }
1780
1781
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1782 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1783 {
1784 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1785 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1786 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1787 u32 ulAntennaTx = pHalData->antenna_tx_path;
1788 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1789 u8 rfPath;
1790
1791 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1792 #ifdef PHYDM_MP_SUPPORT
1793 #ifdef CONFIG_RTL8814B
1794 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1795 {
1796 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1797 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1798 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1799 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1800 /* @RF LO enabled */
1801 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1802 /* @SYN1 */
1803 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1804 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1805 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1806 }
1807 #endif
1808 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1809 #endif
1810 return;
1811 }
1812
1813 switch (ulAntennaTx) {
1814 case ANTENNA_B:
1815 rfPath = RF_PATH_B;
1816 break;
1817 case ANTENNA_C:
1818 rfPath = RF_PATH_C;
1819 break;
1820 case ANTENNA_D:
1821 rfPath = RF_PATH_D;
1822 break;
1823 case ANTENNA_A:
1824 default:
1825 rfPath = RF_PATH_A;
1826 break;
1827 }
1828
1829 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1830 if (bStart) {
1831 /*/ Start Single Tone.*/
1832 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1833 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1834 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1835 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1836 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1837 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1838 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1839 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1840 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1841 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1842 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1843 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1844 #ifdef CONFIG_RTL8192F
1845 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1846 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1847 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1848 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1849 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1850 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1851 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1852 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1853 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1854 #endif
1855 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1856 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1857 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1858 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1859 } else {
1860 /*/ S0/S1 both use PATH A to configure*/
1861 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1862 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1863 }
1864 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1865 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1866 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1867 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1868 }
1869 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1870 /*Set BB REG 88C: Prevent SingleTone Fail*/
1871 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1872 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1873 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1874
1875 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1876 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1877 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1878 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1879 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1880 } else {/* S0/S1 both use PATH A to configure */
1881 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1882 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1883 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1884 }
1885 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1886 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1887 u8 p = RF_PATH_A;
1888
1889 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1890 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1891 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1892 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1893 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1894
1895 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1896
1897 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1898 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1899 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1900 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1901 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1902 }
1903 } else {
1904 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1905 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1906 #ifdef CONFIG_RTL8821C
1907 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1908 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1909 else
1910 #endif
1911 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1912 }
1913 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1914 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1915 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1916 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1917 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1918 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1919 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1920 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1921 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1922
1923 if (pHalData->external_pa_5g)
1924 {
1925 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1926 }
1927 else if (pHalData->ExternalPA_2G)
1928 {
1929 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1930 }
1931 } else {
1932 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1933 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1934
1935 if (pHalData->external_pa_5g) {
1936 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1937 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1938 } else if (pHalData->ExternalPA_2G) {
1939 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1940 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1941 }
1942 }
1943 #endif
1944 }
1945 #if defined(CONFIG_RTL8814A)
1946 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1947 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1948 #endif
1949 else /*/ Turn On SingleTone and turn off the other test modes.*/
1950 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1951
1952 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1953 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1954
1955 } else {/*/ Stop Single Ton e.*/
1956
1957 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1958 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1959 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1960 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1961 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1962 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1963 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1964 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1965 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1966 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1967 #ifdef CONFIG_RTL8192F
1968 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1969 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1970 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1971 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1972 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1973 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1974 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1975 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1976 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1977 #endif
1978 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1979 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1980 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1981 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1982 } else {
1983 /*/ S0/S1 both use PATH A to configure*/
1984 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1985 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1986 }
1987 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1988 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1989 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1990 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1991 }
1992 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1993 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1994 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1995 /*Set BB REG 88C: Prevent SingleTone Fail*/
1996 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1997 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1998 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1999 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2000 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2001 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
2002 } else { /* S0/S1 both use PATH A to configure */
2003 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2004 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2005 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
2006 }
2007 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
2008 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2009 u8 p = RF_PATH_A;
2010
2011 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
2012
2013 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
2014 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
2015 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2016 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2017 }
2018 } else {
2019 p = pMptCtx->mpt_rf_path;
2020 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2021
2022 if (IS_HARDWARE_TYPE_8821C(pAdapter))
2023 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
2024
2025 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2026 }
2027
2028 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
2029 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
2030 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
2031 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
2032
2033 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
2034 RTW_INFO("Restore RFE control Pin cbc\n");
2035 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
2036 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
2037 }
2038 #endif
2039 }
2040 #if defined(CONFIG_RTL8814A)
2041 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
2042 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
2043
2044 else/*/ Turn off all test modes.*/
2045 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2046 #endif
2047 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2048 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2049
2050 }
2051 }
2052
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)2053 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
2054 {
2055 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2056 struct dm_struct *pdm_odm = &pHalData->odmpriv;
2057 u8 Rate;
2058
2059 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
2060
2061 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2062 #ifdef PHYDM_MP_SUPPORT
2063 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
2064 #endif
2065 return;
2066 }
2067
2068 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2069 if (bStart) {/* Start Carrier Suppression.*/
2070 if (Rate <= MPT_RATE_11M) {
2071 /*/ 1. if CCK block on?*/
2072 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2073 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2074
2075 /*/Turn Off All Test Mode*/
2076 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2077 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2078 else
2079 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2080
2081 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2082 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2083
2084 /*/Set CCK Tx Test Rate*/
2085 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2086 }
2087
2088 /*Set for dynamic set Power index*/
2089 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2090 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2091
2092 } else {/* Stop Carrier Suppression.*/
2093
2094 if (Rate <= MPT_RATE_11M) {
2095 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2096 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2097
2098 /*BB Reset*/
2099 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2100 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2101 }
2102 /*Stop for dynamic set Power index*/
2103 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2104 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2105 }
2106 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2107 }
2108
hal_mpt_query_phytxok(PADAPTER pAdapter)2109 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2110 {
2111 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2112 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2113 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2114 u16 count = 0;
2115
2116 #ifdef PHYDM_MP_SUPPORT
2117 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2118 struct phydm_mp *mp = &dm->dm_mp_table;
2119
2120 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2121 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2122 count = mp->tx_phy_ok_cnt;
2123
2124 } else
2125 #endif
2126 {
2127
2128 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2129 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2130 else
2131 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2132 }
2133
2134 if (count > 50000) {
2135 rtw_reset_phy_trx_ok_counters(pAdapter);
2136 pAdapter->mppriv.tx.sended += count;
2137 count = 0;
2138 }
2139
2140 return pAdapter->mppriv.tx.sended + count;
2141
2142 }
2143
mpt_StopCckContTx(PADAPTER pAdapter)2144 static void mpt_StopCckContTx(
2145 PADAPTER pAdapter
2146 )
2147 {
2148 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2149 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2150 u8 u1bReg;
2151
2152 pMptCtx->bCckContTx = FALSE;
2153 pMptCtx->bOfdmContTx = FALSE;
2154
2155 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2156 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2157
2158 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2159 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2160 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2161
2162 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2163 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2164 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2165 }
2166
2167 /*BB Reset*/
2168 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2169 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2170
2171 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2172 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2173 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2174 }
2175
2176 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2177 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2178 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2179 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2180 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2181 }
2182
2183 } /* mpt_StopCckContTx */
2184
2185
mpt_StopOfdmContTx(PADAPTER pAdapter)2186 static void mpt_StopOfdmContTx(
2187 PADAPTER pAdapter
2188 )
2189 {
2190 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2191 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2192 u8 u1bReg;
2193 u32 data;
2194
2195 pMptCtx->bCckContTx = FALSE;
2196 pMptCtx->bOfdmContTx = FALSE;
2197
2198 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2199 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2200 else
2201 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2202
2203 rtw_mdelay_os(10);
2204
2205 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2206 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2207 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2208 }
2209
2210 /*BB Reset*/
2211 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2212 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2213
2214 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2215 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2216 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2217 }
2218 } /* mpt_StopOfdmContTx */
2219
2220
mpt_StartCckContTx(PADAPTER pAdapter)2221 static void mpt_StartCckContTx(
2222 PADAPTER pAdapter
2223 )
2224 {
2225 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2226 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2227 u32 cckrate;
2228
2229 /* 1. if CCK block on */
2230 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2231 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2232
2233 /*Turn Off All Test Mode*/
2234 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2235 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2236 else
2237 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2238
2239 cckrate = pAdapter->mppriv.rateidx;
2240
2241 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2242
2243 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2244 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2245
2246 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2247 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2248 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2249 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2250 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2251 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2252 }
2253
2254 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2255 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2256 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2257 }
2258
2259 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2260 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2261 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2262 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2263 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2264 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2265 else
2266 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2267 }
2268
2269 pMptCtx->bCckContTx = TRUE;
2270 pMptCtx->bOfdmContTx = FALSE;
2271
2272 } /* mpt_StartCckContTx */
2273
2274
mpt_StartOfdmContTx(PADAPTER pAdapter)2275 static void mpt_StartOfdmContTx(
2276 PADAPTER pAdapter
2277 )
2278 {
2279 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2280 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2281
2282 /* 1. if OFDM block on?*/
2283 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2284 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2285
2286 /* 2. set CCK test mode off, set to CCK normal mode*/
2287 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2288
2289 /* 3. turn on scramble setting*/
2290 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2291
2292 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2293 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2294 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2295 }
2296
2297 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2298 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2299 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2300 else
2301 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2302
2303 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2304 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2305 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2306 }
2307
2308 pMptCtx->bCckContTx = FALSE;
2309 pMptCtx->bOfdmContTx = TRUE;
2310 } /* mpt_StartOfdmContTx */
2311
2312 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \
2313 || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
2314 || defined(CONFIG_RTL8723F)
2315 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO * pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2316 static void mpt_convert_phydm_txinfo_for_jaguar3(
2317 RT_PMAC_TX_INFO *pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2318 {
2319 phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
2320 phydmtxinfo->mode = pMacTxInfo->Mode;
2321 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
2322 phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
2323 phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
2324 phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
2325 phydmtxinfo->bw = pMacTxInfo->BandWidth;
2326 phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
2327 phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
2328 phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
2329 phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
2330 phydmtxinfo->sfd = pMacTxInfo->SFD;
2331 phydmtxinfo->signal_field = pMacTxInfo->SignalField;
2332 phydmtxinfo->service_field = pMacTxInfo->ServiceField;
2333 phydmtxinfo->length = pMacTxInfo->LENGTH;
2334 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
2335 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
2336 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
2337 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
2338 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
2339 phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
2340 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
2341 }
2342 #endif
2343
2344 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2345 u8 mpt_ProSetPMacTx(PADAPTER Adapter)
2346 {
2347 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2348 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2349 struct mp_priv *pmppriv = &Adapter->mppriv;
2350 struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
2351 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2352 struct dm_struct *p_dm_odm;
2353 u32 u4bTmp;
2354 u8 status = _TRUE;
2355
2356 p_dm_odm = &pHalData->odmpriv;
2357
2358 #if 0
2359 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2360 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2361 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2362 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2363 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2364 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2365
2366 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2367 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2368 #endif
2369 if (pmppriv->pktInterval != 0)
2370 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2371
2372 if (pmppriv->tx.count != 0)
2373 PMacTxInfo.PacketCount = pmppriv->tx.count;
2374
2375 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2376 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2377 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2378
2379 if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
2380 return _FALSE;
2381 if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
2382 return _FALSE;
2383 if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
2384 return _FALSE;
2385 if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
2386 return _FALSE;
2387 if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
2388 return _FALSE;
2389
2390 if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
2391 PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
2392 else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
2393 PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
2394 else
2395 PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
2396
2397 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2398 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2399 struct phydm_pmac_info phydm_mactxinfo;
2400
2401 if (PMacTxInfo.bEnPMacTx == TRUE) {
2402 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2403 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2404 if (PMacTxInfo.Mode == CONTINUOUS_TX)
2405 hal_mpt_SetTxPower(Adapter);
2406 } else {
2407 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2408 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2409 pMptCtx->HWTxmode = TEST_NONE;
2410 }
2411 mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
2412 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2413 #endif
2414 return status;
2415 }
2416
2417 if (PMacTxInfo.bEnPMacTx == FALSE) {
2418 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2419 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2420 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2421 mpt_StopCckContTx(Adapter);
2422 else
2423 mpt_StopOfdmContTx(Adapter);
2424 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2425 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2426 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2427 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2428 } else
2429 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2430
2431 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2432 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2433 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2434 mpt_StopCckContTx(Adapter);
2435 else
2436 mpt_StopOfdmContTx(Adapter);
2437
2438 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2439 }
2440 pMptCtx->HWTxmode = TEST_NONE;
2441 return status;
2442 }
2443
2444 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2445
2446 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2447 pMptCtx->HWTxmode = CONTINUOUS_TX;
2448 PMacTxInfo.PacketCount = 1;
2449
2450 hal_mpt_SetTxPower(Adapter);
2451
2452 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2453 mpt_StartCckContTx(Adapter);
2454 else
2455 mpt_StartOfdmContTx(Adapter);
2456 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2457 /* Continuous TX -> HW TX -> RF Setting */
2458 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2459 PMacTxInfo.PacketCount = 1;
2460
2461 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2462 mpt_StartCckContTx(Adapter);
2463 else
2464 mpt_StartOfdmContTx(Adapter);
2465 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2466 pMptCtx->HWTxmode = PACKETS_TX;
2467 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2468 PMacTxInfo.PacketCount = 0xffff;
2469 }
2470
2471 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2472 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2473 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2474 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2475 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2476 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2477 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2478 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2479 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2480
2481 if (PMacTxInfo.bSPreamble)
2482 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2483 else
2484 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2485 } else {
2486 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2487
2488 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2489 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2490
2491 if (PMacTxInfo.PacketPattern == 0x12)
2492 u4bTmp = 0x3000000;
2493 else
2494 u4bTmp = 0;
2495 }
2496
2497 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2498 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2499 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2500 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2501 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2502 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2503 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2504 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2505 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2506 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2507
2508 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2509 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2510 }
2511
2512 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2513 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2514 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2515
2516 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2517 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2518
2519 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2520 /*& Duration & Frame control*/
2521 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2522
2523 /* Address1 [0:3]*/
2524 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2525 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2526
2527 /* Address3 [3:0]*/
2528 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2529
2530 /* Address2[0:1] & Address1 [5:4]*/
2531 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2532 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2533
2534 /* Address2 [5:2]*/
2535 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2536 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2537
2538 /* Sequence Control & Address3 [5:4]*/
2539 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2540 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2541 } else {
2542 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2543 /* & Duration & Frame control */
2544 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2545
2546 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2547 /* Address1 [0:3]*/
2548 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2549 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2550
2551 /* Address3 [3:0]*/
2552 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2553
2554 /* Address2[0:1] & Address1 [5:4]*/
2555 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2556 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2557
2558 /* Address2 [5:2] */
2559 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2560 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2561
2562 /* Sequence Control & Address3 [5:4]*/
2563 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2564 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2565 }
2566
2567 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2568
2569 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2570 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2571 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2572
2573 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2574 u32 offset = 0xb44;
2575
2576 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2577 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2578 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2579 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2580 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2581 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2582
2583 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2584 u32 offset = 0xb4c;
2585
2586 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2587 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2588 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2589 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2590 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2591 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2592 }
2593
2594 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2595 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2596 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2597 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2598 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2599 } else
2600 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2601
2602 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2603 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2604
2605 return status;
2606 }
2607
2608 #endif
2609
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2610 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2611 {
2612 u8 Rate;
2613
2614 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2615 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2616 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2617
2618 if (Rate <= MPT_RATE_11M) {
2619 if (bStart)
2620 mpt_StartCckContTx(pAdapter);
2621 else
2622 mpt_StopCckContTx(pAdapter);
2623
2624 } else if (Rate >= MPT_RATE_6M) {
2625 if (bStart)
2626 mpt_StartOfdmContTx(pAdapter);
2627 else
2628 mpt_StopOfdmContTx(pAdapter);
2629 }
2630 }
2631
mpt_trigger_tssi_tracking(PADAPTER pAdapter,u8 rf_path)2632 void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
2633 {
2634 #ifdef CONFIG_RTL8814B
2635 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2636 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2637
2638 halrf_do_tssi_8814b(pDM_Odm, rf_path);
2639 #endif
2640 }
2641
2642 #endif /* CONFIG_MP_INCLUDE*/
2643