1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #define _HAL_INTF_C_
17
18 #include <drv_types.h>
19 #include <hal_data.h>
20
21 const u32 _chip_type_to_odm_ic_type[] = {
22 0,
23 ODM_RTL8188E,
24 ODM_RTL8192E,
25 ODM_RTL8812,
26 ODM_RTL8821,
27 ODM_RTL8723B,
28 ODM_RTL8814A,
29 ODM_RTL8703B,
30 ODM_RTL8188F,
31 ODM_RTL8188F,
32 ODM_RTL8822B,
33 ODM_RTL8723D,
34 ODM_RTL8821C,
35 ODM_RTL8710B,
36 ODM_RTL8192F,
37 ODM_RTL8822C,
38 ODM_RTL8814B,
39 ODM_RTL8723F,
40 0,
41 };
42
rtw_hal_chip_configure(_adapter * padapter)43 void rtw_hal_chip_configure(_adapter *padapter)
44 {
45 padapter->hal_func.intf_chip_configure(padapter);
46 }
47
48 /*
49 * Description:
50 * Read chip internal ROM data
51 *
52 * Return:
53 * _SUCCESS success
54 * _FAIL fail
55 */
rtw_hal_read_chip_info(_adapter * padapter)56 u8 rtw_hal_read_chip_info(_adapter *padapter)
57 {
58 u8 rtn = _SUCCESS;
59 u8 hci_type = rtw_get_intf_type(padapter);
60 systime start = rtw_get_current_time();
61
62 /* before access eFuse, make sure card enable has been called */
63 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
64 && !rtw_is_hw_init_completed(padapter))
65 rtw_hal_power_on(padapter);
66
67 rtn = padapter->hal_func.read_adapter_info(padapter);
68
69 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
70 && !rtw_is_hw_init_completed(padapter))
71 rtw_hal_power_off(padapter);
72
73 RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
74
75 return rtn;
76 }
77
rtw_hal_read_chip_version(_adapter * padapter)78 void rtw_hal_read_chip_version(_adapter *padapter)
79 {
80 padapter->hal_func.read_chip_version(padapter);
81 rtw_odm_init_ic_type(padapter);
82 }
83
rtw_init_wireless_mode(_adapter * padapter)84 static void rtw_init_wireless_mode(_adapter *padapter)
85 {
86 u8 proto_wireless_mode = 0;
87 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
88 if(hal_spec->proto_cap & PROTO_CAP_11B)
89 proto_wireless_mode |= WIRELESS_11B;
90
91 if(hal_spec->proto_cap & PROTO_CAP_11G)
92 proto_wireless_mode |= WIRELESS_11G;
93 #ifdef CONFIG_80211AC_VHT
94 if(hal_spec->band_cap & BAND_CAP_5G)
95 proto_wireless_mode |= WIRELESS_11A;
96 #endif
97
98 #ifdef CONFIG_80211N_HT
99 if(hal_spec->proto_cap & PROTO_CAP_11N) {
100
101 if(hal_spec->band_cap & BAND_CAP_2G)
102 proto_wireless_mode |= WIRELESS_11_24N;
103 if(hal_spec->band_cap & BAND_CAP_5G)
104 proto_wireless_mode |= WIRELESS_11_5N;
105 }
106 #endif
107
108 #ifdef CONFIG_80211AC_VHT
109 if(hal_spec->proto_cap & PROTO_CAP_11AC)
110 proto_wireless_mode |= WIRELESS_11AC;
111 #endif
112 padapter->registrypriv.wireless_mode &= proto_wireless_mode;
113 }
114
rtw_hal_def_value_init(_adapter * padapter)115 void rtw_hal_def_value_init(_adapter *padapter)
116 {
117 if (is_primary_adapter(padapter)) {
118 /*init fw_psmode_iface_id*/
119 adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
120 /*wireless_mode*/
121 rtw_init_wireless_mode(padapter);
122 padapter->hal_func.init_default_value(padapter);
123
124 rtw_init_hal_com_default_value(padapter);
125
126 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
127 adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
128 adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
129 #endif
130 #ifdef CONFIG_HW_P0_TSF_SYNC
131 adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
132 adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
133 #endif
134
135 GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
136 }
137 }
138
rtw_hal_data_init(_adapter * padapter)139 u8 rtw_hal_data_init(_adapter *padapter)
140 {
141 if (is_primary_adapter(padapter)) {
142 padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
143 padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
144 if (padapter->HalData == NULL) {
145 RTW_INFO("cant not alloc memory for HAL DATA\n");
146 return _FAIL;
147 }
148 rtw_phydm_priv_init(padapter);
149 }
150 return _SUCCESS;
151 }
152
rtw_hal_data_deinit(_adapter * padapter)153 void rtw_hal_data_deinit(_adapter *padapter)
154 {
155 if (is_primary_adapter(padapter)) {
156 if (padapter->HalData) {
157 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
158 phy_free_filebuf(padapter);
159 #endif
160 rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
161 padapter->HalData = NULL;
162 padapter->hal_data_sz = 0;
163 }
164 }
165 }
166
rtw_hal_free_data(_adapter * padapter)167 void rtw_hal_free_data(_adapter *padapter)
168 {
169 /* free HAL Data */
170 rtw_hal_data_deinit(padapter);
171 }
rtw_hal_dm_init(_adapter * padapter)172 void rtw_hal_dm_init(_adapter *padapter)
173 {
174 if (is_primary_adapter(padapter)) {
175 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
176
177 padapter->hal_func.dm_init(padapter);
178
179 _rtw_spinlock_init(&pHalData->IQKSpinLock);
180
181 #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
182 if (pHalData->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX)
183 hal_load_txpwr_info(padapter);
184 #endif
185 phy_load_tx_power_ext_info(padapter, 1);
186 }
187 }
rtw_hal_dm_deinit(_adapter * padapter)188 void rtw_hal_dm_deinit(_adapter *padapter)
189 {
190 if (is_primary_adapter(padapter)) {
191 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
192
193 padapter->hal_func.dm_deinit(padapter);
194
195 _rtw_spinlock_free(&pHalData->IQKSpinLock);
196 }
197 }
198
rtw_chip_rftype_to_hal_rftype(_adapter * adapter,u8 limit)199 enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit)
200 {
201 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
202 u8 tx_num = 0, rx_num = 0;
203
204 /*get RF PATH from version_id.RF_TYPE */
205 if (IS_1T1R(hal_data->version_id)) {
206 tx_num = 1;
207 rx_num = 1;
208 } else if (IS_1T2R(hal_data->version_id)) {
209 tx_num = 1;
210 rx_num = 2;
211 } else if (IS_2T2R(hal_data->version_id)) {
212 tx_num = 2;
213 rx_num = 2;
214 } else if (IS_2T3R(hal_data->version_id)) {
215 tx_num = 2;
216 rx_num = 3;
217 } else if (IS_2T4R(hal_data->version_id)) {
218 tx_num = 2;
219 rx_num = 4;
220 } else if (IS_3T3R(hal_data->version_id)) {
221 tx_num = 3;
222 rx_num = 3;
223 } else if (IS_3T4R(hal_data->version_id)) {
224 tx_num = 3;
225 rx_num = 4;
226 } else if (IS_4T4R(hal_data->version_id)) {
227 tx_num = 4;
228 rx_num = 4;
229 }
230
231 if (limit) {
232 tx_num = rtw_min(tx_num, limit);
233 rx_num = rtw_min(rx_num, limit);
234 }
235
236 return trx_num_to_rf_type(tx_num, rx_num);
237 }
238
dump_hal_runtime_trx_mode(void * sel,_adapter * adapter)239 void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter)
240 {
241 struct registry_priv *regpriv = &adapter->registrypriv;
242 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
243 int i;
244
245 RTW_PRINT_SEL(sel, "txpath=0x%x, rxpath=0x%x\n", hal_data->txpath, hal_data->rxpath);
246 for (i = 0; i < hal_data->tx_nss; i++)
247 RTW_PRINT_SEL(sel, "txpath_%uss:0x%x, num:%u\n"
248 , i + 1, hal_data->txpath_nss[i]
249 , hal_data->txpath_num_nss[i]);
250 }
251
dump_hal_trx_mode(void * sel,_adapter * adapter)252 void dump_hal_trx_mode(void *sel, _adapter *adapter)
253 {
254 struct registry_priv *regpriv = &adapter->registrypriv;
255 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
256 int i;
257
258 RTW_PRINT_SEL(sel, "trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
259 , hal_data->trx_path_bmp
260 , rf_type_to_rfpath_str(hal_data->rf_type)
261 , hal_data->NumTotalRFPath
262 , hal_data->max_tx_cnt
263 );
264 RTW_PRINT_SEL(sel, "tx_nss:%u, rx_nss:%u\n"
265 , hal_data->tx_nss, hal_data->rx_nss);
266 for (i = 0; i < hal_data->tx_nss; i++)
267 RTW_PRINT_SEL(sel, "txpath_cap_num_%uss:%u\n"
268 , i + 1, hal_data->txpath_cap_num_nss[i]);
269 RTW_PRINT_SEL(sel, "\n");
270
271 dump_hal_runtime_trx_mode(sel, adapter);
272 }
273
_dump_rf_path(void * sel,_adapter * adapter)274 void _dump_rf_path(void *sel, _adapter *adapter)
275 {
276 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
277 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
278 struct registry_priv *regsty = adapter_to_regsty(adapter);
279
280 RTW_PRINT_SEL(sel, "[RF_PATH] ver_id.RF_TYPE:%s\n"
281 , rf_type_to_rfpath_str(rtw_chip_rftype_to_hal_rftype(adapter, 0)));
282 RTW_PRINT_SEL(sel, "[RF_PATH] HALSPEC's rf_reg_trx_path_bmp:0x%02x, rf_reg_path_avail_num:%u, max_tx_cnt:%u\n"
283 , hal_spec->rf_reg_trx_path_bmp, hal_spec->rf_reg_path_avail_num, hal_spec->max_tx_cnt);
284 RTW_PRINT_SEL(sel, "[RF_PATH] PG's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
285 , hal_data->eeprom_trx_path_bmp, hal_data->eeprom_max_tx_cnt);
286 RTW_PRINT_SEL(sel, "[RF_PATH] Registry's trx_path_bmp:0x%02x, tx_path_lmt:%u, rx_path_lmt:%u\n"
287 , regsty->trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
288 RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
289 , hal_data->trx_path_bmp, hal_data->max_tx_cnt);
290 RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's rf_type:%s, NumTotalRFPath:%d\n"
291 , rf_type_to_rfpath_str(hal_data->rf_type), hal_data->NumTotalRFPath);
292 }
293
294 #ifdef CONFIG_RTL8814A
295 extern enum rf_type rtl8814a_rfpath_decision(_adapter *adapter);
296 #endif
297
rtw_hal_rfpath_init(_adapter * adapter)298 u8 rtw_hal_rfpath_init(_adapter *adapter)
299 {
300 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
301 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
302
303 #ifdef CONFIG_RTL8814A
304 if (IS_HARDWARE_TYPE_8814A(adapter)) {
305 enum bb_path tx_bmp, rx_bmp;
306 hal_data->rf_type = rtl8814a_rfpath_decision(adapter);
307 rf_type_to_default_trx_bmp(hal_data->rf_type, &tx_bmp, &rx_bmp);
308 hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
309 hal_data->NumTotalRFPath = 4;
310 hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
311 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));
312 } else
313 #endif
314 {
315 struct registry_priv *regsty = adapter_to_regsty(adapter);
316 u8 trx_path_bmp;
317 u8 tx_path_num;
318 u8 rx_path_num;
319 int i;
320
321 trx_path_bmp = hal_spec->rf_reg_trx_path_bmp;
322
323 if (regsty->trx_path_bmp != 0x00) {
324 /* restrict trx_path_bmp with regsty.trx_path_bmp */
325 trx_path_bmp &= regsty->trx_path_bmp;
326 if (!trx_path_bmp) {
327 RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, regsty->trx_path_bmp:0x%02x no intersection\n"
328 , __func__, hal_spec->rf_reg_trx_path_bmp, regsty->trx_path_bmp);
329 return _FAIL;
330 }
331 } else if (hal_data->eeprom_trx_path_bmp != 0x00) {
332 /* restrict trx_path_bmp with eeprom_trx_path_bmp */
333 trx_path_bmp &= hal_data->eeprom_trx_path_bmp;
334 if (!trx_path_bmp) {
335 RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, hal_data->eeprom_trx_path_bmp:0x%02x no intersection\n"
336 , __func__, hal_spec->rf_reg_trx_path_bmp, hal_data->eeprom_trx_path_bmp);
337 return _FAIL;
338 }
339 }
340
341 /* restrict trx_path_bmp with TX and RX num limit */
342 trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
343 , regsty->tx_path_lmt, regsty->rx_path_lmt, &tx_path_num, &rx_path_num);
344 if (!trx_path_bmp) {
345 RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%02x, %u, %u) failed\n"
346 , __func__, trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
347 return _FAIL;
348 }
349 hal_data->trx_path_bmp = trx_path_bmp;
350 hal_data->rf_type = trx_bmp_to_rf_type((trx_path_bmp & 0xF0) >> 4, trx_path_bmp & 0x0F);
351 hal_data->NumTotalRFPath = rtw_max(tx_path_num, rx_path_num);
352
353 hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
354 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, tx_path_num);
355 if (hal_data->eeprom_max_tx_cnt)
356 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, hal_data->eeprom_max_tx_cnt);
357
358 if (1)
359 _dump_rf_path(RTW_DBGDUMP, adapter);
360 }
361
362 RTW_INFO("%s trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
363 , __func__
364 , hal_data->trx_path_bmp
365 , rf_type_to_rfpath_str(hal_data->rf_type)
366 , hal_data->NumTotalRFPath
367 , hal_data->max_tx_cnt);
368
369 return _SUCCESS;
370 }
371
_dump_trx_nss(void * sel,_adapter * adapter)372 void _dump_trx_nss(void *sel, _adapter *adapter)
373 {
374 struct registry_priv *regpriv = &adapter->registrypriv;
375 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
376
377 RTW_PRINT_SEL(sel, "[TRX_Nss] HALSPEC - tx_nss:%d, rx_nss:%d\n", hal_spec->tx_nss_num, hal_spec->rx_nss_num);
378 RTW_PRINT_SEL(sel, "[TRX_Nss] Registry - tx_nss:%d, rx_nss:%d\n", regpriv->tx_nss, regpriv->rx_nss);
379 RTW_PRINT_SEL(sel, "[TRX_Nss] HALDATA - tx_nss:%d, rx_nss:%d\n", GET_HAL_TX_NSS(adapter), GET_HAL_RX_NSS(adapter));
380
381 }
382 #define NSS_VALID(nss) (nss > 0)
383
rtw_hal_trxnss_init(_adapter * adapter)384 u8 rtw_hal_trxnss_init(_adapter *adapter)
385 {
386 struct registry_priv *regpriv = &adapter->registrypriv;
387 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
388 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
389 enum rf_type rf_path = GET_HAL_RFPATH(adapter);
390 int i;
391
392 hal_data->tx_nss = hal_spec->tx_nss_num;
393 hal_data->rx_nss = hal_spec->rx_nss_num;
394
395 if (NSS_VALID(regpriv->tx_nss))
396 hal_data->tx_nss = rtw_min(hal_data->tx_nss, regpriv->tx_nss);
397 hal_data->tx_nss = rtw_min(hal_data->tx_nss, hal_data->max_tx_cnt);
398 if (NSS_VALID(regpriv->rx_nss))
399 hal_data->rx_nss = rtw_min(hal_data->rx_nss, regpriv->rx_nss);
400 hal_data->rx_nss = rtw_min(hal_data->rx_nss, rf_type_to_rf_rx_cnt(rf_path));
401
402 for (i = 0; i < 4; i++) {
403 if (hal_data->tx_nss < i + 1)
404 break;
405
406 if (IS_HARDWARE_TYPE_8814B(adapter) /* 8814B is always full-TX */
407 #ifdef CONFIG_RTW_TX_NPATH_EN
408 /* these IC is capable of full-TX when macro defined */
409 || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
410 || IS_HARDWARE_TYPE_8812(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
411 || IS_HARDWARE_TYPE_8822C(adapter)
412 #endif
413 )
414 hal_data->txpath_cap_num_nss[i] = hal_data->max_tx_cnt;
415 else
416 hal_data->txpath_cap_num_nss[i] = i + 1;
417 }
418
419 if (1)
420 _dump_trx_nss(RTW_DBGDUMP, adapter);
421
422 RTW_INFO("%s tx_nss:%u, rx_nss:%u\n", __func__
423 , hal_data->tx_nss, hal_data->rx_nss);
424
425 return _SUCCESS;
426 }
427
428 #ifdef CONFIG_RTW_SW_LED
rtw_hal_sw_led_init(_adapter * padapter)429 void rtw_hal_sw_led_init(_adapter *padapter)
430 {
431 struct led_priv *ledpriv = adapter_to_led(padapter);
432
433 if (ledpriv->bRegUseLed == _FALSE)
434 return;
435
436 if (!is_primary_adapter(padapter))
437 return;
438
439 if (padapter->hal_func.InitSwLeds) {
440 padapter->hal_func.InitSwLeds(padapter);
441 rtw_led_set_ctl_en_mask_primary(padapter);
442 rtw_led_set_iface_en(padapter, 1);
443 }
444 }
445
rtw_hal_sw_led_deinit(_adapter * padapter)446 void rtw_hal_sw_led_deinit(_adapter *padapter)
447 {
448 struct led_priv *ledpriv = adapter_to_led(padapter);
449
450 if (ledpriv->bRegUseLed == _FALSE)
451 return;
452
453 if (!is_primary_adapter(padapter))
454 return;
455
456 if (padapter->hal_func.DeInitSwLeds)
457 padapter->hal_func.DeInitSwLeds(padapter);
458 }
459 #endif
460
rtw_hal_power_on(_adapter * padapter)461 u32 rtw_hal_power_on(_adapter *padapter)
462 {
463 u32 ret = 0;
464 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
465
466 ret = padapter->hal_func.hal_power_on(padapter);
467
468 #ifdef CONFIG_BT_COEXIST
469 if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
470 rtw_btcoex_PowerOnSetting(padapter);
471 #endif
472
473 return ret;
474 }
rtw_hal_power_off(_adapter * padapter)475 void rtw_hal_power_off(_adapter *padapter)
476 {
477 struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
478
479 _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
480 _rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
481
482 #ifdef CONFIG_LPS_1T1R
483 GET_HAL_DATA(padapter)->lps_1t1r = 0;
484 #endif
485
486 #ifdef CONFIG_BT_COEXIST
487 rtw_btcoex_PowerOffSetting(padapter);
488 #endif
489
490 padapter->hal_func.hal_power_off(padapter);
491 }
492
493
rtw_hal_init_opmode(_adapter * padapter)494 void rtw_hal_init_opmode(_adapter *padapter)
495 {
496 NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
497 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
498 sint fw_state;
499
500 fw_state = get_fwstate(pmlmepriv);
501
502 if (fw_state & WIFI_ADHOC_STATE)
503 networkType = Ndis802_11IBSS;
504 else if (fw_state & WIFI_STATION_STATE)
505 networkType = Ndis802_11Infrastructure;
506 #ifdef CONFIG_AP_MODE
507 else if (fw_state & WIFI_AP_STATE)
508 networkType = Ndis802_11APMode;
509 #endif
510 #ifdef CONFIG_RTW_MESH
511 else if (fw_state & WIFI_MESH_STATE)
512 networkType = Ndis802_11_mesh;
513 #endif
514 else
515 return;
516
517 rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
518 }
519
520 #ifdef CONFIG_NEW_NETDEV_HDL
rtw_hal_iface_init(_adapter * adapter)521 uint rtw_hal_iface_init(_adapter *adapter)
522 {
523 uint status = _SUCCESS;
524
525 rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
526 #ifdef RTW_HALMAC
527 rtw_hal_hw_port_enable(adapter);
528 #endif
529 rtw_sec_restore_wep_key(adapter);
530 rtw_hal_init_opmode(adapter);
531 rtw_hal_start_thread(adapter);
532 return status;
533 }
rtw_hal_init(_adapter * padapter)534 uint rtw_hal_init(_adapter *padapter)
535 {
536 uint status = _SUCCESS;
537 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
538
539 halrf_set_rfsupportability(adapter_to_phydm(padapter));
540
541 status = padapter->hal_func.hal_init(padapter);
542
543 if(pHalData ->phydm_init_result) {
544
545 status = _FAIL;
546 RTW_ERR("%s phydm init fail reason=%u \n",
547 __func__,
548 pHalData ->phydm_init_result);
549 }
550
551 if (status == _SUCCESS) {
552 rtw_set_hw_init_completed(padapter, _TRUE);
553 if (padapter->registrypriv.notch_filter == 1)
554 rtw_hal_notch_filter(padapter, 1);
555 rtw_led_control(padapter, LED_CTL_POWER_ON);
556 init_hw_mlme_ext(padapter);
557 #ifdef CONFIG_RF_POWER_TRIM
558 rtw_bb_rf_gain_offset(padapter);
559 #endif /*CONFIG_RF_POWER_TRIM*/
560 GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
561 #ifdef CONFIG_MI_WITH_MBSSID_CAM
562 rtw_mi_set_mbid_cam(padapter);
563 #endif
564 #ifdef CONFIG_SUPPORT_MULTI_BCN
565 rtw_ap_multi_bcn_cfg(padapter);
566 #endif
567 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
568 #ifdef CONFIG_DYNAMIC_SOML
569 rtw_dyn_soml_config(padapter);
570 #endif
571 #endif
572 #ifdef CONFIG_TDMADIG
573 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
574 #endif/*CONFIG_TDMADIG*/
575 rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
576 #ifdef RTW_HALMAC
577 RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
578 if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
579 rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
580 #endif
581 } else {
582 rtw_set_hw_init_completed(padapter, _FALSE);
583 RTW_ERR("%s: hal_init fail\n", __func__);
584 }
585 return status;
586 }
587 #else
rtw_hal_init(_adapter * padapter)588 uint rtw_hal_init(_adapter *padapter)
589 {
590 uint status = _SUCCESS;
591 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
592 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
593 int i;
594
595 halrf_set_rfsupportability(adapter_to_phydm(padapter));
596
597 status = padapter->hal_func.hal_init(padapter);
598
599 if(pHalData ->phydm_init_result) {
600
601 status = _FAIL;
602 RTW_ERR("%s phydm init fail reason=%u \n",
603 __func__,
604 pHalData->phydm_init_result);
605 }
606
607 if (status == _SUCCESS) {
608 rtw_set_hw_init_completed(padapter, _TRUE);
609 rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
610 #ifdef RTW_HALMAC
611 rtw_restore_hw_port_cfg(padapter);
612 #endif
613 if (padapter->registrypriv.notch_filter == 1)
614 rtw_hal_notch_filter(padapter, 1);
615
616 for (i = 0; i < dvobj->iface_nums; i++)
617 rtw_sec_restore_wep_key(dvobj->padapters[i]);
618
619 rtw_led_control(padapter, LED_CTL_POWER_ON);
620
621 init_hw_mlme_ext(padapter);
622
623 rtw_hal_init_opmode(padapter);
624
625 #ifdef CONFIG_RF_POWER_TRIM
626 rtw_bb_rf_gain_offset(padapter);
627 #endif /*CONFIG_RF_POWER_TRIM*/
628
629 #ifdef CONFIG_SUPPORT_MULTI_BCN
630 rtw_ap_multi_bcn_cfg(padapter);
631 #endif
632
633 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
634 #ifdef CONFIG_DYNAMIC_SOML
635 rtw_dyn_soml_config(padapter);
636 #endif
637 #endif
638 #ifdef CONFIG_TDMADIG
639 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
640 #endif/*CONFIG_TDMADIG*/
641
642 rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
643 #ifdef RTW_HALMAC
644 RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
645 if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
646 rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
647 #endif
648
649 } else {
650 rtw_set_hw_init_completed(padapter, _FALSE);
651 RTW_ERR("%s: fail\n", __func__);
652 }
653
654
655 return status;
656
657 }
658 #endif
659
rtw_hal_deinit(_adapter * padapter)660 uint rtw_hal_deinit(_adapter *padapter)
661 {
662 uint status = _SUCCESS;
663
664 status = padapter->hal_func.hal_deinit(padapter);
665
666 if (status == _SUCCESS) {
667 rtw_led_control(padapter, LED_CTL_POWER_OFF);
668 rtw_set_hw_init_completed(padapter, _FALSE);
669 } else
670 RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
671
672
673 return status;
674 }
675
rtw_hal_set_hwreg(_adapter * padapter,u8 variable,u8 * val)676 u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
677 {
678 return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
679 }
680
rtw_hal_get_hwreg(_adapter * padapter,u8 variable,u8 * val)681 void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
682 {
683 padapter->hal_func.GetHwRegHandler(padapter, variable, val);
684 }
685
rtw_hal_set_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)686 u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
687 {
688 return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
689 }
rtw_hal_get_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)690 u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
691 {
692 return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
693 }
694
rtw_hal_set_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)695 void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
696 {
697 padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
698 }
rtw_hal_get_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)699 void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
700 {
701 padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
702 }
703
704 /* FOR SDIO & PCIE */
rtw_hal_enable_interrupt(_adapter * padapter)705 void rtw_hal_enable_interrupt(_adapter *padapter)
706 {
707 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
708 padapter->hal_func.enable_interrupt(padapter);
709 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
710 }
711
712 /* FOR SDIO & PCIE */
rtw_hal_disable_interrupt(_adapter * padapter)713 void rtw_hal_disable_interrupt(_adapter *padapter)
714 {
715 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
716 padapter->hal_func.disable_interrupt(padapter);
717 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
718 }
719
720
rtw_hal_check_ips_status(_adapter * padapter)721 u8 rtw_hal_check_ips_status(_adapter *padapter)
722 {
723 u8 val = _FALSE;
724 if (padapter->hal_func.check_ips_status)
725 val = padapter->hal_func.check_ips_status(padapter);
726 else
727 RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
728
729 return val;
730 }
731
rtw_hal_fw_dl(_adapter * padapter,u8 wowlan)732 s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
733 {
734 s32 ret;
735
736 ret = padapter->hal_func.fw_dl(padapter, wowlan);
737
738 #ifdef CONFIG_LPS_1T1R
739 GET_HAL_DATA(padapter)->lps_1t1r = 0;
740 #endif
741
742 return ret;
743 }
744
745 #ifdef RTW_HALMAC
rtw_hal_fw_mem_dl(_adapter * padapter,enum fw_mem mem)746 s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
747 {
748 systime dlfw_start_time = rtw_get_current_time();
749 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
750 struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
751 s32 rst = _FALSE;
752
753 rst = padapter->hal_func.fw_mem_dl(padapter, mem);
754 RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
755
756 if (rst == _FALSE)
757 pdbgpriv->dbg_fw_mem_dl_error_cnt++;
758 if (1)
759 RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
760 return rst;
761 }
762 #endif
763
764 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
rtw_hal_clear_interrupt(_adapter * padapter)765 void rtw_hal_clear_interrupt(_adapter *padapter)
766 {
767 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
768 padapter->hal_func.clear_interrupt(padapter);
769 #endif
770 }
771 #endif
772
773 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
rtw_hal_inirp_init(_adapter * padapter)774 u32 rtw_hal_inirp_init(_adapter *padapter)
775 {
776 if (is_primary_adapter(padapter))
777 return padapter->hal_func.inirp_init(padapter);
778 return _SUCCESS;
779 }
rtw_hal_inirp_deinit(_adapter * padapter)780 u32 rtw_hal_inirp_deinit(_adapter *padapter)
781 {
782
783 if (is_primary_adapter(padapter))
784 return padapter->hal_func.inirp_deinit(padapter);
785
786 return _SUCCESS;
787 }
788 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
789
790 #if defined(CONFIG_PCI_HCI)
rtw_hal_irp_reset(_adapter * padapter)791 void rtw_hal_irp_reset(_adapter *padapter)
792 {
793 padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
794 }
795
rtw_hal_pci_dbi_write(_adapter * padapter,u16 addr,u8 data)796 void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
797 {
798 u16 cmd[2];
799
800 cmd[0] = addr;
801 cmd[1] = data;
802
803 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
804 }
805
rtw_hal_pci_dbi_read(_adapter * padapter,u16 addr)806 u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
807 {
808 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
809
810 return (u8)addr;
811 }
812
rtw_hal_pci_mdio_write(_adapter * padapter,u8 addr,u16 data)813 void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
814 {
815 u16 cmd[2];
816
817 cmd[0] = (u16)addr;
818 cmd[1] = data;
819
820 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
821 }
822
rtw_hal_pci_mdio_read(_adapter * padapter,u8 addr)823 u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
824 {
825 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
826
827 return (u8)addr;
828 }
829
rtw_hal_pci_l1off_nic_support(_adapter * padapter)830 u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
831 {
832 u8 l1off;
833
834 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
835 return l1off;
836 }
837
rtw_hal_pci_l1off_capability(_adapter * padapter)838 u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
839 {
840 u8 l1off;
841
842 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
843 return l1off;
844 }
845
846
847 #endif /* #if defined(CONFIG_PCI_HCI) */
848
849 /* for USB Auto-suspend */
rtw_hal_intf_ps_func(_adapter * padapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)850 u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
851 {
852 if (padapter->hal_func.interface_ps_func)
853 return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
854 return _FAIL;
855 }
856
857 #ifdef CONFIG_RTW_MGMT_QUEUE
rtw_hal_mgmt_xmitframe_enqueue(_adapter * padapter,struct xmit_frame * pxmitframe)858 s32 rtw_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
859 {
860 return padapter->hal_func.hal_mgmt_xmitframe_enqueue(padapter, pxmitframe);
861 }
862 #endif
863
rtw_hal_xmitframe_enqueue(_adapter * padapter,struct xmit_frame * pxmitframe)864 s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
865 {
866 return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
867 }
868
rtw_hal_xmit(_adapter * padapter,struct xmit_frame * pxmitframe)869 s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
870 {
871 return padapter->hal_func.hal_xmit(padapter, pxmitframe);
872 }
873
874 /*
875 * [IMPORTANT] This function would be run in interrupt context.
876 */
rtw_hal_mgnt_xmit(_adapter * padapter,struct xmit_frame * pmgntframe)877 s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
878 {
879 #ifdef CONFIG_RTW_MGMT_QUEUE
880 _irqL irqL;
881 struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
882 #endif
883 s32 ret = _FAIL;
884
885 update_mgntframe_attrib_addr(padapter, pmgntframe);
886 #ifdef CONFIG_RTW_MGMT_QUEUE
887 update_mgntframe_subtype(padapter, pmgntframe);
888 #endif
889
890 #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
891 if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
892 #ifdef CONFIG_RTW_MESH
893 || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
894 #endif
895 )
896 rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
897 #endif
898
899 #ifdef CONFIG_RTW_MGMT_QUEUE
900 if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
901 _enter_critical_bh(&pxmitpriv->lock, &irqL);
902 ret = mgmt_xmitframe_enqueue_for_sleeping_sta(padapter, pmgntframe);
903 _exit_critical_bh(&pxmitpriv->lock, &irqL);
904
905 #ifdef DBG_MGMT_QUEUE
906 if (ret == _TRUE)
907 RTW_INFO("%s doesn't be queued, dattrib->ra:"MAC_FMT" seq_num = %u, subtype = 0x%x\n",
908 __func__, MAC_ARG(pmgntframe->attrib.ra), pmgntframe->attrib.seqnum, pmgntframe->attrib.subtype);
909 #endif
910
911 if (ret == RTW_QUEUE_MGMT)
912 return ret;
913 }
914 #endif
915
916 ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
917 return ret;
918 }
919
rtw_hal_init_xmit_priv(_adapter * padapter)920 s32 rtw_hal_init_xmit_priv(_adapter *padapter)
921 {
922 return padapter->hal_func.init_xmit_priv(padapter);
923 }
rtw_hal_free_xmit_priv(_adapter * padapter)924 void rtw_hal_free_xmit_priv(_adapter *padapter)
925 {
926 padapter->hal_func.free_xmit_priv(padapter);
927 }
928
rtw_hal_init_recv_priv(_adapter * padapter)929 s32 rtw_hal_init_recv_priv(_adapter *padapter)
930 {
931 return padapter->hal_func.init_recv_priv(padapter);
932 }
rtw_hal_free_recv_priv(_adapter * padapter)933 void rtw_hal_free_recv_priv(_adapter *padapter)
934 {
935 padapter->hal_func.free_recv_priv(padapter);
936 }
937
rtw_sta_ra_registed(_adapter * padapter,struct sta_info * psta)938 void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
939 {
940 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
941
942 if (psta == NULL) {
943 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
944 rtw_warn_on(1);
945 return;
946 }
947
948 #ifdef CONFIG_AP_MODE
949 if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
950 if (psta->cmn.aid > padapter->stapriv.max_aid) {
951 RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
952 rtw_warn_on(1);
953 return;
954 }
955 rtw_ap_update_sta_ra_info(padapter, psta);
956 }
957 #endif
958
959 psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
960 /*set correct initial date rate for each mac_id */
961 hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
962
963 rtw_phydm_ra_registed(padapter, psta);
964 }
965
rtw_hal_update_ra_mask(struct sta_info * psta)966 void rtw_hal_update_ra_mask(struct sta_info *psta)
967 {
968 _adapter *padapter;
969
970 if (!psta)
971 return;
972
973 padapter = psta->padapter;
974 rtw_sta_ra_registed(padapter, psta);
975 }
976
977 /* Start specifical interface thread */
rtw_hal_start_thread(_adapter * padapter)978 void rtw_hal_start_thread(_adapter *padapter)
979 {
980 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
981 #ifndef CONFIG_SDIO_TX_TASKLET
982 padapter->hal_func.run_thread(padapter);
983 #endif
984 #endif
985 }
986 /* Start specifical interface thread */
rtw_hal_stop_thread(_adapter * padapter)987 void rtw_hal_stop_thread(_adapter *padapter)
988 {
989 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
990 #ifndef CONFIG_SDIO_TX_TASKLET
991
992 padapter->hal_func.cancel_thread(padapter);
993
994 #endif
995 #endif
996 }
997
rtw_hal_read_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask)998 u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
999 {
1000 u32 data = 0;
1001 if (padapter->hal_func.read_bbreg)
1002 data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
1003 return data;
1004 }
rtw_hal_write_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)1005 void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
1006 {
1007 if (padapter->hal_func.write_bbreg)
1008 padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
1009 }
1010
rtw_hal_read_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)1011 u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
1012 {
1013 u32 data = 0;
1014
1015 if (padapter->hal_func.read_rfreg) {
1016 data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
1017
1018 #ifdef DBG_IO
1019 if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
1020 RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
1021 , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
1022 }
1023 #endif
1024 }
1025
1026 return data;
1027 }
1028
rtw_hal_write_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)1029 void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1030 {
1031 if (padapter->hal_func.write_rfreg) {
1032
1033 #ifdef DBG_IO
1034 if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
1035 RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
1036 , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
1037 }
1038 #endif
1039
1040 padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
1041
1042 #ifdef CONFIG_PCI_HCI
1043 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
1044 rtw_udelay_os(2);
1045 #endif
1046 }
1047 }
1048
1049 #ifdef CONFIG_SYSON_INDIRECT_ACCESS
rtw_hal_read_syson_reg(PADAPTER padapter,u32 RegAddr,u32 BitMask)1050 u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
1051 {
1052 u32 data = 0;
1053 if (padapter->hal_func.read_syson_reg)
1054 data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
1055
1056 return data;
1057 }
1058
rtw_hal_write_syson_reg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)1059 void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
1060 {
1061 if (padapter->hal_func.write_syson_reg)
1062 padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
1063 }
1064 #endif
1065
1066 #if defined(CONFIG_PCI_HCI)
rtw_hal_interrupt_handler(_adapter * padapter)1067 s32 rtw_hal_interrupt_handler(_adapter *padapter)
1068 {
1069 s32 ret = _FAIL;
1070 ret = padapter->hal_func.interrupt_handler(padapter);
1071 return ret;
1072 }
1073
rtw_hal_unmap_beacon_icf(_adapter * padapter)1074 void rtw_hal_unmap_beacon_icf(_adapter *padapter)
1075 {
1076 padapter->hal_func.unmap_beacon_icf(padapter);
1077 }
1078 #endif
1079 #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
rtw_hal_interrupt_handler(_adapter * padapter,u16 pkt_len,u8 * pbuf)1080 void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
1081 {
1082 padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
1083 }
1084 #endif
1085
rtw_hal_set_chnl_bw(_adapter * padapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1086 void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
1087 {
1088 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1089 /*u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;*/
1090 u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
1091 u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
1092 u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
1093
1094 if (rtw_phydm_is_iqk_in_progress(padapter))
1095 RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
1096
1097 #ifdef CONFIG_MP_INCLUDED
1098 /* MP mode channel don't use secondary channel */
1099 if (rtw_mp_mode_check(padapter) == _FALSE)
1100 #endif
1101 {
1102 #if 0
1103 if (cch_160 != 0)
1104 cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
1105 #endif
1106 if (cch_80 != 0)
1107 cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
1108 if (cch_40 != 0)
1109 cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
1110 }
1111
1112 pHalData->cch_80 = cch_80;
1113 pHalData->cch_40 = cch_40;
1114 pHalData->cch_20 = cch_20;
1115
1116 if (0)
1117 RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
1118 , channel, ch_width_str(Bandwidth), Offset40, Offset80
1119 , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
1120
1121 padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
1122 }
1123
rtw_hal_dm_watchdog(_adapter * padapter)1124 void rtw_hal_dm_watchdog(_adapter *padapter)
1125 {
1126
1127 rtw_hal_turbo_edca(padapter);
1128 padapter->hal_func.hal_dm_watchdog(padapter);
1129 }
1130
1131 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_hal_dm_watchdog_in_lps(_adapter * padapter)1132 void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
1133 {
1134 #if defined(CONFIG_CONCURRENT_MODE)
1135 #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
1136 if (padapter->hw_port != HW_PORT0)
1137 return;
1138 #endif
1139 #endif
1140
1141 if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
1142 rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
1143 }
1144 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1145
rtw_hal_bcn_related_reg_setting(_adapter * padapter)1146 void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
1147 {
1148 padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
1149 }
1150
1151 #ifdef CONFIG_HOSTAPD_MLME
rtw_hal_hostap_mgnt_xmit_entry(_adapter * padapter,_pkt * pkt)1152 s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
1153 {
1154 if (padapter->hal_func.hostap_mgnt_xmit_entry)
1155 return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
1156 return _FAIL;
1157 }
1158 #endif /* CONFIG_HOSTAPD_MLME */
1159
1160 #ifdef DBG_CONFIG_ERROR_DETECT
rtw_hal_sreset_init(_adapter * padapter)1161 void rtw_hal_sreset_init(_adapter *padapter)
1162 {
1163 padapter->hal_func.sreset_init_value(padapter);
1164 }
rtw_hal_sreset_reset(_adapter * padapter)1165 void rtw_hal_sreset_reset(_adapter *padapter)
1166 {
1167 padapter = GET_PRIMARY_ADAPTER(padapter);
1168 padapter->hal_func.silentreset(padapter);
1169 }
1170
rtw_hal_sreset_reset_value(_adapter * padapter)1171 void rtw_hal_sreset_reset_value(_adapter *padapter)
1172 {
1173 padapter->hal_func.sreset_reset_value(padapter);
1174 }
1175
rtw_hal_sreset_xmit_status_check(_adapter * padapter)1176 void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
1177 {
1178 padapter->hal_func.sreset_xmit_status_check(padapter);
1179 }
rtw_hal_sreset_linked_status_check(_adapter * padapter)1180 void rtw_hal_sreset_linked_status_check(_adapter *padapter)
1181 {
1182 padapter->hal_func.sreset_linked_status_check(padapter);
1183 }
rtw_hal_sreset_get_wifi_status(_adapter * padapter)1184 u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
1185 {
1186 return padapter->hal_func.sreset_get_wifi_status(padapter);
1187 }
1188
rtw_hal_sreset_inprogress(_adapter * padapter)1189 bool rtw_hal_sreset_inprogress(_adapter *padapter)
1190 {
1191 padapter = GET_PRIMARY_ADAPTER(padapter);
1192 return padapter->hal_func.sreset_inprogress(padapter);
1193 }
1194 #endif /* DBG_CONFIG_ERROR_DETECT */
1195
1196 #ifdef CONFIG_IOL
rtw_hal_iol_cmd(ADAPTER * adapter,struct xmit_frame * xmit_frame,u32 max_waiting_ms,u32 bndy_cnt)1197 int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
1198 {
1199 if (adapter->hal_func.IOL_exec_cmds_sync)
1200 return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
1201 return _FAIL;
1202 }
1203 #endif
1204
1205 #ifdef CONFIG_XMIT_THREAD_MODE
rtw_hal_xmit_thread_handler(_adapter * padapter)1206 s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
1207 {
1208 return padapter->hal_func.xmit_thread_handler(padapter);
1209 }
1210 #endif
1211
1212 #ifdef CONFIG_RECV_THREAD_MODE
rtw_hal_recv_hdl(_adapter * adapter)1213 s32 rtw_hal_recv_hdl(_adapter *adapter)
1214 {
1215 return adapter->hal_func.recv_hdl(adapter);
1216 }
1217 #endif
1218
rtw_hal_notch_filter(_adapter * adapter,bool enable)1219 void rtw_hal_notch_filter(_adapter *adapter, bool enable)
1220 {
1221 if (adapter->hal_func.hal_notch_filter)
1222 adapter->hal_func.hal_notch_filter(adapter, enable);
1223 }
1224
1225 #ifdef CONFIG_FW_C2H_REG
rtw_hal_c2h_valid(_adapter * adapter,u8 * buf)1226 inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
1227 {
1228 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1229 bool ret = _FAIL;
1230
1231 ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
1232
1233 return ret;
1234 }
1235
rtw_hal_c2h_evt_read(_adapter * adapter,u8 * buf)1236 inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
1237 {
1238 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1239 s32 ret = _FAIL;
1240
1241 ret = c2h_evt_read_88xx(adapter, buf);
1242
1243 return ret;
1244 }
1245
rtw_hal_c2h_reg_hdr_parse(_adapter * adapter,u8 * buf,u8 * id,u8 * seq,u8 * plen,u8 ** payload)1246 bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
1247 {
1248 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1249 bool ret = _FAIL;
1250
1251 *id = C2H_ID_88XX(buf);
1252 *seq = C2H_SEQ_88XX(buf);
1253 *plen = C2H_PLEN_88XX(buf);
1254 *payload = C2H_PAYLOAD_88XX(buf);
1255 ret = _SUCCESS;
1256
1257 return ret;
1258 }
1259 #endif /* CONFIG_FW_C2H_REG */
1260
1261 #ifdef CONFIG_FW_C2H_PKT
rtw_hal_c2h_pkt_hdr_parse(_adapter * adapter,u8 * buf,u16 len,u8 * id,u8 * seq,u8 * plen,u8 ** payload)1262 bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
1263 {
1264 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1265 bool ret = _FAIL;
1266
1267 if (!buf || len > 256 || len < 3)
1268 goto exit;
1269
1270 *id = C2H_ID_88XX(buf);
1271 *seq = C2H_SEQ_88XX(buf);
1272 *plen = len - 2;
1273 *payload = C2H_PAYLOAD_88XX(buf);
1274 ret = _SUCCESS;
1275
1276 exit:
1277 return ret;
1278 }
1279 #endif /* CONFIG_FW_C2H_PKT */
1280
1281 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1282 #include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
1283 #endif
c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1284 s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1285 {
1286 u8 sub_id = 0;
1287 s32 ret = _SUCCESS;
1288
1289 switch (id) {
1290 case C2H_FW_SCAN_COMPLETE:
1291 RTW_INFO("[C2H], FW Scan Complete\n");
1292 break;
1293
1294 #ifdef CONFIG_BT_COEXIST
1295 case C2H_BT_INFO:
1296 rtw_btcoex_BtInfoNotify(adapter, plen, payload);
1297 break;
1298 case C2H_BT_MP_INFO:
1299 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1300 MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
1301 #endif
1302 rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
1303 break;
1304 case C2H_MAILBOX_STATUS:
1305 RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
1306 break;
1307 case C2H_WLAN_INFO:
1308 rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
1309 break;
1310 #endif /* CONFIG_BT_COEXIST */
1311
1312 case C2H_IQK_FINISH:
1313 c2h_iqk_offload(adapter, payload, plen);
1314 break;
1315
1316 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1317 case C2H_FW_CHNL_SWITCH_COMPLETE:
1318 #ifndef CONFIG_TDLS_CH_SW_V2
1319 rtw_tdls_chsw_oper_done(adapter);
1320 #endif
1321 break;
1322 #endif
1323
1324 case C2H_BCN_EARLY_RPT:
1325 rtw_hal_bcn_early_rpt_c2h_handler(adapter);
1326 break;
1327
1328 #ifdef CONFIG_MCC_MODE
1329 case C2H_MCC:
1330 rtw_hal_mcc_c2h_handler(adapter, plen, payload);
1331 break;
1332 #endif
1333
1334 #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
1335 case C2H_MAC_HIDDEN_RPT:
1336 c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
1337 break;
1338 case C2H_MAC_HIDDEN_RPT_2:
1339 c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
1340 break;
1341 #endif
1342
1343 case C2H_DEFEATURE_DBG:
1344 c2h_defeature_dbg_hdl(adapter, payload, plen);
1345 break;
1346
1347 #ifdef CONFIG_RTW_CUSTOMER_STR
1348 case C2H_CUSTOMER_STR_RPT:
1349 c2h_customer_str_rpt_hdl(adapter, payload, plen);
1350 break;
1351 case C2H_CUSTOMER_STR_RPT_2:
1352 c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
1353 break;
1354 #endif
1355 #ifdef RTW_PER_CMD_SUPPORT_FW
1356 case C2H_PER_RATE_RPT:
1357 c2h_per_rate_rpt_hdl(adapter, payload, plen);
1358 break;
1359 #endif
1360 #ifdef CONFIG_LPS_ACK
1361 case C2H_LPS_STATUS_RPT:
1362 c2h_lps_status_rpt(adapter, payload, plen);
1363 break;
1364 #endif
1365 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
1366 case C2H_SET_TXPWR_FINISH:
1367 c2h_txpwr_idx_offload_done(adapter, payload, plen);
1368 break;
1369 #endif
1370 case C2H_EXTEND:
1371 sub_id = payload[0];
1372 /* no handle, goto default */
1373 /* fall through */
1374
1375 default:
1376 if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
1377 ret = _FAIL;
1378 break;
1379 }
1380
1381 if (ret != _SUCCESS) {
1382 if (id == C2H_EXTEND)
1383 RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
1384 else
1385 RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
1386 }
1387
1388 return ret;
1389 }
1390
1391 #ifndef RTW_HALMAC
rtw_hal_c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1392 s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1393 {
1394 s32 ret = _FAIL;
1395
1396 ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
1397 if (ret != _SUCCESS)
1398 ret = c2h_handler(adapter, id, seq, plen, payload);
1399
1400 return ret;
1401 }
1402
rtw_hal_c2h_id_handle_directly(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1403 s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1404 {
1405 switch (id) {
1406 case C2H_CCX_TX_RPT:
1407 case C2H_BT_MP_INFO:
1408 case C2H_FW_CHNL_SWITCH_COMPLETE:
1409 case C2H_IQK_FINISH:
1410 case C2H_MCC:
1411 case C2H_BCN_EARLY_RPT:
1412 case C2H_AP_REQ_TXRPT:
1413 case C2H_SPC_STAT:
1414 case C2H_SET_TXPWR_FINISH:
1415 return _TRUE;
1416 default:
1417 return _FALSE;
1418 }
1419 }
1420 #endif /* !RTW_HALMAC */
1421
rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)1422 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
1423 {
1424 return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
1425 }
1426
1427 #ifdef CONFIG_PROTSEL_MACSLEEP
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1428 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1429 {
1430 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1431 u16 reg_sleep_info = macid_ctl->reg_sleep_info;
1432 u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
1433 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1434 u8 bit_shift;
1435 u32 val32;
1436 s32 ret = _FAIL;
1437
1438 if (macid >= macid_ctl->num) {
1439 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1440 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1441 goto exit;
1442 }
1443
1444 if (macid < 32) {
1445 bit_shift = macid;
1446 #if (MACID_NUM_SW_LIMIT > 32)
1447 } else if (macid < 64) {
1448 bit_shift = macid - 32;
1449 #endif
1450 #if (MACID_NUM_SW_LIMIT > 64)
1451 } else if (macid < 96) {
1452 bit_shift = macid - 64;
1453 #endif
1454 #if (MACID_NUM_SW_LIMIT > 96)
1455 } else if (macid < 128) {
1456 bit_shift = macid - 96;
1457 #endif
1458 } else {
1459 rtw_warn_on(1);
1460 goto exit;
1461 }
1462
1463 if (!reg_sleep_ctrl || !reg_sleep_info) {
1464 rtw_warn_on(1);
1465 goto exit;
1466 }
1467
1468 val32 = rtw_read32(adapter, reg_sleep_ctrl);
1469 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1470 rtw_write32(adapter, reg_sleep_ctrl, val32);
1471
1472 val32 = rtw_read32(adapter, reg_sleep_info);
1473 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1474 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1475 , macid, reg_sleep_info, val32);
1476
1477 ret = _SUCCESS;
1478
1479 if (sleep) {
1480 if (val32 & BIT(bit_shift))
1481 goto exit;
1482 val32 |= BIT(bit_shift);
1483 } else {
1484 if (!(val32 & BIT(bit_shift)))
1485 goto exit;
1486 val32 &= ~BIT(bit_shift);
1487 }
1488
1489 rtw_write32(adapter, reg_sleep_info, val32);
1490
1491 exit:
1492 return ret;
1493 }
1494 #else
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1495 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1496 {
1497 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1498 u16 reg_sleep;
1499 u8 bit_shift;
1500 u32 val32;
1501 s32 ret = _FAIL;
1502
1503 if (macid >= macid_ctl->num) {
1504 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1505 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1506 goto exit;
1507 }
1508
1509 if (macid < 32) {
1510 reg_sleep = macid_ctl->reg_sleep_m0;
1511 bit_shift = macid;
1512 #if (MACID_NUM_SW_LIMIT > 32)
1513 } else if (macid < 64) {
1514 reg_sleep = macid_ctl->reg_sleep_m1;
1515 bit_shift = macid - 32;
1516 #endif
1517 #if (MACID_NUM_SW_LIMIT > 64)
1518 } else if (macid < 96) {
1519 reg_sleep = macid_ctl->reg_sleep_m2;
1520 bit_shift = macid - 64;
1521 #endif
1522 #if (MACID_NUM_SW_LIMIT > 96)
1523 } else if (macid < 128) {
1524 reg_sleep = macid_ctl->reg_sleep_m3;
1525 bit_shift = macid - 96;
1526 #endif
1527 } else {
1528 rtw_warn_on(1);
1529 goto exit;
1530 }
1531
1532 if (!reg_sleep) {
1533 rtw_warn_on(1);
1534 goto exit;
1535 }
1536
1537 val32 = rtw_read32(adapter, reg_sleep);
1538 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1539 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1540 , macid, reg_sleep, val32);
1541
1542 ret = _SUCCESS;
1543
1544 if (sleep) {
1545 if (val32 & BIT(bit_shift))
1546 goto exit;
1547 val32 |= BIT(bit_shift);
1548 } else {
1549 if (!(val32 & BIT(bit_shift)))
1550 goto exit;
1551 val32 &= ~BIT(bit_shift);
1552 }
1553
1554 rtw_write32(adapter, reg_sleep, val32);
1555
1556 exit:
1557 return ret;
1558 }
1559 #endif
1560
rtw_hal_macid_sleep(_adapter * adapter,u8 macid)1561 inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
1562 {
1563 return _rtw_hal_macid_sleep(adapter, macid, 1);
1564 }
1565
rtw_hal_macid_wakeup(_adapter * adapter,u8 macid)1566 inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
1567 {
1568 return _rtw_hal_macid_sleep(adapter, macid, 0);
1569 }
1570
1571 #ifdef CONFIG_PROTSEL_MACSLEEP
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1572 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1573 {
1574 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1575 u16 reg_sleep_info = macid_ctl->reg_sleep_info;
1576 u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
1577 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1578 u32 m;
1579 u8 mid = 0;
1580 u32 val32;
1581
1582 do {
1583 if (mid == 0) {
1584 m = bmp->m0;
1585 #if (MACID_NUM_SW_LIMIT > 32)
1586 } else if (mid == 1) {
1587 m = bmp->m1;
1588 #endif
1589 #if (MACID_NUM_SW_LIMIT > 64)
1590 } else if (mid == 2) {
1591 m = bmp->m2;
1592 #endif
1593 #if (MACID_NUM_SW_LIMIT > 96)
1594 } else if (mid == 3) {
1595 m = bmp->m3;
1596 #endif
1597 } else {
1598 rtw_warn_on(1);
1599 break;
1600 }
1601
1602 if (m == 0)
1603 goto move_next;
1604
1605 if (!reg_sleep_ctrl || !reg_sleep_info) {
1606 rtw_warn_on(1);
1607 break;
1608 }
1609
1610 val32 = rtw_read32(adapter, reg_sleep_ctrl);
1611 val32 = (val32 &~sel_mask_sel) | (mid & sel_mask_sel);
1612 rtw_write32(adapter, reg_sleep_ctrl, val32);
1613
1614 val32 = rtw_read32(adapter, reg_sleep_info);
1615 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1616 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1617 , mid, m, reg_sleep_info, val32);
1618
1619 if (sleep) {
1620 if ((val32 & m) == m)
1621 goto move_next;
1622 val32 |= m;
1623 } else {
1624 if ((val32 & m) == 0)
1625 goto move_next;
1626 val32 &= ~m;
1627 }
1628
1629 rtw_write32(adapter, reg_sleep_info, val32);
1630
1631 move_next:
1632 mid++;
1633 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1634
1635 return _SUCCESS;
1636 }
1637 #else
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1638 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1639 {
1640 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1641 u16 reg_sleep;
1642 u32 m;
1643 u8 mid = 0;
1644 u32 val32;
1645
1646 do {
1647 if (mid == 0) {
1648 m = bmp->m0;
1649 reg_sleep = macid_ctl->reg_sleep_m0;
1650 #if (MACID_NUM_SW_LIMIT > 32)
1651 } else if (mid == 1) {
1652 m = bmp->m1;
1653 reg_sleep = macid_ctl->reg_sleep_m1;
1654 #endif
1655 #if (MACID_NUM_SW_LIMIT > 64)
1656 } else if (mid == 2) {
1657 m = bmp->m2;
1658 reg_sleep = macid_ctl->reg_sleep_m2;
1659 #endif
1660 #if (MACID_NUM_SW_LIMIT > 96)
1661 } else if (mid == 3) {
1662 m = bmp->m3;
1663 reg_sleep = macid_ctl->reg_sleep_m3;
1664 #endif
1665 } else {
1666 rtw_warn_on(1);
1667 break;
1668 }
1669
1670 if (m == 0)
1671 goto move_next;
1672
1673 if (!reg_sleep) {
1674 rtw_warn_on(1);
1675 break;
1676 }
1677
1678 val32 = rtw_read32(adapter, reg_sleep);
1679 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1680 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1681 , mid, m, reg_sleep, val32);
1682
1683 if (sleep) {
1684 if ((val32 & m) == m)
1685 goto move_next;
1686 val32 |= m;
1687 } else {
1688 if ((val32 & m) == 0)
1689 goto move_next;
1690 val32 &= ~m;
1691 }
1692
1693 rtw_write32(adapter, reg_sleep, val32);
1694
1695 move_next:
1696 mid++;
1697 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1698
1699 return _SUCCESS;
1700 }
1701 #endif
1702
rtw_hal_macid_sleep_all_used(_adapter * adapter)1703 inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
1704 {
1705 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1706
1707 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
1708 }
1709
rtw_hal_macid_wakeup_all_used(_adapter * adapter)1710 inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
1711 {
1712 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1713
1714 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
1715 }
1716
_rtw_hal_macid_drop(_adapter * adapter,u8 macid,u8 drop)1717 static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
1718 {
1719 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1720 #ifndef CONFIG_PROTSEL_MACSLEEP
1721 u16 reg_drop = 0;
1722 #else
1723 u16 reg_drop_info = macid_ctl->reg_drop_info;
1724 u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
1725 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1726 #endif /* CONFIG_PROTSEL_MACSLEEP */
1727 u8 bit_shift;
1728 u32 val32;
1729 s32 ret = _FAIL;
1730 /* some IC doesn't have this register */
1731 #ifndef REG_PKT_BUFF_ACCESS_CTRL
1732 #define REG_PKT_BUFF_ACCESS_CTRL 0
1733 #endif
1734
1735 if (macid >= macid_ctl->num) {
1736 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1737 , ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
1738 goto exit;
1739 }
1740
1741 if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
1742 if (macid < 32) {
1743 #ifndef CONFIG_PROTSEL_MACSLEEP
1744 reg_drop = macid_ctl->reg_drop_m0;
1745 #endif /* CONFIG_PROTSEL_MACSLEEP */
1746 bit_shift = macid;
1747 #if (MACID_NUM_SW_LIMIT > 32)
1748 } else if (macid < 64) {
1749 #ifndef CONFIG_PROTSEL_MACSLEEP
1750 reg_drop = macid_ctl->reg_drop_m1;
1751 #endif /* CONFIG_PROTSEL_MACSLEEP */
1752 bit_shift = macid - 32;
1753 #endif
1754 #if (MACID_NUM_SW_LIMIT > 64)
1755 } else if (macid < 96) {
1756 #ifndef CONFIG_PROTSEL_MACSLEEP
1757 reg_drop = macid_ctl->reg_drop_m2;
1758 #endif /* CONFIG_PROTSEL_MACSLEEP */
1759 bit_shift = macid - 64;
1760 #endif
1761 #if (MACID_NUM_SW_LIMIT > 96)
1762 } else if (macid < 128) {
1763 #ifndef CONFIG_PROTSEL_MACSLEEP
1764 reg_drop = macid_ctl->reg_drop_m3;
1765 #endif /* CONFIG_PROTSEL_MACSLEEP */
1766 bit_shift = macid - 96;
1767 #endif
1768 } else {
1769 rtw_warn_on(1);
1770 goto exit;
1771 }
1772
1773 #ifndef CONFIG_PROTSEL_MACSLEEP
1774 if (!reg_drop) {
1775 rtw_warn_on(1);
1776 goto exit;
1777 }
1778 val32 = rtw_read32(adapter, reg_drop);
1779 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
1780 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1781 , macid, reg_drop, val32);*/
1782 #else
1783 if (!reg_drop_ctrl || !reg_drop_info) {
1784 rtw_warn_on(1);
1785 goto exit;
1786 }
1787
1788 val32 = rtw_read32(adapter, reg_drop_ctrl);
1789 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1790 rtw_write32(adapter, reg_drop_ctrl, val32);
1791
1792 val32 = rtw_read32(adapter, reg_drop_info);
1793 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1794 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1795 , macid, reg_drop_info, val32);*/
1796 #endif /* CONFIG_PROTSEL_MACSLEEP */
1797 ret = _SUCCESS;
1798
1799 if (drop) {
1800 if (val32 & BIT(bit_shift))
1801 goto exit;
1802 val32 |= BIT(bit_shift);
1803 } else {
1804 if (!(val32 & BIT(bit_shift)))
1805 goto exit;
1806 val32 &= ~BIT(bit_shift);
1807 }
1808
1809 #ifndef CONFIG_PROTSEL_MACSLEEP
1810 rtw_write32(adapter, reg_drop, val32);
1811 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1812 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1813 , macid, reg_drop, val32);
1814 #else
1815 rtw_write32(adapter, reg_drop_info, val32);
1816 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1817 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1818 , macid, reg_drop_info, val32);
1819 #endif /* CONFIG_PROTSEL_MACSLEEP */
1820
1821
1822 } else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
1823 u16 start_addr = macid_ctl->macid_txrpt/8;
1824 u32 txrpt_h4b = 0;
1825 u8 i;
1826
1827 /* each address means 1 byte */
1828 start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
1829 /* select tx report buffer */
1830 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
1831 /* set tx report buffer start address for reading */
1832 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1833 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
1834 /* OFFSET5 BIT2 is BIT10 of high 4 bytes */
1835 if (drop) {
1836 if (txrpt_h4b & BIT(10))
1837 goto exit;
1838 txrpt_h4b |= BIT(10);
1839 } else {
1840 if (!(txrpt_h4b & BIT(10)))
1841 goto exit;
1842 txrpt_h4b &= ~BIT(10);
1843 }
1844 /* set to macid drop field */
1845 rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
1846 /* 0x20800000 only write BIT10 of tx report buf */
1847 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
1848 #if 0 /* some ICs doesn't clear the write done bit */
1849 /* checking TX queue status */
1850 for (i = 0 ; i < 50 ; i++) {
1851 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
1852 if (txrpt_h4b & BIT(23)) {
1853 RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
1854 rtw_mdelay_os(10);
1855 } else {
1856 RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
1857 break;
1858 }
1859 }
1860 #endif
1861 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1862 RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
1863 ,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
1864 } else {
1865 RTW_INFO("There is no definition for camctl cap , please correct it\n");
1866 }
1867 exit:
1868 return ret;
1869 }
1870
rtw_hal_macid_drop(_adapter * adapter,u8 macid)1871 inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
1872 {
1873 return _rtw_hal_macid_drop(adapter, macid, 1);
1874 }
1875
rtw_hal_macid_undrop(_adapter * adapter,u8 macid)1876 inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
1877 {
1878 return _rtw_hal_macid_drop(adapter, macid, 0);
1879 }
1880
rtw_hal_fill_h2c_cmd(PADAPTER padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)1881 s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
1882 {
1883 _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
1884
1885 if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
1886 return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
1887 else if (padapter->registrypriv.mp_mode == 0)
1888 RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
1889 , FUNC_ADPT_ARG(padapter), ElementID);
1890 return _FAIL;
1891 }
1892
rtw_hal_fill_fake_txdesc(_adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)1893 void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
1894 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
1895 {
1896 padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
1897
1898 }
1899
rtw_hal_get_txbuff_rsvd_page_num(_adapter * adapter,bool wowlan)1900 u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
1901 {
1902 u8 num = 0;
1903
1904
1905 if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1906 num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
1907 } else {
1908 #ifdef RTW_HALMAC
1909 num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
1910 #endif /* RTW_HALMAC */
1911 }
1912
1913 return num;
1914 }
1915
1916 #ifdef CONFIG_GPIO_API
rtw_hal_update_hisr_hsisr_ind(_adapter * padapter,u32 flag)1917 void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
1918 {
1919 if (padapter->hal_func.update_hisr_hsisr_ind)
1920 padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
1921 }
1922
rtw_hal_gpio_func_check(_adapter * padapter,u8 gpio_num)1923 int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
1924 {
1925 int ret = _SUCCESS;
1926
1927 if (padapter->hal_func.hal_gpio_func_check)
1928 ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
1929
1930 return ret;
1931 }
1932
rtw_hal_gpio_multi_func_reset(_adapter * padapter,u8 gpio_num)1933 void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
1934 {
1935 if (padapter->hal_func.hal_gpio_multi_func_reset)
1936 padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
1937 }
1938 #endif
1939
1940 #ifdef CONFIG_FW_CORRECT_BCN
rtw_hal_fw_correct_bcn(_adapter * padapter)1941 void rtw_hal_fw_correct_bcn(_adapter *padapter)
1942 {
1943 if (padapter->hal_func.fw_correct_bcn)
1944 padapter->hal_func.fw_correct_bcn(padapter);
1945 }
1946 #endif
1947
rtw_hal_set_tx_power_level(_adapter * adapter,u8 channel)1948 void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
1949 {
1950 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1951
1952 if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
1953 return;
1954
1955 hal_data->set_entire_txpwr = 1;
1956
1957 adapter->hal_func.set_tx_power_level_handler(adapter, channel);
1958 rtw_hal_set_txpwr_done(adapter);
1959
1960 hal_data->set_entire_txpwr = 0;
1961 }
1962
rtw_hal_update_txpwr_level(_adapter * adapter)1963 void rtw_hal_update_txpwr_level(_adapter *adapter)
1964 {
1965 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1966
1967 rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
1968 rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), 0, 0);
1969 }
1970
rtw_hal_set_txpwr_done(_adapter * adapter)1971 void rtw_hal_set_txpwr_done(_adapter *adapter)
1972 {
1973 if (adapter->hal_func.set_txpwr_done)
1974 adapter->hal_func.set_txpwr_done(adapter);
1975 }
1976
rtw_hal_set_tx_power_index(_adapter * adapter,u32 powerindex,enum rf_path rfpath,u8 rate)1977 void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
1978 , enum rf_path rfpath, u8 rate)
1979 {
1980 adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
1981 }
1982
rtw_hal_get_tx_power_index(_adapter * adapter,enum rf_path rfpath,RATE_SECTION rs,enum MGN_RATE rate,enum channel_width bw,BAND_TYPE band,u8 cch,u8 opch,struct txpwr_idx_comp * tic)1983 u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
1984 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
1985 , struct txpwr_idx_comp *tic)
1986 {
1987 return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath
1988 , rs, rate, bw, band, cch, opch, tic);
1989 }
1990
rtw_hal_get_txpwr_target_extra_bias(_adapter * adapter,enum rf_path rfpath,RATE_SECTION rs,enum MGN_RATE rate,enum channel_width bw,BAND_TYPE band,u8 cch)1991 s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
1992 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch)
1993 {
1994 s8 val = 0;
1995
1996 if (adapter->hal_func.get_txpwr_target_extra_bias) {
1997 val = adapter->hal_func.get_txpwr_target_extra_bias(adapter
1998 , rfpath, rs, rate, bw, band, cch);
1999 }
2000
2001 return val;
2002 }
2003
2004 #ifdef RTW_HALMAC
2005 /*
2006 * Description:
2007 * Initialize MAC registers
2008 *
2009 * Return:
2010 * _TRUE success
2011 * _FALSE fail
2012 */
rtw_hal_init_mac_register(PADAPTER adapter)2013 u8 rtw_hal_init_mac_register(PADAPTER adapter)
2014 {
2015 return adapter->hal_func.init_mac_register(adapter);
2016 }
2017
2018 /*
2019 * Description:
2020 * Initialize PHY(BB/RF) related functions
2021 *
2022 * Return:
2023 * _TRUE success
2024 * _FALSE fail
2025 */
rtw_hal_init_phy(PADAPTER adapter)2026 u8 rtw_hal_init_phy(PADAPTER adapter)
2027 {
2028 return adapter->hal_func.init_phy(adapter);
2029 }
2030 #endif /* RTW_HALMAC */
2031
2032 #ifdef CONFIG_RFKILL_POLL
rtw_hal_rfkill_poll(_adapter * adapter,u8 * valid)2033 bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
2034 {
2035 bool ret;
2036
2037 if (adapter->hal_func.hal_radio_onoff_check)
2038 ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
2039 else {
2040 *valid = 0;
2041 ret = _FALSE;
2042 }
2043 return ret;
2044 }
2045 #endif
2046
2047 #define rtw_hal_error_msg(ops_fun) \
2048 RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
2049
rtw_hal_ops_check(_adapter * padapter)2050 u8 rtw_hal_ops_check(_adapter *padapter)
2051 {
2052 u8 ret = _SUCCESS;
2053 #if 1
2054 /*** initialize section ***/
2055 if (NULL == padapter->hal_func.read_chip_version) {
2056 rtw_hal_error_msg("read_chip_version");
2057 ret = _FAIL;
2058 }
2059 if (NULL == padapter->hal_func.init_default_value) {
2060 rtw_hal_error_msg("init_default_value");
2061 ret = _FAIL;
2062 }
2063 if (NULL == padapter->hal_func.intf_chip_configure) {
2064 rtw_hal_error_msg("intf_chip_configure");
2065 ret = _FAIL;
2066 }
2067 if (NULL == padapter->hal_func.read_adapter_info) {
2068 rtw_hal_error_msg("read_adapter_info");
2069 ret = _FAIL;
2070 }
2071
2072 if (NULL == padapter->hal_func.hal_power_on) {
2073 rtw_hal_error_msg("hal_power_on");
2074 ret = _FAIL;
2075 }
2076 if (NULL == padapter->hal_func.hal_power_off) {
2077 rtw_hal_error_msg("hal_power_off");
2078 ret = _FAIL;
2079 }
2080
2081 if (NULL == padapter->hal_func.hal_init) {
2082 rtw_hal_error_msg("hal_init");
2083 ret = _FAIL;
2084 }
2085 if (NULL == padapter->hal_func.hal_deinit) {
2086 rtw_hal_error_msg("hal_deinit");
2087 ret = _FAIL;
2088 }
2089
2090 /*** xmit section ***/
2091 if (NULL == padapter->hal_func.init_xmit_priv) {
2092 rtw_hal_error_msg("init_xmit_priv");
2093 ret = _FAIL;
2094 }
2095 if (NULL == padapter->hal_func.free_xmit_priv) {
2096 rtw_hal_error_msg("free_xmit_priv");
2097 ret = _FAIL;
2098 }
2099 if (NULL == padapter->hal_func.hal_xmit) {
2100 rtw_hal_error_msg("hal_xmit");
2101 ret = _FAIL;
2102 }
2103 if (NULL == padapter->hal_func.mgnt_xmit) {
2104 rtw_hal_error_msg("mgnt_xmit");
2105 ret = _FAIL;
2106 }
2107 #ifdef CONFIG_XMIT_THREAD_MODE
2108 if (NULL == padapter->hal_func.xmit_thread_handler) {
2109 rtw_hal_error_msg("xmit_thread_handler");
2110 ret = _FAIL;
2111 }
2112 #endif
2113 if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
2114 rtw_hal_error_msg("hal_xmitframe_enqueue");
2115 ret = _FAIL;
2116 }
2117 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2118 #ifndef CONFIG_SDIO_TX_TASKLET
2119 if (NULL == padapter->hal_func.run_thread) {
2120 rtw_hal_error_msg("run_thread");
2121 ret = _FAIL;
2122 }
2123 if (NULL == padapter->hal_func.cancel_thread) {
2124 rtw_hal_error_msg("cancel_thread");
2125 ret = _FAIL;
2126 }
2127 #endif
2128 #endif
2129
2130 /*** recv section ***/
2131 if (NULL == padapter->hal_func.init_recv_priv) {
2132 rtw_hal_error_msg("init_recv_priv");
2133 ret = _FAIL;
2134 }
2135 if (NULL == padapter->hal_func.free_recv_priv) {
2136 rtw_hal_error_msg("free_recv_priv");
2137 ret = _FAIL;
2138 }
2139 #ifdef CONFIG_RECV_THREAD_MODE
2140 if (NULL == padapter->hal_func.recv_hdl) {
2141 rtw_hal_error_msg("recv_hdl");
2142 ret = _FAIL;
2143 }
2144 #endif
2145 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
2146 if (NULL == padapter->hal_func.inirp_init) {
2147 rtw_hal_error_msg("inirp_init");
2148 ret = _FAIL;
2149 }
2150 if (NULL == padapter->hal_func.inirp_deinit) {
2151 rtw_hal_error_msg("inirp_deinit");
2152 ret = _FAIL;
2153 }
2154 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
2155
2156
2157 /*** interrupt hdl section ***/
2158 #if defined(CONFIG_PCI_HCI)
2159 if (NULL == padapter->hal_func.irp_reset) {
2160 rtw_hal_error_msg("irp_reset");
2161 ret = _FAIL;
2162 }
2163 #endif/*#if defined(CONFIG_PCI_HCI)*/
2164 #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
2165 if (NULL == padapter->hal_func.interrupt_handler) {
2166 rtw_hal_error_msg("interrupt_handler");
2167 ret = _FAIL;
2168 }
2169 #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
2170
2171 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
2172 if (NULL == padapter->hal_func.enable_interrupt) {
2173 rtw_hal_error_msg("enable_interrupt");
2174 ret = _FAIL;
2175 }
2176 if (NULL == padapter->hal_func.disable_interrupt) {
2177 rtw_hal_error_msg("disable_interrupt");
2178 ret = _FAIL;
2179 }
2180 #endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
2181
2182
2183 /*** DM section ***/
2184 if (NULL == padapter->hal_func.dm_init) {
2185 rtw_hal_error_msg("dm_init");
2186 ret = _FAIL;
2187 }
2188 if (NULL == padapter->hal_func.dm_deinit) {
2189 rtw_hal_error_msg("dm_deinit");
2190 ret = _FAIL;
2191 }
2192 if (NULL == padapter->hal_func.hal_dm_watchdog) {
2193 rtw_hal_error_msg("hal_dm_watchdog");
2194 ret = _FAIL;
2195 }
2196
2197 /*** xxx section ***/
2198 if (NULL == padapter->hal_func.set_chnl_bw_handler) {
2199 rtw_hal_error_msg("set_chnl_bw_handler");
2200 ret = _FAIL;
2201 }
2202
2203 if (NULL == padapter->hal_func.set_hw_reg_handler) {
2204 rtw_hal_error_msg("set_hw_reg_handler");
2205 ret = _FAIL;
2206 }
2207 if (NULL == padapter->hal_func.GetHwRegHandler) {
2208 rtw_hal_error_msg("GetHwRegHandler");
2209 ret = _FAIL;
2210 }
2211 if (NULL == padapter->hal_func.get_hal_def_var_handler) {
2212 rtw_hal_error_msg("get_hal_def_var_handler");
2213 ret = _FAIL;
2214 }
2215 if (NULL == padapter->hal_func.SetHalDefVarHandler) {
2216 rtw_hal_error_msg("SetHalDefVarHandler");
2217 ret = _FAIL;
2218 }
2219 if (NULL == padapter->hal_func.GetHalODMVarHandler) {
2220 rtw_hal_error_msg("GetHalODMVarHandler");
2221 ret = _FAIL;
2222 }
2223 if (NULL == padapter->hal_func.SetHalODMVarHandler) {
2224 rtw_hal_error_msg("SetHalODMVarHandler");
2225 ret = _FAIL;
2226 }
2227
2228 if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
2229 rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
2230 ret = _FAIL;
2231 }
2232
2233 if (NULL == padapter->hal_func.fill_h2c_cmd) {
2234 rtw_hal_error_msg("fill_h2c_cmd");
2235 ret = _FAIL;
2236 }
2237
2238 #ifdef RTW_HALMAC
2239 if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
2240 rtw_hal_error_msg("hal_mac_c2h_handler");
2241 ret = _FAIL;
2242 }
2243 #elif !defined(CONFIG_RTL8188E)
2244 if (NULL == padapter->hal_func.c2h_handler) {
2245 rtw_hal_error_msg("c2h_handler");
2246 ret = _FAIL;
2247 }
2248 #endif
2249
2250 #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2251 if (NULL == padapter->hal_func.fill_fake_txdesc) {
2252 rtw_hal_error_msg("fill_fake_txdesc");
2253 ret = _FAIL;
2254 }
2255 #endif
2256
2257 #ifndef RTW_HALMAC
2258 if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
2259 rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
2260 ret = _FAIL;
2261 }
2262 #endif /* !RTW_HALMAC */
2263
2264 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2265 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2266 if (NULL == padapter->hal_func.clear_interrupt) {
2267 rtw_hal_error_msg("clear_interrupt");
2268 ret = _FAIL;
2269 }
2270 #endif
2271 #endif /* CONFIG_WOWLAN */
2272
2273 if (NULL == padapter->hal_func.fw_dl) {
2274 rtw_hal_error_msg("fw_dl");
2275 ret = _FAIL;
2276 }
2277
2278 #ifdef CONFIG_FW_CORRECT_BCN
2279 if (IS_HARDWARE_TYPE_8814A(padapter)
2280 && NULL == padapter->hal_func.fw_correct_bcn) {
2281 rtw_hal_error_msg("fw_correct_bcn");
2282 ret = _FAIL;
2283 }
2284 #endif
2285
2286 if (!padapter->hal_func.set_tx_power_level_handler) {
2287 rtw_hal_error_msg("set_tx_power_level_handler");
2288 ret = _FAIL;
2289 }
2290 if (!padapter->hal_func.set_tx_power_index_handler) {
2291 rtw_hal_error_msg("set_tx_power_index_handler");
2292 ret = _FAIL;
2293 }
2294 if (!padapter->hal_func.get_tx_power_index_handler) {
2295 rtw_hal_error_msg("get_tx_power_index_handler");
2296 ret = _FAIL;
2297 }
2298
2299 /*** SReset section ***/
2300 #ifdef DBG_CONFIG_ERROR_DETECT
2301 if (NULL == padapter->hal_func.sreset_init_value) {
2302 rtw_hal_error_msg("sreset_init_value");
2303 ret = _FAIL;
2304 }
2305 if (NULL == padapter->hal_func.sreset_reset_value) {
2306 rtw_hal_error_msg("sreset_reset_value");
2307 ret = _FAIL;
2308 }
2309 if (NULL == padapter->hal_func.silentreset) {
2310 rtw_hal_error_msg("silentreset");
2311 ret = _FAIL;
2312 }
2313 if (NULL == padapter->hal_func.sreset_xmit_status_check) {
2314 rtw_hal_error_msg("sreset_xmit_status_check");
2315 ret = _FAIL;
2316 }
2317 if (NULL == padapter->hal_func.sreset_linked_status_check) {
2318 rtw_hal_error_msg("sreset_linked_status_check");
2319 ret = _FAIL;
2320 }
2321 if (NULL == padapter->hal_func.sreset_get_wifi_status) {
2322 rtw_hal_error_msg("sreset_get_wifi_status");
2323 ret = _FAIL;
2324 }
2325 if (NULL == padapter->hal_func.sreset_inprogress) {
2326 rtw_hal_error_msg("sreset_inprogress");
2327 ret = _FAIL;
2328 }
2329 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
2330
2331 #ifdef RTW_HALMAC
2332 if (NULL == padapter->hal_func.init_mac_register) {
2333 rtw_hal_error_msg("init_mac_register");
2334 ret = _FAIL;
2335 }
2336 if (NULL == padapter->hal_func.init_phy) {
2337 rtw_hal_error_msg("init_phy");
2338 ret = _FAIL;
2339 }
2340 #endif /* RTW_HALMAC */
2341
2342 #ifdef CONFIG_RFKILL_POLL
2343 if (padapter->hal_func.hal_radio_onoff_check == NULL) {
2344 rtw_hal_error_msg("hal_radio_onoff_check");
2345 ret = _FAIL;
2346 }
2347 #endif
2348 #endif
2349 return ret;
2350 }
2351