1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21 #ifndef __HAL_PG_H__ 22 #define __HAL_PG_H__ 23 24 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F 25 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0 26 27 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F 28 #define PPG_THERMAL_OFFSET_MASK 0x1F 29 #define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) 30 #define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) 31 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) 32 33 //==================================================== 34 // EEPROM/Efuse PG Offset for 88EE/88EU/88ES 35 //==================================================== 36 #define EEPROM_TX_PWR_INX_88E 0x10 37 38 #define EEPROM_ChannelPlan_88E 0xB8 39 #define EEPROM_XTAL_88E 0xB9 40 #define EEPROM_THERMAL_METER_88E 0xBA 41 #define EEPROM_IQK_LCK_88E 0xBB 42 43 #define EEPROM_RF_BOARD_OPTION_88E 0xC1 44 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 45 #define EEPROM_RF_BT_SETTING_88E 0xC3 46 #define EEPROM_VERSION_88E 0xC4 47 #define EEPROM_CustomID_88E 0xC5 48 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9 49 #define EEPROM_COUNTRY_CODE_88E 0xCB 50 51 // RTL88EE 52 #define EEPROM_MAC_ADDR_88EE 0xD0 53 #define EEPROM_VID_88EE 0xD6 54 #define EEPROM_DID_88EE 0xD8 55 #define EEPROM_SVID_88EE 0xDA 56 #define EEPROM_SMID_88EE 0xDC 57 58 //RTL88EU 59 #define EEPROM_MAC_ADDR_88EU 0xD7 60 #define EEPROM_VID_88EU 0xD0 61 #define EEPROM_PID_88EU 0xD2 62 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8188EU,8192EU, 8812AU is the same 63 #define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104 64 65 // RTL88ES 66 #define EEPROM_MAC_ADDR_88ES 0x11A 67 //==================================================== 68 // EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES 69 //==================================================== 70 #define GET_PG_KFREE_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) 71 #define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 72 73 #define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6 74 #define PPG_THERMAL_OFFSET_8192E 0x1F5 75 76 // 0x10 ~ 0x63 = TX power area. 77 #define EEPROM_TX_PWR_INX_8192E 0x10 78 79 #define EEPROM_ChannelPlan_8192E 0xB8 80 #define EEPROM_XTAL_8192E 0xB9 81 #define EEPROM_THERMAL_METER_8192E 0xBA 82 #define EEPROM_IQK_LCK_8192E 0xBB 83 #define EEPROM_2G_5G_PA_TYPE_8192E 0xBC 84 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD 85 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF 86 87 #define EEPROM_RF_BOARD_OPTION_8192E 0xC1 88 #define EEPROM_RF_FEATURE_OPTION_8192E 0xC2 89 #define EEPROM_RF_BT_SETTING_8192E 0xC3 90 #define EEPROM_VERSION_8192E 0xC4 91 #define EEPROM_CustomID_8192E 0xC5 92 #define EEPROM_TX_BBSWING_2G_8192E 0xC6 93 #define EEPROM_TX_BBSWING_5G_8192E 0xC7 94 #define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8 95 #define EEPROM_RF_ANTENNA_OPT_8192E 0xC9 96 #define EEPROM_RFE_OPTION_8192E 0xCA 97 #define EEPROM_RFE_OPTION_8188E 0xCA 98 #define EEPROM_COUNTRY_CODE_8192E 0xCB 99 100 // RTL8192EE 101 #define EEPROM_MAC_ADDR_8192EE 0xD0 102 #define EEPROM_VID_8192EE 0xD6 103 #define EEPROM_DID_8192EE 0xD8 104 #define EEPROM_SVID_8192EE 0xDA 105 #define EEPROM_SMID_8192EE 0xDC 106 107 //RTL8192EU 108 #define EEPROM_MAC_ADDR_8192EU 0xD7 109 #define EEPROM_VID_8192EU 0xD0 110 #define EEPROM_PID_8192EU 0xD2 111 #define EEPROM_PA_TYPE_8192EU 0xBC 112 #define EEPROM_LNA_TYPE_2G_8192EU 0xBD 113 #define EEPROM_LNA_TYPE_5G_8192EU 0xBF 114 115 // RTL8192ES 116 #define EEPROM_MAC_ADDR_8192ES 0x11A 117 //==================================================== 118 // EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS 119 //==================================================== 120 // 0x10 ~ 0x63 = TX power area. 121 #define EEPROM_USB_MODE_8812 0x08 122 #define EEPROM_TX_PWR_INX_8812 0x10 123 124 #define EEPROM_ChannelPlan_8812 0xB8 125 #define EEPROM_XTAL_8812 0xB9 126 #define EEPROM_THERMAL_METER_8812 0xBA 127 #define EEPROM_IQK_LCK_8812 0xBB 128 #define EEPROM_2G_5G_PA_TYPE_8812 0xBC 129 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD 130 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF 131 132 #define EEPROM_RF_BOARD_OPTION_8812 0xC1 133 #define EEPROM_RF_FEATURE_OPTION_8812 0xC2 134 #define EEPROM_RF_BT_SETTING_8812 0xC3 135 #define EEPROM_VERSION_8812 0xC4 136 #define EEPROM_CustomID_8812 0xC5 137 #define EEPROM_TX_BBSWING_2G_8812 0xC6 138 #define EEPROM_TX_BBSWING_5G_8812 0xC7 139 #define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8 140 #define EEPROM_RF_ANTENNA_OPT_8812 0xC9 141 #define EEPROM_RFE_OPTION_8812 0xCA 142 #define EEPROM_COUNTRY_CODE_8812 0xCB 143 144 // RTL8812AE 145 #define EEPROM_MAC_ADDR_8812AE 0xD0 146 #define EEPROM_VID_8812AE 0xD6 147 #define EEPROM_DID_8812AE 0xD8 148 #define EEPROM_SVID_8812AE 0xDA 149 #define EEPROM_SMID_8812AE 0xDC 150 151 //RTL8812AU 152 #define EEPROM_MAC_ADDR_8812AU 0xD7 153 #define EEPROM_VID_8812AU 0xD0 154 #define EEPROM_PID_8812AU 0xD2 155 #define EEPROM_PA_TYPE_8812AU 0xBC 156 #define EEPROM_LNA_TYPE_2G_8812AU 0xBD 157 #define EEPROM_LNA_TYPE_5G_8812AU 0xBF 158 159 //RTL8814AU 160 #define EEPROM_MAC_ADDR_8814AU 0xD8 161 #define EEPROM_VID_8814AU 0xD0 162 #define EEPROM_PID_8814AU 0xD2 163 #define EEPROM_PA_TYPE_8814AU 0xBC 164 #define EEPROM_LNA_TYPE_2G_8814AU 0xBD 165 #define EEPROM_LNA_TYPE_5G_8814AU 0xBF 166 167 /* RTL8814AE */ 168 #define EEPROM_MAC_ADDR_8814AE 0xD0 169 #define EEPROM_VID_8814AE 0xD6 170 #define EEPROM_DID_8814AE 0xD8 171 #define EEPROM_SVID_8814AE 0xDA 172 #define EEPROM_SMID_8814AE 0xDC 173 174 //==================================================== 175 // EEPROM/Efuse PG Offset for 8814AU 176 //==================================================== 177 #define GET_PG_KFREE_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) 178 #define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 179 #define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2) 180 181 #define KFREE_GAIN_DATA_LENGTH_8814A 22 182 183 #define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A 0x3EE 184 185 #define PPG_THERMAL_OFFSET_8814A 0x3EF 186 187 #define EEPROM_TX_PWR_INX_8814 0x10 188 #define EEPROM_ChannelPlan_8814 0xB8 189 #define EEPROM_XTAL_8814 0xB9 190 #define EEPROM_THERMAL_METER_8814 0xBA 191 #define EEPROM_IQK_LCK_8814 0xBB 192 193 194 #define EEPROM_PA_TYPE_8814 0xBC 195 #define EEPROM_LNA_TYPE_AB_2G_8814 0xBD 196 #define EEPROM_LNA_TYPE_CD_2G_8814 0xBE 197 #define EEPROM_LNA_TYPE_AB_5G_8814 0xBF 198 #define EEPROM_LNA_TYPE_CD_5G_8814 0xC0 199 #define EEPROM_RF_BOARD_OPTION_8814 0xC1 200 #define EEPROM_RF_BT_SETTING_8814 0xC3 201 #define EEPROM_VERSION_8814 0xC4 202 #define EEPROM_CustomID_8814 0xC5 203 #define EEPROM_TX_BBSWING_2G_8814 0xC6 204 #define EEPROM_TX_BBSWING_5G_8814 0xC7 205 #define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9 206 #define EEPROM_RFE_OPTION_8814 0xCA 207 #define EEPROM_COUNTRY_CODE_8814 0xCB 208 209 /*Extra Info for 8814A Initial Gain Fine Tune suggested by Willis, JIRA: MP123*/ 210 #define EEPROM_IG_OFFSET_4_AB_2G_8814A 0x120 211 #define EEPROM_IG_OFFSET_4_CD_2G_8814A 0x121 212 #define EEPROM_IG_OFFSET_4_AB_5GL_8814A 0x122 213 #define EEPROM_IG_OFFSET_4_CD_5GL_8814A 0x123 214 #define EEPROM_IG_OFFSET_4_AB_5GM_8814A 0x124 215 #define EEPROM_IG_OFFSET_4_CD_5GM_8814A 0x125 216 #define EEPROM_IG_OFFSET_4_AB_5GH_8814A 0x126 217 #define EEPROM_IG_OFFSET_4_CD_5GH_8814A 0x127 218 219 //==================================================== 220 // EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS 221 //==================================================== 222 223 #define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) 224 #define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 225 226 #define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6 227 #define PPG_THERMAL_OFFSET_8821A 0x1F5 228 #define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4 229 #define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3 230 #define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2 231 #define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 232 #define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 233 234 #define EEPROM_TX_PWR_INX_8821 0x10 235 236 #define EEPROM_ChannelPlan_8821 0xB8 237 #define EEPROM_XTAL_8821 0xB9 238 #define EEPROM_THERMAL_METER_8821 0xBA 239 #define EEPROM_IQK_LCK_8821 0xBB 240 241 242 #define EEPROM_RF_BOARD_OPTION_8821 0xC1 243 #define EEPROM_RF_FEATURE_OPTION_8821 0xC2 244 #define EEPROM_RF_BT_SETTING_8821 0xC3 245 #define EEPROM_VERSION_8821 0xC4 246 #define EEPROM_CustomID_8821 0xC5 247 #define EEPROM_RF_ANTENNA_OPT_8821 0xC9 248 249 // RTL8821AE 250 #define EEPROM_MAC_ADDR_8821AE 0xD0 251 #define EEPROM_VID_8821AE 0xD6 252 #define EEPROM_DID_8821AE 0xD8 253 #define EEPROM_SVID_8821AE 0xDA 254 #define EEPROM_SMID_8821AE 0xDC 255 256 //RTL8821AU 257 #define EEPROM_PA_TYPE_8821AU 0xBC 258 #define EEPROM_LNA_TYPE_8821AU 0xBF 259 260 // RTL8821AS 261 #define EEPROM_MAC_ADDR_8821AS 0x11A 262 263 //RTL8821AU 264 #define EEPROM_MAC_ADDR_8821AU 0x107 265 #define EEPROM_VID_8821AU 0x100 266 #define EEPROM_PID_8821AU 0x102 267 268 269 //==================================================== 270 // EEPROM/Efuse PG Offset for 8192 SE/SU 271 //==================================================== 272 #define EEPROM_VID_92SE 0x0A 273 #define EEPROM_DID_92SE 0x0C 274 #define EEPROM_SVID_92SE 0x0E 275 #define EEPROM_SMID_92SE 0x10 276 277 #define EEPROM_MAC_ADDR_92S 0x12 278 279 #define EEPROM_TSSI_A_92SE 0x74 280 #define EEPROM_TSSI_B_92SE 0x75 281 282 #define EEPROM_Version_92SE 0x7C 283 284 285 #define EEPROM_VID_92SU 0x08 286 #define EEPROM_PID_92SU 0x0A 287 288 #define EEPROM_Version_92SU 0x50 289 #define EEPROM_TSSI_A_92SU 0x6b 290 #define EEPROM_TSSI_B_92SU 0x6c 291 292 /* ==================================================== 293 EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS 294 ==================================================== 295 */ 296 297 #define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) 298 #define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 299 300 #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE 301 #define PPG_THERMAL_OFFSET_8188F 0xEF 302 303 /* 0x10 ~ 0x63 = TX power area. */ 304 #define EEPROM_TX_PWR_INX_8188F 0x10 305 306 #define EEPROM_ChannelPlan_8188F 0xB8 307 #define EEPROM_XTAL_8188F 0xB9 308 #define EEPROM_THERMAL_METER_8188F 0xBA 309 #define EEPROM_IQK_LCK_8188F 0xBB 310 #define EEPROM_2G_5G_PA_TYPE_8188F 0xBC 311 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD 312 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF 313 314 #define EEPROM_RF_BOARD_OPTION_8188F 0xC1 315 #define EEPROM_FEATURE_OPTION_8188F 0xC2 316 #define EEPROM_RF_BT_SETTING_8188F 0xC3 317 #define EEPROM_VERSION_8188F 0xC4 318 #define EEPROM_CustomID_8188F 0xC5 319 #define EEPROM_TX_BBSWING_2G_8188F 0xC6 320 #define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8 321 #define EEPROM_RF_ANTENNA_OPT_8188F 0xC9 322 #define EEPROM_RFE_OPTION_8188F 0xCA 323 #define EEPROM_COUNTRY_CODE_8188F 0xCB 324 #define EEPROM_CUSTOMER_ID_8188F 0x7F 325 #define EEPROM_SUBCUSTOMER_ID_8188F 0x59 326 327 /* RTL8188FU */ 328 #define EEPROM_MAC_ADDR_8188FU 0xD7 329 #define EEPROM_VID_8188FU 0xD0 330 #define EEPROM_PID_8188FU 0xD2 331 #define EEPROM_PA_TYPE_8188FU 0xBC 332 #define EEPROM_LNA_TYPE_2G_8188FU 0xBD 333 #define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4 334 335 /* RTL8188FS */ 336 #define EEPROM_MAC_ADDR_8188FS 0x11A 337 #define EEPROM_Voltage_ADDR_8188F 0x8 338 339 //==================================================== 340 // EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS 341 //==================================================== 342 // 0x10 ~ 0x63 = TX power area. 343 #define EEPROM_TX_PWR_INX_8723B 0x10 344 345 #define EEPROM_ChannelPlan_8723B 0xB8 346 #define EEPROM_XTAL_8723B 0xB9 347 #define EEPROM_THERMAL_METER_8723B 0xBA 348 #define EEPROM_IQK_LCK_8723B 0xBB 349 #define EEPROM_2G_5G_PA_TYPE_8723B 0xBC 350 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD 351 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF 352 353 #define EEPROM_RF_BOARD_OPTION_8723B 0xC1 354 #define EEPROM_FEATURE_OPTION_8723B 0xC2 355 #define EEPROM_RF_BT_SETTING_8723B 0xC3 356 #define EEPROM_VERSION_8723B 0xC4 357 #define EEPROM_CustomID_8723B 0xC5 358 #define EEPROM_TX_BBSWING_2G_8723B 0xC6 359 #define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8 360 #define EEPROM_RF_ANTENNA_OPT_8723B 0xC9 361 #define EEPROM_RFE_OPTION_8723B 0xCA 362 #define EEPROM_COUNTRY_CODE_8723B 0xCB 363 364 // RTL8723BE 365 #define EEPROM_MAC_ADDR_8723BE 0xD0 366 #define EEPROM_VID_8723BE 0xD6 367 #define EEPROM_DID_8723BE 0xD8 368 #define EEPROM_SVID_8723BE 0xDA 369 #define EEPROM_SMID_8723BE 0xDC 370 371 //RTL8723BU 372 #define EEPROM_MAC_ADDR_8723BU 0x107 373 #define EEPROM_VID_8723BU 0x100 374 #define EEPROM_PID_8723BU 0x102 375 #define EEPROM_PA_TYPE_8723BU 0xBC 376 #define EEPROM_LNA_TYPE_2G_8723BU 0xBD 377 378 379 //RTL8723BS 380 #define EEPROM_MAC_ADDR_8723BS 0x11A 381 #define EEPROM_Voltage_ADDR_8723B 0x8 382 383 //==================================================== 384 /* EEPROM/Efuse PG Offset for 8703B */ 385 //==================================================== 386 #define GET_PG_KFREE_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) 387 #define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) 388 389 #define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE 390 #define PPG_THERMAL_OFFSET_8703B 0xEF 391 392 #define EEPROM_TX_PWR_INX_8703B 0x10 393 394 #define EEPROM_ChannelPlan_8703B 0xB8 395 #define EEPROM_XTAL_8703B 0xB9 396 #define EEPROM_THERMAL_METER_8703B 0xBA 397 #define EEPROM_IQK_LCK_8703B 0xBB 398 #define EEPROM_2G_5G_PA_TYPE_8703B 0xBC 399 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD 400 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF 401 402 #define EEPROM_RF_BOARD_OPTION_8703B 0xC1 403 #define EEPROM_FEATURE_OPTION_8703B 0xC2 404 #define EEPROM_RF_BT_SETTING_8703B 0xC3 405 #define EEPROM_VERSION_8703B 0xC4 406 #define EEPROM_CustomID_8703B 0xC5 407 #define EEPROM_TX_BBSWING_2G_8703B 0xC6 408 #define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8 409 #define EEPROM_RF_ANTENNA_OPT_8703B 0xC9 410 #define EEPROM_RFE_OPTION_8703B 0xCA 411 #define EEPROM_COUNTRY_CODE_8703B 0xCB 412 413 /* MAC Hidden */ 414 #define PPG_MAC_HIDDEN_START_8703B 0xF0 415 #define PPG_MAC_HIDDEN_END_8703B 0xFF 416 #define EEPROM_HCI_AND_PACKAGE_TYPE_8703B 0xF8 417 #define EEPROM_WL_FUNC_CAP_8703B 0xF9 418 #define EEPROM_BW_AND_ANT_NUM_CAP_8703B 0xFB 419 #define GET_PMH_HCI_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4) 420 #define GET_PMH_PACKAGE_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 4, 4) 421 #define GET_PMH_WL_FUNC_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_WL_FUNC_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4) 422 #define GET_PMH_BW_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 3) 423 #define GET_PMH_ANT_NUM_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 5, 3) 424 425 /* RTL8703BU */ 426 #define EEPROM_MAC_ADDR_8703BU 0x107 427 #define EEPROM_VID_8703BU 0x100 428 #define EEPROM_PID_8703BU 0x102 429 #define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU 0x104 430 #define EEPROM_PA_TYPE_8703BU 0xBC 431 #define EEPROM_LNA_TYPE_2G_8703BU 0xBD 432 433 //RTL8703BS 434 #define EEPROM_MAC_ADDR_8703BS 0x11A 435 #define EEPROM_Voltage_ADDR_8703B 0x8 436 437 //==================================================== 438 // EEPROM/Efuse Value Type 439 //==================================================== 440 #define EETYPE_TX_PWR 0x0 441 //==================================================== 442 // EEPROM/Efuse Default Value 443 //==================================================== 444 #define EEPROM_CID_DEFAULT 0x0 445 #define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek 446 #define EEPROM_CID_TOSHIBA 0x4 447 #define EEPROM_CID_CCX 0x10 448 #define EEPROM_CID_QMI 0x0D 449 #define EEPROM_CID_WHQL 0xFE 450 451 #define EEPROM_CHANNEL_PLAN_FCC 0x0 452 #define EEPROM_CHANNEL_PLAN_IC 0x1 453 #define EEPROM_CHANNEL_PLAN_ETSI 0x2 454 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 455 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 456 #define EEPROM_CHANNEL_PLAN_MKK 0x5 457 #define EEPROM_CHANNEL_PLAN_MKK1 0x6 458 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 459 #define EEPROM_CHANNEL_PLAN_TELEC 0x8 460 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 461 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 462 #define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB 463 #define EEPROM_CHANNEL_PLAN_CHIAN 0XC 464 #define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD 465 #define EEPROM_CHANNEL_PLAN_KOREA 0xE 466 #define EEPROM_CHANNEL_PLAN_TURKEY 0xF 467 #define EEPROM_CHANNEL_PLAN_JAPAN 0x10 468 #define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 469 #define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 470 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 471 #define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 472 473 #define EEPROM_USB_OPTIONAL1 0xE 474 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 475 476 #define RTL_EEPROM_ID 0x8129 477 #define EEPROM_Default_TSSI 0x0 478 #define EEPROM_Default_BoardType 0x02 479 #define EEPROM_Default_ThermalMeter 0x12 480 #define EEPROM_Default_ThermalMeter_92SU 0x7 481 #define EEPROM_Default_ThermalMeter_88E 0x18 482 #define EEPROM_Default_ThermalMeter_8812 0x18 483 #define EEPROM_Default_ThermalMeter_8192E 0x1A 484 #define EEPROM_Default_ThermalMeter_8723B 0x18 485 #define EEPROM_Default_ThermalMeter_8703B 0x18 486 #define EEPROM_Default_ThermalMeter_8188F 0x18 487 #define EEPROM_Default_ThermalMeter_8814A 0x18 488 489 490 #define EEPROM_Default_CrystalCap 0x0 491 #define EEPROM_Default_CrystalCap_8723A 0x20 492 #define EEPROM_Default_CrystalCap_88E 0x20 493 #define EEPROM_Default_CrystalCap_8812 0x20 494 #define EEPROM_Default_CrystalCap_8814 0x20 495 #define EEPROM_Default_CrystalCap_8192E 0x20 496 #define EEPROM_Default_CrystalCap_8723B 0x20 497 #define EEPROM_Default_CrystalCap_8703B 0x20 498 #define EEPROM_Default_CrystalCap_8188F 0x20 499 #define EEPROM_Default_CrystalFreq 0x0 500 #define EEPROM_Default_TxPowerLevel_92C 0x22 501 #define EEPROM_Default_TxPowerLevel_2G 0x2C 502 #define EEPROM_Default_TxPowerLevel_5G 0x22 503 #define EEPROM_Default_TxPowerLevel 0x22 504 #define EEPROM_Default_HT40_2SDiff 0x0 505 #define EEPROM_Default_HT20_Diff 2 506 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 507 #define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 508 #define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 509 #define EEPROM_Default_HT40_PwrMaxOffset 0 510 #define EEPROM_Default_HT20_PwrMaxOffset 0 511 512 #define EEPROM_Default_PID 0x1234 513 #define EEPROM_Default_VID 0x5678 514 #define EEPROM_Default_CustomerID 0xAB 515 #define EEPROM_Default_CustomerID_8188E 0x00 516 #define EEPROM_Default_SubCustomerID 0xCD 517 #define EEPROM_Default_Version 0 518 519 #define EEPROM_Default_externalPA_C9 0x00 520 #define EEPROM_Default_externalPA_CC 0xFF 521 #define EEPROM_Default_internalPA_SP3T_C9 0xAA 522 #define EEPROM_Default_internalPA_SP3T_CC 0xAF 523 #define EEPROM_Default_internalPA_SPDT_C9 0xAA 524 #ifdef CONFIG_PCI_HCI 525 #define EEPROM_Default_internalPA_SPDT_CC 0xA0 526 #else 527 #define EEPROM_Default_internalPA_SPDT_CC 0xFA 528 #endif 529 #define EEPROM_Default_PAType 0 530 #define EEPROM_Default_LNAType 0 531 532 //New EFUSE deafult value 533 #define EEPROM_DEFAULT_24G_INDEX 0x2D 534 #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 535 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 536 537 #define EEPROM_DEFAULT_5G_INDEX 0X2A 538 #define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 539 #define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 540 541 #define EEPROM_DEFAULT_DIFF 0XFE 542 #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F 543 #define EEPROM_DEFAULT_BOARD_OPTION 0x00 544 #define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF 545 #define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF 546 #define EEPROM_DEFAULT_RFE_OPTION 0x04 547 #define EEPROM_DEFAULT_FEATURE_OPTION 0x00 548 #define EEPROM_DEFAULT_BT_OPTION 0x10 549 550 551 #define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 552 553 // PCIe related 554 #define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74 555 #define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75 556 557 558 // 559 // For VHT series TX power by rate table. 560 // VHT TX power by rate off setArray = 561 // Band:-2G&5G = 0 / 1 562 // RF: at most 4*4 = ABCD=0/1/2/3 563 // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 564 // 565 #define TX_PWR_BY_RATE_NUM_BAND 2 566 #define TX_PWR_BY_RATE_NUM_RF 4 567 #define TX_PWR_BY_RATE_NUM_RATE 84 568 569 #define TXPWR_LMT_MAX_RF 4 570 571 //---------------------------------------------------------------------------- 572 // EEPROM/EFUSE data structure definition. 573 //---------------------------------------------------------------------------- 574 575 //For 88E new structure 576 577 /* 578 2.4G: 579 { 580 {1,2}, 581 {3,4,5}, 582 {6,7,8}, 583 {9,10,11}, 584 {12,13}, 585 {14} 586 } 587 588 5G: 589 { 590 {36,38,40}, 591 {44,46,48}, 592 {52,54,56}, 593 {60,62,64}, 594 {100,102,104}, 595 {108,110,112}, 596 {116,118,120}, 597 {124,126,128}, 598 {132,134,136}, 599 {140,142,144}, 600 {149,151,153}, 601 {157,159,161}, 602 {173,175,177}, 603 } 604 */ 605 #define MAX_RF_PATH 4 606 #define RF_PATH_MAX MAX_RF_PATH 607 #define MAX_CHNL_GROUP_24G 6 608 #define MAX_CHNL_GROUP_5G 14 609 610 //It must always set to 4, otherwise read efuse table secquence will be wrong. 611 #define MAX_TX_COUNT 4 612 613 typedef struct _TxPowerInfo24G{ 614 u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 615 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 616 //If only one tx, only BW20 and OFDM are used. 617 s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 618 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 619 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 620 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 621 }TxPowerInfo24G, *PTxPowerInfo24G; 622 623 typedef struct _TxPowerInfo5G{ 624 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 625 //If only one tx, only BW20, OFDM, BW80 and BW160 are used. 626 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 627 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 628 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 629 s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 630 s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 631 }TxPowerInfo5G, *PTxPowerInfo5G; 632 633 634 typedef enum _BT_Ant_NUM{ 635 Ant_x2 = 0, 636 Ant_x1 = 1 637 } BT_Ant_NUM, *PBT_Ant_NUM; 638 639 typedef enum _BT_CoType{ 640 BT_2WIRE = 0, 641 BT_ISSC_3WIRE = 1, 642 BT_ACCEL = 2, 643 BT_CSR_BC4 = 3, 644 BT_CSR_BC8 = 4, 645 BT_RTL8756 = 5, 646 BT_RTL8723A = 6, 647 BT_RTL8821 = 7, 648 BT_RTL8723B = 8, 649 BT_RTL8192E = 9, 650 BT_RTL8814A = 10, 651 BT_RTL8812A = 11, 652 BT_RTL8703B = 12 653 } BT_CoType, *PBT_CoType; 654 655 typedef enum _BT_RadioShared{ 656 BT_Radio_Shared = 0, 657 BT_Radio_Individual = 1, 658 } BT_RadioShared, *PBT_RadioShared; 659 660 661 #endif 662