1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __HAL_DATA_H__ 21 #define __HAL_DATA_H__ 22 23 #if 1//def CONFIG_SINGLE_IMG 24 25 #include "../hal/phydm/phydm_precomp.h" 26 #ifdef CONFIG_BT_COEXIST 27 #include <hal_btcoex.h> 28 #endif 29 30 #ifdef CONFIG_SDIO_HCI 31 #include <hal_sdio.h> 32 #endif 33 #ifdef CONFIG_GSPI_HCI 34 #include <hal_gspi.h> 35 #endif 36 // 37 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 38 // 39 typedef enum _RT_MULTI_FUNC{ 40 RT_MULTI_FUNC_NONE = 0x00, 41 RT_MULTI_FUNC_WIFI = 0x01, 42 RT_MULTI_FUNC_BT = 0x02, 43 RT_MULTI_FUNC_GPS = 0x04, 44 }RT_MULTI_FUNC,*PRT_MULTI_FUNC; 45 // 46 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 47 // 48 typedef enum _RT_POLARITY_CTL { 49 RT_POLARITY_LOW_ACT = 0, 50 RT_POLARITY_HIGH_ACT = 1, 51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 52 53 // For RTL8723 regulator mode. by tynli. 2011.01.14. 54 typedef enum _RT_REGULATOR_MODE { 55 RT_SWITCHING_REGULATOR = 0, 56 RT_LDO_REGULATOR = 1, 57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 58 59 // 60 // Interface type. 61 // 62 typedef enum _INTERFACE_SELECT_PCIE{ 63 INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard 64 INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard 65 INTF_SEL2_PCIe = 2, // PCIe Card 66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 67 68 69 typedef enum _INTERFACE_SELECT_USB{ 70 INTF_SEL0_USB = 0, // USB 71 INTF_SEL1_USB_High_Power = 1, // USB with high power PA 72 INTF_SEL2_MINICARD = 2, // Minicard 73 INTF_SEL3_USB_Solo = 3, // USB solo-Slim module 74 INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module 75 INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card 76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 77 78 typedef enum _RT_AMPDU_BRUST_MODE{ 79 RT_AMPDU_BRUST_NONE = 0, 80 RT_AMPDU_BRUST_92D = 1, 81 RT_AMPDU_BRUST_88E = 2, 82 RT_AMPDU_BRUST_8812_4 = 3, 83 RT_AMPDU_BRUST_8812_8 = 4, 84 RT_AMPDU_BRUST_8812_12 = 5, 85 RT_AMPDU_BRUST_8812_15 = 6, 86 RT_AMPDU_BRUST_8723B = 7, 87 }RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE; 88 89 /* 90 #define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number 91 */ 92 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */ 93 #define MAX_PG_GROUP 13 94 95 // Tx Power Limit Table Size 96 #define MAX_REGULATION_NUM 4 97 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 98 #define MAX_2_4G_BANDWIDTH_NUM 2 99 #define MAX_RATE_SECTION_NUM 10 100 #define MAX_5G_BANDWIDTH_NUM 4 101 102 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4 103 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4 104 105 106 //###### duplicate code,will move to ODM ######### 107 //#define IQK_MAC_REG_NUM 4 108 //#define IQK_ADDA_REG_NUM 16 109 110 //#define IQK_BB_REG_NUM 10 111 #define IQK_BB_REG_NUM_92C 9 112 #define IQK_BB_REG_NUM_92D 10 113 #define IQK_BB_REG_NUM_test 6 114 115 #define IQK_Matrix_Settings_NUM_92D 1+24+21 116 117 //#define HP_THERMAL_NUM 8 118 //###### duplicate code,will move to ODM ######### 119 120 #ifdef CONFIG_USB_RX_AGGREGATION 121 typedef enum _USB_RX_AGG_MODE{ 122 USB_RX_AGG_DISABLE, 123 USB_RX_AGG_DMA, 124 USB_RX_AGG_USB, 125 USB_RX_AGG_MIX 126 }USB_RX_AGG_MODE; 127 128 //#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer 129 130 #endif 131 132 /* For store initial value of BB register */ 133 typedef struct _BB_INIT_REGISTER { 134 u16 offset; 135 u32 value; 136 137 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 138 139 #define PAGE_SIZE_128 128 140 #define PAGE_SIZE_256 256 141 #define PAGE_SIZE_512 512 142 143 #define HCI_SUS_ENTER 0 144 #define HCI_SUS_LEAVING 1 145 #define HCI_SUS_LEAVE 2 146 #define HCI_SUS_ENTERING 3 147 #define HCI_SUS_ERR 4 148 149 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 150 typedef enum _ACS_OP { 151 ACS_INIT, /*ACS - Variable init*/ 152 ACS_RESET, /*ACS - NHM Counter reset*/ 153 ACS_SELECT, /*ACS - NHM Counter Statistics */ 154 } ACS_OP; 155 156 typedef enum _ACS_STATE { 157 ACS_DISABLE, 158 ACS_ENABLE, 159 } ACS_STATE; 160 161 struct auto_chan_sel { 162 ATOMIC_T state; 163 u8 ch; /* previous channel*/ 164 }; 165 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 166 167 #define EFUSE_FILE_UNUSED 0 168 #define EFUSE_FILE_FAILED 1 169 #define EFUSE_FILE_LOADED 2 170 171 #define MACADDR_FILE_UNUSED 0 172 #define MACADDR_FILE_FAILED 1 173 #define MACADDR_FILE_LOADED 2 174 175 #define KFREE_FLAG_ON BIT0 176 #define KFREE_FLAG_THERMAL_K_ON BIT1 177 178 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 179 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 180 181 struct kfree_data_t { 182 u8 flag; 183 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 184 185 #ifdef CONFIG_IEEE80211_BAND_5GHZ 186 s8 pa_bias_5g[RF_PATH_MAX]; 187 s8 pad_bias_5g[RF_PATH_MAX]; 188 #endif 189 s8 thermal; 190 }; 191 192 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 193 194 struct hal_spec_t { 195 u8 macid_num; 196 197 u8 sec_cam_ent_num; 198 u8 sec_cap; 199 200 u8 nss_num; 201 u8 band_cap; /* value of BAND_CAP_XXX */ 202 u8 bw_cap; /* value of BW_CAP_XXX */ 203 u8 proto_cap; /* value of PROTO_CAP_XXX */ 204 205 u8 wl_func; /* value of WL_FUNC_XXX */ 206 }; 207 208 struct hal_iqk_reg_backup { 209 u8 central_chnl; 210 u8 bw_mode; 211 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 212 }; 213 214 typedef struct hal_com_data 215 { 216 HAL_VERSION VersionID; 217 RT_MULTI_FUNC MultiFunc; // For multi-function consideration. 218 RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. 219 RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO 220 u8 hw_init_completed; 221 /****** FW related ******/ 222 u16 FirmwareVersion; 223 u16 FirmwareVersionRev; 224 u16 FirmwareSubVersion; 225 u16 FirmwareSignature; 226 u8 RegFWOffload; 227 u8 fw_ractrl; 228 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ 229 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 230 231 /****** current WIFI_PHY values ******/ 232 WIRELESS_MODE CurrentWirelessMode; 233 CHANNEL_WIDTH CurrentChannelBW; 234 BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ 235 BAND_TYPE BandSet; 236 u8 CurrentChannel; 237 u8 CurrentCenterFrequencyIndex1; 238 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 239 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 240 BOOLEAN bSwChnlAndSetBWInProgress; 241 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 242 u16 BasicRateSet; 243 u32 ReceiveConfig; 244 BOOLEAN bSwChnl; 245 BOOLEAN bSetChnlBW; 246 BOOLEAN bSWToBW40M; 247 BOOLEAN bSWToBW80M; 248 BOOLEAN bChnlBWInitialized; 249 u32 BackUp_BB_REG_4_2nd_CCA[3]; 250 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 251 struct auto_chan_sel acs; 252 #endif 253 /****** rf_ctrl *****/ 254 u8 rf_chip; 255 u8 rf_type; 256 u8 PackageType; 257 u8 NumTotalRFPath; 258 259 /****** Debug ******/ 260 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 261 u8 u1ForcedIgiLb; /* forced IGI lower bound */ 262 u8 bDumpRxPkt; 263 u8 bDumpTxPkt; 264 u8 bDisableTXPowerTraining; 265 266 267 /****** EEPROM setting.******/ 268 u8 bautoload_fail_flag; 269 u8 efuse_file_status; 270 u8 macaddr_file_status; 271 u8 EepromOrEfuse; 272 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 273 u8 InterfaceSel; /* board type kept in eFuse */ 274 u16 CustomerID; 275 276 u16 EEPROMVID; 277 u16 EEPROMSVID; 278 #ifdef CONFIG_USB_HCI 279 u16 EEPROMPID; 280 u16 EEPROMSDID; 281 #endif 282 #ifdef CONFIG_PCI_HCI 283 u16 EEPROMDID; 284 u16 EEPROMSMID; 285 #endif 286 287 u8 EEPROMCustomerID; 288 u8 EEPROMSubCustomerID; 289 u8 EEPROMVersion; 290 u8 EEPROMRegulatory; 291 u8 EEPROMThermalMeter; 292 u8 EEPROMBluetoothCoexist; 293 u8 EEPROMBluetoothType; 294 u8 EEPROMBluetoothAntNum; 295 u8 EEPROMBluetoothAntIsolation; 296 u8 EEPROMBluetoothRadioShared; 297 u8 bTXPowerDataReadFromEEPORM; 298 u8 EEPROMMACAddr[ETH_ALEN]; 299 300 #ifdef CONFIG_RF_GAIN_OFFSET 301 u8 EEPROMRFGainOffset; 302 u8 EEPROMRFGainVal; 303 struct kfree_data_t kfree_data; 304 #endif /*CONFIG_RF_GAIN_OFFSET*/ 305 306 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) 307 u8 adjuseVoltageVal; 308 #endif 309 u8 EfuseUsedPercentage; 310 u16 EfuseUsedBytes; 311 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 312 EFUSE_HAL EfuseHal; 313 314 /*---------------------------------------------------------------------------------*/ 315 //3 [2.4G] 316 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 317 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 318 //If only one tx, only BW20 and OFDM are used. 319 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 320 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 321 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 322 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 323 //3 [5G] 324 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 325 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 326 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 327 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 328 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 329 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 330 331 u8 Regulation2_4G; 332 u8 Regulation5G; 333 334 u8 TxPwrInPercentage; 335 336 /******************************** 337 * TX power by rate table at most 4RF path. 338 * The register is 339 * 340 * VHT TX power by rate off setArray = 341 * Band:-2G&5G = 0 / 1 342 * RF: at most 4*4 = ABCD=0/1/2/3 343 * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 344 **********************************/ 345 u8 TxPwrByRateTable; 346 u8 TxPwrByRateBand; 347 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 348 [TX_PWR_BY_RATE_NUM_RF] 349 [TX_PWR_BY_RATE_NUM_RF] 350 [TX_PWR_BY_RATE_NUM_RATE]; 351 //---------------------------------------------------------------------------------// 352 353 /* 354 //2 Power Limit Table 355 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 356 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr 357 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr 358 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff 359 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff 360 */ 361 362 u8 tx_pwr_lmt_5g_20_40_ref; 363 364 // Power Limit Table for 2.4G 365 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] 366 [MAX_2_4G_BANDWIDTH_NUM] 367 [MAX_RATE_SECTION_NUM] 368 [CENTER_CH_2G_NUM] 369 [MAX_RF_PATH]; 370 371 // Power Limit Table for 5G 372 s8 TxPwrLimit_5G[MAX_REGULATION_NUM] 373 [MAX_5G_BANDWIDTH_NUM] 374 [MAX_RATE_SECTION_NUM] 375 [CENTER_CH_5G_ALL_NUM] 376 [MAX_RF_PATH]; 377 378 379 // Store the original power by rate value of the base of each rate section of rf path A & B 380 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 381 [TX_PWR_BY_RATE_NUM_RF] 382 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 383 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 384 [TX_PWR_BY_RATE_NUM_RF] 385 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 386 387 u8 txpwr_by_rate_loaded:1; 388 u8 txpwr_by_rate_from_file:1; 389 u8 txpwr_limit_loaded:1; 390 u8 txpwr_limit_from_file:1; 391 392 // For power group 393 /* 394 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 395 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 396 */ 397 u8 PGMaxGroup; 398 399 // The current Tx Power Level 400 u8 CurrentCckTxPwrIdx; 401 u8 CurrentOfdm24GTxPwrIdx; 402 u8 CurrentBW2024GTxPwrIdx; 403 u8 CurrentBW4024GTxPwrIdx; 404 405 // Read/write are allow for following hardware information variables 406 u8 pwrGroupCnt; 407 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 408 u32 CCKTxPowerLevelOriginalOffset; 409 410 u8 CrystalCap; 411 412 u8 PAType_2G; 413 u8 PAType_5G; 414 u8 LNAType_2G; 415 u8 LNAType_5G; 416 u8 ExternalPA_2G; 417 u8 ExternalLNA_2G; 418 u8 ExternalPA_5G; 419 u8 ExternalLNA_5G; 420 u16 TypeGLNA; 421 u16 TypeGPA; 422 u16 TypeALNA; 423 u16 TypeAPA; 424 u16 RFEType; 425 426 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 427 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 428 429 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D 430 431 u32 RfRegChnlVal[MAX_RF_PATH]; 432 433 //RDG enable 434 BOOLEAN bRDGEnable; 435 436 u8 RegTxPause; 437 // Beacon function related global variable. 438 u8 RegBcnCtrlVal; 439 u8 RegFwHwTxQCtrl; 440 u8 RegReg542; 441 u8 RegCR_1; 442 u8 Reg837; 443 u16 RegRRSR; 444 445 /****** antenna diversity ******/ 446 u8 AntDivCfg; 447 u8 AntDetection; 448 u8 TRxAntDivType; 449 u8 ant_path; //for 8723B s0/s1 selection 450 u32 AntennaTxPath; /* Antenna path Tx */ 451 u32 AntennaRxPath; /* Antenna path Rx */ 452 u8 sw_antdiv_bl_state; 453 454 /******** PHY DM & DM Section **********/ 455 u8 DM_Type; 456 _lock IQKSpinLock; 457 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 458 /* Upper and Lower Signal threshold for Rate Adaptive*/ 459 int EntryMinUndecoratedSmoothedPWDB; 460 int EntryMaxUndecoratedSmoothedPWDB; 461 int MinUndecoratedPWDBForDM; 462 DM_ODM_T odmpriv; 463 u8 bIQKInitialized; 464 u8 bNeedIQK; 465 /******** PHY DM & DM Section **********/ 466 467 468 469 // 2010/08/09 MH Add CU power down mode. 470 BOOLEAN pwrdown; 471 472 // Add for dual MAC 0--Mac0 1--Mac1 473 u32 interfaceIndex; 474 475 #ifdef CONFIG_P2P 476 u8 p2p_ps_offload; 477 #endif 478 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 479 u8 bMacPwrCtrlOn; 480 u8 hci_sus_state; 481 482 u8 RegIQKFWOffload; 483 struct submit_ctx iqk_sctx; 484 485 RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully 486 487 u8 OutEpQueueSel; 488 u8 OutEpNumber; 489 490 #if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 491 // 492 // For SDIO Interface HAL related 493 // 494 495 // 496 // SDIO ISR Related 497 // 498 // u32 IntrMask[1]; 499 // u32 IntrMaskToSet[1]; 500 // LOG_INTERRUPT InterruptLog; 501 u32 sdio_himr; 502 u32 sdio_hisr; 503 504 // 505 // SDIO Tx FIFO related. 506 // 507 // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg 508 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 509 _lock SdioTxFIFOFreePageLock; 510 u8 SdioTxOQTMaxFreeSpace; 511 u8 SdioTxOQTFreeSpace; 512 513 // 514 // SDIO Rx FIFO related. 515 // 516 u8 SdioRxFIFOCnt; 517 u16 SdioRxFIFOSize; 518 519 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue 520 #endif //CONFIG_SDIO_HCI 521 522 #ifdef CONFIG_USB_HCI 523 524 // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. 525 BOOLEAN UsbRxHighSpeedMode; 526 BOOLEAN UsbTxVeryHighSpeedMode; 527 u32 UsbBulkOutSize; 528 BOOLEAN bSupportUSB3; 529 530 // Interrupt relatd register information. 531 u32 IntArray[3];//HISR0,HISR1,HSISR 532 u32 IntrMask[3]; 533 u8 C2hArray[16]; 534 #ifdef CONFIG_USB_TX_AGGREGATION 535 u8 UsbTxAggMode; 536 u8 UsbTxAggDescNum; 537 #endif // CONFIG_USB_TX_AGGREGATION 538 539 #ifdef CONFIG_USB_RX_AGGREGATION 540 u16 HwRxPageSize; // Hardware setting 541 u32 MaxUsbRxAggBlock; 542 543 USB_RX_AGG_MODE UsbRxAggMode; 544 u8 UsbRxAggBlockCount; /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */ 545 u8 UsbRxAggBlockTimeout; 546 u8 UsbRxAggPageCount; /* FOR DMA Mode, 8192C DMA page count*/ 547 u8 UsbRxAggPageTimeout; 548 549 u8 RegAcUsbDmaSize; 550 u8 RegAcUsbDmaTime; 551 #endif//CONFIG_USB_RX_AGGREGATION 552 #endif //CONFIG_USB_HCI 553 554 555 #ifdef CONFIG_PCI_HCI 556 // 557 // EEPROM setting. 558 // 559 u32 TransmitConfig; 560 u32 IntrMaskToSet[2]; 561 u32 IntArray[2]; 562 u32 IntrMask[2]; 563 u32 SysIntArray[1]; 564 u32 SysIntrMask[1]; 565 u32 IntrMaskReg[2]; 566 u32 IntrMaskDefault[2]; 567 568 BOOLEAN bL1OffSupport; 569 BOOLEAN bSupportBackDoor; 570 571 u8 bDefaultAntenna; 572 573 u8 bInterruptMigration; 574 u8 bDisableTxInt; 575 576 u16 RxTag; 577 #endif //CONFIG_PCI_HCI 578 579 580 #ifdef DBG_CONFIG_ERROR_DETECT 581 struct sreset_priv srestpriv; 582 #endif //#ifdef DBG_CONFIG_ERROR_DETECT 583 584 #ifdef CONFIG_BT_COEXIST 585 // For bluetooth co-existance 586 BT_COEXIST bt_coexist; 587 #endif // CONFIG_BT_COEXIST 588 589 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F) 590 #ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI 591 // Interrupt relatd register information. 592 u32 SysIntrStatus; 593 u32 SysIntrMask; 594 #endif 595 #endif /*endif CONFIG_RTL8723B */ 596 597 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 598 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 599 char *mac_reg; 600 u32 mac_reg_len; 601 char *bb_phy_reg; 602 u32 bb_phy_reg_len; 603 char *bb_agc_tab; 604 u32 bb_agc_tab_len; 605 char *bb_phy_reg_pg; 606 u32 bb_phy_reg_pg_len; 607 char *bb_phy_reg_mp; 608 u32 bb_phy_reg_mp_len; 609 char *rf_radio_a; 610 u32 rf_radio_a_len; 611 char *rf_radio_b; 612 u32 rf_radio_b_len; 613 char *rf_tx_pwr_track; 614 u32 rf_tx_pwr_track_len; 615 char *rf_tx_pwr_lmt; 616 u32 rf_tx_pwr_lmt_len; 617 #endif 618 619 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 620 s16 noise[ODM_MAX_CHANNEL_NUM]; 621 #endif 622 623 struct hal_spec_t hal_spec; 624 625 u8 RfKFreeEnable; 626 u8 RfKFree_ch_group; 627 BOOLEAN bCCKinCH14; 628 BB_INIT_REGISTER RegForRecover[5]; 629 630 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 631 BOOLEAN bCorrectBCN; 632 #endif 633 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 634 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 635 636 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 637 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 638 639 640 641 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 642 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) 643 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 644 645 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath ) 646 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 647 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) 648 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 649 650 #define SUPPORT_HW_RADIO_DETECT(Adapter) ( RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\ 651 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\ 652 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 653 654 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 655 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 656 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 657 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 658 #endif 659 660 #ifdef CONFIG_AUTO_CHNL_SEL_NHM 661 #define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) 662 #define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) 663 #define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) 664 #define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) 665 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ 666 667 #endif //__HAL_DATA_H__ 668 669