1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 /*++
21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
22
23 Module Name:
24 HalPwrSeqCmd.c
25
26 Abstract:
27 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
28
29 Major Change History:
30 When Who What
31 ---------- --------------- -------------------------------
32 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
33 2011-07-07 Roger Create.
34
35 --*/
36 #include <HalPwrSeqCmd.h>
37
38
39 //
40 // Description:
41 // This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
42 //
43 // Assumption:
44 // We should follow specific format which was released from HW SD.
45 //
46 // 2011.07.07, added by Roger.
47 //
HalPwrSeqCmdParsing(PADAPTER padapter,u8 CutVersion,u8 FabVersion,u8 InterfaceType,WLAN_PWR_CFG PwrSeqCmd[])48 u8 HalPwrSeqCmdParsing(
49 PADAPTER padapter,
50 u8 CutVersion,
51 u8 FabVersion,
52 u8 InterfaceType,
53 WLAN_PWR_CFG PwrSeqCmd[])
54 {
55 WLAN_PWR_CFG PwrCfgCmd = {0};
56 u8 bPollingBit = _FALSE;
57 u32 AryIdx = 0;
58 u8 value = 0;
59 u32 offset = 0;
60 u32 pollingCount = 0; // polling autoload done.
61 u32 maxPollingCnt = 5000;
62
63 do {
64 PwrCfgCmd = PwrSeqCmd[AryIdx];
65
66 RT_TRACE(_module_hal_init_c_ , _drv_info_,
67 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
68 GET_PWR_CFG_OFFSET(PwrCfgCmd),
69 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
70 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
71 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
72 GET_PWR_CFG_BASE(PwrCfgCmd),
73 GET_PWR_CFG_CMD(PwrCfgCmd),
74 GET_PWR_CFG_MASK(PwrCfgCmd),
75 GET_PWR_CFG_VALUE(PwrCfgCmd)));
76
77 //2 Only Handle the command whose FAB, CUT, and Interface are matched
78 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
79 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
80 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
81 {
82 switch (GET_PWR_CFG_CMD(PwrCfgCmd))
83 {
84 case PWR_CMD_READ:
85 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
86 break;
87
88 case PWR_CMD_WRITE:
89 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
90 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
91
92 #ifdef CONFIG_SDIO_HCI
93 //
94 // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
95 // 2011.07.07.
96 //
97 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
98 {
99 // Read Back SDIO Local value
100 value = SdioLocalCmd52Read1Byte(padapter, offset);
101
102 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
103 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
104
105 // Write Back SDIO Local value
106 SdioLocalCmd52Write1Byte(padapter, offset, value);
107 }
108 else
109 #endif
110 {
111 #ifdef CONFIG_GSPI_HCI
112 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
113 offset = SPI_LOCAL_OFFSET | offset;
114 #endif
115 // Read the value from system register
116 value = rtw_read8(padapter, offset);
117
118 value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
119 value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
120
121 // Write the value back to sytem register
122 rtw_write8(padapter, offset, value);
123 }
124 break;
125
126 case PWR_CMD_POLLING:
127 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
128
129 bPollingBit = _FALSE;
130 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
131 #ifdef CONFIG_GSPI_HCI
132 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
133 offset = SPI_LOCAL_OFFSET | offset;
134 #endif
135 do {
136 #ifdef CONFIG_SDIO_HCI
137 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
138 value = SdioLocalCmd52Read1Byte(padapter, offset);
139 else
140 #endif
141 value = rtw_read8(padapter, offset);
142
143 value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
144 if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
145 bPollingBit = _TRUE;
146 else
147 rtw_udelay_os(10);
148
149 if (pollingCount++ > maxPollingCnt) {
150 DBG_871X_LEVEL(_drv_err_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
151 return _FALSE;
152 }
153 } while (!bPollingBit);
154
155 break;
156
157 case PWR_CMD_DELAY:
158 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
159 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
160 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
161 else
162 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
163 break;
164
165 case PWR_CMD_END:
166 // When this command is parsed, end the process
167 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
168 return _TRUE;
169 break;
170
171 default:
172 RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
173 break;
174 }
175 }
176
177 AryIdx++;//Add Array Index
178 }while(1);
179
180 return _TRUE;
181 }
182
183
184