1 /****************************************************************************** 2 * 3 * Copyright(c) 2013 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8821A_SPEC_H__ 16 #define __RTL8821A_SPEC_H__ 17 18 #include <drv_conf.h> 19 /* This file should based on "hal_com_reg.h" */ 20 #include <hal_com_reg.h> 21 /* Because 8812a and 8821a is the same serial, 22 * most of 8821a register definitions are the same as 8812a. */ 23 #include <rtl8812a_spec.h> 24 25 26 /* ************************************************************ 27 * 8821A Regsiter offset definition 28 * ************************************************************ */ 29 30 /* ************************************************************ 31 * MAC register 32 * ************************************************************ */ 33 34 /* ----------------------------------------------------- 35 * 0x0000h ~ 0x00FFh System Configuration 36 * ----------------------------------------------------- */ 37 38 /* ----------------------------------------------------- 39 * 0x0100h ~ 0x01FFh MACTOP General Configuration 40 * ----------------------------------------------------- */ 41 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 42 43 /* ----------------------------------------------------- 44 * 0x0200h ~ 0x027Fh TXDMA Configuration 45 * ----------------------------------------------------- */ 46 47 /* ----------------------------------------------------- 48 * 0x0280h ~ 0x02FFh RXDMA Configuration 49 * ----------------------------------------------------- */ 50 51 /* ----------------------------------------------------- 52 * 0x0300h ~ 0x03FFh PCIe 53 * ----------------------------------------------------- */ 54 55 /* ----------------------------------------------------- 56 * 0x0400h ~ 0x047Fh Protocol Configuration 57 * ----------------------------------------------------- */ 58 59 /* ----------------------------------------------------- 60 * 0x0500h ~ 0x05FFh EDCA Configuration 61 * ----------------------------------------------------- */ 62 63 /* ----------------------------------------------------- 64 * 0x0600h ~ 0x07FFh WMAC Configuration 65 * ----------------------------------------------------- */ 66 67 68 /* ************************************************************ 69 * SDIO Bus Specification 70 * ************************************************************ */ 71 72 /* ----------------------------------------------------- 73 * SDIO CMD Address Mapping 74 * ----------------------------------------------------- */ 75 76 /* ----------------------------------------------------- 77 * I/O bus domain (Host) 78 * ----------------------------------------------------- */ 79 80 /* ----------------------------------------------------- 81 * SDIO register 82 * ----------------------------------------------------- */ 83 #define SDIO_REG_FREE_TXPG2 0x024 84 #define SDIO_REG_HCPWM1_8821A 0x025 85 86 /* ************************************************************ 87 * Regsiter Bit and Content definition 88 * ************************************************************ */ 89 90 #endif /* __RTL8821A_SPEC_H__ */ 91