1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8188F_SPEC_H__ 16 #define __RTL8188F_SPEC_H__ 17 18 #include <drv_conf.h> 19 20 21 #define HAL_NAV_UPPER_UNIT_8188F 128 /* micro-second */ 22 23 /* ----------------------------------------------------- 24 * 25 * 0x0000h ~ 0x00FFh System Configuration 26 * 27 * ----------------------------------------------------- */ 28 #define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */ 29 #define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038 30 #define REG_HSISR_8188F 0x005c 31 #define REG_PAD_CTRL1_8188F 0x0064 32 #define REG_AFE_CTRL_4_8188F 0x0078 33 #define REG_HMEBOX_DBG_0_8188F 0x0088 34 #define REG_HMEBOX_DBG_1_8188F 0x008A 35 #define REG_HMEBOX_DBG_2_8188F 0x008C 36 #define REG_HMEBOX_DBG_3_8188F 0x008E 37 #define REG_HIMR0_8188F 0x00B0 38 #define REG_HISR0_8188F 0x00B4 39 #define REG_HIMR1_8188F 0x00B8 40 #define REG_HISR1_8188F 0x00BC 41 #define REG_PMC_DBG_CTRL2_8188F 0x00CC 42 43 /* ----------------------------------------------------- 44 * 45 * 0x0100h ~ 0x01FFh MACTOP General Configuration 46 * 47 * ----------------------------------------------------- */ 48 #define REG_C2HEVT_CMD_ID_8188F 0x01A0 49 #define REG_C2HEVT_CMD_LEN_8188F 0x01AE 50 #define REG_WOWLAN_WAKE_REASON 0x01C7 51 #define REG_WOWLAN_GTK_DBG1 0x630 52 #define REG_WOWLAN_GTK_DBG2 0x634 53 54 #define REG_HMEBOX_EXT0_8188F 0x01F0 55 #define REG_HMEBOX_EXT1_8188F 0x01F4 56 #define REG_HMEBOX_EXT2_8188F 0x01F8 57 #define REG_HMEBOX_EXT3_8188F 0x01FC 58 59 /* ----------------------------------------------------- 60 * 61 * 0x0200h ~ 0x027Fh TXDMA Configuration 62 * 63 * ----------------------------------------------------- */ 64 65 /* ----------------------------------------------------- 66 * 67 * 0x0280h ~ 0x02FFh RXDMA Configuration 68 * 69 * ----------------------------------------------------- */ 70 #define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */ 71 #define REG_RXDMA_MODE_CTRL_8188F 0x0290 72 73 /* ----------------------------------------------------- 74 * 75 * 0x0300h ~ 0x03FFh PCIe 76 * 77 * ----------------------------------------------------- */ 78 #define REG_PCIE_CTRL_REG_8188F 0x0300 79 #define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */ 80 #define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */ 81 #define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */ 82 #define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */ 83 #define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */ 84 #define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */ 85 #define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */ 86 #define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */ 87 #define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */ 88 #define REG_DBI_WDATA_8188F 0x0348 /* DBI Write Data */ 89 #define REG_DBI_RDATA_8188F 0x034C /* DBI Read Data */ 90 #define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */ 91 #define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */ 92 #define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */ 93 #define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */ 94 #define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */ 95 #define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */ 96 #define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */ 97 #define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */ 98 #define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */ 99 100 /* ----------------------------------------------------- 101 * 102 * 0x0400h ~ 0x047Fh Protocol Configuration 103 * 104 * ----------------------------------------------------- */ 105 #define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 106 #define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 107 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D 108 #ifdef CONFIG_WOWLAN 109 #define REG_TXPKTBUF_IV_LOW 0x0484 110 #define REG_TXPKTBUF_IV_HIGH 0x0488 111 #endif 112 #define REG_AMPDU_BURST_MODE_8188F 0x04BC 113 114 /* ----------------------------------------------------- 115 * 116 * 0x0500h ~ 0x05FFh EDCA Configuration 117 * 118 * ----------------------------------------------------- */ 119 #define REG_SECONDARY_CCA_CTRL_8188F 0x0577 120 121 /* ----------------------------------------------------- 122 * 123 * 0x0600h ~ 0x07FFh WMAC Configuration 124 * 125 * ----------------------------------------------------- */ 126 127 128 /* ************************************************************ 129 * SDIO Bus Specification 130 * ************************************************************ */ 131 132 /* ----------------------------------------------------- 133 * SDIO CMD Address Mapping 134 * ----------------------------------------------------- */ 135 136 /* ----------------------------------------------------- 137 * I/O bus domain (Host) 138 * ----------------------------------------------------- */ 139 140 /* ----------------------------------------------------- 141 * SDIO register 142 * ----------------------------------------------------- */ 143 #define SDIO_REG_HIQ_FREEPG_8188F 0x0020 144 #define SDIO_REG_MID_FREEPG_8188F 0x0022 145 #define SDIO_REG_LOW_FREEPG_8188F 0x0024 146 #define SDIO_REG_PUB_FREEPG_8188F 0x0026 147 #define SDIO_REG_EXQ_FREEPG_8188F 0x0028 148 #define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A 149 #define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B 150 151 #define SDIO_REG_HCPWM1_8188F 0x0038 152 153 /* indirect access */ 154 #define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40 155 #define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr)) 156 #define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0) 157 #define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1) 158 #define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2) 159 #define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1) 160 #define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1) 161 #define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1) 162 163 #define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44 164 165 /* **************************************************************************** 166 * 8188 Regsiter Bit and Content definition 167 * **************************************************************************** */ 168 169 /* 2 HSISR 170 * interrupt mask which needs to clear */ 171 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 172 HSISR_SPS_OCP_INT |\ 173 HSISR_RON_INT |\ 174 HSISR_PDNINT |\ 175 HSISR_GPIO9_INT) 176 177 /* ----------------------------------------------------- 178 * 179 * 0x0100h ~ 0x01FFh MACTOP General Configuration 180 * 181 * ----------------------------------------------------- */ 182 183 184 /* ----------------------------------------------------- 185 * 186 * 0x0200h ~ 0x027Fh TXDMA Configuration 187 * 188 * ----------------------------------------------------- */ 189 190 /* ----------------------------------------------------- 191 * 192 * 0x0280h ~ 0x02FFh RXDMA Configuration 193 * 194 * ----------------------------------------------------- */ 195 #define BIT_USB_RXDMA_AGG_EN BIT(31) 196 #define RXDMA_AGG_MODE_EN BIT(1) 197 198 #ifdef CONFIG_WOWLAN 199 #define RXPKT_RELEASE_POLL BIT(16) 200 #define RXDMA_IDLE BIT(17) 201 #define RW_RELEASE_EN BIT(18) 202 #endif 203 204 /* ----------------------------------------------------- 205 * 206 * 0x0400h ~ 0x047Fh Protocol Configuration 207 * 208 * ----------------------------------------------------- */ 209 210 /* ---------------------------------------------------------------------------- 211 * 8188F REG_CCK_CHECK (offset 0x454) 212 * ---------------------------------------------------------------------------- */ 213 #define BIT_BCN_PORT_SEL BIT(5) 214 215 /* ----------------------------------------------------- 216 * 217 * 0x0500h ~ 0x05FFh EDCA Configuration 218 * 219 * ----------------------------------------------------- */ 220 221 /* ----------------------------------------------------- 222 * 223 * 0x0600h ~ 0x07FFh WMAC Configuration 224 * 225 * ----------------------------------------------------- */ 226 227 /* ---------------------------------------------------------------------------- 228 * 8195 IMR/ISR bits (offset 0xB0, 8bits) 229 * ---------------------------------------------------------------------------- */ 230 #define IMR_DISABLED_8188F 0 231 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 232 #define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */ 233 #define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */ 234 #define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */ 235 #define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 236 #define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 237 #define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */ 238 #define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */ 239 #define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ 240 #define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */ 241 #define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */ 242 #define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 243 #define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 244 #define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */ 245 #define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 246 #define IMR_CPWM2_8188F BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 247 #define IMR_CPWM_8188F BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 248 #define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */ 249 #define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */ 250 #define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */ 251 #define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */ 252 #define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */ 253 #define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */ 254 #define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */ 255 #define IMR_ROK_8188F BIT(0) /* Receive DMA OK */ 256 257 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 258 #define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */ 259 #define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */ 260 #define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */ 261 #define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */ 262 #define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */ 263 #define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */ 264 #define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */ 265 #define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 266 #define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 267 #define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 268 #define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 269 #define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 270 #define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 271 #define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 272 #define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */ 273 #define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ 274 #define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ 275 #define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */ 276 #define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */ 277 278 #ifdef CONFIG_PCI_HCI 279 /* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */ 280 #define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F) 281 282 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F) 283 284 #define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F) 285 #endif 286 287 #endif /* __RTL8188F_SPEC_H__ */ 288