1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __HAL_DATA_H__ 16 #define __HAL_DATA_H__ 17 18 #if 1/* def CONFIG_SINGLE_IMG */ 19 20 #include "../hal/phydm/phydm_precomp.h" 21 #ifdef CONFIG_BT_COEXIST 22 #include <hal_btcoex.h> 23 #endif 24 25 #ifdef CONFIG_SDIO_HCI 26 #include <hal_sdio.h> 27 #endif 28 #ifdef CONFIG_GSPI_HCI 29 #include <hal_gspi.h> 30 #endif 31 32 #if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) 33 #include "../hal/hal_dm_acs.h" 34 #endif 35 36 /* 37 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 38 * */ 39 typedef enum _RT_MULTI_FUNC { 40 RT_MULTI_FUNC_NONE = 0x00, 41 RT_MULTI_FUNC_WIFI = 0x01, 42 RT_MULTI_FUNC_BT = 0x02, 43 RT_MULTI_FUNC_GPS = 0x04, 44 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 45 /* 46 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 47 * */ 48 typedef enum _RT_POLARITY_CTL { 49 RT_POLARITY_LOW_ACT = 0, 50 RT_POLARITY_HIGH_ACT = 1, 51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 52 53 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 54 typedef enum _RT_REGULATOR_MODE { 55 RT_SWITCHING_REGULATOR = 0, 56 RT_LDO_REGULATOR = 1, 57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 58 59 /* 60 * Interface type. 61 * */ 62 typedef enum _INTERFACE_SELECT_PCIE { 63 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 64 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 65 INTF_SEL2_PCIe = 2, /* PCIe Card */ 66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 67 68 69 typedef enum _INTERFACE_SELECT_USB { 70 INTF_SEL0_USB = 0, /* USB */ 71 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 72 INTF_SEL2_MINICARD = 2, /* Minicard */ 73 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 74 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 75 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 77 78 typedef enum _RT_AMPDU_BRUST_MODE { 79 RT_AMPDU_BRUST_NONE = 0, 80 RT_AMPDU_BRUST_92D = 1, 81 RT_AMPDU_BRUST_88E = 2, 82 RT_AMPDU_BRUST_8812_4 = 3, 83 RT_AMPDU_BRUST_8812_8 = 4, 84 RT_AMPDU_BRUST_8812_12 = 5, 85 RT_AMPDU_BRUST_8812_15 = 6, 86 RT_AMPDU_BRUST_8723B = 7, 87 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 88 89 /* Tx Power Limit Table Size */ 90 #define MAX_REGULATION_NUM 4 91 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 92 #define MAX_2_4G_BANDWIDTH_NUM 2 93 #define MAX_RATE_SECTION_NUM 10 94 #define MAX_5G_BANDWIDTH_NUM 4 95 96 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 97 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ 98 99 100 /* ###### duplicate code,will move to ODM ######### */ 101 /* #define IQK_MAC_REG_NUM 4 */ 102 /* #define IQK_ADDA_REG_NUM 16 */ 103 104 /* #define IQK_BB_REG_NUM 10 */ 105 #define IQK_BB_REG_NUM_92C 9 106 #define IQK_BB_REG_NUM_92D 10 107 #define IQK_BB_REG_NUM_test 6 108 109 #define IQK_Matrix_Settings_NUM_92D (1+24+21) 110 111 /* #define HP_THERMAL_NUM 8 */ 112 /* ###### duplicate code,will move to ODM ######### */ 113 114 #ifdef RTW_RX_AGGREGATION 115 typedef enum _RX_AGG_MODE { 116 RX_AGG_DISABLE, 117 RX_AGG_DMA, 118 RX_AGG_USB, 119 RX_AGG_MIX 120 } RX_AGG_MODE; 121 122 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 123 124 #endif /* RTW_RX_AGGREGATION */ 125 126 /* E-Fuse */ 127 #ifdef CONFIG_RTL8188E 128 #define EFUSE_MAP_SIZE 512 129 #endif 130 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) 131 #define EFUSE_MAP_SIZE 512 132 #endif 133 #ifdef CONFIG_RTL8192E 134 #define EFUSE_MAP_SIZE 512 135 #endif 136 #ifdef CONFIG_RTL8723B 137 #define EFUSE_MAP_SIZE 512 138 #endif 139 #ifdef CONFIG_RTL8814A 140 #define EFUSE_MAP_SIZE 512 141 #endif 142 #ifdef CONFIG_RTL8703B 143 #define EFUSE_MAP_SIZE 512 144 #endif 145 #ifdef CONFIG_RTL8723D 146 #define EFUSE_MAP_SIZE 512 147 #endif 148 #ifdef CONFIG_RTL8188F 149 #define EFUSE_MAP_SIZE 512 150 #endif 151 152 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) 153 #define EFUSE_MAX_SIZE 1024 154 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B) 155 #define EFUSE_MAX_SIZE 256 156 #else 157 #define EFUSE_MAX_SIZE 512 158 #endif 159 /* end of E-Fuse */ 160 161 #define Mac_OFDM_OK 0x00000000 162 #define Mac_OFDM_Fail 0x10000000 163 #define Mac_OFDM_FasleAlarm 0x20000000 164 #define Mac_CCK_OK 0x30000000 165 #define Mac_CCK_Fail 0x40000000 166 #define Mac_CCK_FasleAlarm 0x50000000 167 #define Mac_HT_OK 0x60000000 168 #define Mac_HT_Fail 0x70000000 169 #define Mac_HT_FasleAlarm 0x90000000 170 #define Mac_DropPacket 0xA0000000 171 172 #ifdef CONFIG_RF_POWER_TRIM 173 #if defined(CONFIG_RTL8723B) 174 #define REG_RF_BB_GAIN_OFFSET 0x7f 175 #define RF_GAIN_OFFSET_MASK 0xfffff 176 #elif defined(CONFIG_RTL8188E) 177 #define REG_RF_BB_GAIN_OFFSET 0x55 178 #define RF_GAIN_OFFSET_MASK 0xfffff 179 #else 180 #define REG_RF_BB_GAIN_OFFSET 0x55 181 #define RF_GAIN_OFFSET_MASK 0xfffff 182 #endif /* CONFIG_RTL8723B */ 183 #endif /*CONFIG_RF_POWER_TRIM*/ 184 185 /* For store initial value of BB register */ 186 typedef struct _BB_INIT_REGISTER { 187 u16 offset; 188 u32 value; 189 190 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 191 192 #define PAGE_SIZE_128 128 193 #define PAGE_SIZE_256 256 194 #define PAGE_SIZE_512 512 195 196 #define HCI_SUS_ENTER 0 197 #define HCI_SUS_LEAVING 1 198 #define HCI_SUS_LEAVE 2 199 #define HCI_SUS_ENTERING 3 200 #define HCI_SUS_ERR 4 201 202 #define EFUSE_FILE_UNUSED 0 203 #define EFUSE_FILE_FAILED 1 204 #define EFUSE_FILE_LOADED 2 205 206 #define MACADDR_FILE_UNUSED 0 207 #define MACADDR_FILE_FAILED 1 208 #define MACADDR_FILE_LOADED 2 209 210 #define KFREE_FLAG_ON BIT(0) 211 #define KFREE_FLAG_THERMAL_K_ON BIT(1) 212 213 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 214 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 215 216 struct kfree_data_t { 217 u8 flag; 218 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 219 220 #ifdef CONFIG_IEEE80211_BAND_5GHZ 221 s8 pa_bias_5g[RF_PATH_MAX]; 222 s8 pad_bias_5g[RF_PATH_MAX]; 223 #endif 224 s8 thermal; 225 }; 226 227 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 228 229 struct hal_spec_t { 230 char *ic_name; 231 u8 macid_num; 232 233 u8 sec_cam_ent_num; 234 u8 sec_cap; 235 236 u8 rfpath_num_2g:4; /* used for tx power index path */ 237 u8 rfpath_num_5g:4; /* used for tx power index path */ 238 239 u8 max_tx_cnt; 240 u8 tx_nss_num:4; 241 u8 rx_nss_num:4; 242 u8 band_cap; /* value of BAND_CAP_XXX */ 243 u8 bw_cap; /* value of BW_CAP_XXX */ 244 u8 port_num; 245 u8 proto_cap; /* value of PROTO_CAP_XXX */ 246 u8 wl_func; /* value of WL_FUNC_XXX */ 247 u8 hci_type; /* value of HCI Type */ 248 }; 249 250 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) 251 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) 252 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ 253 _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ 254 _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) 255 256 #define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx)) 257 258 #ifdef CONFIG_PHY_CAPABILITY_QUERY 259 struct phy_spec_t { 260 u32 trx_cap; 261 u32 stbc_cap; 262 u32 ldpc_cap; 263 u32 txbf_param; 264 u32 txbf_cap; 265 }; 266 #endif 267 struct hal_iqk_reg_backup { 268 u8 central_chnl; 269 u8 bw_mode; 270 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 271 }; 272 273 274 typedef struct hal_p2p_ps_para { 275 /*DW0*/ 276 u8 offload_en:1; 277 u8 role:1; 278 u8 ctwindow_en:1; 279 u8 noa_en:1; 280 u8 noa_sel:1; 281 u8 all_sta_sleep:1; 282 u8 discovery:1; 283 u8 rsvd2:1; 284 u8 p2p_port_id; 285 u8 p2p_group; 286 u8 p2p_macid; 287 288 /*DW1*/ 289 u8 ctwindow_length; 290 u8 rsvd3; 291 u8 rsvd4; 292 u8 rsvd5; 293 294 /*DW2*/ 295 u32 noa_duration_para; 296 297 /*DW3*/ 298 u32 noa_interval_para; 299 300 /*DW4*/ 301 u32 noa_start_time_para; 302 303 /*DW5*/ 304 u32 noa_count_para; 305 } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; 306 307 #define TXPWR_LMT_RS_CCK 0 308 #define TXPWR_LMT_RS_OFDM 1 309 #define TXPWR_LMT_RS_HT 2 310 #define TXPWR_LMT_RS_VHT 3 311 #define TXPWR_LMT_RS_NUM 4 312 313 #define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ 314 #define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ 315 316 #ifdef CONFIG_TXPWR_LIMIT 317 extern const char *const _txpwr_lmt_rs_str[]; 318 #define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) 319 320 struct txpwr_lmt_ent { 321 _list list; 322 323 s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] 324 [TXPWR_LMT_RS_NUM_2G] 325 [CENTER_CH_2G_NUM] 326 [MAX_TX_COUNT]; 327 328 #ifdef CONFIG_IEEE80211_BAND_5GHZ 329 s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] 330 [TXPWR_LMT_RS_NUM_5G] 331 [CENTER_CH_5G_ALL_NUM] 332 [MAX_TX_COUNT]; 333 #endif 334 335 char regd_name[0]; 336 }; 337 #endif /* CONFIG_TXPWR_LIMIT */ 338 339 typedef struct hal_com_data { 340 HAL_VERSION version_id; 341 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 342 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 343 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 344 u8 hw_init_completed; 345 /****** FW related ******/ 346 u32 firmware_size; 347 u16 firmware_version; 348 u16 FirmwareVersionRev; 349 u16 firmware_sub_version; 350 u16 FirmwareSignature; 351 u8 RegFWOffload; 352 u8 bFWReady; 353 u8 fw_ractrl; 354 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 355 356 /****** current WIFI_PHY values ******/ 357 WIRELESS_MODE CurrentWirelessMode; 358 enum channel_width current_channel_bw; 359 BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ 360 BAND_TYPE BandSet; 361 u8 current_channel; 362 u8 cch_20; 363 u8 cch_40; 364 u8 cch_80; 365 u8 CurrentCenterFrequencyIndex1; 366 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 367 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 368 BOOLEAN bSwChnlAndSetBWInProgress; 369 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 370 u16 BasicRateSet; 371 u32 ReceiveConfig; 372 u32 rcr_backup; /* used for switching back from monitor mode */ 373 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 374 BOOLEAN bSwChnl; 375 BOOLEAN bSetChnlBW; 376 BOOLEAN bSWToBW40M; 377 BOOLEAN bSWToBW80M; 378 BOOLEAN bChnlBWInitialized; 379 u32 BackUp_BB_REG_4_2nd_CCA[3]; 380 381 #ifdef CONFIG_RTW_ACS 382 struct auto_chan_sel acs; 383 #endif 384 #ifdef CONFIG_BCN_RECOVERY 385 u8 issue_bcn_fail; 386 #endif /*CONFIG_BCN_RECOVERY*/ 387 388 /****** rf_ctrl *****/ 389 u8 rf_chip; 390 u8 rf_type; /*enum rf_type*/ 391 u8 PackageType; 392 u8 NumTotalRFPath; 393 u8 antenna_test; 394 395 /****** Debug ******/ 396 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 397 u8 bDumpRxPkt; 398 u8 bDumpTxPkt; 399 u8 bDisableTXPowerTraining; 400 u8 dis_turboedca; 401 402 403 /****** EEPROM setting.******/ 404 u8 bautoload_fail_flag; 405 u8 efuse_file_status; 406 u8 macaddr_file_status; 407 u8 EepromOrEfuse; 408 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 409 u8 InterfaceSel; /* board type kept in eFuse */ 410 u16 CustomerID; 411 412 u16 EEPROMVID; 413 u16 EEPROMSVID; 414 #ifdef CONFIG_USB_HCI 415 u8 EEPROMUsbSwitch; 416 u16 EEPROMPID; 417 u16 EEPROMSDID; 418 #endif 419 #ifdef CONFIG_PCI_HCI 420 u16 EEPROMDID; 421 u16 EEPROMSMID; 422 #endif 423 424 u8 EEPROMCustomerID; 425 u8 EEPROMSubCustomerID; 426 u8 EEPROMVersion; 427 u8 EEPROMRegulatory; 428 u8 eeprom_thermal_meter; 429 u8 EEPROMBluetoothCoexist; 430 u8 EEPROMBluetoothType; 431 u8 EEPROMBluetoothAntNum; 432 u8 EEPROMBluetoothAntIsolation; 433 u8 EEPROMBluetoothRadioShared; 434 u8 EEPROMMACAddr[ETH_ALEN]; 435 u8 tx_bbswing_24G; 436 u8 tx_bbswing_5G; 437 u8 efuse0x3d7; /* efuse[0x3D7] */ 438 u8 efuse0x3d8; /* efuse[0x3D8] */ 439 440 #ifdef CONFIG_RF_POWER_TRIM 441 u8 EEPROMRFGainOffset; 442 u8 EEPROMRFGainVal; 443 struct kfree_data_t kfree_data; 444 #endif /*CONFIG_RF_POWER_TRIM*/ 445 446 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 447 defined(CONFIG_RTL8723D) 448 u8 adjuseVoltageVal; 449 u8 need_restore; 450 #endif 451 u8 EfuseUsedPercentage; 452 u16 EfuseUsedBytes; 453 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 454 EFUSE_HAL EfuseHal; 455 456 /*---------------------------------------------------------------------------------*/ 457 /* 2.4G TX power info for target TX power*/ 458 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 459 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 460 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 461 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 462 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 463 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 464 465 /* 5G TX power info for target TX power*/ 466 #ifdef CONFIG_IEEE80211_BAND_5GHZ 467 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 468 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 469 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 470 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 471 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 472 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 473 #endif 474 475 u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] 476 [TX_PWR_BY_RATE_NUM_RF]; 477 478 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 479 [TX_PWR_BY_RATE_NUM_RF] 480 [TX_PWR_BY_RATE_NUM_RATE]; 481 482 /* Store the original power by rate value of the base rate for each rate section and rf path */ 483 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 484 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 485 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 486 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 487 488 u8 txpwr_by_rate_loaded:1; 489 u8 txpwr_by_rate_from_file:1; 490 u8 txpwr_limit_loaded:1; 491 u8 txpwr_limit_from_file:1; 492 u8 rf_power_tracking_type; 493 494 /* Read/write are allow for following hardware information variables */ 495 u8 crystal_cap; 496 497 u8 PAType_2G; 498 u8 PAType_5G; 499 u8 LNAType_2G; 500 u8 LNAType_5G; 501 u8 ExternalPA_2G; 502 u8 ExternalLNA_2G; 503 u8 external_pa_5g; 504 u8 external_lna_5g; 505 u16 TypeGLNA; 506 u16 TypeGPA; 507 u16 TypeALNA; 508 u16 TypeAPA; 509 u16 rfe_type; 510 511 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 512 u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ 513 u8 is_turbo_edca; 514 u8 prv_traffic_idx; 515 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 516 517 u32 RfRegChnlVal[MAX_RF_PATH]; 518 519 /* RDG enable */ 520 BOOLEAN bRDGEnable; 521 522 u16 RegRRSR; 523 /****** antenna diversity ******/ 524 u8 AntDivCfg; 525 u8 with_extenal_ant_switch; 526 u8 b_fix_tx_ant; 527 u8 AntDetection; 528 u8 TRxAntDivType; 529 u8 ant_path; /* for 8723B s0/s1 selection */ 530 u32 antenna_tx_path; /* Antenna path Tx */ 531 u32 AntennaRxPath; /* Antenna path Rx */ 532 u8 sw_antdiv_bl_state; 533 534 /******** PHY DM & DM Section **********/ 535 _lock IQKSpinLock; 536 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 537 538 struct PHY_DM_STRUCT odmpriv; 539 u64 bk_rf_ability; 540 u8 bIQKInitialized; 541 u8 bNeedIQK; 542 u8 IQK_MP_Switch; 543 u8 bScanInProcess; 544 /******** PHY DM & DM Section **********/ 545 546 547 548 /* 2010/08/09 MH Add CU power down mode. */ 549 BOOLEAN pwrdown; 550 551 /* Add for dual MAC 0--Mac0 1--Mac1 */ 552 u32 interfaceIndex; 553 554 #ifdef CONFIG_P2P 555 u8 p2p_ps_offload; 556 #endif 557 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 558 u8 bMacPwrCtrlOn; 559 u8 hci_sus_state; 560 561 u8 RegIQKFWOffload; 562 struct submit_ctx iqk_sctx; 563 564 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 565 566 u8 OutEpQueueSel; 567 u8 OutEpNumber; 568 569 #ifdef RTW_RX_AGGREGATION 570 RX_AGG_MODE rxagg_mode; 571 572 /* For RX Aggregation DMA Mode */ 573 u8 rxagg_dma_size; 574 u8 rxagg_dma_timeout; 575 #endif /* RTW_RX_AGGREGATION */ 576 577 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 578 /* */ 579 /* For SDIO Interface HAL related */ 580 /* */ 581 582 /* */ 583 /* SDIO ISR Related */ 584 /* 585 * u32 IntrMask[1]; 586 * u32 IntrMaskToSet[1]; 587 * LOG_INTERRUPT InterruptLog; */ 588 u32 sdio_himr; 589 u32 sdio_hisr; 590 #ifndef RTW_HALMAC 591 /* */ 592 /* SDIO Tx FIFO related. */ 593 /* */ 594 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 595 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 596 _lock SdioTxFIFOFreePageLock; 597 u8 SdioTxOQTMaxFreeSpace; 598 u8 SdioTxOQTFreeSpace; 599 #else /* RTW_HALMAC */ 600 u16 SdioTxOQTFreeSpace; 601 #endif /* RTW_HALMAC */ 602 603 /* */ 604 /* SDIO Rx FIFO related. */ 605 /* */ 606 u8 SdioRxFIFOCnt; 607 u16 SdioRxFIFOSize; 608 609 #ifndef RTW_HALMAC 610 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 611 #else 612 #ifdef CONFIG_RTL8821C 613 u16 tx_high_page; 614 u16 tx_low_page; 615 u16 tx_normal_page; 616 u16 tx_extra_page; 617 u16 tx_pub_page; 618 u8 max_oqt_size; 619 #ifdef XMIT_BUF_SIZE 620 u32 max_xmit_size_vovi; 621 u32 max_xmit_size_bebk; 622 #endif /*XMIT_BUF_SIZE*/ 623 u16 max_xmit_page; 624 u16 max_xmit_page_vo; 625 u16 max_xmit_page_vi; 626 u16 max_xmit_page_be; 627 u16 max_xmit_page_bk; 628 629 #endif /*#ifdef CONFIG_RTL8821C*/ 630 #endif /* !RTW_HALMAC */ 631 #endif /* CONFIG_SDIO_HCI */ 632 633 #ifdef CONFIG_USB_HCI 634 635 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 636 BOOLEAN UsbRxHighSpeedMode; 637 BOOLEAN UsbTxVeryHighSpeedMode; 638 u32 UsbBulkOutSize; 639 BOOLEAN bSupportUSB3; 640 u8 usb_intf_start; 641 642 /* Interrupt relatd register information. */ 643 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 644 u32 IntrMask[3]; 645 #ifdef CONFIG_USB_TX_AGGREGATION 646 u8 UsbTxAggMode; 647 u8 UsbTxAggDescNum; 648 #endif /* CONFIG_USB_TX_AGGREGATION */ 649 650 #ifdef CONFIG_USB_RX_AGGREGATION 651 u16 HwRxPageSize; /* Hardware setting */ 652 653 /* For RX Aggregation USB Mode */ 654 u8 rxagg_usb_size; 655 u8 rxagg_usb_timeout; 656 #endif/* CONFIG_USB_RX_AGGREGATION */ 657 #endif /* CONFIG_USB_HCI */ 658 659 660 #ifdef CONFIG_PCI_HCI 661 /* */ 662 /* EEPROM setting. */ 663 /* */ 664 u32 TransmitConfig; 665 u32 IntrMaskToSet[2]; 666 u32 IntArray[4]; 667 u32 IntrMask[4]; 668 u32 SysIntArray[1]; 669 u32 SysIntrMask[1]; 670 u32 IntrMaskReg[2]; 671 u32 IntrMaskDefault[4]; 672 673 BOOLEAN bL1OffSupport; 674 BOOLEAN bSupportBackDoor; 675 u32 pci_backdoor_ctrl; 676 677 u8 bDefaultAntenna; 678 679 u8 bInterruptMigration; 680 u8 bDisableTxInt; 681 682 u16 RxTag; 683 #endif /* CONFIG_PCI_HCI */ 684 685 686 #ifdef DBG_CONFIG_ERROR_DETECT 687 struct sreset_priv srestpriv; 688 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 689 690 #ifdef CONFIG_BT_COEXIST 691 /* For bluetooth co-existance */ 692 BT_COEXIST bt_coexist; 693 #endif /* CONFIG_BT_COEXIST */ 694 695 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 696 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D) 697 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 698 /* Interrupt relatd register information. */ 699 u32 SysIntrStatus; 700 u32 SysIntrMask; 701 #endif 702 #endif /*endif CONFIG_RTL8723B */ 703 704 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 705 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 706 char *mac_reg; 707 u32 mac_reg_len; 708 char *bb_phy_reg; 709 u32 bb_phy_reg_len; 710 char *bb_agc_tab; 711 u32 bb_agc_tab_len; 712 char *bb_phy_reg_pg; 713 u32 bb_phy_reg_pg_len; 714 char *bb_phy_reg_mp; 715 u32 bb_phy_reg_mp_len; 716 char *rf_radio_a; 717 u32 rf_radio_a_len; 718 char *rf_radio_b; 719 u32 rf_radio_b_len; 720 char *rf_tx_pwr_track; 721 u32 rf_tx_pwr_track_len; 722 char *rf_tx_pwr_lmt; 723 u32 rf_tx_pwr_lmt_len; 724 #endif 725 726 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 727 struct noise_monitor nm; 728 #endif 729 730 struct hal_spec_t hal_spec; 731 #ifdef CONFIG_PHY_CAPABILITY_QUERY 732 struct phy_spec_t phy_spec; 733 #endif 734 u8 RfKFreeEnable; 735 u8 RfKFree_ch_group; 736 BOOLEAN bCCKinCH14; 737 BB_INIT_REGISTER RegForRecover[5]; 738 739 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 740 BOOLEAN bCorrectBCN; 741 #endif 742 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 743 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 744 745 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 746 747 #ifdef RTW_HALMAC 748 u8 drv_rsvd_page_number; 749 #endif 750 751 #ifdef CONFIG_BEAMFORMING 752 u8 backup_snd_ptcl_ctrl; 753 #ifdef RTW_BEAMFORMING_VERSION_2 754 struct beamforming_info beamforming_info; 755 #endif /* RTW_BEAMFORMING_VERSION_2 */ 756 #endif /* CONFIG_BEAMFORMING */ 757 758 u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ 759 u8 phydm_op_mode; 760 761 u8 in_cta_test; 762 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 763 764 765 766 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 767 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) 768 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 769 770 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) 771 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 772 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) 773 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 774 775 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 776 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 777 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 778 779 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 780 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 781 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 782 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 783 #endif 784 785 #ifdef RTW_HALMAC 786 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 787 #endif /* RTW_HALMAC */ 788 789 /* alias for phydm coding style */ 790 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 791 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 792 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 793 #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 794 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 795 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 796 #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 797 #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 798 799 #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 800 #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 801 #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 802 #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 803 #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 804 #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 805 #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 806 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 807 #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 808 #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 809 #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 810 #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 811 #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 812 #define REG_IQK_AGC_CONT rIQK_AGC_Cont 813 #define REG_IQK_AGC_PTS rIQK_AGC_Pts 814 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 815 #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 816 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 817 #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 818 #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 819 #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 820 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 821 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 822 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 823 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 824 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 825 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 826 #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 827 #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 828 829 /*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/ 830 #define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar 831 /*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/ 832 #define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar 833 #define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar 834 /*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/ 835 #define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar 836 /*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/ 837 #define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar 838 /*#define REG_A_TX_AGC rA_TXAGC*/ 839 #define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar 840 #define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar 841 /*#define REG_B_BBSWING rB_BBSWING*/ 842 /*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/ 843 #define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar 844 /*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/ 845 #define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar 846 /*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/ 847 #define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar 848 /*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/ 849 #define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar 850 /*#define REG_B_TX_AGC rB_TXAGC*/ 851 #define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar 852 #define REG_BLUE_TOOTH rBlue_Tooth 853 #define REG_CCK_0_AFE_SETTING rCCK0_AFESetting 854 /*#define REG_C_BBSWING rC_BBSWING*/ 855 /*#define REG_C_TX_AGC rC_TXAGC*/ 856 #define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2 857 #define REG_CONFIG_ANT_A rConfig_AntA 858 #define REG_CONFIG_ANT_B rConfig_AntB 859 #define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA 860 #define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB 861 #define REG_DPDT_CONTROL rDPDT_control 862 /*#define REG_D_BBSWING rD_BBSWING*/ 863 /*#define REG_D_TX_AGC rD_TXAGC*/ 864 #define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2 865 #define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4 866 #define REG_FPGA0_IQK rFPGA0_IQK 867 #define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction 868 #define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport 869 #define REG_FPGA0_RFMOD rFPGA0_RFMOD 870 #define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage 871 #define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW 872 #define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter 873 #define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 874 #define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter 875 #define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE 876 #define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 877 #define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter 878 #define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack 879 #define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE 880 #define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW 881 #define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl 882 #define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock 883 #define REG_FPGA1_TX_INFO rFPGA1_TxInfo 884 #define REG_IQK_AGC_CONT rIQK_AGC_Cont 885 #define REG_IQK_AGC_PTS rIQK_AGC_Pts 886 #define REG_IQK_AGC_RSP rIQK_AGC_Rsp 887 #define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable 888 #define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold 889 #define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta 890 #define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar 891 #define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable 892 #define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 893 #define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance 894 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance 895 #define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 896 #define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance 897 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance 898 #define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE 899 #define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE 900 #define REG_PMPD_ANAEN rPMPD_ANAEN 901 #define REG_PDP_ANT_A rPdp_AntA 902 #define REG_PDP_ANT_A_4 rPdp_AntA_4 903 #define REG_PDP_ANT_B rPdp_AntB 904 #define REG_PDP_ANT_B_4 rPdp_AntB_4 905 #define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar 906 #define REG_RX_CCK rRx_CCK 907 #define REG_RX_IQK rRx_IQK 908 #define REG_RX_IQK_PI_A rRx_IQK_PI_A 909 #define REG_RX_IQK_PI_B rRx_IQK_PI_B 910 #define REG_RX_IQK_TONE_A rRx_IQK_Tone_A 911 #define REG_RX_IQK_TONE_B rRx_IQK_Tone_B 912 #define REG_RX_OFDM rRx_OFDM 913 #define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2 914 #define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2 915 #define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2 916 #define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2 917 #define REG_RX_TO_RX rRx_TO_Rx 918 #define REG_RX_WAIT_CCA rRx_Wait_CCA 919 #define REG_RX_WAIT_RIFS rRx_Wait_RIFS 920 #define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch 921 /*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/ 922 #define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar 923 /*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/ 924 #define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar 925 #define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL 926 #define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar 927 #define REG_SLEEP rSleep 928 #define REG_STANDBY rStandby 929 #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar 930 #define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32 931 #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar 932 #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar 933 #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar 934 #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar 935 #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar 936 #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar 937 #define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00 938 #define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04 939 #define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08 940 #define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12 941 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 942 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 943 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 944 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 945 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 946 #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 947 #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 948 #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 949 #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar 950 #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar 951 #define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06 952 #define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24 953 #define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11 954 #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar 955 #define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32 956 #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar 957 #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar 958 #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar 959 #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar 960 #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar 961 #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar 962 #define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00 963 #define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04 964 #define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08 965 #define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12 966 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 967 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 968 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 969 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 970 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 971 #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 972 #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 973 #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 974 #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar 975 #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar 976 #define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06 977 #define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24 978 #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar 979 #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar 980 #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar 981 #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar 982 #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar 983 #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar 984 #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar 985 #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 986 #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 987 #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 988 #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 989 #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 990 #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 991 #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 992 #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 993 #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar 994 #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar 995 #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar 996 #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar 997 #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar 998 #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar 999 #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar 1000 #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar 1001 #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar 1002 #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 1003 #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 1004 #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 1005 #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 1006 #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 1007 #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 1008 #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 1009 #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 1010 #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar 1011 #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar 1012 #define REG_TX_PATH_JAGUAR rTxPath_Jaguar 1013 #define REG_TX_CCK_BBON rTx_CCK_BBON 1014 #define REG_TX_CCK_RFON rTx_CCK_RFON 1015 #define REG_TX_IQK rTx_IQK 1016 #define REG_TX_IQK_PI_A rTx_IQK_PI_A 1017 #define REG_TX_IQK_PI_B rTx_IQK_PI_B 1018 #define REG_TX_IQK_TONE_A rTx_IQK_Tone_A 1019 #define REG_TX_IQK_TONE_B rTx_IQK_Tone_B 1020 #define REG_TX_OFDM_BBON rTx_OFDM_BBON 1021 #define REG_TX_OFDM_RFON rTx_OFDM_RFON 1022 #define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A 1023 #define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B 1024 #define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A 1025 #define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B 1026 #define REG_TX_TO_RX rTx_To_Rx 1027 #define REG_TX_TO_TX rTx_To_Tx 1028 #define REG_APK rAPK 1029 #define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar 1030 1031 1032 1033 #define rf_welut_jaguar RF_WeLut_Jaguar 1034 #define rf_mode_table_addr RF_ModeTableAddr 1035 #define rf_mode_table_data0 RF_ModeTableData0 1036 #define rf_mode_table_data1 RF_ModeTableData1 1037 1038 1039 1040 1041 1042 1043 #define RX_SMOOTH_FACTOR Rx_Smooth_Factor 1044 1045 #endif /* __HAL_DATA_H__ */ 1046