1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2012 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 /***************************************************************************** 17 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. 18 * 19 * Module: __INC_HAL8192SPHYREG_H 20 * 21 * 22 * Note: 1. Define PMAC/BB register map 23 * 2. Define RF register map 24 * 3. PMAC/BB register bit mask. 25 * 4. RF reg bit mask. 26 * 5. Other BB/RF relative definition. 27 * 28 * 29 * Export: Constants, macro, functions(API), global variables(None). 30 * 31 * Abbrev: 32 * 33 * History: 34 * Data Who Remark 35 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 36 * 2. Reorganize code architecture. 37 * 09/25/2008 MH 1. Add RL6052 register definition 38 * 39 *****************************************************************************/ 40 #ifndef __INC_HAL8192EPHYREG_H 41 #define __INC_HAL8192EPHYREG_H 42 43 44 /*--------------------------Define Parameters-------------------------------*/ 45 46 /* ************************************************************ 47 * 8192S Regsiter offset definition 48 * ************************************************************ */ 49 50 /* 51 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 52 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 53 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 54 * 3. RF register 0x00-2E 55 * 4. Bit Mask for BB/RF register 56 * 5. Other defintion for BB/RF R/W 57 * */ 58 59 60 /* 61 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 62 * 1. Page1(0x100) 63 * */ 64 #define rPMAC_Reset 0x100 65 #define rPMAC_TxStart 0x104 66 #define rPMAC_TxLegacySIG 0x108 67 #define rPMAC_TxHTSIG1 0x10c 68 #define rPMAC_TxHTSIG2 0x110 69 #define rPMAC_PHYDebug 0x114 70 #define rPMAC_TxPacketNum 0x118 71 #define rPMAC_TxIdle 0x11c 72 #define rPMAC_TxMACHeader0 0x120 73 #define rPMAC_TxMACHeader1 0x124 74 #define rPMAC_TxMACHeader2 0x128 75 #define rPMAC_TxMACHeader3 0x12c 76 #define rPMAC_TxMACHeader4 0x130 77 #define rPMAC_TxMACHeader5 0x134 78 #define rPMAC_TxDataType 0x138 79 #define rPMAC_TxRandomSeed 0x13c 80 #define rPMAC_CCKPLCPPreamble 0x140 81 #define rPMAC_CCKPLCPHeader 0x144 82 #define rPMAC_CCKCRC16 0x148 83 #define rPMAC_OFDMRxCRC32OK 0x170 84 #define rPMAC_OFDMRxCRC32Er 0x174 85 #define rPMAC_OFDMRxParityEr 0x178 86 #define rPMAC_OFDMRxCRC8Er 0x17c 87 #define rPMAC_CCKCRxRC16Er 0x180 88 #define rPMAC_CCKCRxRC32Er 0x184 89 #define rPMAC_CCKCRxRC32OK 0x188 90 #define rPMAC_TxStatus 0x18c 91 92 93 /* 94 * 3. Page8(0x800) 95 * */ 96 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 97 98 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 99 #define rFPGA0_PSDFunction 0x808 100 101 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 102 103 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 104 #define rFPGA0_RFTiming2 0x814 105 106 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 107 #define rFPGA0_XA_HSSIParameter2 0x824 108 #define rFPGA0_XB_HSSIParameter1 0x828 109 #define rFPGA0_XB_HSSIParameter2 0x82c 110 111 #define rFPGA0_XA_LSSIParameter 0x840 112 #define rFPGA0_XB_LSSIParameter 0x844 113 114 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 115 #define rFPGA0_RFSleepUpParameter 0x854 116 117 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 118 #define rFPGA0_XCD_SwitchControl 0x85c 119 120 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 121 #define rFPGA0_XB_RFInterfaceOE 0x864 122 123 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 124 #define rFPGA0_XCD_RFInterfaceSW 0x874 125 126 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 127 #define rFPGA0_XCD_RFParameter 0x87c 128 129 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 130 #define rFPGA0_AnalogParameter2 0x884 131 #define rFPGA0_AnalogParameter3 0x888 132 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 133 #define rFPGA0_AnalogParameter4 0x88c 134 135 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 136 #define rFPGA0_XB_LSSIReadBack 0x8a4 137 #define rFPGA0_XC_LSSIReadBack 0x8a8 138 #define rFPGA0_XD_LSSIReadBack 0x8ac 139 140 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 141 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 142 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 143 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 144 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 145 146 /* 147 * 4. Page9(0x900) 148 * */ 149 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 150 151 #define rFPGA1_TxBlock 0x904 /* Useless now */ 152 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 153 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 154 155 /* 156 * 5. PageA(0xA00) 157 * 158 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 159 #define rCCK0_System 0xa00 160 161 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 162 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 163 164 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 165 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 166 167 #define rCCK0_RxHP 0xa14 168 169 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 170 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 171 172 #define rCCK0_TxFilter1 0xa20 173 #define rCCK0_TxFilter2 0xa24 174 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 175 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 176 #define rCCK0_TRSSIReport 0xa50 177 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 178 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 179 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 180 181 /* 182 * PageB(0xB00) 183 * */ 184 #define rPdp_AntA 0xb00 185 #define rPdp_AntA_4 0xb04 186 #define rConfig_Pmpd_AntA 0xb28 187 #define rConfig_ram64x16 0xb2c 188 189 #define rConfig_AntA 0xb68 190 #define rConfig_AntB 0xb6c 191 #define rPdp_AntB 0xb70 192 #define rPdp_AntB_4 0xb74 193 #define rConfig_Pmpd_AntB 0xb98 194 #define rAPK 0xbd8 195 196 197 198 /* 199 * 6. PageC(0xC00) 200 * */ 201 #define rOFDM0_LSTF 0xc00 202 203 #define rOFDM0_TRxPathEnable 0xc04 204 #define rOFDM0_TRMuxPar 0xc08 205 #define rOFDM0_TRSWIsolation 0xc0c 206 207 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 208 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 209 #define rOFDM0_XBRxAFE 0xc18 210 #define rOFDM0_XBRxIQImbalance 0xc1c 211 #define rOFDM0_XCRxAFE 0xc20 212 #define rOFDM0_XCRxIQImbalance 0xc24 213 #define rOFDM0_XDRxAFE 0xc28 214 #define rOFDM0_XDRxIQImbalance 0xc2c 215 216 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 217 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 218 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 219 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 220 221 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 222 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 223 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 224 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 225 226 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 227 #define rOFDM0_XAAGCCore2 0xc54 228 #define rOFDM0_XBAGCCore1 0xc58 229 #define rOFDM0_XBAGCCore2 0xc5c 230 #define rOFDM0_XCAGCCore1 0xc60 231 #define rOFDM0_XCAGCCore2 0xc64 232 #define rOFDM0_XDAGCCore1 0xc68 233 #define rOFDM0_XDAGCCore2 0xc6c 234 235 #define rOFDM0_AGCParameter1 0xc70 236 #define rOFDM0_AGCParameter2 0xc74 237 #define rOFDM0_AGCRSSITable 0xc78 238 #define rOFDM0_HTSTFAGC 0xc7c 239 240 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 241 #define rOFDM0_XATxAFE 0xc84 242 #define rOFDM0_XBTxIQImbalance 0xc88 243 #define rOFDM0_XBTxAFE 0xc8c 244 #define rOFDM0_XCTxIQImbalance 0xc90 245 #define rOFDM0_XCTxAFE 0xc94 246 #define rOFDM0_XDTxIQImbalance 0xc98 247 #define rOFDM0_XDTxAFE 0xc9c 248 249 #define rOFDM0_RxIQExtAnta 0xca0 250 #define rOFDM0_TxCoeff1 0xca4 251 #define rOFDM0_TxCoeff2 0xca8 252 #define rOFDM0_TxCoeff3 0xcac 253 #define rOFDM0_TxCoeff4 0xcb0 254 #define rOFDM0_TxCoeff5 0xcb4 255 #define rOFDM0_RxHPParameter 0xce0 256 #define rOFDM0_TxPseudoNoiseWgt 0xce4 257 #define rOFDM0_FrameSync 0xcf0 258 #define rOFDM0_DFSReport 0xcf4 259 260 261 /* 262 * 7. PageD(0xD00) 263 * */ 264 #define rOFDM1_LSTF 0xd00 265 #define rOFDM1_TRxPathEnable 0xd04 266 267 #define rOFDM1_CFO 0xd08 /* No setting now */ 268 #define rOFDM1_CSI1 0xd10 269 #define rOFDM1_SBD 0xd14 270 #define rOFDM1_CSI2 0xd18 271 #define rOFDM1_CFOTracking 0xd2c 272 #define rOFDM1_TRxMesaure1 0xd34 273 #define rOFDM1_IntfDet 0xd3c 274 #define rOFDM1_PseudoNoiseStateAB 0xd50 275 #define rOFDM1_PseudoNoiseStateCD 0xd54 276 #define rOFDM1_RxPseudoNoiseWgt 0xd58 277 278 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 279 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 280 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 281 282 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 283 #define rOFDM_ShortCFOCD 0xdb0 284 #define rOFDM_LongCFOAB 0xdb4 285 #define rOFDM_LongCFOCD 0xdb8 286 #define rOFDM_TailCFOAB 0xdbc 287 #define rOFDM_TailCFOCD 0xdc0 288 #define rOFDM_PWMeasure1 0xdc4 289 #define rOFDM_PWMeasure2 0xdc8 290 #define rOFDM_BWReport 0xdcc 291 #define rOFDM_AGCReport 0xdd0 292 #define rOFDM_RxSNR 0xdd4 293 #define rOFDM_RxEVMCSI 0xdd8 294 #define rOFDM_SIGReport 0xddc 295 296 297 /* 298 * 8. PageE(0xE00) 299 * */ 300 #define rTxAGC_A_Rate18_06 0xe00 301 #define rTxAGC_A_Rate54_24 0xe04 302 #define rTxAGC_A_CCK1_Mcs32 0xe08 303 #define rTxAGC_A_Mcs03_Mcs00 0xe10 304 #define rTxAGC_A_Mcs07_Mcs04 0xe14 305 #define rTxAGC_A_Mcs11_Mcs08 0xe18 306 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 307 308 #define rTxAGC_B_Rate18_06 0x830 309 #define rTxAGC_B_Rate54_24 0x834 310 #define rTxAGC_B_CCK1_55_Mcs32 0x838 311 #define rTxAGC_B_Mcs03_Mcs00 0x83c 312 #define rTxAGC_B_Mcs07_Mcs04 0x848 313 #define rTxAGC_B_Mcs11_Mcs08 0x84c 314 #define rTxAGC_B_Mcs15_Mcs12 0x868 315 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 316 317 #define rFPGA0_IQK 0xe28 318 #define rTx_IQK_Tone_A 0xe30 319 #define rRx_IQK_Tone_A 0xe34 320 #define rTx_IQK_PI_A 0xe38 321 #define rRx_IQK_PI_A 0xe3c 322 323 #define rTx_IQK 0xe40 324 #define rRx_IQK 0xe44 325 #define rIQK_AGC_Pts 0xe48 326 #define rIQK_AGC_Rsp 0xe4c 327 #define rTx_IQK_Tone_B 0xe50 328 #define rRx_IQK_Tone_B 0xe54 329 #define rTx_IQK_PI_B 0xe58 330 #define rRx_IQK_PI_B 0xe5c 331 #define rIQK_AGC_Cont 0xe60 332 333 #define rBlue_Tooth 0xe6c 334 #define rRx_Wait_CCA 0xe70 335 #define rTx_CCK_RFON 0xe74 336 #define rTx_CCK_BBON 0xe78 337 #define rTx_OFDM_RFON 0xe7c 338 #define rTx_OFDM_BBON 0xe80 339 #define rTx_To_Rx 0xe84 340 #define rTx_To_Tx 0xe88 341 #define rRx_CCK 0xe8c 342 343 #define rTx_Power_Before_IQK_A 0xe94 344 #define rTx_Power_After_IQK_A 0xe9c 345 346 #define rRx_Power_Before_IQK_A 0xea0 347 #define rRx_Power_Before_IQK_A_2 0xea4 348 #define rRx_Power_After_IQK_A 0xea8 349 #define rRx_Power_After_IQK_A_2 0xeac 350 351 #define rTx_Power_Before_IQK_B 0xeb4 352 #define rTx_Power_After_IQK_B 0xebc 353 354 #define rRx_Power_Before_IQK_B 0xec0 355 #define rRx_Power_Before_IQK_B_2 0xec4 356 #define rRx_Power_After_IQK_B 0xec8 357 #define rRx_Power_After_IQK_B_2 0xecc 358 359 #define rRx_OFDM 0xed0 360 #define rRx_Wait_RIFS 0xed4 361 #define rRx_TO_Rx 0xed8 362 #define rStandby 0xedc 363 #define rSleep 0xee0 364 #define rPMPD_ANAEN 0xeec 365 366 /* 367 * 7. RF Register 0x00-0x2E (RF 8256) 368 * RF-0222D 0x00-3F 369 * 370 * Zebra1 */ 371 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 372 #define rZebra1_TRxEnable1 0x1 373 #define rZebra1_TRxEnable2 0x2 374 #define rZebra1_AGC 0x4 375 #define rZebra1_ChargePump 0x5 376 #define rZebra1_Channel 0x7 /* RF channel switch */ 377 378 /* #endif */ 379 #define rZebra1_TxGain 0x8 /* Useless now */ 380 #define rZebra1_TxLPF 0x9 381 #define rZebra1_RxLPF 0xb 382 #define rZebra1_RxHPFCorner 0xc 383 384 /* Zebra4 */ 385 #define rGlobalCtrl 0 /* Useless now */ 386 #define rRTL8256_TxLPF 19 387 #define rRTL8256_RxLPF 11 388 389 /* RTL8258 */ 390 #define rRTL8258_TxLPF 0x11 /* Useless now */ 391 #define rRTL8258_RxLPF 0x13 392 #define rRTL8258_RSSILPF 0xa 393 394 /* 395 * RL6052 Register definition 396 * */ 397 #define RF_AC 0x00 /* */ 398 399 #define RF_IQADJ_G1 0x01 /* */ 400 #define RF_IQADJ_G2 0x02 /* */ 401 402 #define RF_POW_TRSW 0x05 /* */ 403 404 #define RF_GAIN_RX 0x06 /* */ 405 #define RF_GAIN_TX 0x07 /* */ 406 407 #define RF_TXM_IDAC 0x08 /* */ 408 #define RF_IPA_G 0x09 /* */ 409 #define RF_TXBIAS_G 0x0A 410 #define RF_TXPA_AG 0x0B 411 #define RF_IPA_A 0x0C /* */ 412 #define RF_TXBIAS_A 0x0D 413 #define RF_BS_PA_APSET_G9_G11 0x0E 414 #define RF_BS_IQGEN 0x0F /* */ 415 416 #define RF_MODE1 0x10 /* */ 417 #define RF_MODE2 0x11 /* */ 418 419 #define RF_RX_AGC_HP 0x12 /* */ 420 #define RF_TX_AGC 0x13 /* */ 421 #define RF_BIAS 0x14 /* */ 422 #define RF_IPA 0x15 /* */ 423 #define RF_TXBIAS 0x16 424 #define RF_POW_ABILITY 0x17 /* */ 425 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 426 #define RF_TOP 0x19 /* */ 427 428 #define RF_RX_G1 0x1A /* */ 429 #define RF_RX_G2 0x1B /* */ 430 431 #define RF_RX_BB2 0x1C /* */ 432 #define RF_RX_BB1 0x1D /* */ 433 434 #define RF_RCK1 0x1E /* */ 435 #define RF_RCK2 0x1F /* */ 436 437 #define RF_TX_G1 0x20 /* */ 438 #define RF_TX_G2 0x21 /* */ 439 #define RF_TX_G3 0x22 /* */ 440 441 #define RF_TX_BB1 0x23 /* */ 442 443 #define RF_T_METER_8192E 0x42 /* */ 444 #define RF_T_METER_88E 0x42 445 #define RF_T_METER 0x24 /* */ 446 447 /* #endif */ 448 449 #define RF_SYN_G1 0x25 /* RF TX Power control */ 450 #define RF_SYN_G2 0x26 /* RF TX Power control */ 451 #define RF_SYN_G3 0x27 /* RF TX Power control */ 452 #define RF_SYN_G4 0x28 /* RF TX Power control */ 453 #define RF_SYN_G5 0x29 /* RF TX Power control */ 454 #define RF_SYN_G6 0x2A /* RF TX Power control */ 455 #define RF_SYN_G7 0x2B /* RF TX Power control */ 456 #define RF_SYN_G8 0x2C /* RF TX Power control */ 457 458 #define RF_RCK_OS 0x30 /* RF TX PA control */ 459 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 460 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 461 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 462 #define RF_TX_BIAS_A 0x35 463 #define RF_TX_BIAS_D 0x36 464 #define RF_LOBF_9 0x38 465 #define RF_RXRF_A3 0x3C /* */ 466 #define RF_TRSW 0x3F 467 468 #define RF_TXRF_A2 0x41 469 #define RF_TXPA_G4 0x46 470 #define RF_TXPA_A4 0x4B 471 #define RF_0x52 0x52 472 #define RF_LDO 0xB1 473 #define RF_WE_LUT 0xEF 474 475 476 /* 477 * Bit Mask 478 * 479 * 1. Page1(0x100) */ 480 #define bBBResetB 0x100 /* Useless now? */ 481 #define bGlobalResetB 0x200 482 #define bOFDMTxStart 0x4 483 #define bCCKTxStart 0x8 484 #define bCRC32Debug 0x100 485 #define bPMACLoopback 0x10 486 #define bTxLSIG 0xffffff 487 #define bOFDMTxRate 0xf 488 #define bOFDMTxReserved 0x10 489 #define bOFDMTxLength 0x1ffe0 490 #define bOFDMTxParity 0x20000 491 #define bTxHTSIG1 0xffffff 492 #define bTxHTMCSRate 0x7f 493 #define bTxHTBW 0x80 494 #define bTxHTLength 0xffff00 495 #define bTxHTSIG2 0xffffff 496 #define bTxHTSmoothing 0x1 497 #define bTxHTSounding 0x2 498 #define bTxHTReserved 0x4 499 #define bTxHTAggreation 0x8 500 #define bTxHTSTBC 0x30 501 #define bTxHTAdvanceCoding 0x40 502 #define bTxHTShortGI 0x80 503 #define bTxHTNumberHT_LTF 0x300 504 #define bTxHTCRC8 0x3fc00 505 #define bCounterReset 0x10000 506 #define bNumOfOFDMTx 0xffff 507 #define bNumOfCCKTx 0xffff0000 508 #define bTxIdleInterval 0xffff 509 #define bOFDMService 0xffff0000 510 #define bTxMACHeader 0xffffffff 511 #define bTxDataInit 0xff 512 #define bTxHTMode 0x100 513 #define bTxDataType 0x30000 514 #define bTxRandomSeed 0xffffffff 515 #define bCCKTxPreamble 0x1 516 #define bCCKTxSFD 0xffff0000 517 #define bCCKTxSIG 0xff 518 #define bCCKTxService 0xff00 519 #define bCCKLengthExt 0x8000 520 #define bCCKTxLength 0xffff0000 521 #define bCCKTxCRC16 0xffff 522 #define bCCKTxStatus 0x1 523 #define bOFDMTxStatus 0x2 524 525 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 526 #define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) 527 528 529 /* 2. Page8(0x800) */ 530 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 531 #define bJapanMode 0x2 532 #define bCCKTxSC 0x30 533 #define bCCKEn 0x1000000 534 #define bOFDMEn 0x2000000 535 536 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 537 #define bOFDMTxDACPhase 0x40000 538 #define bXATxAGC 0x3f 539 540 #define bAntennaSelect 0x0300 541 542 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 543 #define bXCTxAGC 0xf000 544 #define bXDTxAGC 0xf0000 545 546 #define bPAStart 0xf0000000 /* Useless now */ 547 #define bTRStart 0x00f00000 548 #define bRFStart 0x0000f000 549 #define bBBStart 0x000000f0 550 #define bBBCCKStart 0x0000000f 551 #define bPAEnd 0xf /* Reg0x814 */ 552 #define bTREnd 0x0f000000 553 #define bRFEnd 0x000f0000 554 #define bCCAMask 0x000000f0 /* T2R */ 555 #define bR2RCCAMask 0x00000f00 556 #define bHSSI_R2TDelay 0xf8000000 557 #define bHSSI_T2RDelay 0xf80000 558 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 559 #define bIGFromCCK 0x200 560 #define bAGCAddress 0x3f 561 #define bRxHPTx 0x7000 562 #define bRxHPT2R 0x38000 563 #define bRxHPCCKIni 0xc0000 564 #define bAGCTxCode 0xc00000 565 #define bAGCRxCode 0x300000 566 567 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 568 #define b3WireAddressLength 0x400 569 570 #define b3WireRFPowerDown 0x1 /* Useless now 571 * #define bHWSISelect 0x8 */ 572 #define b5GPAPEPolarity 0x40000000 573 #define b2GPAPEPolarity 0x80000000 574 #define bRFSW_TxDefaultAnt 0x3 575 #define bRFSW_TxOptionAnt 0x30 576 #define bRFSW_RxDefaultAnt 0x300 577 #define bRFSW_RxOptionAnt 0x3000 578 #define bRFSI_3WireData 0x1 579 #define bRFSI_3WireClock 0x2 580 #define bRFSI_3WireLoad 0x4 581 #define bRFSI_3WireRW 0x8 582 #define bRFSI_3Wire 0xf 583 584 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 585 586 #define bRFSI_TRSW 0x20 /* Useless now */ 587 #define bRFSI_TRSWB 0x40 588 #define bRFSI_ANTSW 0x100 589 #define bRFSI_ANTSWB 0x200 590 #define bRFSI_PAPE 0x400 591 #define bRFSI_PAPE5G 0x800 592 #define bBandSelect 0x1 593 #define bHTSIG2_GI 0x80 594 #define bHTSIG2_Smoothing 0x01 595 #define bHTSIG2_Sounding 0x02 596 #define bHTSIG2_Aggreaton 0x08 597 #define bHTSIG2_STBC 0x30 598 #define bHTSIG2_AdvCoding 0x40 599 #define bHTSIG2_NumOfHTLTF 0x300 600 #define bHTSIG2_CRC8 0x3fc 601 #define bHTSIG1_MCS 0x7f 602 #define bHTSIG1_BandWidth 0x80 603 #define bHTSIG1_HTLength 0xffff 604 #define bLSIG_Rate 0xf 605 #define bLSIG_Reserved 0x10 606 #define bLSIG_Length 0x1fffe 607 #define bLSIG_Parity 0x20 608 #define bCCKRxPhase 0x4 609 610 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 611 612 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 613 614 #define bLSSIReadBackData 0xfffff /* T65 RF */ 615 616 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 617 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 618 #define bRegulator0Standby 0x1 619 #define bRegulatorPLLStandby 0x2 620 #define bRegulator1Standby 0x4 621 #define bPLLPowerUp 0x8 622 #define bDPLLPowerUp 0x10 623 #define bDA10PowerUp 0x20 624 #define bAD7PowerUp 0x200 625 #define bDA6PowerUp 0x2000 626 #define bXtalPowerUp 0x4000 627 #define b40MDClkPowerUP 0x8000 628 #define bDA6DebugMode 0x20000 629 #define bDA6Swing 0x380000 630 631 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 632 633 #define b80MClkDelay 0x18000000 /* Useless */ 634 #define bAFEWatchDogEnable 0x20000000 635 636 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 637 #define bXtalCap23 0x3 638 #define bXtalCap92x 0x0f000000 639 #define bXtalCap 0x0f000000 640 641 #define bIntDifClkEnable 0x400 /* Useless */ 642 #define bExtSigClkEnable 0x800 643 #define bBandgapMbiasPowerUp 0x10000 644 #define bAD11SHGain 0xc0000 645 #define bAD11InputRange 0x700000 646 #define bAD11OPCurrent 0x3800000 647 #define bIPathLoopback 0x4000000 648 #define bQPathLoopback 0x8000000 649 #define bAFELoopback 0x10000000 650 #define bDA10Swing 0x7e0 651 #define bDA10Reverse 0x800 652 #define bDAClkSource 0x1000 653 #define bAD7InputRange 0x6000 654 #define bAD7Gain 0x38000 655 #define bAD7OutputCMMode 0x40000 656 #define bAD7InputCMMode 0x380000 657 #define bAD7Current 0xc00000 658 #define bRegulatorAdjust 0x7000000 659 #define bAD11PowerUpAtTx 0x1 660 #define bDA10PSAtTx 0x10 661 #define bAD11PowerUpAtRx 0x100 662 #define bDA10PSAtRx 0x1000 663 #define bCCKRxAGCFormat 0x200 664 #define bPSDFFTSamplepPoint 0xc000 665 #define bPSDAverageNum 0x3000 666 #define bIQPathControl 0xc00 667 #define bPSDFreq 0x3ff 668 #define bPSDAntennaPath 0x30 669 #define bPSDIQSwitch 0x40 670 #define bPSDRxTrigger 0x400000 671 #define bPSDTxTrigger 0x80000000 672 #define bPSDSineToneScale 0x7f000000 673 #define bPSDReport 0xffff 674 675 /* 3. Page9(0x900) */ 676 #define bOFDMTxSC 0x30000000 /* Useless */ 677 #define bCCKTxOn 0x1 678 #define bOFDMTxOn 0x2 679 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 680 #define bDebugItem 0xff /* reset debug page and LWord */ 681 #define bAntL 0x10 682 #define bAntNonHT 0x100 683 #define bAntHT1 0x1000 684 #define bAntHT2 0x10000 685 #define bAntHT1S1 0x100000 686 #define bAntNonHTS1 0x1000000 687 688 /* 4. PageA(0xA00) */ 689 #define bCCKBBMode 0x3 /* Useless */ 690 #define bCCKTxPowerSaving 0x80 691 #define bCCKRxPowerSaving 0x40 692 693 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 694 695 #define bCCKScramble 0x8 /* Useless */ 696 #define bCCKAntDiversity 0x8000 697 #define bCCKCarrierRecovery 0x4000 698 #define bCCKTxRate 0x3000 699 #define bCCKDCCancel 0x0800 700 #define bCCKISICancel 0x0400 701 #define bCCKMatchFilter 0x0200 702 #define bCCKEqualizer 0x0100 703 #define bCCKPreambleDetect 0x800000 704 #define bCCKFastFalseCCA 0x400000 705 #define bCCKChEstStart 0x300000 706 #define bCCKCCACount 0x080000 707 #define bCCKcs_lim 0x070000 708 #define bCCKBistMode 0x80000000 709 #define bCCKCCAMask 0x40000000 710 #define bCCKTxDACPhase 0x4 711 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 712 #define bCCKr_cp_mode0 0x0100 713 #define bCCKTxDCOffset 0xf0 714 #define bCCKRxDCOffset 0xf 715 #define bCCKCCAMode 0xc000 716 #define bCCKFalseCS_lim 0x3f00 717 #define bCCKCS_ratio 0xc00000 718 #define bCCKCorgBit_sel 0x300000 719 #define bCCKPD_lim 0x0f0000 720 #define bCCKNewCCA 0x80000000 721 #define bCCKRxHPofIG 0x8000 722 #define bCCKRxIG 0x7f00 723 #define bCCKLNAPolarity 0x800000 724 #define bCCKRx1stGain 0x7f0000 725 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 726 #define bCCKRxAGCSatLevel 0x1f000000 727 #define bCCKRxAGCSatCount 0xe0 728 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 729 #define bCCKFixedRxAGC 0x8000 730 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 731 #define bCCKAntennaPolarity 0x2000 732 #define bCCKTxFilterType 0x0c00 733 #define bCCKRxAGCReportType 0x0300 734 #define bCCKRxDAGCEn 0x80000000 735 #define bCCKRxDAGCPeriod 0x20000000 736 #define bCCKRxDAGCSatLevel 0x1f000000 737 #define bCCKTimingRecovery 0x800000 738 #define bCCKTxC0 0x3f0000 739 #define bCCKTxC1 0x3f000000 740 #define bCCKTxC2 0x3f 741 #define bCCKTxC3 0x3f00 742 #define bCCKTxC4 0x3f0000 743 #define bCCKTxC5 0x3f000000 744 #define bCCKTxC6 0x3f 745 #define bCCKTxC7 0x3f00 746 #define bCCKDebugPort 0xff0000 747 #define bCCKDACDebug 0x0f000000 748 #define bCCKFalseAlarmEnable 0x8000 749 #define bCCKFalseAlarmRead 0x4000 750 #define bCCKTRSSI 0x7f 751 #define bCCKRxAGCReport 0xfe 752 #define bCCKRxReport_AntSel 0x80000000 753 #define bCCKRxReport_MFOff 0x40000000 754 #define bCCKRxRxReport_SQLoss 0x20000000 755 #define bCCKRxReport_Pktloss 0x10000000 756 #define bCCKRxReport_Lockedbit 0x08000000 757 #define bCCKRxReport_RateError 0x04000000 758 #define bCCKRxReport_RxRate 0x03000000 759 #define bCCKRxFACounterLower 0xff 760 #define bCCKRxFACounterUpper 0xff000000 761 #define bCCKRxHPAGCStart 0xe000 762 #define bCCKRxHPAGCFinal 0x1c00 763 #define bCCKRxFalseAlarmEnable 0x8000 764 #define bCCKFACounterFreeze 0x4000 765 #define bCCKTxPathSel 0x10000000 766 #define bCCKDefaultRxPath 0xc000000 767 #define bCCKOptionRxPath 0x3000000 768 769 /* 5. PageC(0xC00) */ 770 #define bNumOfSTF 0x3 /* Useless */ 771 #define bShift_L 0xc0 772 #define bGI_TH 0xc 773 #define bRxPathA 0x1 774 #define bRxPathB 0x2 775 #define bRxPathC 0x4 776 #define bRxPathD 0x8 777 #define bTxPathA 0x1 778 #define bTxPathB 0x2 779 #define bTxPathC 0x4 780 #define bTxPathD 0x8 781 #define bTRSSIFreq 0x200 782 #define bADCBackoff 0x3000 783 #define bDFIRBackoff 0xc000 784 #define bTRSSILatchPhase 0x10000 785 #define bRxIDCOffset 0xff 786 #define bRxQDCOffset 0xff00 787 #define bRxDFIRMode 0x1800000 788 #define bRxDCNFType 0xe000000 789 #define bRXIQImb_A 0x3ff 790 #define bRXIQImb_B 0xfc00 791 #define bRXIQImb_C 0x3f0000 792 #define bRXIQImb_D 0xffc00000 793 #define bDC_dc_Notch 0x60000 794 #define bRxNBINotch 0x1f000000 795 #define bPD_TH 0xf 796 #define bPD_TH_Opt2 0xc000 797 #define bPWED_TH 0x700 798 #define bIfMF_Win_L 0x800 799 #define bPD_Option 0x1000 800 #define bMF_Win_L 0xe000 801 #define bBW_Search_L 0x30000 802 #define bwin_enh_L 0xc0000 803 #define bBW_TH 0x700000 804 #define bED_TH2 0x3800000 805 #define bBW_option 0x4000000 806 #define bRatio_TH 0x18000000 807 #define bWindow_L 0xe0000000 808 #define bSBD_Option 0x1 809 #define bFrame_TH 0x1c 810 #define bFS_Option 0x60 811 #define bDC_Slope_check 0x80 812 #define bFGuard_Counter_DC_L 0xe00 813 #define bFrame_Weight_Short 0x7000 814 #define bSub_Tune 0xe00000 815 #define bFrame_DC_Length 0xe000000 816 #define bSBD_start_offset 0x30000000 817 #define bFrame_TH_2 0x7 818 #define bFrame_GI2_TH 0x38 819 #define bGI2_Sync_en 0x40 820 #define bSarch_Short_Early 0x300 821 #define bSarch_Short_Late 0xc00 822 #define bSarch_GI2_Late 0x70000 823 #define bCFOAntSum 0x1 824 #define bCFOAcc 0x2 825 #define bCFOStartOffset 0xc 826 #define bCFOLookBack 0x70 827 #define bCFOSumWeight 0x80 828 #define bDAGCEnable 0x10000 829 #define bTXIQImb_A 0x3ff 830 #define bTXIQImb_B 0xfc00 831 #define bTXIQImb_C 0x3f0000 832 #define bTXIQImb_D 0xffc00000 833 #define bTxIDCOffset 0xff 834 #define bTxQDCOffset 0xff00 835 #define bTxDFIRMode 0x10000 836 #define bTxPesudoNoiseOn 0x4000000 837 #define bTxPesudoNoise_A 0xff 838 #define bTxPesudoNoise_B 0xff00 839 #define bTxPesudoNoise_C 0xff0000 840 #define bTxPesudoNoise_D 0xff000000 841 #define bCCADropOption 0x20000 842 #define bCCADropThres 0xfff00000 843 #define bEDCCA_H 0xf 844 #define bEDCCA_L 0xf0 845 #define bLambda_ED 0x300 846 #define bRxInitialGain 0x7f 847 #define bRxAntDivEn 0x80 848 #define bRxAGCAddressForLNA 0x7f00 849 #define bRxHighPowerFlow 0x8000 850 #define bRxAGCFreezeThres 0xc0000 851 #define bRxFreezeStep_AGC1 0x300000 852 #define bRxFreezeStep_AGC2 0xc00000 853 #define bRxFreezeStep_AGC3 0x3000000 854 #define bRxFreezeStep_AGC0 0xc000000 855 #define bRxRssi_Cmp_En 0x10000000 856 #define bRxQuickAGCEn 0x20000000 857 #define bRxAGCFreezeThresMode 0x40000000 858 #define bRxOverFlowCheckType 0x80000000 859 #define bRxAGCShift 0x7f 860 #define bTRSW_Tri_Only 0x80 861 #define bPowerThres 0x300 862 #define bRxAGCEn 0x1 863 #define bRxAGCTogetherEn 0x2 864 #define bRxAGCMin 0x4 865 #define bRxHP_Ini 0x7 866 #define bRxHP_TRLNA 0x70 867 #define bRxHP_RSSI 0x700 868 #define bRxHP_BBP1 0x7000 869 #define bRxHP_BBP2 0x70000 870 #define bRxHP_BBP3 0x700000 871 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 872 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 873 #define bRxSettle_TRSW 0x7 874 #define bRxSettle_LNA 0x38 875 #define bRxSettle_RSSI 0x1c0 876 #define bRxSettle_BBP 0xe00 877 #define bRxSettle_RxHP 0x7000 878 #define bRxSettle_AntSW_RSSI 0x38000 879 #define bRxSettle_AntSW 0xc0000 880 #define bRxProcessTime_DAGC 0x300000 881 #define bRxSettle_HSSI 0x400000 882 #define bRxProcessTime_BBPPW 0x800000 883 #define bRxAntennaPowerShift 0x3000000 884 #define bRSSITableSelect 0xc000000 885 #define bRxHP_Final 0x7000000 886 #define bRxHTSettle_BBP 0x7 887 #define bRxHTSettle_HSSI 0x8 888 #define bRxHTSettle_RxHP 0x70 889 #define bRxHTSettle_BBPPW 0x80 890 #define bRxHTSettle_Idle 0x300 891 #define bRxHTSettle_Reserved 0x1c00 892 #define bRxHTRxHPEn 0x8000 893 #define bRxHTAGCFreezeThres 0x30000 894 #define bRxHTAGCTogetherEn 0x40000 895 #define bRxHTAGCMin 0x80000 896 #define bRxHTAGCEn 0x100000 897 #define bRxHTDAGCEn 0x200000 898 #define bRxHTRxHP_BBP 0x1c00000 899 #define bRxHTRxHP_Final 0xe0000000 900 #define bRxPWRatioTH 0x3 901 #define bRxPWRatioEn 0x4 902 #define bRxMFHold 0x3800 903 #define bRxPD_Delay_TH1 0x38 904 #define bRxPD_Delay_TH2 0x1c0 905 #define bRxPD_DC_COUNT_MAX 0x600 906 /* #define bRxMF_Hold 0x3800 */ 907 #define bRxPD_Delay_TH 0x8000 908 #define bRxProcess_Delay 0xf0000 909 #define bRxSearchrange_GI2_Early 0x700000 910 #define bRxFrame_Guard_Counter_L 0x3800000 911 #define bRxSGI_Guard_L 0xc000000 912 #define bRxSGI_Search_L 0x30000000 913 #define bRxSGI_TH 0xc0000000 914 #define bDFSCnt0 0xff 915 #define bDFSCnt1 0xff00 916 #define bDFSFlag 0xf0000 917 #define bMFWeightSum 0x300000 918 #define bMinIdxTH 0x7f000000 919 #define bDAFormat 0x40000 920 #define bTxChEmuEnable 0x01000000 921 #define bTRSWIsolation_A 0x7f 922 #define bTRSWIsolation_B 0x7f00 923 #define bTRSWIsolation_C 0x7f0000 924 #define bTRSWIsolation_D 0x7f000000 925 #define bExtLNAGain 0x7c00 926 927 /* 6. PageE(0xE00) */ 928 #define bSTBCEn 0x4 /* Useless */ 929 #define bAntennaMapping 0x10 930 #define bNss 0x20 931 #define bCFOAntSumD 0x200 932 #define bPHYCounterReset 0x8000000 933 #define bCFOReportGet 0x4000000 934 #define bOFDMContinueTx 0x10000000 935 #define bOFDMSingleCarrier 0x20000000 936 #define bOFDMSingleTone 0x40000000 937 /* #define bRxPath1 0x01 */ 938 /* #define bRxPath2 0x02 */ 939 /* #define bRxPath3 0x04 */ 940 /* #define bRxPath4 0x08 */ 941 /* #define bTxPath1 0x10 */ 942 /* #define bTxPath2 0x20 */ 943 #define bHTDetect 0x100 944 #define bCFOEn 0x10000 945 #define bCFOValue 0xfff00000 946 #define bSigTone_Re 0x3f 947 #define bSigTone_Im 0x7f00 948 #define bCounter_CCA 0xffff 949 #define bCounter_ParityFail 0xffff0000 950 #define bCounter_RateIllegal 0xffff 951 #define bCounter_CRC8Fail 0xffff0000 952 #define bCounter_MCSNoSupport 0xffff 953 #define bCounter_FastSync 0xffff 954 #define bShortCFO 0xfff 955 #define bShortCFOTLength 12 /* total */ 956 #define bShortCFOFLength 11 /* fraction */ 957 #define bLongCFO 0x7ff 958 #define bLongCFOTLength 11 959 #define bLongCFOFLength 11 960 #define bTailCFO 0x1fff 961 #define bTailCFOTLength 13 962 #define bTailCFOFLength 12 963 #define bmax_en_pwdB 0xffff 964 #define bCC_power_dB 0xffff0000 965 #define bnoise_pwdB 0xffff 966 #define bPowerMeasTLength 10 967 #define bPowerMeasFLength 3 968 #define bRx_HT_BW 0x1 969 #define bRxSC 0x6 970 #define bRx_HT 0x8 971 #define bNB_intf_det_on 0x1 972 #define bIntf_win_len_cfg 0x30 973 #define bNB_Intf_TH_cfg 0x1c0 974 #define bRFGain 0x3f 975 #define bTableSel 0x40 976 #define bTRSW 0x80 977 #define bRxSNR_A 0xff 978 #define bRxSNR_B 0xff00 979 #define bRxSNR_C 0xff0000 980 #define bRxSNR_D 0xff000000 981 #define bSNREVMTLength 8 982 #define bSNREVMFLength 1 983 #define bCSI1st 0xff 984 #define bCSI2nd 0xff00 985 #define bRxEVM1st 0xff0000 986 #define bRxEVM2nd 0xff000000 987 #define bSIGEVM 0xff 988 #define bPWDB 0xff00 989 #define bSGIEN 0x10000 990 991 #define bSFactorQAM1 0xf /* Useless */ 992 #define bSFactorQAM2 0xf0 993 #define bSFactorQAM3 0xf00 994 #define bSFactorQAM4 0xf000 995 #define bSFactorQAM5 0xf0000 996 #define bSFactorQAM6 0xf0000 997 #define bSFactorQAM7 0xf00000 998 #define bSFactorQAM8 0xf000000 999 #define bSFactorQAM9 0xf0000000 1000 #define bCSIScheme 0x100000 1001 1002 #define bNoiseLvlTopSet 0x3 /* Useless */ 1003 #define bChSmooth 0x4 1004 #define bChSmoothCfg1 0x38 1005 #define bChSmoothCfg2 0x1c0 1006 #define bChSmoothCfg3 0xe00 1007 #define bChSmoothCfg4 0x7000 1008 #define bMRCMode 0x800000 1009 #define bTHEVMCfg 0x7000000 1010 1011 #define bLoopFitType 0x1 /* Useless */ 1012 #define bUpdCFO 0x40 1013 #define bUpdCFOOffData 0x80 1014 #define bAdvUpdCFO 0x100 1015 #define bAdvTimeCtrl 0x800 1016 #define bUpdClko 0x1000 1017 #define bFC 0x6000 1018 #define bTrackingMode 0x8000 1019 #define bPhCmpEnable 0x10000 1020 #define bUpdClkoLTF 0x20000 1021 #define bComChCFO 0x40000 1022 #define bCSIEstiMode 0x80000 1023 #define bAdvUpdEqz 0x100000 1024 #define bUChCfg 0x7000000 1025 #define bUpdEqz 0x8000000 1026 1027 /* Rx Pseduo noise */ 1028 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1029 #define bRxPesudoNoise_A 0xff 1030 #define bRxPesudoNoise_B 0xff00 1031 #define bRxPesudoNoise_C 0xff0000 1032 #define bRxPesudoNoise_D 0xff000000 1033 #define bPesudoNoiseState_A 0xffff 1034 #define bPesudoNoiseState_B 0xffff0000 1035 #define bPesudoNoiseState_C 0xffff 1036 #define bPesudoNoiseState_D 0xffff0000 1037 1038 /* 7. RF Register 1039 * Zebra1 */ 1040 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1041 #define bZebra1_TRxControl 0xc00 1042 #define bZebra1_TRxGainSetting 0x07f 1043 #define bZebra1_RxCorner 0xc00 1044 #define bZebra1_TxChargePump 0x38 1045 #define bZebra1_RxChargePump 0x7 1046 #define bZebra1_ChannelNum 0xf80 1047 #define bZebra1_TxLPFBW 0x400 1048 #define bZebra1_RxLPFBW 0x600 1049 1050 /* Zebra4 */ 1051 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1052 #define bRTL8256RegModeCtrl0 0x40 1053 #define bRTL8256_TxLPFBW 0x18 1054 #define bRTL8256_RxLPFBW 0x600 1055 1056 /* RTL8258 */ 1057 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1058 #define bRTL8258_RxLPFBW 0xc00 1059 #define bRTL8258_RSSILPFBW 0xc0 1060 1061 1062 /* 1063 * Other Definition 1064 * */ 1065 1066 /* byte endable for sb_write */ 1067 #define bByte0 0x1 /* Useless */ 1068 #define bByte1 0x2 1069 #define bByte2 0x4 1070 #define bByte3 0x8 1071 #define bWord0 0x3 1072 #define bWord1 0xc 1073 #define bDWord 0xf 1074 1075 /* for PutRegsetting & GetRegSetting BitMask */ 1076 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1077 #define bMaskByte1 0xff00 1078 #define bMaskByte2 0xff0000 1079 #define bMaskByte3 0xff000000 1080 #define bMaskHWord 0xffff0000 1081 #define bMaskLWord 0x0000ffff 1082 #define bMaskDWord 0xffffffff 1083 #define bMaskH3Bytes 0xffffff00 1084 #define bMask12Bits 0xfff 1085 #define bMaskH4Bits 0xf0000000 1086 #define bMaskOFDM_D 0xffc00000 1087 #define bMaskCCK 0x3f3f3f3f 1088 1089 /* for PutRFRegsetting & GetRFRegSetting BitMask 1090 * #define bMask12Bits 0xfffff */ /* RF Reg mask bits 1091 * #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ 1092 #define bRFRegOffsetMask 0xfffff 1093 1094 #define bEnable 0x1 /* Useless */ 1095 #define bDisable 0x0 1096 1097 #define LeftAntenna 0x0 /* Useless */ 1098 #define RightAntenna 0x1 1099 1100 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1101 #define tUpdateRxCounter 100 /* 100ms */ 1102 1103 #define rateCCK 0 /* Useless */ 1104 #define rateOFDM 1 1105 #define rateHT 2 1106 1107 /* define Register-End */ 1108 #define bPMAC_End 0x1ff /* Useless */ 1109 #define bFPGAPHY0_End 0x8ff 1110 #define bFPGAPHY1_End 0x9ff 1111 #define bCCKPHY0_End 0xaff 1112 #define bOFDMPHY0_End 0xcff 1113 #define bOFDMPHY1_End 0xdff 1114 1115 /* define max debug item in each debug page 1116 * #define bMaxItem_FPGA_PHY0 0x9 1117 * #define bMaxItem_FPGA_PHY1 0x3 1118 * #define bMaxItem_PHY_11B 0x16 1119 * #define bMaxItem_OFDM_PHY0 0x29 1120 * #define bMaxItem_OFDM_PHY1 0x0 */ 1121 1122 #define bPMACControl 0x0 /* Useless */ 1123 #define bWMACControl 0x1 1124 #define bWNICControl 0x2 1125 1126 #define PathA 0x0 /* Useless */ 1127 #define PathB 0x1 1128 #define PathC 0x2 1129 #define PathD 0x3 1130 1131 1132 /* RSSI Dump Message */ 1133 #define rA_RSSIDump_92E 0xcb0 1134 #define rB_RSSIDump_92E 0xcb1 1135 #define rS1_RXevmDump_92E 0xcb2 1136 #define rS2_RXevmDump_92E 0xcb3 1137 #define rA_RXsnrDump_92E 0xcb4 1138 #define rB_RXsnrDump_92E 0xcb5 1139 #define rA_CfoShortDump_92E 0xcb6 1140 #define rB_CfoShortDump_92E 0xcb8 1141 #define rA_CfoLongDump_92E 0xcba 1142 #define rB_CfoLongDump_92E 0xcbc 1143 1144 /*--------------------------Define Parameters-------------------------------*/ 1145 1146 1147 #endif /* __INC_HAL8188EPHYREG_H */ 1148