1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __INC_HAL8188EPHYCFG_H__ 16 #define __INC_HAL8188EPHYCFG_H__ 17 18 19 /*--------------------------Define Parameters-------------------------------*/ 20 #define LOOP_LIMIT 5 21 #define MAX_STALL_TIME 50 /* us */ 22 #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 23 #define MAX_TXPWR_IDX_NMODE_92S 63 24 #define Reset_Cnt_Limit 3 25 26 #ifdef CONFIG_PCI_HCI 27 #define MAX_AGGR_NUM 0x0B 28 #else 29 #define MAX_AGGR_NUM 0x07 30 #endif /* CONFIG_PCI_HCI */ 31 32 33 /*--------------------------Define Parameters-------------------------------*/ 34 35 36 /*------------------------------Define structure----------------------------*/ 37 38 #define MAX_TX_COUNT_8188E 1 39 40 /* BB/RF related */ 41 42 43 /*------------------------------Define structure----------------------------*/ 44 45 46 /*------------------------Export global variable----------------------------*/ 47 /*------------------------Export global variable----------------------------*/ 48 49 50 /*------------------------Export Marco Definition---------------------------*/ 51 /*------------------------Export Marco Definition---------------------------*/ 52 53 54 /*--------------------------Exported Function prototype---------------------*/ 55 /* 56 * BB and RF register read/write 57 * */ 58 u32 PHY_QueryBBReg8188E(IN PADAPTER Adapter, 59 IN u32 RegAddr, 60 IN u32 BitMask); 61 void PHY_SetBBReg8188E(IN PADAPTER Adapter, 62 IN u32 RegAddr, 63 IN u32 BitMask, 64 IN u32 Data); 65 u32 PHY_QueryRFReg8188E(IN PADAPTER Adapter, 66 IN enum rf_path eRFPath, 67 IN u32 RegAddr, 68 IN u32 BitMask); 69 void PHY_SetRFReg8188E(IN PADAPTER Adapter, 70 IN enum rf_path eRFPath, 71 IN u32 RegAddr, 72 IN u32 BitMask, 73 IN u32 Data); 74 75 /* 76 * Initialization related function 77 */ 78 /* MAC/BB/RF HAL config */ 79 int PHY_MACConfig8188E(IN PADAPTER Adapter); 80 int PHY_BBConfig8188E(IN PADAPTER Adapter); 81 int PHY_RFConfig8188E(IN PADAPTER Adapter); 82 83 /* RF config */ 84 int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, enum rf_path eRFPath); 85 86 /* 87 * RF Power setting 88 */ 89 /* extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, 90 * IN RT_RF_POWER_STATE eRFPowerState); */ 91 92 /* 93 * BB TX Power R/W 94 * */ 95 void PHY_GetTxPowerLevel8188E(IN PADAPTER Adapter, 96 OUT s32 *powerlevel); 97 void PHY_SetTxPowerLevel8188E(IN PADAPTER Adapter, 98 IN u8 channel); 99 BOOLEAN PHY_UpdateTxPowerDbm8188E(IN PADAPTER Adapter, 100 IN int powerInDbm); 101 102 VOID 103 PHY_SetTxPowerIndex_8188E( 104 IN PADAPTER Adapter, 105 IN u32 PowerIndex, 106 IN enum rf_path RFPath, 107 IN u8 Rate 108 ); 109 110 u8 111 PHY_GetTxPowerIndex_8188E( 112 IN PADAPTER pAdapter, 113 IN enum rf_path RFPath, 114 IN u8 Rate, 115 IN u8 BandWidth, 116 IN u8 Channel, 117 struct txpwr_idx_comp *tic 118 ); 119 120 /* 121 * Switch bandwidth for 8192S 122 */ 123 /* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */ 124 void PHY_SetBWMode8188E(IN PADAPTER pAdapter, 125 IN enum channel_width ChnlWidth, 126 IN unsigned char Offset); 127 128 /* 129 * Set FW CMD IO for 8192S. 130 */ 131 /* extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, 132 * IN IO_TYPE IOType); */ 133 134 /* 135 * Set A2 entry to fw for 8192S 136 * */ 137 extern void FillA2Entry8192C(IN PADAPTER Adapter, 138 IN u8 index, 139 IN u8 *val); 140 141 142 /* 143 * channel switch related funciton 144 */ 145 /* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */ 146 void PHY_SwChnl8188E(IN PADAPTER pAdapter, 147 IN u8 channel); 148 149 VOID 150 PHY_SetSwChnlBWMode8188E( 151 IN PADAPTER Adapter, 152 IN u8 channel, 153 IN enum channel_width Bandwidth, 154 IN u8 Offset40, 155 IN u8 Offset80 156 ); 157 158 VOID 159 PHY_SetRFEReg_8188E( 160 IN PADAPTER Adapter 161 ); 162 /* 163 * BB/MAC/RF other monitor API 164 * */ 165 VOID phy_set_rf_path_switch_8188e(IN PADAPTER pAdapter, IN bool bMain); 166 167 extern VOID 168 PHY_SwitchEphyParameter( 169 IN PADAPTER Adapter 170 ); 171 172 extern VOID 173 PHY_EnableHostClkReq( 174 IN PADAPTER Adapter 175 ); 176 177 BOOLEAN 178 SetAntennaConfig92C( 179 IN PADAPTER Adapter, 180 IN u8 DefaultAnt 181 ); 182 183 /*--------------------------Exported Function prototype---------------------*/ 184 185 /* 186 * Initialization related function 187 * 188 * MAC/BB/RF HAL config */ 189 /* extern s32 PHY_MACConfig8723(PADAPTER padapter); 190 * s32 PHY_BBConfig8723(PADAPTER padapter); 191 * s32 PHY_RFConfig8723(PADAPTER padapter); */ 192 193 194 195 /* ****************************************************************** 196 * Note: If SIC_ENABLE under PCIE, because of the slow operation 197 * you should 198 * 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows 199 * 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed. 200 * */ 201 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) 202 #define SIC_ENABLE 1 203 #define SIC_HW_SUPPORT 1 204 #else 205 #define SIC_ENABLE 0 206 #define SIC_HW_SUPPORT 0 207 #endif 208 /* ****************************************************************** */ 209 210 211 #define SIC_MAX_POLL_CNT 5 212 213 #if (SIC_HW_SUPPORT == 1) 214 #define SIC_CMD_READY 0 215 #define SIC_CMD_PREWRITE 0x1 216 #if (RTL8188E_SUPPORT == 1) 217 #define SIC_CMD_WRITE 0x40 218 #define SIC_CMD_PREREAD 0x2 219 #define SIC_CMD_READ 0x80 220 #define SIC_CMD_INIT 0xf0 221 #define SIC_INIT_VAL 0xff 222 223 #define SIC_INIT_REG 0x1b7 224 #define SIC_CMD_REG 0x1EB /* 1byte */ 225 #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */ 226 #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */ 227 #else 228 #define SIC_CMD_WRITE 0x11 229 #define SIC_CMD_PREREAD 0x2 230 #define SIC_CMD_READ 0x12 231 #define SIC_CMD_INIT 0x1f 232 #define SIC_INIT_VAL 0xff 233 234 #define SIC_INIT_REG 0x1b7 235 #define SIC_CMD_REG 0x1b6 /* 1byte */ 236 #define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */ 237 #define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */ 238 #endif 239 #else 240 #define SIC_CMD_READY 0 241 #define SIC_CMD_WRITE 1 242 #define SIC_CMD_READ 2 243 244 #if (RTL8188E_SUPPORT == 1) 245 #define SIC_CMD_REG 0x1EB /* 1byte */ 246 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 247 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 248 #else 249 #define SIC_CMD_REG 0x1b8 /* 1byte */ 250 #define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */ 251 #define SIC_DATA_REG 0x1bc /* 1bc~1bf */ 252 #endif 253 #endif 254 255 #if (SIC_ENABLE == 1) 256 VOID SIC_Init(IN PADAPTER Adapter); 257 #endif 258 259 260 #endif /* __INC_HAL8192CPHYCFG_H */ 261