1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8188F
46 #include <rtl8188f_hal.h>
47 #endif
48 #endif /* !RTW_HALMAC */
49
50
MgntQuery_NssTxRate(u16 Rate)51 u8 MgntQuery_NssTxRate(u16 Rate)
52 {
53 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
54
55 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
56 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
57 NssNum = RF_2TX;
58 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
59 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
60 NssNum = RF_3TX;
61 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
62 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
63 NssNum = RF_4TX;
64 else
65 NssNum = RF_1TX;
66
67 return NssNum;
68 }
69
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)70 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
71 {
72 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
73 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
74 u8 ChannelToSw = pMptCtx->MptChannelToSw;
75 ULONG ulRateIdx = pMptCtx->mpt_rate_index;
76 ULONG ulbandwidth = pMptCtx->MptBandWidth;
77
78 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
79 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
80 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
81 pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
82 pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
83
84 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
85 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
86 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
87 } else {
88 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
89 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
90 }
91 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
92 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
98 }
99 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
100 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
101 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
102 }
103 }
104
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)105 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
106 {
107 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
108 struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv);
109
110
111 if (!netif_running(padapter->pnetdev)) {
112 return _FAIL;
113 }
114
115 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
116 return _FAIL;
117 }
118 if (enable)
119 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
120 else
121 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
122
123 return _SUCCESS;
124 }
125
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)126 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
127 {
128 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
129 struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv);
130
131
132 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
133 }
134
135
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)136 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
137 {
138 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
139 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
140 u8 i;
141 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
142 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
143 u1Byte u1Channel = pHalData->current_channel;
144 ULONG ulRateIdx = pMptCtx->mpt_rate_index;
145 u1Byte DataRate = 0xFF;
146
147 /* Do not modify CCK TX filter parameters for 8822B*/
148 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
149 return;
150
151 DataRate = mpt_to_mgnt_rate(ulRateIdx);
152
153 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
154 pHalData->bCCKinCH14 = TRUE;
155 else
156 pHalData->bCCKinCH14 = FALSE;
157
158 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
159 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
160 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
161 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
162 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
163
164 } else {
165 /* Normal setting for 8703B, just recover to the default setting. */
166 /* This hardcore values reference from the parameter which BB team gave. */
167 for (i = 0 ; i < 2 ; ++i)
168 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
169
170 }
171 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
172 /* 2.4G CCK TX DFIR */
173 /* 2016.01.20 Suggest from RS BB mingzhi*/
174 if ((u1Channel == 14)) {
175 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
176 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
177 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
178 } else {
179 for (i = 0 ; i < 3 ; ++i) {
180 phy_set_bb_reg(Adapter,
181 pHalData->RegForRecover[i].offset,
182 bMaskDWord,
183 pHalData->RegForRecover[i].value);
184 }
185 }
186 } else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
187 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
188 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
189 CCKSwingIndex = 20; /* default index */
190
191 if (!pHalData->bCCKinCH14) {
192 /* Readback the current bb cck swing value and compare with the table to */
193 /* get the current swing index */
194 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
195 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
196 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
197 CCKSwingIndex = i;
198 break;
199 }
200 }
201 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
202 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
203 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
204 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
205 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
206 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
207 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
208 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
209 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
210 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
211 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
212 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
213 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
214 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
215 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
216 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
217 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
218 } else {
219 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
220 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
221 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
222 CCKSwingIndex = i;
223 break;
224 }
225 }
226 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
227 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
228 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
229 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
230 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
231 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
232 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
233 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
234 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
235 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
236 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
237 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
238 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
239 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
240 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
241 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
242 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
243 }
244 } else {
245
246 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
247 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
248
249 if (!pHalData->bCCKinCH14) {
250 /* Readback the current bb cck swing value and compare with the table to */
251 /* get the current swing index */
252 for (i = 0; i < CCK_TABLE_SIZE; i++) {
253 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
254 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
255 CCKSwingIndex = i;
256 break;
257 }
258 }
259
260 /*Write 0xa22 0xa23*/
261 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
262 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
263
264
265 /*Write 0xa24 ~ 0xa27*/
266 TempVal2 = 0;
267 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
268 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
269 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
270 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
271
272 /*Write 0xa28 0xa29*/
273 TempVal3 = 0;
274 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
275 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
276 } else {
277 for (i = 0; i < CCK_TABLE_SIZE; i++) {
278 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
279 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
280 CCKSwingIndex = i;
281 break;
282 }
283 }
284
285 /*Write 0xa22 0xa23*/
286 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
287 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
288
289 /*Write 0xa24 ~ 0xa27*/
290 TempVal2 = 0;
291 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
292 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
293 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
294 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
295
296 /*Write 0xa28 0xa29*/
297 TempVal3 = 0;
298 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
299 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
300 }
301
302 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
303 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
304 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
305 }
306
307 }
308
hal_mpt_SetChannel(PADAPTER pAdapter)309 void hal_mpt_SetChannel(PADAPTER pAdapter)
310 {
311 enum rf_path eRFPath;
312 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
313 struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv);
314 struct mp_priv *pmp = &pAdapter->mppriv;
315 u8 channel = pmp->channel;
316 u8 bandwidth = pmp->bandwidth;
317
318 hal_mpt_SwitchRfSetting(pAdapter);
319
320 pHalData->bSwChnl = _TRUE;
321 pHalData->bSetChnlBW = _TRUE;
322 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
323
324 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
325
326 }
327
328 /*
329 * Notice
330 * Switch bandwitdth may change center frequency(channel)
331 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)332 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
333 {
334 struct mp_priv *pmp = &pAdapter->mppriv;
335 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
336
337 u8 channel = pmp->channel;
338 u8 bandwidth = pmp->bandwidth;
339
340 pHalData->bSwChnl = _TRUE;
341 pHalData->bSetChnlBW = _TRUE;
342 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
343
344 hal_mpt_SwitchRfSetting(pAdapter);
345 }
346
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)347 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
348 {
349 switch (Rate) {
350 case MPT_CCK: {
351 u4Byte TxAGC = 0, pwr = 0;
352 u1Byte rf;
353
354 pwr = pTxPower[RF_PATH_A];
355 if (pwr < 0x3f) {
356 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
357 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
358 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
359 }
360 pwr = pTxPower[RF_PATH_B];
361 if (pwr < 0x3f) {
362 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
363 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
364 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
365 }
366 }
367 break;
368
369 case MPT_OFDM_AND_HT: {
370 u4Byte TxAGC = 0;
371 u1Byte pwr = 0, rf;
372
373 pwr = pTxPower[0];
374 if (pwr < 0x3f) {
375 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
376 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
377 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
379 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
380 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
381 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
382 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
383 }
384 TxAGC = 0;
385 pwr = pTxPower[1];
386 if (pwr < 0x3f) {
387 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
388 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
389 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
390 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
391 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
392 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
393 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
394 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
395 }
396 }
397 break;
398
399 default:
400 break;
401 }
402 RTW_INFO("<===mpt_SetTxPower_Old()\n");
403 }
404
405 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,pu1Byte pTxPower)406 mpt_SetTxPower(
407 PADAPTER pAdapter,
408 MPT_TXPWR_DEF Rate,
409 pu1Byte pTxPower
410 )
411 {
412 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
413
414 u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
415 u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B;
416
417 if (IS_HARDWARE_TYPE_8814A(pAdapter))
418 EndPath = RF_PATH_D;
419 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
420 EndPath = RF_PATH_A;
421
422 switch (Rate) {
423 case MPT_CCK: {
424 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
425
426 for (path = StartPath; path <= EndPath; path++)
427 for (i = 0; i < sizeof(rate); ++i)
428 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
429 }
430 break;
431 case MPT_OFDM: {
432 u1Byte rate[] = {
433 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
434 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
435 };
436
437 for (path = StartPath; path <= EndPath; path++)
438 for (i = 0; i < sizeof(rate); ++i)
439 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
440 }
441 break;
442 case MPT_HT: {
443 u1Byte rate[] = {
444 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
445 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
446 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
447 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
448 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
449 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
450 MGN_MCS30, MGN_MCS31,
451 };
452 if (pHalData->rf_type == RF_3T3R)
453 MaxRate = MGN_MCS23;
454 else if (pHalData->rf_type == RF_2T2R)
455 MaxRate = MGN_MCS15;
456 else
457 MaxRate = MGN_MCS7;
458 for (path = StartPath; path <= EndPath; path++) {
459 for (i = 0; i < sizeof(rate); ++i) {
460 if (rate[i] > MaxRate)
461 break;
462 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
463 }
464 }
465 }
466 break;
467 case MPT_VHT: {
468 u1Byte rate[] = {
469 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
470 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
471 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
472 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
473 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
474 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
475 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
476 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
477 };
478 if (pHalData->rf_type == RF_3T3R)
479 MaxRate = MGN_VHT3SS_MCS9;
480 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
481 MaxRate = MGN_VHT2SS_MCS9;
482 else
483 MaxRate = MGN_VHT1SS_MCS9;
484
485 for (path = StartPath; path <= EndPath; path++) {
486 for (i = 0; i < sizeof(rate); ++i) {
487 if (rate[i] > MaxRate)
488 break;
489 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
490 }
491 }
492 }
493 break;
494 default:
495 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
496 break;
497 }
498 }
499
hal_mpt_SetTxPower(PADAPTER pAdapter)500 void hal_mpt_SetTxPower(PADAPTER pAdapter)
501 {
502 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
503 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
504 struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
505
506 if (pHalData->rf_chip < RF_CHIP_MAX) {
507 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
508 IS_HARDWARE_TYPE_8723B(pAdapter) ||
509 IS_HARDWARE_TYPE_8192E(pAdapter) ||
510 IS_HARDWARE_TYPE_8703B(pAdapter) ||
511 IS_HARDWARE_TYPE_8188F(pAdapter)) {
512 u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
513
514 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
515
516 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
517 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
518
519 } else {
520 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
521 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
522 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
523 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
524 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
525
526 }
527 } else
528 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
529
530 odm_clear_txpowertracking_state(pDM_Odm);
531 }
532
hal_mpt_SetDataRate(PADAPTER pAdapter)533 void hal_mpt_SetDataRate(PADAPTER pAdapter)
534 {
535 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
536 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
537 u32 DataRate;
538
539 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
540
541 hal_mpt_SwitchRfSetting(pAdapter);
542
543 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
544 #ifdef CONFIG_RTL8723B
545 if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
546 if (IS_CCK_RATE(DataRate)) {
547 if (pMptCtx->mpt_rf_path == RF_PATH_A)
548 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
549 else
550 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
551 } else {
552 if (pMptCtx->mpt_rf_path == RF_PATH_A)
553 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
554 else
555 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
556 }
557 }
558
559 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
560 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
561 if (pMptCtx->mpt_rf_path == RF_PATH_A)
562 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
563 else
564 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
565 }
566 #endif
567 }
568
569 #define RF_PATH_AB 22
570
571 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)572 VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
573 {
574 u1Byte Path = 0;
575 u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
576
577 for (Path; Path <= RF_PATH_D; Path++) {
578 switch (Path) {
579 case RF_PATH_B:
580 IGReg = rB_IGI_Jaguar;
581 break;
582 case RF_PATH_C:
583 IGReg = rC_IGI_Jaguar2;
584 break;
585 case RF_PATH_D:
586 IGReg = rD_IGI_Jaguar2;
587 break;
588 default:
589 IGReg = rA_IGI_Jaguar;
590 break;
591 }
592
593 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
594 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
595 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
596 }
597 }
598
mpt_SetRFPath_8814A(PADAPTER pAdapter)599 VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
600 {
601
602 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
603 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
604 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
605 R_ANTENNA_SELECT_CCK *p_cck_txrx;
606 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
607 u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
608 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
609 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
610
611 u32 ulAntennaTx = pHalData->antenna_tx_path;
612 u32 ulAntennaRx = pHalData->AntennaRxPath;
613 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
614
615 if (NssforRate == RF_3TX) {
616 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
617
618 switch (ulAntennaTx) {
619 case ANTENNA_BCD:
620 pMptCtx->mpt_rf_path = RF_PATH_BCD;
621 /*pHalData->ValidTxPath = 0x0e;*/
622 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
623 break;
624
625 case ANTENNA_ABC:
626 default:
627 pMptCtx->mpt_rf_path = RF_PATH_ABC;
628 /*pHalData->ValidTxPath = 0x0d;*/
629 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
630 break;
631 }
632
633 } else { /*/if(NssforRate == RF_1TX)*/
634 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
635 switch (ulAntennaTx) {
636 case ANTENNA_BCD:
637 pMptCtx->mpt_rf_path = RF_PATH_BCD;
638 /*pHalData->ValidTxPath = 0x0e;*/
639 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
640 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
641 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
642 break;
643
644 case ANTENNA_BC:
645 pMptCtx->mpt_rf_path = RF_PATH_BC;
646 /*pHalData->ValidTxPath = 0x06;*/
647 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
648 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
649 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
650 break;
651 case ANTENNA_B:
652 pMptCtx->mpt_rf_path = RF_PATH_B;
653 /*pHalData->ValidTxPath = 0x02;*/
654 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
655 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
656 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
657 break;
658
659 case ANTENNA_C:
660 pMptCtx->mpt_rf_path = RF_PATH_C;
661 /*pHalData->ValidTxPath = 0x04;*/
662 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
663 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
664 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
665 break;
666
667 case ANTENNA_D:
668 pMptCtx->mpt_rf_path = RF_PATH_D;
669 /*pHalData->ValidTxPath = 0x08;*/
670 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
671 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
672 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
673 break;
674
675 case ANTENNA_A:
676 default:
677 pMptCtx->mpt_rf_path = RF_PATH_A;
678 /*pHalData->ValidTxPath = 0x01;*/
679 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
680 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
681 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
682 break;
683 }
684 }
685
686 switch (ulAntennaRx) {
687 case ANTENNA_A:
688 /*pHalData->ValidRxPath = 0x01;*/
689 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
690 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
691 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
692 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
693 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
694 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
695 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
696 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
697 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
698 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
699 /*/ CCA related PD_delay_th*/
700 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
701 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
702 break;
703
704 case ANTENNA_B:
705 /*pHalData->ValidRxPath = 0x02;*/
706 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
707 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
708 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
709 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
710 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
711 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
712 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
713 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
714 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
715 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
716 /*/ CCA related PD_delay_th*/
717 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
718 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
719 break;
720
721 case ANTENNA_C:
722 /*pHalData->ValidRxPath = 0x04;*/
723 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
724 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
725 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
726 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
727 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
728 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
729 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
730 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
731 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
732 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
733 /*/ CCA related PD_delay_th*/
734 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
735 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
736 break;
737
738 case ANTENNA_D:
739 /*pHalData->ValidRxPath = 0x08;*/
740 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
741 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
742 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
743 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
744 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
745 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
746 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
747 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
748 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
749 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
750 /*/ CCA related PD_delay_th*/
751 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
752 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
753 break;
754
755 case ANTENNA_BC:
756 /*pHalData->ValidRxPath = 0x06;*/
757 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
758 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
759 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
760 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
761 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
762 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
763 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
764 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
765 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
766 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
767 /*/ CCA related PD_delay_th*/
768 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
769 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
770 break;
771
772 case ANTENNA_CD:
773 /*pHalData->ValidRxPath = 0x0C;*/
774 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
775 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
776 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
777 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
778 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
779 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
780 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
781 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
782 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
783 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
784 /*/ CCA related PD_delay_th*/
785 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
786 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
787 break;
788
789 case ANTENNA_BCD:
790 /*pHalData->ValidRxPath = 0x0e;*/
791 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
792 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
793 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
794 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
795 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
796 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
797 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
798 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
799 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
800 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
801 /*/ CCA related PD_delay_th*/
802 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
803 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
804 break;
805
806 case ANTENNA_ABCD:
807 /*pHalData->ValidRxPath = 0x0f;*/
808 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
809 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
810 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
811 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
812 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
813 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
814 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
815 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
816 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
817 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
818 /*/ CCA related PD_delay_th*/
819 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
820 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
821 break;
822
823 default:
824 break;
825 }
826
827 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
828
829 mpt_ToggleIG_8814A(pAdapter);
830 }
831 #endif /* CONFIG_RTL8814A */
832 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
833 VOID
mpt_SetSingleTone_8814A(IN PADAPTER pAdapter,IN BOOLEAN bSingleTone,IN BOOLEAN bEnPMacTx)834 mpt_SetSingleTone_8814A(
835 IN PADAPTER pAdapter,
836 IN BOOLEAN bSingleTone,
837 IN BOOLEAN bEnPMacTx)
838 {
839
840 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
841 u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_A;
842 static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
843
844 if (bSingleTone) {
845 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
846 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
847 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
848 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
849
850 switch (pMptCtx->mpt_rf_path) {
851 case RF_PATH_A:
852 case RF_PATH_B:
853 case RF_PATH_C:
854 case RF_PATH_D:
855 StartPath = pMptCtx->mpt_rf_path;
856 EndPath = pMptCtx->mpt_rf_path;
857 break;
858 case RF_PATH_AB:
859 EndPath = RF_PATH_B;
860 break;
861 case RF_PATH_BC:
862 StartPath = RF_PATH_B;
863 EndPath = RF_PATH_C;
864 break;
865 case RF_PATH_ABC:
866 EndPath = RF_PATH_C;
867 break;
868 case RF_PATH_BCD:
869 StartPath = RF_PATH_B;
870 EndPath = RF_PATH_D;
871 break;
872 case RF_PATH_ABCD:
873 EndPath = RF_PATH_D;
874 break;
875 }
876
877 if (bEnPMacTx == FALSE) {
878 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
879 issue_nulldata(pAdapter, NULL, 1, 3, 500);
880 }
881
882 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
883
884 for (StartPath; StartPath <= EndPath; StartPath++) {
885 phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
886 phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
887
888 phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
889 }
890
891 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
892 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
893 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
894 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
895 } else {
896 switch (pMptCtx->mpt_rf_path) {
897 case RF_PATH_A:
898 case RF_PATH_B:
899 case RF_PATH_C:
900 case RF_PATH_D:
901 StartPath = pMptCtx->mpt_rf_path;
902 EndPath = pMptCtx->mpt_rf_path;
903 break;
904 case RF_PATH_AB:
905 EndPath = RF_PATH_B;
906 break;
907 case RF_PATH_BC:
908 StartPath = RF_PATH_B;
909 EndPath = RF_PATH_C;
910 break;
911 case RF_PATH_ABC:
912 EndPath = RF_PATH_C;
913 break;
914 case RF_PATH_BCD:
915 StartPath = RF_PATH_B;
916 EndPath = RF_PATH_D;
917 break;
918 case RF_PATH_ABCD:
919 EndPath = RF_PATH_D;
920 break;
921 }
922 for (StartPath; StartPath <= EndPath; StartPath++)
923 phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
924
925 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
926
927 if (bEnPMacTx == FALSE)
928 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
929
930 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
931 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
932 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
933 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
934 }
935 }
936
937 #endif
938
939 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)940 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
941 {
942 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
943 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
944 struct mp_priv *pmp = &pAdapter->mppriv;
945 u8 channel = pmp->channel;
946 u8 bandwidth = pmp->bandwidth;
947 u8 eLNA_2g = pHalData->ExternalLNA_2G;
948 u32 ulAntennaTx, ulAntennaRx;
949
950 ulAntennaTx = pHalData->antenna_tx_path;
951 ulAntennaRx = pHalData->AntennaRxPath;
952
953 switch (ulAntennaTx) {
954 case ANTENNA_A:
955 pMptCtx->mpt_rf_path = RF_PATH_A;
956 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
957 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
958 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
959 break;
960 case ANTENNA_B:
961 pMptCtx->mpt_rf_path = RF_PATH_B;
962 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
963 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
964 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
965 break;
966 case ANTENNA_AB:
967 pMptCtx->mpt_rf_path = RF_PATH_AB;
968 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
969 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
970 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
971 break;
972 default:
973 pMptCtx->mpt_rf_path = RF_PATH_AB;
974 RTW_INFO("Unknown Tx antenna.\n");
975 break;
976 }
977
978 switch (ulAntennaRx) {
979 u32 reg0xC50 = 0;
980 case ANTENNA_A:
981 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
982 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
983 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
984 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
985
986 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
987 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
988 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
989 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
990
991 /* set PWED_TH for BB Yn user guide R29 */
992 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
993 if (channel <= 14) { /* 2.4G */
994 if (bandwidth == CHANNEL_WIDTH_20
995 && eLNA_2g == 0) {
996 /* 0x830[3:1]=3'b010 */
997 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
998 } else
999 /* 0x830[3:1]=3'b100 */
1000 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1001 } else
1002 /* 0x830[3:1]=3'b100 for 5G */
1003 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1004 }
1005 break;
1006 case ANTENNA_B:
1007 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1008 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1009 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1010 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1011
1012 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1013 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1014 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1015 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1016
1017 /* set PWED_TH for BB Yn user guide R29 */
1018 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1019 if (channel <= 14) {
1020 if (bandwidth == CHANNEL_WIDTH_20
1021 && eLNA_2g == 0) {
1022 /* 0x830[3:1]=3'b010 */
1023 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1024 } else
1025 /* 0x830[3:1]=3'b100 */
1026 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1027 } else
1028 /* 0x830[3:1]=3'b100 for 5G */
1029 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1030 }
1031 break;
1032 case ANTENNA_AB:
1033 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1034 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1035 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1036 /* set PWED_TH for BB Yn user guide R29 */
1037 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1038 break;
1039 default:
1040 RTW_INFO("Unknown Rx antenna.\n");
1041 break;
1042 }
1043
1044 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1045 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1046 /* WiFi */
1047 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1048 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1049 } else {
1050 /* BT */
1051 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1052 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1053 }
1054 }
1055 }
1056 #endif
1057
1058 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1059 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1060 {
1061 u8 i = 0;
1062 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1063 u32 ulAntennaTx, ulAntennaRx;
1064 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1065 struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
1066 struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1067
1068 ulAntennaTx = pHalData->antenna_tx_path;
1069 ulAntennaRx = pHalData->AntennaRxPath;
1070
1071 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1072 RTW_INFO("This RF chip ID is not supported\n");
1073 return;
1074 }
1075
1076 switch (pAdapter->mppriv.antenna_tx) {
1077 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1078 pMptCtx->mpt_rf_path = RF_PATH_A;
1079 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1080 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1081
1082 for (i = 0; i < 3; ++i) {
1083 u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1084 u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1085
1086 if (offset != 0) {
1087 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1088 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1089 }
1090 }
1091 for (i = 0; i < 2; ++i) {
1092 u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1093 u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1094
1095 if (offset != 0) {
1096 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1097 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1098 }
1099 }
1100 }
1101 break;
1102 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1103 u4Byte offset;
1104 u4Byte data;
1105
1106 pMptCtx->mpt_rf_path = RF_PATH_B;
1107 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1108 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1109
1110 for (i = 0; i < 3; ++i) {
1111 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1112 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1113 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1114 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1115 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1116 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1117 }
1118 }
1119 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1120 for (i = 0; i < 2; ++i) {
1121 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1122 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1123 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1124 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1125 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1126 }
1127 }
1128 }
1129 break;
1130 default:
1131 pMptCtx->mpt_rf_path = RF_PATH_AB;
1132 break;
1133 }
1134 }
1135 #endif
1136
1137 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1138 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1139 {
1140 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1141 u4Byte ulAntennaTx, ulAntennaRx;
1142 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1143 struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
1144 struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1145
1146 ulAntennaTx = pHalData->antenna_tx_path;
1147 ulAntennaRx = pHalData->AntennaRxPath;
1148
1149 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1150 RTW_INFO("This RF chip ID is not supported\n");
1151 return;
1152 }
1153
1154 switch (pAdapter->mppriv.antenna_tx) {
1155 u1Byte p = 0, i = 0;
1156
1157 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1158 pMptCtx->mpt_rf_path = RF_PATH_A;
1159 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1160 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1161
1162 for (i = 0; i < 3; ++i) {
1163 u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1164 u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1165
1166 if (offset != 0) {
1167 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1168 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1169 }
1170
1171 }
1172 for (i = 0; i < 2; ++i) {
1173 u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1174 u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1175
1176 if (offset != 0) {
1177 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1178 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1179 }
1180 }
1181 }
1182 break;
1183 case ANTENNA_B: { /* Actually path S0 (BT)*/
1184 pMptCtx->mpt_rf_path = RF_PATH_B;
1185 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1186 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1187
1188 for (i = 0; i < 3; ++i) {
1189 u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1190 u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1191
1192 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1193 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1194 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1195 }
1196 }
1197 for (i = 0; i < 2; ++i) {
1198 u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1199 u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1200
1201 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1202 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1203 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1204 }
1205 }
1206 }
1207 break;
1208 default:
1209 pMptCtx->mpt_rf_path = RF_PATH_AB;
1210 break;
1211 }
1212
1213 }
1214 #endif
1215
1216 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1217 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1218 {
1219 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1220 u1Byte p = 0, i = 0;
1221 u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1222 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1223 struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
1224 struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1225
1226 ulAntennaTx = pHalData->antenna_tx_path;
1227 ulAntennaRx = pHalData->AntennaRxPath;
1228
1229 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1230 RTW_INFO("This RF chip ID is not supported\n");
1231 return;
1232 }
1233
1234 switch (pAdapter->mppriv.antenna_tx) {
1235 /* Actually path S1 (Wi-Fi) */
1236 case ANTENNA_A: {
1237 pMptCtx->mpt_rf_path = RF_PATH_A;
1238 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1239 }
1240 break;
1241 /* Actually path S0 (BT) */
1242 case ANTENNA_B: {
1243 pMptCtx->mpt_rf_path = RF_PATH_B;
1244 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1245
1246 }
1247 break;
1248 default:
1249 pMptCtx->mpt_rf_path = RF_PATH_AB;
1250 break;
1251 }
1252 }
1253 #endif
1254
mpt_SetRFPath_819X(PADAPTER pAdapter)1255 VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
1256 {
1257 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1258 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1259 u4Byte ulAntennaTx, ulAntennaRx;
1260 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1261 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1262 u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1263 u1Byte chgTx = 0, chgRx = 0;
1264 u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1265
1266 ulAntennaTx = pHalData->antenna_tx_path;
1267 ulAntennaRx = pHalData->AntennaRxPath;
1268
1269 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1270 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1271
1272 p_ofdm_tx->r_ant_ht1 = 0x1;
1273 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1274 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1275
1276 switch (ulAntennaTx) {
1277 case ANTENNA_A:
1278 p_ofdm_tx->r_tx_antenna = 0x1;
1279 r_ofdm_tx_en_val = 0x1;
1280 p_ofdm_tx->r_ant_l = 0x1;
1281 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1282 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1283 p_cck_txrx->r_ccktx_enable = 0x8;
1284 chgTx = 1;
1285 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1286 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1287 {
1288 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1289 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1290 r_ofdm_tx_en_val = 0x3;
1291 /*/ Power save*/
1292 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1293 /*/ We need to close RFB by SW control*/
1294 if (pHalData->rf_type == RF_2T2R) {
1295 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1296 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1297 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1298 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1299 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1300 }
1301 }
1302 pMptCtx->mpt_rf_path = RF_PATH_A;
1303 break;
1304 case ANTENNA_B:
1305 p_ofdm_tx->r_tx_antenna = 0x2;
1306 r_ofdm_tx_en_val = 0x2;
1307 p_ofdm_tx->r_ant_l = 0x2;
1308 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1309 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1310 p_cck_txrx->r_ccktx_enable = 0x4;
1311 chgTx = 1;
1312 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1313 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1314 {
1315 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1316 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1317
1318 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1319 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1320 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1321 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1322 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1323 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1324 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1325 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1326 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1327 }
1328 }
1329 pMptCtx->mpt_rf_path = RF_PATH_B;
1330 break;
1331 case ANTENNA_AB:/*/ For 8192S*/
1332 p_ofdm_tx->r_tx_antenna = 0x3;
1333 r_ofdm_tx_en_val = 0x3;
1334 p_ofdm_tx->r_ant_l = 0x3;
1335 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1336 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1337 p_cck_txrx->r_ccktx_enable = 0xC;
1338 chgTx = 1;
1339 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1340 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1341 {
1342 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1343 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1344 /* Disable Power save*/
1345 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1346 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1347 if (pHalData->rf_type == RF_2T2R) {
1348 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1349
1350 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1351 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1352 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1353 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1354 }
1355 }
1356 pMptCtx->mpt_rf_path = RF_PATH_AB;
1357 break;
1358 default:
1359 break;
1360 }
1361 #if 0
1362 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1363 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1364 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1365 #endif
1366 switch (ulAntennaRx) {
1367 case ANTENNA_A:
1368 r_rx_antenna_ofdm = 0x1; /* A*/
1369 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1370 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1371 chgRx = 1;
1372 break;
1373 case ANTENNA_B:
1374 r_rx_antenna_ofdm = 0x2; /*/ B*/
1375 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1376 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1377 chgRx = 1;
1378 break;
1379 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1380 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1381 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1382 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1383 chgRx = 1;
1384 break;
1385 default:
1386 break;
1387 }
1388
1389
1390 if (chgTx && chgRx) {
1391 switch (pHalData->rf_chip) {
1392 case RF_8225:
1393 case RF_8256:
1394 case RF_6052:
1395 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1396 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1397 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1398 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1399 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1400 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1401 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1402 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1403 }
1404 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1405 break;
1406
1407 default:
1408 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1409 break;
1410 }
1411 }
1412 } /* MPT_ProSetRFPath */
1413
1414
hal_mpt_SetAntenna(PADAPTER pAdapter)1415 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1416
1417 {
1418 RTW_INFO("Do %s\n", __func__);
1419 #ifdef CONFIG_RTL8814A
1420 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1421 mpt_SetRFPath_8814A(pAdapter);
1422 return;
1423 }
1424 #endif
1425 #ifdef CONFIG_RTL8822B
1426 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1427 rtl8822b_mp_config_rfpath(pAdapter);
1428 return;
1429 }
1430 #endif
1431 #ifdef CONFIG_RTL8821C
1432 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1433 rtl8821c_mp_config_rfpath(pAdapter);
1434 return;
1435 }
1436 #endif
1437 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1438 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1439 mpt_SetRFPath_8812A(pAdapter);
1440 return;
1441 }
1442 #endif
1443 #ifdef CONFIG_RTL8723B
1444 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1445 mpt_SetRFPath_8723B(pAdapter);
1446 return;
1447 }
1448 #endif
1449
1450 #ifdef CONFIG_RTL8703B
1451 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1452 mpt_SetRFPath_8703B(pAdapter);
1453 return;
1454 }
1455 #endif
1456
1457 #ifdef CONFIG_RTL8723D
1458 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1459 mpt_SetRFPath_8723D(pAdapter);
1460 return;
1461 }
1462 #endif
1463 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1464 mpt_SetRFPath_8821B(pAdapter);
1465 Prepare for 8822B
1466 else if (IS_HARDWARE_TYPE_8822B(Context))
1467 mpt_SetRFPath_8822B(Context);
1468 */
1469 mpt_SetRFPath_819X(pAdapter);
1470 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1471 }
1472
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1473 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1474 {
1475 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1476
1477 if (!netif_running(pAdapter->pnetdev)) {
1478 return _FAIL;
1479 }
1480
1481
1482 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1483 return _FAIL;
1484 }
1485
1486
1487 target_ther &= 0xff;
1488 if (target_ther < 0x07)
1489 target_ther = 0x07;
1490 else if (target_ther > 0x1d)
1491 target_ther = 0x1d;
1492
1493 pHalData->eeprom_thermal_meter = target_ther;
1494
1495 return _SUCCESS;
1496 }
1497
1498
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1499 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1500 {
1501 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1502
1503 }
1504
1505
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)1506 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1507
1508 {
1509 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(pAdapter);
1510 u32 ThermalValue = 0;
1511 s32 thermal_value_temp = 0;
1512 s8 thermal_offset = 0;
1513
1514 ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
1515 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1516
1517 thermal_value_temp = ThermalValue + thermal_offset;
1518
1519 if (thermal_value_temp > 63)
1520 ThermalValue = 63;
1521 else if (thermal_value_temp < 0)
1522 ThermalValue = 0;
1523 else
1524 ThermalValue = thermal_value_temp;
1525
1526 return (u8)ThermalValue;
1527 }
1528
1529
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 * value)1530 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1531 {
1532 #if 0
1533 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1534 rtw_msleep_os(1000);
1535 fw_cmd_data(pAdapter, value, 1);
1536 *value &= 0xFF;
1537 #else
1538 hal_mpt_TriggerRFThermalMeter(pAdapter);
1539 rtw_msleep_os(1000);
1540 *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1541 #endif
1542
1543 }
1544
1545
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1546 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1547 {
1548 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1549
1550 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1551
1552 if (bStart) {/*/ Start Single Carrier.*/
1553 /*/ Start Single Carrier.*/
1554 /*/ 1. if OFDM block on?*/
1555 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1556 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1557
1558 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1559 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1560
1561 /*/ 3. turn on scramble setting*/
1562 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1563
1564 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1565 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1566 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1567 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1568 else
1569 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1570 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1571
1572 } else {
1573 /*/ Stop Single Carrier.*/
1574 /*/ Stop Single Carrier.*/
1575 /*/ Turn off all test modes.*/
1576 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1577 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1578 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1579 else
1580 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1581 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1582
1583 rtw_msleep_os(10);
1584 /*/BB Reset*/
1585 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1586 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1587 }
1588 }
1589
1590
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1591 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1592 {
1593 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1594 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1595 u4Byte ulAntennaTx = pHalData->antenna_tx_path;
1596 static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1597 u8 rfPath;
1598
1599 switch (ulAntennaTx) {
1600 case ANTENNA_B:
1601 rfPath = RF_PATH_B;
1602 break;
1603 case ANTENNA_C:
1604 rfPath = RF_PATH_C;
1605 break;
1606 case ANTENNA_D:
1607 rfPath = RF_PATH_D;
1608 break;
1609 case ANTENNA_A:
1610 default:
1611 rfPath = RF_PATH_A;
1612 break;
1613 }
1614
1615 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1616 if (bStart) {
1617 /*/ Start Single Tone.*/
1618 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1619 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1620 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1621 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1622 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1623 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1624 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1625 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1626 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1627 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1628 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1629 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1630 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1631 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1632 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1633 } else {
1634 /*/ S0/S1 both use PATH A to configure*/
1635 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1636 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1637 }
1638 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1639 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1640 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1641 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1642 }
1643 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1644 /*Set BB REG 88C: Prevent SingleTone Fail*/
1645 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1646 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1647 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1648
1649 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1650 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1651 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1652 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1653 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1654 } else {/* S0/S1 both use PATH A to configure */
1655 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1656 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1657 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1658 }
1659 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1660 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B)
1661 u1Byte p = RF_PATH_A;
1662
1663 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1664 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1665 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1666 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1667 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1668
1669 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1670
1671 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1672 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1673 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1674 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1675 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1676 }
1677 } else {
1678 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1679 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1680 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1681 }
1682
1683 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1684 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1685
1686 if (pHalData->external_pa_5g) {
1687 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1688 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1689 } else if (pHalData->ExternalPA_2G) {
1690 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1691 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1692 }
1693 #endif
1694 }
1695 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821C)
1696 else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
1697 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1698 #endif
1699
1700 else /*/ Turn On SingleTone and turn off the other test modes.*/
1701 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1702
1703 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1704 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1705
1706 } else {/*/ Stop Single Ton e.*/
1707
1708 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1709 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1710 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1711 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1712 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1713 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1714 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1715 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1716 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1717 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1718 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1719 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1720 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1721 } else {
1722 /*/ S0/S1 both use PATH A to configure*/
1723 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1724 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1725 }
1726 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1727 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1728 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1729 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1730 }
1731 } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1732 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1733 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1734 /*Set BB REG 88C: Prevent SingleTone Fail*/
1735 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1736 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1737 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1738 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1739 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1740 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1741 } else { /* S0/S1 both use PATH A to configure */
1742 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1743 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1744 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
1745 }
1746 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
1747 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B)
1748 u1Byte p = RF_PATH_A;
1749
1750 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1751
1752 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1753 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1754 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1755 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1756 }
1757 } else {
1758 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1759 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1760 }
1761
1762 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1763 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1764 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1765 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1766 #endif
1767 }
1768 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1769 else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
1770 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1771
1772 else/*/ Turn off all test modes.*/
1773 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1774 #endif
1775 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1776 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1777
1778 }
1779 }
1780
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1781 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1782 {
1783 u8 Rate;
1784
1785 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
1786
1787 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1788 if (bStart) {/* Start Carrier Suppression.*/
1789 if (Rate <= MPT_RATE_11M) {
1790 /*/ 1. if CCK block on?*/
1791 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1792 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1793
1794 /*/Turn Off All Test Mode*/
1795 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1796 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1797 else
1798 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1799
1800 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1801 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
1802
1803 /*/Set CCK Tx Test Rate*/
1804 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
1805 }
1806
1807 /*Set for dynamic set Power index*/
1808 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1809 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1810
1811 } else {/* Stop Carrier Suppression.*/
1812
1813 if (Rate <= MPT_RATE_11M) {
1814 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1815 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1816
1817 /*BB Reset*/
1818 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1819 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1820 }
1821 /*Stop for dynamic set Power index*/
1822 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1823 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1824 }
1825 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
1826 }
1827
hal_mpt_query_phytxok(PADAPTER pAdapter)1828 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
1829 {
1830 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1831 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1832 u16 count = 0;
1833
1834 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
1835 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
1836 else
1837 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
1838
1839 if (count > 50000) {
1840 rtw_reset_phy_trx_ok_counters(pAdapter);
1841 pAdapter->mppriv.tx.sended += count;
1842 count = 0;
1843 }
1844
1845 return pAdapter->mppriv.tx.sended + count;
1846
1847 }
1848
mpt_StopCckContTx(PADAPTER pAdapter)1849 static VOID mpt_StopCckContTx(
1850 PADAPTER pAdapter
1851 )
1852 {
1853 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1854 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1855 u1Byte u1bReg;
1856
1857 pMptCtx->bCckContTx = FALSE;
1858 pMptCtx->bOfdmContTx = FALSE;
1859
1860 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1861 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1862
1863 if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1864 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
1865 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
1866
1867 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1868 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
1869 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
1870 }
1871
1872 /*BB Reset*/
1873 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1874 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1875
1876 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1877 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1878
1879 } /* mpt_StopCckContTx */
1880
1881
mpt_StopOfdmContTx(PADAPTER pAdapter)1882 static VOID mpt_StopOfdmContTx(
1883 PADAPTER pAdapter
1884 )
1885 {
1886 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1887 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1888 u1Byte u1bReg;
1889 u4Byte data;
1890
1891 pMptCtx->bCckContTx = FALSE;
1892 pMptCtx->bOfdmContTx = FALSE;
1893
1894 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1895 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1896 else
1897 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1898
1899 rtw_mdelay_os(10);
1900
1901 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1902 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
1903 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
1904 }
1905
1906 /*BB Reset*/
1907 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1908 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1909
1910 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1911 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1912 } /* mpt_StopOfdmContTx */
1913
1914
mpt_StartCckContTx(PADAPTER pAdapter)1915 static VOID mpt_StartCckContTx(
1916 PADAPTER pAdapter
1917 )
1918 {
1919 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1920 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1921 u4Byte cckrate;
1922
1923 /* 1. if CCK block on */
1924 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1925 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
1926
1927 /*Turn Off All Test Mode*/
1928 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1929 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1930 else
1931 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1932
1933 cckrate = pAdapter->mppriv.rateidx;
1934
1935 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1936
1937 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
1938 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1939
1940 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1941 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
1942 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1943 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1944 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
1945 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
1946 }
1947
1948 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1949 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1950
1951 pMptCtx->bCckContTx = TRUE;
1952 pMptCtx->bOfdmContTx = FALSE;
1953
1954 } /* mpt_StartCckContTx */
1955
1956
mpt_StartOfdmContTx(PADAPTER pAdapter)1957 static VOID mpt_StartOfdmContTx(
1958 PADAPTER pAdapter
1959 )
1960 {
1961 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1962 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1963
1964 /* 1. if OFDM block on?*/
1965 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1966 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
1967
1968 /* 2. set CCK test mode off, set to CCK normal mode*/
1969 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1970
1971 /* 3. turn on scramble setting*/
1972 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1973
1974 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
1975 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
1976 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
1977 }
1978
1979 /* 4. Turn On Continue Tx and turn off the other test modes.*/
1980 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
1981 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
1982 else
1983 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
1984
1985 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1986 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1987
1988 pMptCtx->bCckContTx = FALSE;
1989 pMptCtx->bOfdmContTx = TRUE;
1990 } /* mpt_StartOfdmContTx */
1991
1992
1993 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1994 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)1995 void mpt_ProSetPMacTx(PADAPTER Adapter)
1996 {
1997 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
1998 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
1999 u32 u4bTmp;
2000
2001 dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2002 dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2003 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2004 #if 0
2005 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2006 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2007 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2008 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2009 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2010 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2011
2012 PRINT_DATA("Src Address", Adapter->mac_addr, 6);
2013 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
2014 #endif
2015
2016 if (PMacTxInfo.bEnPMacTx == FALSE) {
2017 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2018 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2019 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2020 mpt_StopCckContTx(Adapter);
2021 else
2022 mpt_StopOfdmContTx(Adapter);
2023 } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2024 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2025 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2026 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2027 } else
2028 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2029
2030 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2031 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2032 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2033 mpt_StopCckContTx(Adapter);
2034 else
2035 mpt_StopOfdmContTx(Adapter);
2036
2037 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2038 }
2039
2040 return;
2041 }
2042
2043 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2044 PMacTxInfo.PacketCount = 1;
2045
2046 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2047 mpt_StartCckContTx(Adapter);
2048 else
2049 mpt_StartOfdmContTx(Adapter);
2050 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2051 /* Continuous TX -> HW TX -> RF Setting */
2052 PMacTxInfo.PacketCount = 1;
2053
2054 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2055 mpt_StartCckContTx(Adapter);
2056 else
2057 mpt_StartOfdmContTx(Adapter);
2058 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2059 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2060 PMacTxInfo.PacketCount = 0xffff;
2061 }
2062
2063 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2064 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2065 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2066 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2067 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2068 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2069 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2070 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2071 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2072
2073 if (PMacTxInfo.bSPreamble)
2074 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2075 else
2076 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2077 } else {
2078 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2079
2080 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2081 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2082
2083 if (PMacTxInfo.PacketPattern == 0x12)
2084 u4bTmp = 0x3000000;
2085 else
2086 u4bTmp = 0;
2087 }
2088
2089 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2090 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2091 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2092 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2093 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2094 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2095 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2096 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2097 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2098 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2099
2100 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2101 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2102 }
2103
2104 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2105 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2106 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2107
2108 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2109 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2110
2111 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2112 /*& Duration & Frame control*/
2113 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2114
2115 /* Address1 [0:3]*/
2116 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2117 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2118
2119 /* Address3 [3:0]*/
2120 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2121
2122 /* Address2[0:1] & Address1 [5:4]*/
2123 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2124 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2125
2126 /* Address2 [5:2]*/
2127 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2128 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2129
2130 /* Sequence Control & Address3 [5:4]*/
2131 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2132 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2133 } else {
2134 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2135 /* & Duration & Frame control */
2136 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2137
2138 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2139 /* Address1 [0:3]*/
2140 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2141 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2142
2143 /* Address3 [3:0]*/
2144 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2145
2146 /* Address2[0:1] & Address1 [5:4]*/
2147 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2148 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2149
2150 /* Address2 [5:2] */
2151 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2152 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2153
2154 /* Sequence Control & Address3 [5:4]*/
2155 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2156 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2157 }
2158
2159 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2160
2161 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2162 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2163 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2164
2165 if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
2166 u4Byte offset = 0xb44;
2167
2168 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2169 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2170 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2171 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2172 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2173 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2174 }
2175
2176 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2177 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2178 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2179 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2180 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2181 } else
2182 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2183
2184 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2185 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2186
2187 }
2188
2189 #endif
2190
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2191 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2192 {
2193 u8 Rate;
2194
2195 RT_TRACE(_module_mp_, _drv_info_,
2196 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
2197 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2198 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2199
2200 if (Rate <= MPT_RATE_11M) {
2201 if (bStart)
2202 mpt_StartCckContTx(pAdapter);
2203 else
2204 mpt_StopCckContTx(pAdapter);
2205
2206 } else if (Rate >= MPT_RATE_6M) {
2207 if (bStart)
2208 mpt_StartOfdmContTx(pAdapter);
2209 else
2210 mpt_StopOfdmContTx(pAdapter);
2211 }
2212 }
2213
2214 #endif /* CONFIG_MP_INCLUDE*/
2215