1 /****************************************************************************** 2 * 3 * Copyright(c) 2015 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_HALMAC_H_ 16 #define _HAL_HALMAC_H_ 17 18 #include <drv_types.h> /* adapter_to_dvobj(), struct intf_hdl and etc. */ 19 #include <hal_data.h> /* struct hal_spec_t */ 20 #include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */ 21 22 /* HALMAC Definition for Driver */ 23 #define RTW_HALMAC_H2C_MAX_SIZE 8 24 #define RTW_HALMAC_BA_SSN_RPT_SIZE 4 25 26 #define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) 27 #define dvobj_to_halmac(d) ((PHALMAC_ADAPTER)((d)->halmac)) 28 #define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) 29 30 /* for H2C cmd */ 31 #define MAX_H2C_BOX_NUMS 4 32 #define MESSAGE_BOX_SIZE 4 33 #define EX_MESSAGE_BOX_SIZE 4 34 35 typedef enum _RTW_HALMAC_MODE { 36 RTW_HALMAC_MODE_NORMAL, 37 RTW_HALMAC_MODE_WIFI_TEST, 38 } RTW_HALMAC_MODE; 39 40 union rtw_phy_para_data { 41 struct _mac { 42 u32 value; 43 u32 msk; 44 u16 offset; 45 u8 msk_en; /* Enable bit mask(msk) or not */ 46 u8 size; /* Unit is bytes, and value should be 1/2/4 */ 47 } mac; 48 struct _bb { 49 u32 value; 50 u32 msk; 51 u16 offset; 52 u8 msk_en; 53 u8 size; 54 } bb; 55 struct _rf { 56 u32 value; 57 u32 msk; 58 u8 offset; 59 u8 msk_en; 60 /* 61 * 0: path A 62 * 1: path B 63 * 2: path C 64 * 3: path D 65 */ 66 u8 path; 67 } rf; 68 struct _delay { 69 /* 70 * 0: microsecond (us) 71 * 1: millisecond (ms) 72 */ 73 u8 unit; 74 u16 value; 75 } delay; 76 }; 77 78 struct rtw_phy_parameter { 79 /* 80 * 0: MAC register 81 * 1: BB register 82 * 2: RF register 83 * 3: Delay 84 * 0xFF: Latest(End) command 85 */ 86 u8 cmd; 87 union rtw_phy_para_data data; 88 }; 89 90 struct rtw_halmac_bcn_ctrl { 91 u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */ 92 u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */ 93 u8 tsf_update:1; /* Update TSF when beacon or probe response */ 94 u8 enable_bcn:1; /* Enable beacon related functions */ 95 u8 rxbcn_rpt:1; /* Enable RXBCNOK report */ 96 u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */ 97 u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */ 98 }; 99 100 extern HALMAC_PLATFORM_API rtw_halmac_platform_api; 101 102 /* HALMAC API for Driver(HAL) */ 103 u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); 104 u16 rtw_halmac_read16(struct intf_hdl *, u32 addr); 105 u32 rtw_halmac_read32(struct intf_hdl *, u32 addr); 106 void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); 107 #ifdef CONFIG_SDIO_INDIRECT_ACCESS 108 u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); 109 u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); 110 u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); 111 #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ 112 int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); 113 int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); 114 int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); 115 116 /* Software Information */ 117 void rtw_halmac_get_version(char *str, u32 len); 118 119 /* Software Initialization */ 120 int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API); 121 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 122 123 /* Get operations */ 124 int rtw_halmac_get_hw_value(struct dvobj_priv *, HALMAC_HW_ID hw_id, VOID *pvalue); 125 int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size); 126 int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size); 127 int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy); 128 int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size); 129 int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size); 130 int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size); 131 int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz); 132 int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size); 133 int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size); 134 int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size); 135 int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); 136 int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); 137 int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 138 int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type); 139 int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 140 /*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/ 141 142 /* Set operations */ 143 int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO); 144 int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size); 145 int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 146 int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 147 int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 148 int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type); 149 int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport); 150 int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space); 151 int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 152 int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid); 153 int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw); 154 int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); 155 156 /* Functions */ 157 int rtw_halmac_poweron(struct dvobj_priv *); 158 int rtw_halmac_poweroff(struct dvobj_priv *); 159 int rtw_halmac_init_hal(struct dvobj_priv *); 160 int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); 161 int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); 162 int rtw_halmac_deinit_hal(struct dvobj_priv *); 163 int rtw_halmac_self_verify(struct dvobj_priv *); 164 int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout); 165 int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); 166 int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); 167 int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); 168 int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem); 169 int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); 170 int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); 171 int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); 172 173 /* eFuse */ 174 int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); 175 int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); 176 int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 177 int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 178 int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 179 int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); 180 int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 181 int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 182 int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 183 int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 184 185 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 186 int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 187 188 int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); 189 int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); 190 191 /* Specific function APIs*/ 192 int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); 193 int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); 194 int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); 195 int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); 196 int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para); 197 198 #ifdef CONFIG_SDIO_HCI 199 int rtw_halmac_query_tx_page_num(struct dvobj_priv *); 200 int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page); 201 u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size); 202 int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size); 203 u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq); 204 #endif /* CONFIG_SDIO_HCI */ 205 206 #ifdef CONFIG_USB_HCI 207 u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); 208 int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num); 209 u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); 210 #endif /* CONFIG_USB_HCI */ 211 212 #ifdef CONFIG_SUPPORT_TRX_SHARED 213 void dump_trx_share_mode(void *sel, _adapter *adapter); 214 #endif 215 #endif /* _HAL_HALMAC_H_ */ 216