1 /******************************************************************************
2 *
3 * Copyright(c) 2014 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <drv_types.h>
17 #include <hal_data.h>
18
19 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)20 enum odm_board_type_e boardType(u8 InterfaceSel)
21 {
22 enum odm_board_type_e board = ODM_BOARD_DEFAULT;
23
24 #ifdef CONFIG_PCI_HCI
25 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
26 switch (pcie) {
27 case INTF_SEL0_SOLO_MINICARD:
28 board |= ODM_BOARD_MINICARD;
29 break;
30 case INTF_SEL1_BT_COMBO_MINICARD:
31 board |= ODM_BOARD_BT;
32 board |= ODM_BOARD_MINICARD;
33 break;
34 default:
35 board = ODM_BOARD_DEFAULT;
36 break;
37 }
38
39 #elif defined(CONFIG_USB_HCI)
40 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
41 switch (usb) {
42 case INTF_SEL1_USB_High_Power:
43 board |= ODM_BOARD_EXT_LNA;
44 board |= ODM_BOARD_EXT_PA;
45 break;
46 case INTF_SEL2_MINICARD:
47 board |= ODM_BOARD_MINICARD;
48 break;
49 case INTF_SEL4_USB_Combo:
50 board |= ODM_BOARD_BT;
51 break;
52 case INTF_SEL5_USB_Combo_MF:
53 board |= ODM_BOARD_BT;
54 break;
55 case INTF_SEL0_USB:
56 case INTF_SEL3_USB_Solo:
57 default:
58 board = ODM_BOARD_DEFAULT;
59 break;
60 }
61
62 #endif
63 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
64
65 return board;
66 }
67
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)68 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
69 {
70 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
71 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
72
73 if (hal->RegIQKFWOffload) {
74 rtw_sctx_init(&hal->iqk_sctx, 0);
75 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
76 } else
77 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
78
79 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
80 }
81
82 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)83 void rtw_phydm_iqk_trigger(_adapter *adapter)
84 {
85 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
86 u8 clear = _FALSE;
87 u8 segment = _FALSE;
88 u8 rfk_forbidden = _FALSE;
89
90 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
91 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
92 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
93 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
94 }
95 #endif
96
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)97 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
98 {
99 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
100
101 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
102 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
103 #else
104 halrf_iqk_trigger(p_dm_odm, recovery);
105 #endif
106 }
rtw_phydm_lck_trigger(_adapter * adapter)107 void rtw_phydm_lck_trigger(_adapter *adapter)
108 {
109 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
110
111 halrf_lck_trigger(p_dm_odm);
112 }
113 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)114 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
115 {
116 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
117
118 rtw_ps_deny(adapter, PS_DENY_IOCTL);
119 LeaveAllPowerSaveModeDirect(adapter);
120
121 rtw_phydm_ability_backup(adapter);
122 rtw_phydm_func_disable_all(adapter);
123
124 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
125
126 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
127 rtw_phydm_ability_restore(adapter);
128
129 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
130 }
131
rtw_hal_lck_test(_adapter * adapter)132 void rtw_hal_lck_test(_adapter *adapter)
133 {
134 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
135
136 rtw_ps_deny(adapter, PS_DENY_IOCTL);
137 LeaveAllPowerSaveModeDirect(adapter);
138
139 rtw_phydm_ability_backup(adapter);
140 rtw_phydm_func_disable_all(adapter);
141
142 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
143
144 rtw_phydm_lck_trigger(adapter);
145
146 rtw_phydm_ability_restore(adapter);
147 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
148 }
149 #endif
150
151 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)152 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
153 {
154 struct PHY_DM_STRUCT *p_dm_odm = adapter_to_phydm(adapter);
155
156 if (adapter->registrypriv.fw_param_init)
157 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
158 else
159 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
160
161 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
162 }
163 #endif
164
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)165 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
166 {
167 struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
168 _adapter *adapter = p_dm->adapter;
169 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
170 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
171
172 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
173 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
174 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
175 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
176
177 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
178 }
179
rtw_phydm_ops_func_init(struct PHY_DM_STRUCT * p_phydm)180 void rtw_phydm_ops_func_init(struct PHY_DM_STRUCT *p_phydm)
181 {
182 struct _rate_adaptive_table_ *p_ra_t = &p_phydm->dm_ra_table;
183
184 p_ra_t->record_ra_info = record_ra_info;
185 }
186
Init_ODM_ComInfo(_adapter * adapter)187 void Init_ODM_ComInfo(_adapter *adapter)
188 {
189 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
190 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
191 struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv);
192 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
193 int i;
194
195 _rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm));
196
197 pDM_Odm->adapter = adapter;
198
199 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
200 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
201
202 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE);
203
204 rtw_odm_init_ic_type(adapter);
205
206 if (rtw_get_intf_type(adapter) == RTW_GSPI)
207 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
208 else
209 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
210
211 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
212
213 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
214
215 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
216
217 #ifdef CONFIG_ADVANCE_OTA
218 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
219 #endif
220 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
221
222 {
223 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
224 u8 odm_board_type = ODM_BOARD_DEFAULT;
225
226 if (pHalData->ExternalLNA_2G != 0) {
227 odm_board_type |= ODM_BOARD_EXT_LNA;
228 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
229 }
230 if (pHalData->external_lna_5g != 0) {
231 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
232 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
233 }
234 if (pHalData->ExternalPA_2G != 0) {
235 odm_board_type |= ODM_BOARD_EXT_PA;
236 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
237 }
238 if (pHalData->external_pa_5g != 0) {
239 odm_board_type |= ODM_BOARD_EXT_PA_5G;
240 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
241 }
242 if (pHalData->EEPROMBluetoothCoexist)
243 odm_board_type |= ODM_BOARD_BT;
244
245 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
246 /* 1 ============== End of BoardType ============== */
247 }
248
249 rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
250
251 #ifdef CONFIG_DFS_MASTER
252 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
253 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled));
254 #endif
255
256 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
257 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
258 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
259 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
260
261 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
262
263 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
264
265 /*Add by YuChen for kfree init*/
266 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
267 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
268
269 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
270 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
271 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
272
273 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
274 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
275 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
276
277 /*Add by YuChen for adaptivity init*/
278 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
279 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
280 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff);
281 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE);
282 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
283 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
284
285 /*halrf info init*/
286 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
287 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_FW_VER,
288 ((pHalData->firmware_version << 16) | pHalData->firmware_sub_version));
289
290 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
291 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
292
293 #ifdef CONFIG_IQK_PA_OFF
294 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
295 #endif
296 rtw_hal_update_iqk_fw_offload_cap(adapter);
297 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
298 rtw_hal_update_param_init_fw_offload_cap(adapter);
299 #endif
300
301 /* Pointer reference */
302 /*Antenna diversity relative parameters*/
303 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
304 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
305
306 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
307 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
308 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
309
310 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
311 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
312
313 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
314 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
315 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
316 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
317 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
318
319 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
320 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
321 /*Add by Yuchen for phydm beamforming*/
322 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
323 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
324 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
325 #ifdef CONFIG_RTL8723B
326 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
327 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
328 #endif /*CONFIG_RTL8723B*/
329 #ifdef CONFIG_USB_HCI
330 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
331 #endif
332
333 /*halrf info hook*/
334 #ifdef CONFIG_MP_INCLUDED
335 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
336 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
337 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
338 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
339 #endif/*CONFIG_MP_INCLUDED*/
340 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
341 odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
342
343 phydm_init_debug_setting(pDM_Odm);
344 rtw_phydm_ops_func_init(pDM_Odm);
345 /* TODO */
346 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
347 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
348 }
349
350
351 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
352 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
353 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
354 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
355
356 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
357 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
358 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
359 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
360
361 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
362 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
363 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
364 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
365
rtw_hal_turbo_edca(_adapter * adapter)366 void rtw_hal_turbo_edca(_adapter *adapter)
367 {
368 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
369 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
370 struct recv_priv *precvpriv = &(adapter->recvpriv);
371 struct registry_priv *pregpriv = &adapter->registrypriv;
372 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
373 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
374
375 /* Parameter suggested by Scott */
376 #if 0
377 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
378 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
379 #endif
380 u32 EDCA_BE_UL = 0x5ea42b;
381 u32 EDCA_BE_DL = 0x00a42b;
382 u8 ic_type = rtw_get_chip_type(adapter);
383
384 u8 iot_peer = 0;
385 u8 wireless_mode = 0xFF; /* invalid value */
386 u8 traffic_index;
387 u32 edca_param;
388 u64 cur_tx_bytes = 0;
389 u64 cur_rx_bytes = 0;
390 u8 bbtchange = _TRUE;
391 u8 is_bias_on_rx = _FALSE;
392 u8 is_linked = _FALSE;
393 u8 interface_type;
394
395 if (hal_data->dis_turboedca)
396 return;
397
398 if (rtw_mi_check_status(adapter, MI_ASSOC))
399 is_linked = _TRUE;
400
401 if (is_linked != _TRUE) {
402 precvpriv->is_any_non_be_pkts = _FALSE;
403 return;
404 }
405
406 if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
407 precvpriv->is_any_non_be_pkts = _FALSE;
408 return;
409 }
410
411 interface_type = rtw_get_intf_type(adapter);
412 wireless_mode = pmlmeext->cur_wireless_mode;
413
414 iot_peer = pmlmeinfo->assoc_AP_vendor;
415
416 if (iot_peer >= HT_IOT_PEER_MAX) {
417 precvpriv->is_any_non_be_pkts = _FALSE;
418 return;
419 }
420
421 if (ic_type == RTL8188E) {
422 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
423 is_bias_on_rx = _TRUE;
424 }
425
426 /* Check if the status needs to be changed. */
427 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
428 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
429 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
430
431 /* traffic, TX or RX */
432 if (is_bias_on_rx) {
433 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
434 /* Uplink TP is present. */
435 traffic_index = UP_LINK;
436 } else {
437 /* Balance TP is present. */
438 traffic_index = DOWN_LINK;
439 }
440 } else {
441 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
442 /* Downlink TP is present. */
443 traffic_index = DOWN_LINK;
444 } else {
445 /* Balance TP is present. */
446 traffic_index = UP_LINK;
447 }
448 }
449 #if 0
450 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
451 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
452 #endif
453 {
454 if (interface_type == RTW_PCIE) {
455 EDCA_BE_UL = 0x6ea42b;
456 EDCA_BE_DL = 0x6ea42b;
457 }
458
459 /* 92D txop can't be set to 0x3e for cisco1250 */
460 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
461 EDCA_BE_DL = edca_setting_DL[iot_peer];
462 EDCA_BE_UL = edca_setting_UL[iot_peer];
463 }
464 /* merge from 92s_92c_merge temp*/
465 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
466 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
467 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
468 EDCA_BE_DL = 0xa630;
469 else if (iot_peer == HT_IOT_PEER_MARVELL) {
470 EDCA_BE_DL = edca_setting_DL[iot_peer];
471 EDCA_BE_UL = edca_setting_UL[iot_peer];
472 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
473 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
474 /* Suggested by SD3 Wilson for ASUS TP issue.*/
475 EDCA_BE_DL = edca_setting_DL[iot_peer];
476 }
477
478 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */
479 EDCA_BE_UL = 0x5ea42b;
480 EDCA_BE_DL = 0x5ea42b;
481
482 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
483 }
484
485 if (interface_type == RTW_PCIE &&
486 ((ic_type == RTL8822B)
487 || (ic_type == RTL8814A))) {
488 EDCA_BE_UL = 0x6ea42b;
489 EDCA_BE_DL = 0x6ea42b;
490 }
491
492 if (traffic_index == DOWN_LINK)
493 edca_param = EDCA_BE_DL;
494 else
495 edca_param = EDCA_BE_UL;
496 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
497 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
498 #endif
499 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
500
501 RTW_DBG("Turbo EDCA =0x%x\n", edca_param);
502
503 hal_data->prv_traffic_idx = traffic_index;
504 }
505
506 hal_data->is_turbo_edca = _TRUE;
507 } else {
508 /* */
509 /* Turn Off EDCA turbo here. */
510 /* Restore original EDCA according to the declaration of AP. */
511 /* */
512 if (hal_data->is_turbo_edca) {
513 edca_param = hal_data->ac_param_be;
514 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
515 hal_data->is_turbo_edca = _FALSE;
516 }
517 }
518
519 }
520
rtw_phydm_get_min_rssi(_adapter * adapter)521 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
522 {
523 struct PHY_DM_STRUCT *phydm = adapter_to_phydm(adapter);
524 s8 rssi_min = 0;
525
526 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_RSSI_MIN);
527 return rssi_min;
528 }
529
rtw_phydm_get_cur_igi(_adapter * adapter)530 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
531 {
532 struct PHY_DM_STRUCT *phydm = adapter_to_phydm(adapter);
533 u8 cur_igi = 0;
534
535 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CURR_IGI);
536 return cur_igi;
537 }
538
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)539 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
540 {
541 struct PHY_DM_STRUCT *phydm = adapter_to_phydm(adapter);
542
543 if (cnt == FA_OFDM)
544 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_FA_OFDM);
545 else if (cnt == FA_CCK)
546 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_FA_CCK);
547 else if (cnt == FA_TOTAL)
548 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_FA_TOTAL);
549 else if (cnt == CCA_OFDM)
550 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CCA_OFDM);
551 else if (cnt == CCA_CCK)
552 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CCA_CCK);
553 else if (cnt == CCA_ALL)
554 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CCA_ALL);
555 else if (cnt == CRC32_OK_VHT)
556 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_OK_VHT);
557 else if (cnt == CRC32_OK_HT)
558 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_OK_HT);
559 else if (cnt == CRC32_OK_LEGACY)
560 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_OK_LEGACY);
561 else if (cnt == CRC32_OK_CCK)
562 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_OK_CCK);
563 else if (cnt == CRC32_ERROR_VHT)
564 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_ERROR_VHT);
565 else if (cnt == CRC32_ERROR_HT)
566 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_ERROR_HT);
567 else if (cnt == CRC32_ERROR_LEGACY)
568 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_ERROR_LEGACY);
569 else if (cnt == CRC32_ERROR_CCK)
570 return phydm_cmn_info_query(phydm, (enum phydm_info_query_e) PHYDM_INFO_CRC32_ERROR_CCK);
571 else
572 return 0;
573 }
574
rtw_phydm_is_iqk_in_progress(_adapter * adapter)575 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
576 {
577 u8 rts = _FALSE;
578 struct PHY_DM_STRUCT *podmpriv = adapter_to_phydm(adapter);
579
580 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
581 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
582 RTW_ERR("IQK InProgress\n");
583 rts = _TRUE;
584 }
585 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
586
587 return rts;
588 }
589
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,PVOID pValue1,BOOLEAN bSet)590 void SetHalODMVar(
591 PADAPTER Adapter,
592 HAL_ODM_VARIABLE eVariable,
593 PVOID pValue1,
594 BOOLEAN bSet)
595 {
596 struct PHY_DM_STRUCT *podmpriv = adapter_to_phydm(Adapter);
597 /* _irqL irqL; */
598 switch (eVariable) {
599 case HAL_ODM_STA_INFO: {
600 struct sta_info *psta = (struct sta_info *)pValue1;
601
602 if (bSet) {
603 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
604 odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta);
605 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
606 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
607 } else {
608 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
609 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
610 psta->cmn.dm_ctrl = 0;
611 odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL);
612 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
613
614 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
615 }
616 }
617 break;
618 case HAL_ODM_P2P_STATE:
619 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
620 break;
621 case HAL_ODM_WIFI_DISPLAY_STATE:
622 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
623 break;
624 case HAL_ODM_REGULATION:
625 /* used to auto enable/disable adaptivity by SD7 */
626 odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0);
627 odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0);
628 break;
629 case HAL_ODM_INITIAL_GAIN: {
630 u8 rx_gain = *((u8 *)(pValue1));
631 /*printk("rx_gain:%x\n",rx_gain);*/
632 if (rx_gain == 0xff) {/*restore rx gain*/
633 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
634 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
635 } else {
636 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
637 /*odm_write_dig(podmpriv,rx_gain);*/
638 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
639 }
640 }
641 break;
642 case HAL_ODM_RX_INFO_DUMP: {
643 u8 cur_igi = 0;
644 s8 rssi_min;
645 void *sel;
646
647 sel = pValue1;
648 cur_igi = rtw_phydm_get_cur_igi(Adapter);
649 rssi_min = rtw_phydm_get_min_rssi(Adapter);
650
651 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
652 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi);
653 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
654 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
655 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
656 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
657
658 if (podmpriv->is_linked) {
659 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
660 if (IS_HARDWARE_TYPE_8814A(Adapter))
661 _RTW_PRINT_SEL(sel, " RSSI_A = %d(%%), RSSI_B = %d(%%), RSSI_C = %d(%%), RSSI_D = %d(%%)\n",
662 podmpriv->RSSI_A, podmpriv->RSSI_B, podmpriv->RSSI_C, podmpriv->RSSI_D);
663 else
664 _RTW_PRINT_SEL(sel, " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B);
665 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
666 rtw_dump_raw_rssi_info(Adapter, sel);
667 #endif
668 }
669 }
670 break;
671 case HAL_ODM_RX_Dframe_INFO: {
672 void *sel;
673
674 sel = pValue1;
675
676 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
677 #ifdef DBG_RX_DFRAME_RAW_DATA
678 rtw_dump_rx_dframe_info(Adapter, sel);
679 #endif
680 }
681 break;
682
683 #ifdef CONFIG_ANTENNA_DIVERSITY
684 case HAL_ODM_ANTDIV_SELECT: {
685 u8 antenna = (*(u8 *)pValue1);
686
687 /*switch antenna*/
688 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
689 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
690
691 }
692 break;
693 #endif
694
695 default:
696 break;
697 }
698 }
699
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,PVOID pValue1,PVOID pValue2)700 void GetHalODMVar(
701 PADAPTER Adapter,
702 HAL_ODM_VARIABLE eVariable,
703 PVOID pValue1,
704 PVOID pValue2)
705 {
706 struct PHY_DM_STRUCT *podmpriv = adapter_to_phydm(Adapter);
707
708 switch (eVariable) {
709 #ifdef CONFIG_ANTENNA_DIVERSITY
710 case HAL_ODM_ANTDIV_SELECT: {
711 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
712 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
713 }
714 break;
715 #endif
716 case HAL_ODM_INITIAL_GAIN:
717 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
718 break;
719 default:
720 break;
721 }
722 }
723
724 #ifdef RTW_HALMAC
725 #include "../hal_halmac.h"
726 #endif
727
728 enum hal_status
rtw_phydm_fw_iqk(struct PHY_DM_STRUCT * p_dm_odm,u8 clear,u8 segment)729 rtw_phydm_fw_iqk(
730 struct PHY_DM_STRUCT *p_dm_odm,
731 u8 clear,
732 u8 segment
733 )
734 {
735 #ifdef RTW_HALMAC
736 struct _ADAPTER *adapter = p_dm_odm->adapter;
737
738 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
739 return HAL_STATUS_SUCCESS;
740 #endif
741 return HAL_STATUS_FAILURE;
742 }
743
744 enum hal_status
rtw_phydm_cfg_phy_para(struct PHY_DM_STRUCT * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)745 rtw_phydm_cfg_phy_para(
746 struct PHY_DM_STRUCT *p_dm_odm,
747 enum phydm_halmac_param config_type,
748 u32 offset,
749 u32 data,
750 u32 mask,
751 enum rf_path e_rf_path,
752 u32 delay_time)
753 {
754 #ifdef RTW_HALMAC
755 struct _ADAPTER *adapter = p_dm_odm->adapter;
756 struct rtw_phy_parameter para;
757
758 switch (config_type) {
759 case PHYDM_HALMAC_CMD_MAC_W8:
760 para.cmd = 0; /* MAC register */
761 para.data.mac.offset = offset;
762 para.data.mac.value = data;
763 para.data.mac.msk = mask;
764 para.data.mac.msk_en = 1;
765 para.data.mac.size = 1;
766 break;
767 case PHYDM_HALMAC_CMD_MAC_W16:
768 para.cmd = 0; /* MAC register */
769 para.data.mac.offset = offset;
770 para.data.mac.value = data;
771 para.data.mac.msk = mask;
772 para.data.mac.msk_en = 1;
773 para.data.mac.size = 2;
774 break;
775 case PHYDM_HALMAC_CMD_MAC_W32:
776 para.cmd = 0; /* MAC register */
777 para.data.mac.offset = offset;
778 para.data.mac.value = data;
779 para.data.mac.msk = mask;
780 para.data.mac.msk_en = 1;
781 para.data.mac.size = 4;
782 break;
783 case PHYDM_HALMAC_CMD_BB_W8:
784 para.cmd = 1; /* BB register */
785 para.data.bb.offset = offset;
786 para.data.bb.value = data;
787 para.data.bb.msk = mask;
788 para.data.bb.msk_en = 1;
789 para.data.bb.size = 1;
790 break;
791 case PHYDM_HALMAC_CMD_BB_W16:
792 para.cmd = 1; /* BB register */
793 para.data.bb.offset = offset;
794 para.data.bb.value = data;
795 para.data.bb.msk = mask;
796 para.data.bb.msk_en = 1;
797 para.data.bb.size = 2;
798 break;
799 case PHYDM_HALMAC_CMD_BB_W32:
800 para.cmd = 1; /* BB register */
801 para.data.bb.offset = offset;
802 para.data.bb.value = data;
803 para.data.bb.msk = mask;
804 para.data.bb.msk_en = 1;
805 para.data.bb.size = 4;
806 break;
807 case PHYDM_HALMAC_CMD_RF_W:
808 para.cmd = 2; /* RF register */
809 para.data.rf.offset = offset;
810 para.data.rf.value = data;
811 para.data.rf.msk = mask;
812 para.data.rf.msk_en = 1;
813 if (e_rf_path == RF_PATH_A)
814 para.data.rf.path = 0;
815 else if (e_rf_path == RF_PATH_B)
816 para.data.rf.path = 1;
817 else if (e_rf_path == RF_PATH_C)
818 para.data.rf.path = 2;
819 else if (e_rf_path == RF_PATH_D)
820 para.data.rf.path = 3;
821 else
822 para.data.rf.path = 0;
823 break;
824 case PHYDM_HALMAC_CMD_DELAY_US:
825 para.cmd = 3; /* Delay */
826 para.data.delay.unit = 0; /* microsecond */
827 para.data.delay.value = delay_time;
828 break;
829 case PHYDM_HALMAC_CMD_DELAY_MS:
830 para.cmd = 3; /* Delay */
831 para.data.delay.unit = 1; /* millisecond */
832 para.data.delay.value = delay_time;
833 break;
834 case PHYDM_HALMAC_CMD_END:
835 para.cmd = 0xFF; /* End command */
836 break;
837 default:
838 return HAL_STATUS_FAILURE;
839 }
840
841 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
842 return HAL_STATUS_FAILURE;
843 #endif /*RTW_HALMAC*/
844 return HAL_STATUS_SUCCESS;
845 }
846
847
848 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)849 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
850 {
851 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
852 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
853 struct PHY_DM_STRUCT *podmpriv = &(pHalData->odmpriv);
854 struct sta_priv *pstapriv = &adapter->stapriv;
855 struct sta_info *psta = NULL;
856 u8 rssi_min = 0;
857 u32 rssi_rpt = 0;
858 bool is_linked = _FALSE;
859
860 if (!rtw_is_hw_init_completed(adapter))
861 return;
862
863 if (rtw_mi_check_status(adapter, MI_ASSOC))
864 is_linked = _TRUE;
865
866 if (is_linked == _FALSE)
867 return;
868
869 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
870 if (psta == NULL)
871 return;
872
873 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
874
875 phydm_watchdog_lps_32k(&pHalData->odmpriv);
876 }
877
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)878 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
879 {
880 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
881 struct sta_priv *pstapriv = &adapter->stapriv;
882 struct sta_info *psta = NULL;
883 u8 cur_igi = 0;
884 s8 min_rssi = 0;
885
886 if (!rtw_is_hw_init_completed(adapter))
887 return;
888
889 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
890 if (psta == NULL)
891 return;
892
893 cur_igi = rtw_phydm_get_cur_igi(adapter);
894 min_rssi = rtw_phydm_get_min_rssi(adapter);
895 if (min_rssi <= 0)
896 min_rssi = psta->cmn.rssi_stat.rssi;
897 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
898
899 if (min_rssi <= 0)
900 return;
901
902 if ((cur_igi > min_rssi + 5) ||
903 (cur_igi < min_rssi - 5)) {
904 #ifdef CONFIG_LPS
905 rtw_dm_in_lps_wk_cmd(adapter);
906 #endif
907 }
908 }
909 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
910
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)911 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
912 {
913 struct ra_sta_info *ra_info;
914 u8 curr_sgi = _FALSE;
915 u8 curr_rate = 0;
916
917 if (!psta)
918 return;
919 _RTW_PRINT_SEL(sel, "====== mac_id : %d ======\n", psta->cmn.mac_id);
920
921 ra_info = &psta->cmn.ra_info;
922 curr_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
923 curr_rate = ra_info->curr_tx_rate & 0x7F;
924 _RTW_PRINT_SEL(sel, "tx_rate : %s(%s) ",
925 HDATA_RATE(curr_rate), (curr_sgi) ? "S" : "L");
926
927 curr_rate = psta->curr_rx_rate & 0x7F;
928 _RTW_PRINT_SEL(sel, "rx_rate : %s, rssi : %d %%\n", HDATA_RATE(curr_rate), psta->cmn.rssi_stat.rssi);
929
930 _RTW_PRINT_SEL(sel, "TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n",
931 (psta->sta_stats.tx_tp_mbytes << 3), (psta->sta_stats.rx_tp_mbytes << 3),
932 (psta->sta_stats.tx_tp_mbytes + psta->sta_stats.rx_tp_mbytes) << 3);
933
934 _RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
935 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
936 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
937
938 }
939
dump_sta_info(void * sel,struct sta_info * psta)940 void dump_sta_info(void *sel, struct sta_info *psta)
941 {
942 struct ra_sta_info *ra_info;
943 u8 curr_tx_sgi = _FALSE;
944 u8 curr_tx_rate = 0;
945
946 if (!psta)
947 return;
948
949 ra_info = &psta->cmn.ra_info;
950
951 _RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
952 MAC_ARG(psta->cmn.mac_addr));
953 _RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
954 _RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
955 _RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
956 _RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
957 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
958 _RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
959 _RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
960 _RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
961 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
962 _RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
963 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
964 _RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
965 _RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
966
967 curr_tx_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
968 curr_tx_rate = ra_info->curr_tx_rate & 0x7F;
969 _RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
970 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
971 _RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
972 _RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
973 _RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n", ra_info->ramask);
974 }
975
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)976 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
977 {
978 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
979
980 if (psta == NULL) {
981 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
982 rtw_warn_on(1);
983 return;
984 }
985
986 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
987 dump_sta_info(RTW_DBGDUMP, psta);
988 }
989
990 #ifdef CONFIG_LPS_PG
_lps_pg_state_update(_adapter * adapter)991 static void _lps_pg_state_update(_adapter *adapter)
992 {
993 u8 is_in_lpspg = _FALSE;
994 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
995 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
996 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
997 struct sta_priv *pstapriv = &adapter->stapriv;
998 struct sta_info *psta = NULL;
999
1000 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1001 is_in_lpspg = _TRUE;
1002 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1003
1004 if (psta)
1005 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1006 }
1007 #endif
1008
1009 /*#define DBG_PHYDM_STATE_CHK*/
1010
1011
_rtw_phydm_rfk_condition_check(_adapter * adapter)1012 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter)
1013 {
1014 u8 rst = _FALSE;
1015
1016 if (rtw_mi_stayin_union_ch_chk(adapter))
1017 rst = _TRUE;
1018
1019 #ifdef CONFIG_MCC_MODE
1020 /*not in MCC State*/
1021 if (MCC_EN(adapter))
1022 if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
1023 rst = _TRUE;
1024 #endif
1025
1026 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1027
1028 #endif
1029
1030 return rst;
1031 }
1032 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter)1033 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter)
1034 {
1035 u8 rst = _FALSE;
1036 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1037
1038 #if 0
1039 if (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2)
1040 rst = _TRUE;
1041 #else
1042 rst = _TRUE;
1043 #endif
1044 return rst;
1045 }
1046 #endif
rtw_phydm_watchdog(_adapter * adapter)1047 void rtw_phydm_watchdog(_adapter *adapter)
1048 {
1049 u8 bLinked = _FALSE;
1050 u8 bsta_state = _FALSE;
1051 u8 bBtDisabled = _TRUE;
1052 u8 rfk_forbidden = _TRUE;
1053 u8 segment_iqk = _TRUE;
1054 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1055 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
1056
1057 if (!rtw_is_hw_init_completed(adapter)) {
1058 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1059 return;
1060 }
1061 if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY))
1062 pHalData->bScanInProcess = _TRUE;
1063 else
1064 pHalData->bScanInProcess = _FALSE;
1065
1066 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1067 bLinked = _TRUE;
1068 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1069 bsta_state = _TRUE;
1070 }
1071
1072 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1073 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1074
1075 #ifdef CONFIG_BT_COEXIST
1076 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1077 #endif /* CONFIG_BT_COEXIST */
1078 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1079 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1080 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_POWER_TRAINING,
1081 (pHalData->bDisableTXPowerTraining) ? _TRUE : _FALSE);
1082 #ifdef CONFIG_LPS_PG
1083 _lps_pg_state_update(adapter);
1084 #endif
1085
1086 if (bLinked == _TRUE) {
1087 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter) == _TRUE) ? _FALSE : _TRUE;
1088 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1089
1090 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
1091 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter);
1092 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1093 #endif
1094 }
1095
1096 #ifdef DBG_PHYDM_STATE_CHK
1097 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1098 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1099 #endif
1100
1101 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1102 #ifdef DBG_PHYDM_STATE_CHK
1103 RTW_ERR("Not stay in union band, skip phydm\n");
1104 #endif
1105 goto _exit;
1106 }*/
1107 if (pwrctl->bpower_saving)
1108 phydm_watchdog_lps(&pHalData->odmpriv);
1109 else
1110 phydm_watchdog(&pHalData->odmpriv);
1111
1112 #ifdef CONFIG_RTW_ACS
1113 rtw_acs_update_current_info(adapter);
1114 #endif
1115
1116 _exit:
1117 return;
1118 }
1119
1120