1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2015 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifdef CONFIG_MCC_MODE 17 18 #ifndef _RTW_MCC_H_ 19 #define _RTW_MCC_H_ 20 21 #include <drv_types.h> /* PADAPTER */ 22 23 #define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0 24 #define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1 25 #define MCC_STATUS_NEED_MCC BIT2 26 #define MCC_STATUS_DOING_MCC BIT3 27 28 29 #define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ 30 #define MCC_EXPIRE_TIME 50 /* ms */ 31 #define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ 32 #define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */ 33 34 #define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0 35 #define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1 36 37 /* Lower for stop, Higher for start */ 38 #define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0 39 #define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1 40 #define MCC_SETCMD_STATUS_START_CONNECT 0x80 41 #define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81 42 43 /* 44 * depenad platform or customer requirement(TP unit:Mbps), 45 * must be provided by PM or sales or product document 46 * too large value means not to limit tx bytes (current for ap mode) 47 * NOTE: following values ref from test results 48 */ 49 #define MCC_AP_BW20_TARGET_TX_TP (300) 50 #define MCC_AP_BW40_TARGET_TX_TP (300) 51 #define MCC_AP_BW80_TARGET_TX_TP (300) 52 #define MCC_STA_BW20_TARGET_TX_TP (35) 53 #define MCC_STA_BW40_TARGET_TX_TP (70) 54 #define MCC_STA_BW80_TARGET_TX_TP (140) 55 #define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */ 56 57 #define MAX_MCC_NUM 2 58 #define DBG_MCC_REG_NUM 4 59 #define DBG_MCC_RF_REG_NUM 1 60 61 #define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop) 62 #define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc) 63 #define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv)) 64 #define SET_MCC_EN_FLAG(adapter, flag)\ 65 do { \ 66 adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \ 67 } while (0) 68 #define SET_MCC_DURATION(adapter, val)\ 69 do { \ 70 adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \ 71 } while (0) 72 #define SET_MCC_RUNTIME_DURATION(adapter, flag)\ 73 do { \ 74 adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \ 75 } while (0) 76 77 #define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\ 78 do { \ 79 adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \ 80 } while (0) 81 82 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 83 enum mcc_cfg_phydm_ops { 84 MCC_CFG_PHYDM_OFFLOAD = 0, 85 MCC_CFG_PHYDM_RF_CH, 86 MCC_CFG_PHYDM_ADD_CLIENT, 87 MCC_CFG_PHYDM_REMOVE_CLIENT, 88 MCC_CFG_PHYDM_START, 89 MCC_CFG_PHYDM_STOP, 90 MCC_CFG_PHYDM_DUMP, 91 MCC_CFG_PHYDM_MAX, 92 }; 93 #endif 94 95 enum rtw_mcc_cmd_id { 96 MCC_CMD_WK_CID = 0, 97 MCC_SET_DURATION_WK_CID, 98 MCC_GET_DBG_REG_WK_CID, 99 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 100 MCC_SET_PHYDM_OFFLOAD_WK_CID, 101 #endif 102 }; 103 104 /* Represent Channel Tx Null setting */ 105 enum mcc_channel_tx_null { 106 MCC_ENABLE_TX_NULL = 0, 107 MCC_DISABLE_TX_NULL = 1, 108 }; 109 110 /* Represent C2H Report setting */ 111 enum mcc_c2h_report { 112 MCC_C2H_REPORT_DISABLE = 0, 113 MCC_C2H_REPORT_FAIL_STATUS = 1, 114 MCC_C2H_REPORT_ALL_STATUS = 2, 115 }; 116 117 /* Represent Channel Scan */ 118 enum mcc_channel_scan { 119 MCC_CHIDX = 0, 120 MCC_SCANCH_RSVD_LOC = 1, 121 }; 122 123 /* Represent FW status report of channel switch */ 124 enum mcc_status_rpt { 125 MCC_RPT_SUCCESS = 0, 126 MCC_RPT_TXNULL_FAIL = 1, 127 MCC_RPT_STOPMCC = 2, 128 MCC_RPT_READY = 3, 129 MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, 130 MCC_RPT_UPDATE_NOA_START_TIME = 8, 131 MCC_RPT_TSF = 9, 132 MCC_RPT_MAX, 133 }; 134 135 enum mcc_role { 136 MCC_ROLE_STA = 0, 137 MCC_ROLE_AP = 1, 138 MCC_ROLE_GC = 2, 139 MCC_ROLE_GO = 3, 140 MCC_ROLE_MAX, 141 }; 142 143 struct mcc_iqk_backup { 144 u16 TX_X; 145 u16 TX_Y; 146 u16 RX_X; 147 u16 RX_Y; 148 }; 149 150 enum mcc_duration_setting { 151 MCC_DURATION_MAPPING = 0, 152 MCC_DURATION_DIRECET = 1, 153 }; 154 155 enum mcc_sched_mode { 156 MCC_FAIR_SCHEDULE = 0, 157 MCC_FAVOR_STA = 1, 158 MCC_FAVOR_P2P = 2, 159 }; 160 161 /* mcc data for adapter */ 162 struct mcc_adapter_priv { 163 u8 order; /* FW document, softap/AP must be 0 */ 164 enum mcc_role role; /* MCC role(AP,STA,GO,GC) */ 165 u8 mcc_duration; /* channel stay period, UNIT:1TU */ 166 167 /* flow control */ 168 u8 mcc_tx_stop; /* check if tp stop or not */ 169 u8 mcc_tp_limit; /* check if tp limit or not */ 170 u32 mcc_target_tx_bytes_to_port; /* customer require */ 171 u32 mcc_tx_bytes_to_port; /* already tx to tx fifo (write port) */ 172 173 /* data from kernel to check if enqueue data or netif stop queue */ 174 u32 mcc_tp; 175 u64 mcc_tx_bytes_from_kernel; 176 u64 mcc_last_tx_bytes_from_kernel; 177 178 /* Backup IQK value for MCC */ 179 struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH]; 180 181 /* mgmt queue macid to avoid RA issue */ 182 u8 mgmt_queue_macid; 183 184 /* set macid bitmap to let fw know which macid should be tx pause */ 185 /* all interface share total 16 macid */ 186 u16 mcc_macid_bitmap; 187 188 /* use for NoA start time (unit: mircoseconds) */ 189 u32 noa_start_time; 190 191 u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; 192 u32 p2p_go_noa_ie_len; 193 u64 tsf; 194 #ifdef CONFIG_TDLS 195 u8 backup_tdls_en; 196 #endif /* CONFIG_TDLS */ 197 198 u8 null_early; 199 u8 null_rty_num; 200 }; 201 202 struct mcc_obj_priv { 203 u8 en_mcc; /* enable MCC or not */ 204 u8 duration; /* store duration(%) from registry, for primary adapter */ 205 u8 interval; 206 u8 start_time; 207 u8 mcc_c2h_status; 208 u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */ 209 u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */ 210 u8 mcc_tolerance_time; /* used for detect mcc switch channel success */ 211 u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ 212 u8 mcc_status; /* mcc status stop or start .... */ 213 u8 policy_index; 214 u8 mcc_stop_threshold; 215 u8 current_order; 216 u8 last_tsfdiff; 217 systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ 218 _mutex mcc_mutex; 219 _lock mcc_lock; 220 PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */ 221 struct submit_ctx mcc_sctx; 222 struct submit_ctx mcc_tsf_req_sctx; 223 _mutex mcc_tsf_req_mutex; 224 u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */ 225 #ifdef CONFIG_MCC_MODE_V2 226 u8 mcc_iqk_value_rsvd_page[3]; 227 #endif /* CONFIG_MCC_MODE_V2 */ 228 u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM]; 229 u8 enable_runtime_duration; 230 /* for LG */ 231 u8 mchan_sched_mode; 232 233 _mutex mcc_dbg_reg_mutex; 234 u32 dbg_reg[DBG_MCC_REG_NUM]; 235 u32 dbg_reg_val[DBG_MCC_REG_NUM]; 236 u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM]; 237 u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH]; 238 u8 mcc_phydm_offload; 239 }; 240 241 /* backup IQK val */ 242 void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter); 243 244 /* check mcc status */ 245 u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status); 246 247 /* set mcc status */ 248 void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status); 249 250 /* clear mcc status */ 251 void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status); 252 253 /* dl mcc rsvd page */ 254 u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index 255 , u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num); 256 257 /* handle C2H */ 258 void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf); 259 260 /* switch channel successfully or not */ 261 void rtw_hal_mcc_sw_status_check(PADAPTER padapter); 262 263 /* change some scan flags under site survey */ 264 u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset); 265 266 /* record data kernel TX to driver to check MCC concurrent TX */ 267 void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len); 268 269 /* record data to port to let driver do flow ctrl */ 270 void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len); 271 272 /* check stop write port or not */ 273 u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter); 274 275 u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter); 276 277 u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter); 278 279 u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped); 280 281 u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter); 282 283 u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter); 284 285 u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow); 286 287 void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj); 288 289 void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); 290 291 u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg); 292 293 void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); 294 295 u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); 296 297 void rtw_hal_dump_mcc_policy_table(void *sel); 298 299 void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add); 300 301 void rtw_hal_mcc_process_noa(PADAPTER padapter); 302 303 void rtw_hal_mcc_parameter_init(PADAPTER padapter); 304 305 u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val); 306 307 u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val); 308 #ifdef CONFIG_MCC_PHYDM_OFFLOAD 309 u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue); 310 #endif /* CONFIG_MCC_PHYDM_OFFLOAD */ 311 #endif /* _RTW_MCC_H_ */ 312 #endif /* CONFIG_MCC_MODE */ 313