1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __HAL_DATA_H__ 17 #define __HAL_DATA_H__ 18 19 #if 1/* def CONFIG_SINGLE_IMG */ 20 21 #include "../hal/phydm/phydm_precomp.h" 22 #ifdef CONFIG_BT_COEXIST 23 #include <hal_btcoex.h> 24 #endif 25 #include <hal_btcoex_wifionly.h> 26 27 #ifdef CONFIG_SDIO_HCI 28 #include <hal_sdio.h> 29 #endif 30 #ifdef CONFIG_GSPI_HCI 31 #include <hal_gspi.h> 32 #endif 33 34 #if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) 35 #include "../hal/hal_dm_acs.h" 36 #endif 37 38 /* 39 * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. 40 * */ 41 typedef enum _RT_MULTI_FUNC { 42 RT_MULTI_FUNC_NONE = 0x00, 43 RT_MULTI_FUNC_WIFI = 0x01, 44 RT_MULTI_FUNC_BT = 0x02, 45 RT_MULTI_FUNC_GPS = 0x04, 46 } RT_MULTI_FUNC, *PRT_MULTI_FUNC; 47 /* 48 * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. 49 * */ 50 typedef enum _RT_POLARITY_CTL { 51 RT_POLARITY_LOW_ACT = 0, 52 RT_POLARITY_HIGH_ACT = 1, 53 } RT_POLARITY_CTL, *PRT_POLARITY_CTL; 54 55 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 56 typedef enum _RT_REGULATOR_MODE { 57 RT_SWITCHING_REGULATOR = 0, 58 RT_LDO_REGULATOR = 1, 59 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; 60 61 /* 62 * Interface type. 63 * */ 64 typedef enum _INTERFACE_SELECT_PCIE { 65 INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ 66 INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ 67 INTF_SEL2_PCIe = 2, /* PCIe Card */ 68 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; 69 70 71 typedef enum _INTERFACE_SELECT_USB { 72 INTF_SEL0_USB = 0, /* USB */ 73 INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ 74 INTF_SEL2_MINICARD = 2, /* Minicard */ 75 INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ 76 INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ 77 INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ 78 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; 79 80 typedef enum _RT_AMPDU_BRUST_MODE { 81 RT_AMPDU_BRUST_NONE = 0, 82 RT_AMPDU_BRUST_92D = 1, 83 RT_AMPDU_BRUST_88E = 2, 84 RT_AMPDU_BRUST_8812_4 = 3, 85 RT_AMPDU_BRUST_8812_8 = 4, 86 RT_AMPDU_BRUST_8812_12 = 5, 87 RT_AMPDU_BRUST_8812_15 = 6, 88 RT_AMPDU_BRUST_8723B = 7, 89 } RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; 90 91 /* Tx Power Limit Table Size */ 92 #define MAX_REGULATION_NUM 4 93 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 94 #define MAX_2_4G_BANDWIDTH_NUM 2 95 #define MAX_RATE_SECTION_NUM 10 96 #define MAX_5G_BANDWIDTH_NUM 4 97 98 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 99 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ 100 101 #ifdef RTW_RX_AGGREGATION 102 typedef enum _RX_AGG_MODE { 103 RX_AGG_DISABLE, 104 RX_AGG_DMA, 105 RX_AGG_USB, 106 RX_AGG_MIX 107 } RX_AGG_MODE; 108 109 /* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */ 110 111 #endif /* RTW_RX_AGGREGATION */ 112 113 /* E-Fuse */ 114 #ifdef CONFIG_RTL8188E 115 #define EFUSE_MAP_SIZE 512 116 #endif 117 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) 118 #define EFUSE_MAP_SIZE 512 119 #endif 120 #ifdef CONFIG_RTL8192E 121 #define EFUSE_MAP_SIZE 512 122 #endif 123 #ifdef CONFIG_RTL8723B 124 #define EFUSE_MAP_SIZE 512 125 #endif 126 #ifdef CONFIG_RTL8814A 127 #define EFUSE_MAP_SIZE 512 128 #endif 129 #ifdef CONFIG_RTL8703B 130 #define EFUSE_MAP_SIZE 512 131 #endif 132 #ifdef CONFIG_RTL8723D 133 #define EFUSE_MAP_SIZE 512 134 #endif 135 #ifdef CONFIG_RTL8188F 136 #define EFUSE_MAP_SIZE 512 137 #endif 138 #ifdef CONFIG_RTL8188GTV 139 #define EFUSE_MAP_SIZE 512 140 #endif 141 #ifdef CONFIG_RTL8710B 142 #define EFUSE_MAP_SIZE 512 143 #endif 144 #ifdef CONFIG_RTL8192F 145 #define EFUSE_MAP_SIZE 512 146 #endif 147 148 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) 149 #define EFUSE_MAX_SIZE 1024 150 #elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B) 151 #define EFUSE_MAX_SIZE 256 152 #else 153 #define EFUSE_MAX_SIZE 512 154 #endif 155 /* end of E-Fuse */ 156 157 #define Mac_OFDM_OK 0x00000000 158 #define Mac_OFDM_Fail 0x10000000 159 #define Mac_OFDM_FasleAlarm 0x20000000 160 #define Mac_CCK_OK 0x30000000 161 #define Mac_CCK_Fail 0x40000000 162 #define Mac_CCK_FasleAlarm 0x50000000 163 #define Mac_HT_OK 0x60000000 164 #define Mac_HT_Fail 0x70000000 165 #define Mac_HT_FasleAlarm 0x90000000 166 #define Mac_DropPacket 0xA0000000 167 168 #ifdef CONFIG_RF_POWER_TRIM 169 #if defined(CONFIG_RTL8723B) 170 #define REG_RF_BB_GAIN_OFFSET 0x7f 171 #define RF_GAIN_OFFSET_MASK 0xfffff 172 #elif defined(CONFIG_RTL8188E) 173 #define REG_RF_BB_GAIN_OFFSET 0x55 174 #define RF_GAIN_OFFSET_MASK 0xfffff 175 #else 176 #define REG_RF_BB_GAIN_OFFSET 0x55 177 #define RF_GAIN_OFFSET_MASK 0xfffff 178 #endif /* CONFIG_RTL8723B */ 179 #endif /*CONFIG_RF_POWER_TRIM*/ 180 181 /* For store initial value of BB register */ 182 typedef struct _BB_INIT_REGISTER { 183 u16 offset; 184 u32 value; 185 186 } BB_INIT_REGISTER, *PBB_INIT_REGISTER; 187 188 #define PAGE_SIZE_128 128 189 #define PAGE_SIZE_256 256 190 #define PAGE_SIZE_512 512 191 192 #define HCI_SUS_ENTER 0 193 #define HCI_SUS_LEAVING 1 194 #define HCI_SUS_LEAVE 2 195 #define HCI_SUS_ENTERING 3 196 #define HCI_SUS_ERR 4 197 198 #define EFUSE_FILE_UNUSED 0 199 #define EFUSE_FILE_FAILED 1 200 #define EFUSE_FILE_LOADED 2 201 202 #define MACADDR_FILE_UNUSED 0 203 #define MACADDR_FILE_FAILED 1 204 #define MACADDR_FILE_LOADED 2 205 206 #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 207 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 208 209 struct kfree_data_t { 210 u8 flag; 211 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; 212 213 #ifdef CONFIG_IEEE80211_BAND_5GHZ 214 s8 pa_bias_5g[RF_PATH_MAX]; 215 s8 pad_bias_5g[RF_PATH_MAX]; 216 #endif 217 s8 thermal; 218 }; 219 220 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); 221 222 struct hal_spec_t { 223 char *ic_name; 224 u8 macid_num; 225 226 u8 sec_cam_ent_num; 227 u8 sec_cap; 228 u8 macid_cap; 229 u16 macid_txrpt; 230 u8 macid_txrpt_pgsz; 231 232 u8 rfpath_num_2g:4; /* used for tx power index path */ 233 u8 rfpath_num_5g:4; /* used for tx power index path */ 234 u8 txgi_max; /* maximum tx power gain index */ 235 u8 txgi_pdbm; /* tx power gain index per dBm */ 236 237 u8 max_tx_cnt; 238 u8 tx_nss_num:4; 239 u8 rx_nss_num:4; 240 u8 band_cap; /* value of BAND_CAP_XXX */ 241 u8 bw_cap; /* value of BW_CAP_XXX */ 242 u8 port_num; 243 u8 proto_cap; /* value of PROTO_CAP_XXX */ 244 u8 wl_func; /* value of WL_FUNC_XXX */ 245 246 #if CONFIG_TX_AC_LIFETIME 247 u8 tx_aclt_unit_factor; /* how many 32us */ 248 #endif 249 250 u8 rx_tsf_filter:1; 251 252 u8 pg_txpwr_saddr; /* starting address of PG tx power info */ 253 u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */ 254 255 u8 hci_type; /* value of HCI Type */ 256 }; 257 258 #define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) 259 #define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) 260 #define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ 261 _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ 262 _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) 263 264 #define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx)) 265 266 #ifdef CONFIG_PHY_CAPABILITY_QUERY 267 struct phy_spec_t { 268 u32 trx_cap; 269 u32 stbc_cap; 270 u32 ldpc_cap; 271 u32 txbf_param; 272 u32 txbf_cap; 273 }; 274 #endif 275 struct hal_iqk_reg_backup { 276 u8 central_chnl; 277 u8 bw_mode; 278 u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; 279 }; 280 281 282 typedef struct hal_p2p_ps_para { 283 /*DW0*/ 284 u8 offload_en:1; 285 u8 role:1; 286 u8 ctwindow_en:1; 287 u8 noa_en:1; 288 u8 noa_sel:1; 289 u8 all_sta_sleep:1; 290 u8 discovery:1; 291 u8 disable_close_rf:1; 292 u8 p2p_port_id; 293 u8 p2p_group; 294 u8 p2p_macid; 295 296 /*DW1*/ 297 u8 ctwindow_length; 298 u8 rsvd3; 299 u8 rsvd4; 300 u8 rsvd5; 301 302 /*DW2*/ 303 u32 noa_duration_para; 304 305 /*DW3*/ 306 u32 noa_interval_para; 307 308 /*DW4*/ 309 u32 noa_start_time_para; 310 311 /*DW5*/ 312 u32 noa_count_para; 313 } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; 314 315 #define TXPWR_LMT_RS_CCK 0 316 #define TXPWR_LMT_RS_OFDM 1 317 #define TXPWR_LMT_RS_HT 2 318 #define TXPWR_LMT_RS_VHT 3 319 #define TXPWR_LMT_RS_NUM 4 320 321 #define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ 322 #define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ 323 324 #if CONFIG_TXPWR_LIMIT 325 extern const char *const _txpwr_lmt_rs_str[]; 326 #define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) 327 328 struct txpwr_lmt_ent { 329 _list list; 330 331 s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] 332 [TXPWR_LMT_RS_NUM_2G] 333 [CENTER_CH_2G_NUM] 334 [MAX_TX_COUNT]; 335 336 #ifdef CONFIG_IEEE80211_BAND_5GHZ 337 s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] 338 [TXPWR_LMT_RS_NUM_5G] 339 [CENTER_CH_5G_ALL_NUM] 340 [MAX_TX_COUNT]; 341 #endif 342 343 char regd_name[0]; 344 }; 345 #endif /* CONFIG_TXPWR_LIMIT */ 346 347 typedef struct hal_com_data { 348 HAL_VERSION version_id; 349 RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ 350 RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ 351 RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ 352 u8 hw_init_completed; 353 /****** FW related ******/ 354 u32 firmware_size; 355 u16 firmware_version; 356 u16 FirmwareVersionRev; 357 u16 firmware_sub_version; 358 u16 FirmwareSignature; 359 u8 RegFWOffload; 360 u8 bFWReady; 361 u8 bBTFWReady; 362 u8 fw_ractrl; 363 u8 LastHMEBoxNum; /* H2C - for host message to fw */ 364 #ifdef CONFIG_LPS_1T1R 365 u8 lps_1t1r; 366 #endif 367 368 /****** current WIFI_PHY values ******/ 369 WIRELESS_MODE CurrentWirelessMode; 370 enum channel_width current_channel_bw; 371 BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ 372 BAND_TYPE BandSet; 373 u8 current_channel; 374 u8 cch_20; 375 u8 cch_40; 376 u8 cch_80; 377 u8 CurrentCenterFrequencyIndex1; 378 u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ 379 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 380 BOOLEAN bSwChnlAndSetBWInProgress; 381 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 382 u16 BasicRateSet; 383 u32 ReceiveConfig; 384 u32 rcr_backup; /* used for switching back from monitor mode */ 385 u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ 386 BOOLEAN bSwChnl; 387 BOOLEAN bSetChnlBW; 388 BOOLEAN bSWToBW40M; 389 BOOLEAN bSWToBW80M; 390 BOOLEAN bChnlBWInitialized; 391 u32 BackUp_BB_REG_4_2nd_CCA[3]; 392 393 #ifdef CONFIG_RTW_ACS 394 struct auto_chan_sel acs; 395 #endif 396 #ifdef CONFIG_BCN_RECOVERY 397 u8 issue_bcn_fail; 398 #endif /*CONFIG_BCN_RECOVERY*/ 399 400 /****** rf_ctrl *****/ 401 u8 rf_chip; 402 u8 rf_type; /*enum rf_type*/ 403 u8 PackageType; 404 u8 NumTotalRFPath; 405 u8 antenna_test; 406 407 /****** Debug ******/ 408 u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 409 u8 bDumpRxPkt; 410 u8 bDumpTxPkt; 411 u8 dis_turboedca; /* 1: disable turboedca, 412 2: disable turboedca and setting EDCA parameter based on the input parameter*/ 413 u32 edca_param_mode; 414 415 /****** EEPROM setting.******/ 416 u8 bautoload_fail_flag; 417 u8 efuse_file_status; 418 u8 macaddr_file_status; 419 u8 EepromOrEfuse; 420 u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ 421 u8 InterfaceSel; /* board type kept in eFuse */ 422 u16 CustomerID; 423 424 u16 EEPROMVID; 425 u16 EEPROMSVID; 426 #ifdef CONFIG_USB_HCI 427 u8 EEPROMUsbSwitch; 428 u16 EEPROMPID; 429 u16 EEPROMSDID; 430 #endif 431 #ifdef CONFIG_PCI_HCI 432 u16 EEPROMDID; 433 u16 EEPROMSMID; 434 #endif 435 436 u8 EEPROMCustomerID; 437 u8 EEPROMSubCustomerID; 438 u8 EEPROMVersion; 439 u8 EEPROMRegulatory; 440 u8 eeprom_thermal_meter; 441 u8 EEPROMBluetoothCoexist; 442 u8 EEPROMBluetoothType; 443 u8 EEPROMBluetoothAntNum; 444 u8 EEPROMBluetoothAntIsolation; 445 u8 EEPROMBluetoothRadioShared; 446 u8 EEPROMMACAddr[ETH_ALEN]; 447 u8 tx_bbswing_24G; 448 u8 tx_bbswing_5G; 449 u8 efuse0x3d7; /* efuse[0x3D7] */ 450 u8 efuse0x3d8; /* efuse[0x3D8] */ 451 452 #ifdef CONFIG_RF_POWER_TRIM 453 u8 EEPROMRFGainOffset; 454 u8 EEPROMRFGainVal; 455 struct kfree_data_t kfree_data; 456 #endif /*CONFIG_RF_POWER_TRIM*/ 457 458 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ 459 defined(CONFIG_RTL8723D) || \ 460 defined(CONFIG_RTL8192F) 461 462 u8 adjuseVoltageVal; 463 u8 need_restore; 464 #endif 465 u8 EfuseUsedPercentage; 466 u16 EfuseUsedBytes; 467 /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ 468 EFUSE_HAL EfuseHal; 469 470 /*---------------------------------------------------------------------------------*/ 471 /* 2.4G TX power info for target TX power*/ 472 u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 473 u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; 474 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 475 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 476 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 477 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 478 479 /* 5G TX power info for target TX power*/ 480 #ifdef CONFIG_IEEE80211_BAND_5GHZ 481 u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; 482 u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; 483 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 484 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 485 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 486 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 487 #endif 488 489 u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] 490 [TX_PWR_BY_RATE_NUM_RF]; 491 492 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] 493 [TX_PWR_BY_RATE_NUM_RF] 494 [TX_PWR_BY_RATE_NUM_RATE]; 495 496 /* Store the original power by rate value of the base rate for each rate section and rf path */ 497 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 498 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 499 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] 500 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 501 502 #if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) 503 u32 txagc_set_buf; 504 #endif 505 506 u8 txpwr_by_rate_loaded:1; 507 u8 txpwr_by_rate_from_file:1; 508 u8 txpwr_limit_loaded:1; 509 u8 txpwr_limit_from_file:1; 510 u8 rf_power_tracking_type; 511 512 /* Read/write are allow for following hardware information variables */ 513 u8 crystal_cap; 514 515 u8 PAType_2G; 516 u8 PAType_5G; 517 u8 LNAType_2G; 518 u8 LNAType_5G; 519 u8 ExternalPA_2G; 520 u8 ExternalLNA_2G; 521 u8 external_pa_5g; 522 u8 external_lna_5g; 523 u16 TypeGLNA; 524 u16 TypeGPA; 525 u16 TypeALNA; 526 u16 TypeAPA; 527 u16 rfe_type; 528 529 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 530 u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ 531 u8 is_turbo_edca; 532 u8 prv_traffic_idx; 533 BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ 534 535 u32 RfRegChnlVal[MAX_RF_PATH]; 536 537 /* RDG enable */ 538 BOOLEAN bRDGEnable; 539 540 #if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) 541 u32 RegRRSR; 542 #endif 543 544 /****** antenna diversity ******/ 545 u8 AntDivCfg; 546 u8 with_extenal_ant_switch; 547 u8 b_fix_tx_ant; 548 u8 AntDetection; 549 u8 TRxAntDivType; 550 u8 ant_path; /* for 8723B s0/s1 selection */ 551 u32 antenna_tx_path; /* Antenna path Tx */ 552 u32 AntennaRxPath; /* Antenna path Rx */ 553 u8 sw_antdiv_bl_state; 554 555 /******** PHY DM & DM Section **********/ 556 _lock IQKSpinLock; 557 u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; 558 559 struct dm_struct odmpriv; 560 u64 bk_rf_ability; 561 u8 bIQKInitialized; 562 u8 bNeedIQK; 563 u8 neediqk_24g; 564 u8 IQK_MP_Switch; 565 u8 bScanInProcess; 566 /******** PHY DM & DM Section **********/ 567 568 569 570 /* 2010/08/09 MH Add CU power down mode. */ 571 BOOLEAN pwrdown; 572 573 /* Add for dual MAC 0--Mac0 1--Mac1 */ 574 u32 interfaceIndex; 575 576 #ifdef CONFIG_P2P 577 #ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 578 u16 p2p_ps_offload; 579 #else 580 u8 p2p_ps_offload; 581 #endif 582 #endif 583 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 584 u8 bMacPwrCtrlOn; 585 u8 hci_sus_state; 586 587 u8 RegIQKFWOffload; 588 struct submit_ctx iqk_sctx; 589 u8 ch_switch_offload; 590 struct submit_ctx chsw_sctx; 591 592 RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 593 594 u8 OutEpQueueSel; 595 u8 OutEpNumber; 596 597 #ifdef RTW_RX_AGGREGATION 598 RX_AGG_MODE rxagg_mode; 599 600 /* For RX Aggregation DMA Mode */ 601 u8 rxagg_dma_size; 602 u8 rxagg_dma_timeout; 603 #endif /* RTW_RX_AGGREGATION */ 604 605 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 606 /* */ 607 /* For SDIO Interface HAL related */ 608 /* */ 609 610 /* */ 611 /* SDIO ISR Related */ 612 /* 613 * u32 IntrMask[1]; 614 * u32 IntrMaskToSet[1]; 615 * LOG_INTERRUPT InterruptLog; */ 616 u32 sdio_himr; 617 u32 sdio_hisr; 618 #ifndef RTW_HALMAC 619 /* */ 620 /* SDIO Tx FIFO related. */ 621 /* */ 622 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 623 #ifdef CONFIG_RTL8192F 624 u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 625 #else 626 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 627 #endif/*CONFIG_RTL8192F*/ 628 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT 629 u8 sdio_avail_int_en_q; 630 #endif 631 _lock SdioTxFIFOFreePageLock; 632 u8 SdioTxOQTMaxFreeSpace; 633 u8 SdioTxOQTFreeSpace; 634 #else /* RTW_HALMAC */ 635 u16 SdioTxOQTFreeSpace; 636 #endif /* RTW_HALMAC */ 637 638 /* */ 639 /* SDIO Rx FIFO related. */ 640 /* */ 641 u8 SdioRxFIFOCnt; 642 #ifdef CONFIG_RTL8822C 643 u32 SdioRxFIFOSize; 644 #else 645 u16 SdioRxFIFOSize; 646 #endif 647 648 #ifndef RTW_HALMAC 649 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 650 #else 651 #ifdef CONFIG_RTL8821C 652 u16 tx_high_page; 653 u16 tx_low_page; 654 u16 tx_normal_page; 655 u16 tx_extra_page; 656 u16 tx_pub_page; 657 u8 max_oqt_size; 658 #ifdef XMIT_BUF_SIZE 659 u32 max_xmit_size_vovi; 660 u32 max_xmit_size_bebk; 661 #endif /*XMIT_BUF_SIZE*/ 662 u16 max_xmit_page; 663 u16 max_xmit_page_vo; 664 u16 max_xmit_page_vi; 665 u16 max_xmit_page_be; 666 u16 max_xmit_page_bk; 667 668 #endif /*#ifdef CONFIG_RTL8821C*/ 669 #endif /* !RTW_HALMAC */ 670 #endif /* CONFIG_SDIO_HCI */ 671 672 #ifdef CONFIG_USB_HCI 673 674 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ 675 BOOLEAN UsbRxHighSpeedMode; 676 BOOLEAN UsbTxVeryHighSpeedMode; 677 u32 UsbBulkOutSize; 678 BOOLEAN bSupportUSB3; 679 u8 usb_intf_start; 680 681 /* Interrupt relatd register information. */ 682 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 683 u32 IntrMask[3]; 684 #ifdef CONFIG_USB_TX_AGGREGATION 685 u8 UsbTxAggMode; 686 u8 UsbTxAggDescNum; 687 #endif /* CONFIG_USB_TX_AGGREGATION */ 688 689 #ifdef CONFIG_USB_RX_AGGREGATION 690 u16 HwRxPageSize; /* Hardware setting */ 691 692 /* For RX Aggregation USB Mode */ 693 u8 rxagg_usb_size; 694 u8 rxagg_usb_timeout; 695 #endif/* CONFIG_USB_RX_AGGREGATION */ 696 #endif /* CONFIG_USB_HCI */ 697 698 699 #ifdef CONFIG_PCI_HCI 700 /* */ 701 /* EEPROM setting. */ 702 /* */ 703 u32 TransmitConfig; 704 u32 IntrMaskToSet[2]; 705 u32 IntArray[4]; 706 u32 IntrMask[4]; 707 u32 SysIntArray[1]; 708 u32 SysIntrMask[1]; 709 u32 IntrMaskReg[2]; 710 u32 IntrMaskDefault[4]; 711 712 BOOLEAN bL1OffSupport; 713 BOOLEAN bSupportBackDoor; 714 u32 pci_backdoor_ctrl; 715 716 u8 bDefaultAntenna; 717 718 u8 bInterruptMigration; 719 u8 bDisableTxInt; 720 721 u16 RxTag; 722 #ifdef CONFIG_PCI_DYNAMIC_ASPM 723 BOOLEAN bAspmL1LastIdle; 724 #endif 725 #endif /* CONFIG_PCI_HCI */ 726 727 728 #ifdef DBG_CONFIG_ERROR_DETECT 729 struct sreset_priv srestpriv; 730 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */ 731 732 #ifdef CONFIG_BT_COEXIST 733 /* For bluetooth co-existance */ 734 BT_COEXIST bt_coexist; 735 #endif /* CONFIG_BT_COEXIST */ 736 737 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ 738 || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F) 739 #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ 740 /* Interrupt relatd register information. */ 741 u32 SysIntrStatus; 742 u32 SysIntrMask; 743 #endif 744 #endif /*endif CONFIG_RTL8723B */ 745 746 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 747 char para_file_buf[MAX_PARA_FILE_BUF_LEN]; 748 char *mac_reg; 749 u32 mac_reg_len; 750 char *bb_phy_reg; 751 u32 bb_phy_reg_len; 752 char *bb_agc_tab; 753 u32 bb_agc_tab_len; 754 char *bb_phy_reg_pg; 755 u32 bb_phy_reg_pg_len; 756 char *bb_phy_reg_mp; 757 u32 bb_phy_reg_mp_len; 758 char *rf_radio_a; 759 u32 rf_radio_a_len; 760 char *rf_radio_b; 761 u32 rf_radio_b_len; 762 char *rf_tx_pwr_track; 763 u32 rf_tx_pwr_track_len; 764 char *rf_tx_pwr_lmt; 765 u32 rf_tx_pwr_lmt_len; 766 #endif 767 768 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR 769 struct noise_monitor nm; 770 #endif 771 772 struct hal_spec_t hal_spec; 773 #ifdef CONFIG_PHY_CAPABILITY_QUERY 774 struct phy_spec_t phy_spec; 775 #endif 776 u8 RfKFreeEnable; 777 u8 RfKFree_ch_group; 778 BOOLEAN bCCKinCH14; 779 BB_INIT_REGISTER RegForRecover[5]; 780 781 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) 782 BOOLEAN bCorrectBCN; 783 #endif 784 u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ 785 u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ 786 787 struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; 788 789 #ifdef RTW_HALMAC 790 u16 drv_rsvd_page_number; 791 #endif 792 793 #ifdef CONFIG_BEAMFORMING 794 u8 backup_snd_ptcl_ctrl; 795 #ifdef RTW_BEAMFORMING_VERSION_2 796 struct beamforming_info beamforming_info; 797 #endif /* RTW_BEAMFORMING_VERSION_2 */ 798 #endif /* CONFIG_BEAMFORMING */ 799 800 u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ 801 u8 phydm_op_mode; 802 803 u8 in_cta_test; 804 805 #ifdef CONFIG_RTW_LED 806 struct led_priv led; 807 #endif 808 /* for multi channel case (ex: MCC/TDLS) */ 809 u8 multi_ch_switch_mode; 810 811 } HAL_DATA_COMMON, *PHAL_DATA_COMMON; 812 813 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; 814 #define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) 815 #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) 816 #define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) 817 818 #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) 819 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 820 #define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) 821 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) 822 823 #define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ 824 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ 825 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) 826 827 #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) 828 #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) 829 #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) 830 #define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) 831 #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) 832 #endif 833 834 #ifdef RTW_HALMAC 835 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 836 #endif /* RTW_HALMAC */ 837 838 #endif /* __HAL_DATA_H__ */ 839