1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8188EPHYCFG_H__ 17 #define __INC_HAL8188EPHYCFG_H__ 18 19 20 /*--------------------------Define Parameters-------------------------------*/ 21 #define LOOP_LIMIT 5 22 #define MAX_STALL_TIME 50 /* us */ 23 #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 24 #define MAX_TXPWR_IDX_NMODE_92S 63 25 #define Reset_Cnt_Limit 3 26 27 #ifdef CONFIG_PCI_HCI 28 #define MAX_AGGR_NUM 0x0B 29 #else 30 #define MAX_AGGR_NUM 0x07 31 #endif /* CONFIG_PCI_HCI */ 32 33 34 /*--------------------------Define Parameters-------------------------------*/ 35 36 37 /*------------------------------Define structure----------------------------*/ 38 39 #define MAX_TX_COUNT_8188E 1 40 41 /* BB/RF related */ 42 43 44 /*------------------------------Define structure----------------------------*/ 45 46 47 /*------------------------Export global variable----------------------------*/ 48 /*------------------------Export global variable----------------------------*/ 49 50 51 /*------------------------Export Marco Definition---------------------------*/ 52 /*------------------------Export Marco Definition---------------------------*/ 53 54 55 /*--------------------------Exported Function prototype---------------------*/ 56 /* 57 * BB and RF register read/write 58 * */ 59 u32 PHY_QueryBBReg8188E(PADAPTER Adapter, 60 u32 RegAddr, 61 u32 BitMask); 62 void PHY_SetBBReg8188E(PADAPTER Adapter, 63 u32 RegAddr, 64 u32 BitMask, 65 u32 Data); 66 u32 PHY_QueryRFReg8188E(PADAPTER Adapter, 67 enum rf_path eRFPath, 68 u32 RegAddr, 69 u32 BitMask); 70 void PHY_SetRFReg8188E(PADAPTER Adapter, 71 enum rf_path eRFPath, 72 u32 RegAddr, 73 u32 BitMask, 74 u32 Data); 75 76 /* 77 * Initialization related function 78 */ 79 /* MAC/BB/RF HAL config */ 80 int PHY_MACConfig8188E(PADAPTER Adapter); 81 int PHY_BBConfig8188E(PADAPTER Adapter); 82 int PHY_RFConfig8188E(PADAPTER Adapter); 83 84 /* RF config */ 85 int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath); 86 87 /* 88 * RF Power setting 89 */ 90 /* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter, 91 * RT_RF_POWER_STATE eRFPowerState); */ 92 93 /* 94 * BB TX Power R/W 95 * */ 96 void PHY_SetTxPowerLevel8188E(PADAPTER Adapter, 97 u8 channel); 98 99 void 100 PHY_SetTxPowerIndex_8188E( 101 PADAPTER Adapter, 102 u32 PowerIndex, 103 enum rf_path RFPath, 104 u8 Rate 105 ); 106 107 u8 108 PHY_GetTxPowerIndex_8188E( 109 PADAPTER pAdapter, 110 enum rf_path RFPath, 111 u8 Rate, 112 u8 BandWidth, 113 u8 Channel, 114 struct txpwr_idx_comp *tic 115 ); 116 117 /* 118 * Switch bandwidth for 8192S 119 */ 120 /* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */ 121 void PHY_SetBWMode8188E(PADAPTER pAdapter, 122 enum channel_width ChnlWidth, 123 unsigned char Offset); 124 125 /* 126 * Set FW CMD IO for 8192S. 127 */ 128 /* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter, 129 * IO_TYPE IOType); */ 130 131 /* 132 * Set A2 entry to fw for 8192S 133 * */ 134 extern void FillA2Entry8192C(PADAPTER Adapter, 135 u8 index, 136 u8 *val); 137 138 139 /* 140 * channel switch related funciton 141 */ 142 /* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */ 143 void PHY_SwChnl8188E(PADAPTER pAdapter, 144 u8 channel); 145 146 void 147 PHY_SetSwChnlBWMode8188E( 148 PADAPTER Adapter, 149 u8 channel, 150 enum channel_width Bandwidth, 151 u8 Offset40, 152 u8 Offset80 153 ); 154 155 void 156 PHY_SetRFEReg_8188E( 157 PADAPTER Adapter 158 ); 159 /* 160 * BB/MAC/RF other monitor API 161 * */ 162 void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain); 163 164 extern void 165 PHY_SwitchEphyParameter( 166 PADAPTER Adapter 167 ); 168 169 extern void 170 PHY_EnableHostClkReq( 171 PADAPTER Adapter 172 ); 173 174 BOOLEAN 175 SetAntennaConfig92C( 176 PADAPTER Adapter, 177 u8 DefaultAnt 178 ); 179 180 /*--------------------------Exported Function prototype---------------------*/ 181 182 /* 183 * Initialization related function 184 * 185 * MAC/BB/RF HAL config */ 186 /* extern s32 PHY_MACConfig8723(PADAPTER padapter); 187 * s32 PHY_BBConfig8723(PADAPTER padapter); 188 * s32 PHY_RFConfig8723(PADAPTER padapter); */ 189 190 191 192 /* ****************************************************************** 193 * Note: If SIC_ENABLE under PCIE, because of the slow operation 194 * you should 195 * 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows 196 * 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed. 197 * */ 198 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1) 199 #define SIC_ENABLE 1 200 #define SIC_HW_SUPPORT 1 201 #else 202 #define SIC_ENABLE 0 203 #define SIC_HW_SUPPORT 0 204 #endif 205 /* ****************************************************************** */ 206 207 208 #define SIC_MAX_POLL_CNT 5 209 210 #if (SIC_HW_SUPPORT == 1) 211 #define SIC_CMD_READY 0 212 #define SIC_CMD_PREWRITE 0x1 213 #if (RTL8188E_SUPPORT == 1) 214 #define SIC_CMD_WRITE 0x40 215 #define SIC_CMD_PREREAD 0x2 216 #define SIC_CMD_READ 0x80 217 #define SIC_CMD_INIT 0xf0 218 #define SIC_INIT_VAL 0xff 219 220 #define SIC_INIT_REG 0x1b7 221 #define SIC_CMD_REG 0x1EB /* 1byte */ 222 #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */ 223 #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */ 224 #else 225 #define SIC_CMD_WRITE 0x11 226 #define SIC_CMD_PREREAD 0x2 227 #define SIC_CMD_READ 0x12 228 #define SIC_CMD_INIT 0x1f 229 #define SIC_INIT_VAL 0xff 230 231 #define SIC_INIT_REG 0x1b7 232 #define SIC_CMD_REG 0x1b6 /* 1byte */ 233 #define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */ 234 #define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */ 235 #endif 236 #else 237 #define SIC_CMD_READY 0 238 #define SIC_CMD_WRITE 1 239 #define SIC_CMD_READ 2 240 241 #if (RTL8188E_SUPPORT == 1) 242 #define SIC_CMD_REG 0x1EB /* 1byte */ 243 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 244 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 245 #else 246 #define SIC_CMD_REG 0x1b8 /* 1byte */ 247 #define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */ 248 #define SIC_DATA_REG 0x1bc /* 1bc~1bf */ 249 #endif 250 #endif 251 252 #if (SIC_ENABLE == 1) 253 void SIC_Init( PADAPTER Adapter); 254 #endif 255 256 257 #endif /* __INC_HAL8192CPHYCFG_H */ 258