1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in the 16 * file called LICENSE. 17 * 18 * Contact Information: 19 * wlanfae <wlanfae@realtek.com> 20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 21 * Hsinchu 300, Taiwan. 22 * 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 *****************************************************************************/ 26 27 #ifndef __HALDMOUTSRC_H__ 28 #define __HALDMOUTSRC_H__ 29 30 /*@============================================================*/ 31 /*@include files*/ 32 /*@============================================================*/ 33 /*PHYDM header*/ 34 #include "phydm_pre_define.h" 35 #include "phydm_features.h" 36 #include "phydm_dig.h" 37 #ifdef CONFIG_PATH_DIVERSITY 38 #include "phydm_pathdiv.h" 39 #endif 40 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 41 #include "phydm_antdiv.h" 42 #endif 43 44 #include "phydm_soml.h" 45 46 #ifdef CONFIG_SMART_ANTENNA 47 #include "phydm_smt_ant.h" 48 #endif 49 #ifdef CONFIG_ANT_DETECTION 50 #include "phydm_antdect.h" 51 #endif 52 #include "phydm_rainfo.h" 53 #ifdef CONFIG_DYNAMIC_TX_TWR 54 #include "phydm_dynamictxpower.h" 55 #endif 56 #include "phydm_cfotracking.h" 57 #include "phydm_adaptivity.h" 58 #include "phydm_dfs.h" 59 #include "phydm_ccx.h" 60 #include "txbf/phydm_hal_txbf_api.h" 61 #if (PHYDM_LA_MODE_SUPPORT) 62 #include "phydm_adc_sampling.h" 63 #endif 64 #ifdef CONFIG_PSD_TOOL 65 #include "phydm_psd.h" 66 #endif 67 #ifdef PHYDM_PRIMARY_CCA 68 #include "phydm_primary_cca.h" 69 #endif 70 #include "phydm_cck_pd.h" 71 #include "phydm_rssi_monitor.h" 72 #ifdef PHYDM_AUTO_DEGBUG 73 #include "phydm_auto_dbg.h" 74 #endif 75 #include "phydm_math_lib.h" 76 #include "phydm_noisemonitor.h" 77 #include "phydm_api.h" 78 #ifdef PHYDM_POWER_TRAINING_SUPPORT 79 #include "phydm_pow_train.h" 80 #endif 81 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 82 #include "phydm_lna_sat.h" 83 #endif 84 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 85 #include "phydm_pmac_tx_setting.h" 86 #endif 87 #ifdef PHYDM_MP_SUPPORT 88 #include "phydm_mp.h" 89 #endif 90 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 91 #include "phydm_beamforming.h" 92 #endif 93 94 #ifdef CONFIG_DIRECTIONAL_BF 95 #include "phydm_direct_bf.h" 96 #endif 97 98 #include "phydm_regtable.h" 99 100 /*@HALRF header*/ 101 #include "halrf/halrf_iqk.h" 102 #include "halrf/halrf_dpk.h" 103 #include "halrf/halrf.h" 104 #include "halrf/halrf_powertracking.h" 105 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 106 #include "halrf/halphyrf_ap.h" 107 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 108 #include "halrf/halphyrf_ce.h" 109 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 110 #include "halrf/halphyrf_win.h" 111 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 112 #include "halrf/halphyrf_iot.h" 113 #endif 114 115 extern const u16 phy_rate_table[84]; 116 117 /*@============================================================*/ 118 /*@Definition */ 119 /*@============================================================*/ 120 121 /* Traffic load decision */ 122 #define TRAFFIC_NO_TP 0 123 #define TRAFFIC_ULTRA_LOW 1 124 #define TRAFFIC_LOW 2 125 #define TRAFFIC_MID 3 126 #define TRAFFIC_HIGH 4 127 128 #define NONE 0 129 130 #if defined(DM_ODM_CE_MAC80211) 131 #define MAX_2(x, y) \ 132 __max2(typeof(x), typeof(y), \ 133 x, y) 134 #define __max2(t1, t2, x, y) ({ \ 135 t1 m80211_max1 = (x); \ 136 t2 m80211_max2 = (y); \ 137 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 138 139 #define MIN_2(x, y) \ 140 __min2(typeof(x), typeof(y), \ 141 x, y) 142 #define __min2(t1, t2, x, y) ({ \ 143 t1 m80211_min1 = (x); \ 144 t2 m80211_min2 = (y); \ 145 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 146 147 #define DIFF_2(x, y) \ 148 __diff2(typeof(x), typeof(y), \ 149 x, y) 150 #define __diff2(t1, t2, x, y) ({ \ 151 t1 __d1 = (x); \ 152 t2 __d2 = (y); \ 153 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 154 #else 155 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 156 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 157 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 158 #endif 159 160 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 161 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 162 163 #if defined(DM_ODM_CE_MAC80211) 164 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 165 u32 __b_dup = (B0);\ 166 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 167 }) 168 #else 169 #define BYTE_DUPLICATE_2_DWORD(B0) \ 170 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 171 #endif 172 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 173 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 174 #define BIT_2_BYTE(B3, B2, B1, B0) \ 175 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 176 177 /*@For cmn sta info*/ 178 #if defined(DM_ODM_CE_MAC80211) 179 #define is_sta_active(sta) ({ \ 180 struct cmn_sta_info *__sta = (sta); \ 181 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 182 }) 183 184 #define IS_FUNC_EN(name) ({ \ 185 u8 *__is_func_name = (name); \ 186 (__is_func_name) && (*__is_func_name); \ 187 }) 188 #else 189 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 190 191 #define IS_FUNC_EN(name) ((name) && (*name)) 192 #endif 193 194 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 195 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 196 #else 197 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 198 #endif 199 200 #define PHY_HIST_SIZE 12 201 202 /*@============================================================*/ 203 /*structure and define*/ 204 /*@============================================================*/ 205 206 #define dm_type_by_fw 0 207 #define dm_type_by_driver 1 208 209 #ifdef BB_RAM_SUPPORT 210 211 struct phydm_bb_ram_per_sta { 212 /* @Reg0x1E84 for RAM I/O*/ 213 boolean hw_igi_en; 214 boolean tx_pwr_offset0_en; 215 boolean tx_pwr_offset1_en; 216 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 217 u8 macid_addr; 218 /* @hw_igi value for paths after packet Tx in a period of time*/ 219 u8 hw_igi; 220 /* @tx_pwr_offset0 offset for Tx power index*/ 221 s8 tx_pwr_offset0; 222 s8 tx_pwr_offset1; 223 224 }; 225 226 struct phydm_bb_ram_ctrl { 227 /*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/ 228 struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM]; 229 /*------------ For table2 do not set power offset by macid --------*/ 230 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 231 boolean tx_pwr_offset_reg0_en; 232 u8 tx_pwr_offset_reg0; 233 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 234 boolean tx_pwr_offset_reg1_en; 235 u8 tx_pwr_offset_reg1; 236 }; 237 238 #endif 239 240 struct phydm_phystatus_statistic { 241 /*@[CCK]*/ 242 u32 rssi_cck_sum; 243 u32 rssi_cck_cnt; 244 u32 rssi_beacon_sum; 245 u32 rssi_beacon_cnt; 246 /*@[OFDM]*/ 247 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 248 u32 rssi_ofdm_cnt; 249 u32 evm_ofdm_sum; 250 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 251 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 252 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 253 /*@[1SS]*/ 254 u32 rssi_1ss_cnt; 255 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 256 u32 evm_1ss_sum; 257 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 258 u16 evm_1ss_hist[PHY_HIST_SIZE]; 259 u16 snr_1ss_hist[PHY_HIST_SIZE]; 260 /*@[2SS]*/ 261 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 262 u32 rssi_2ss_cnt; 263 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 264 u32 evm_2ss_sum[2]; 265 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 266 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 267 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 268 #endif 269 /*@[3SS]*/ 270 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 271 u32 rssi_3ss_cnt; 272 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 273 u32 evm_3ss_sum[3]; 274 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 275 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 276 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 277 #endif 278 /*@[4SS]*/ 279 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 280 u32 rssi_4ss_cnt; 281 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 282 u32 evm_4ss_sum[4]; 283 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 284 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 285 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 286 #endif 287 }; 288 289 struct phydm_phystatus_avg { 290 /*@[CCK]*/ 291 u8 rssi_cck_avg; 292 u8 rssi_beacon_avg; 293 /*@[OFDM]*/ 294 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 295 u8 evm_ofdm_avg; 296 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 297 /*@[1SS]*/ 298 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 299 u8 evm_1ss_avg; 300 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 301 /*@[2SS]*/ 302 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 303 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 304 u8 evm_2ss_avg[2]; 305 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 306 #endif 307 /*@[3SS]*/ 308 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 309 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 310 u8 evm_3ss_avg[3]; 311 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 312 #endif 313 /*@[4SS]*/ 314 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 315 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 316 u8 evm_4ss_avg[4]; 317 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 318 #endif 319 }; 320 321 struct odm_phy_dbg_info { 322 /*@ODM Write,debug info*/ 323 u32 num_qry_phy_status_cck; 324 u32 num_qry_phy_status_ofdm; 325 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 326 u32 num_qry_mu_pkt; 327 u32 num_qry_bf_pkt; 328 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 329 boolean is_ldpc_pkt; 330 boolean is_stbc_pkt; 331 u8 num_of_ppdu[4]; 332 u8 gid_num[4]; 333 #endif 334 u32 condi_num; /*@condition number U(18,4)*/ 335 u8 condi_num_cdf[CN_CNT_MAX]; 336 u8 num_qry_beacon_pkt; 337 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 338 u8 beacon_phy_rate; 339 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 340 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 341 u16 show_phy_sts_cnt; 342 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 343 u16 num_qry_ht_pkt[HT_RATE_NUM]; 344 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 345 boolean ht_pkt_not_zero; 346 boolean low_bw_20_occur; 347 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 348 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 349 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 350 boolean vht_pkt_not_zero; 351 boolean low_bw_40_occur; 352 #endif 353 u16 snr_hist_th[PHY_HIST_SIZE - 1]; 354 u16 evm_hist_th[PHY_HIST_SIZE - 1]; 355 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 356 s16 cfo_tail[4]; /* per-path's cfo_tail */ 357 #endif 358 struct phydm_phystatus_statistic physts_statistic_info; 359 struct phydm_phystatus_avg phystatus_statistic_avg; 360 }; 361 362 enum odm_cmninfo { 363 /*@Fixed value*/ 364 /*@-----------HOOK BEFORE REG INIT-----------*/ 365 ODM_CMNINFO_PLATFORM = 0, 366 ODM_CMNINFO_ABILITY, 367 ODM_CMNINFO_INTERFACE, 368 ODM_CMNINFO_MP_TEST_CHIP, 369 ODM_CMNINFO_IC_TYPE, 370 ODM_CMNINFO_CUT_VER, 371 ODM_CMNINFO_FAB_VER, 372 ODM_CMNINFO_FW_VER, 373 ODM_CMNINFO_FW_SUB_VER, 374 ODM_CMNINFO_RF_TYPE, 375 ODM_CMNINFO_RFE_TYPE, 376 ODM_CMNINFO_DPK_EN, 377 ODM_CMNINFO_BOARD_TYPE, 378 ODM_CMNINFO_PACKAGE_TYPE, 379 ODM_CMNINFO_EXT_LNA, 380 ODM_CMNINFO_5G_EXT_LNA, 381 ODM_CMNINFO_EXT_PA, 382 ODM_CMNINFO_5G_EXT_PA, 383 ODM_CMNINFO_GPA, 384 ODM_CMNINFO_APA, 385 ODM_CMNINFO_GLNA, 386 ODM_CMNINFO_ALNA, 387 ODM_CMNINFO_TDMA, 388 ODM_CMNINFO_EXT_TRSW, 389 ODM_CMNINFO_EXT_LNA_GAIN, 390 ODM_CMNINFO_PATCH_ID, 391 ODM_CMNINFO_BINHCT_TEST, 392 ODM_CMNINFO_BWIFI_TEST, 393 ODM_CMNINFO_SMART_CONCURRENT, 394 ODM_CMNINFO_CONFIG_BB_RF, 395 ODM_CMNINFO_IQKPAOFF, 396 ODM_CMNINFO_HUBUSBMODE, 397 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 398 ODM_CMNINFO_TX_TP, 399 ODM_CMNINFO_RX_TP, 400 ODM_CMNINFO_SOUNDING_SEQ, 401 ODM_CMNINFO_REGRFKFREEENABLE, 402 ODM_CMNINFO_RFKFREEENABLE, 403 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 404 ODM_CMNINFO_VALID_PATH_SET, 405 ODM_CMNINFO_EFUSE0X3D8, 406 ODM_CMNINFO_EFUSE0X3D7, 407 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 408 ODM_CMNINFO_X_CAP_SETTING, 409 ODM_CMNINFO_ADVANCE_OTA, 410 ODM_CMNINFO_HP_HWID, 411 ODM_CMNINFO_DIS_DPD, 412 /*@-----------HOOK BEFORE REG INIT-----------*/ 413 414 /*@Dynamic value:*/ 415 416 /*@--------- POINTER REFERENCE-----------*/ 417 ODM_CMNINFO_TX_UNI, 418 ODM_CMNINFO_RX_UNI, 419 ODM_CMNINFO_BAND, 420 ODM_CMNINFO_SEC_CHNL_OFFSET, 421 ODM_CMNINFO_SEC_MODE, 422 ODM_CMNINFO_BW, 423 ODM_CMNINFO_CHNL, 424 ODM_CMNINFO_FORCED_RATE, 425 ODM_CMNINFO_ANT_DIV, 426 ODM_CMNINFO_PATH_DIV, 427 ODM_CMNINFO_ADAPTIVE_SOML, 428 ODM_CMNINFO_ADAPTIVITY, 429 ODM_CMNINFO_SCAN, 430 ODM_CMNINFO_POWER_SAVING, 431 ODM_CMNINFO_ONE_PATH_CCA, 432 ODM_CMNINFO_DRV_STOP, 433 ODM_CMNINFO_PNP_IN, 434 ODM_CMNINFO_INIT_ON, 435 ODM_CMNINFO_ANT_TEST, 436 ODM_CMNINFO_NET_CLOSED, 437 ODM_CMNINFO_P2P_LINK, 438 ODM_CMNINFO_FCS_MODE, 439 ODM_CMNINFO_IS1ANTENNA, 440 ODM_CMNINFO_RFDEFAULTPATH, 441 ODM_CMNINFO_DFS_MASTER_ENABLE, 442 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 443 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 444 ODM_CMNINFO_SOFT_AP_MODE, 445 ODM_CMNINFO_MP_MODE, 446 ODM_CMNINFO_INTERRUPT_MASK, 447 ODM_CMNINFO_BB_OPERATION_MODE, 448 ODM_CMNINFO_BF_ANTDIV_DECISION, 449 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 450 /*@--------- POINTER REFERENCE-----------*/ 451 452 /*@------------CALL BY VALUE-------------*/ 453 ODM_CMNINFO_WIFI_DIRECT, 454 ODM_CMNINFO_WIFI_DISPLAY, 455 ODM_CMNINFO_LINK_IN_PROGRESS, 456 ODM_CMNINFO_LINK, 457 ODM_CMNINFO_CMW500LINK, 458 ODM_CMNINFO_STATION_STATE, 459 ODM_CMNINFO_RSSI_MIN, 460 ODM_CMNINFO_RSSI_MIN_BY_PATH, 461 ODM_CMNINFO_DBG_COMP, 462 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 463 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 464 ODM_CMNINFO_RF_ANTENNA_TYPE, 465 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 466 ODM_CMNINFO_BE_FIX_TX_ANT, 467 ODM_CMNINFO_BT_ENABLED, 468 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 469 ODM_CMNINFO_BT_HS_RSSI, 470 ODM_CMNINFO_BT_OPERATION, 471 ODM_CMNINFO_BT_LIMITED_DIG, 472 ODM_CMNINFO_AP_TOTAL_NUM, 473 ODM_CMNINFO_POWER_TRAINING, 474 ODM_CMNINFO_DFS_REGION_DOMAIN, 475 ODM_CMNINFO_BT_CONTINUOUS_TURN, 476 ODM_CMNINFO_IS_DOWNLOAD_FW, 477 ODM_CMNINFO_PHYDM_PATCH_ID, 478 ODM_CMNINFO_RRSR_VAL, 479 /*@------------CALL BY VALUE-------------*/ 480 481 /*@Dynamic ptr array hook itms.*/ 482 ODM_CMNINFO_STA_STATUS, 483 ODM_CMNINFO_MAX, 484 485 }; 486 487 enum phydm_rfe_bb_source_sel { 488 PAPE_2G = 0, 489 PAPE_5G = 1, 490 LNA0N_2G = 2, 491 LNAON_5G = 3, 492 TRSW = 4, 493 TRSW_B = 5, 494 GNT_BT = 6, 495 ZERO = 7, 496 ANTSEL_0 = 8, 497 ANTSEL_1 = 9, 498 ANTSEL_2 = 0xa, 499 ANTSEL_3 = 0xb, 500 ANTSEL_4 = 0xc, 501 ANTSEL_5 = 0xd, 502 ANTSEL_6 = 0xe, 503 ANTSEL_7 = 0xf 504 }; 505 506 enum phydm_info_query { 507 PHYDM_INFO_FA_OFDM, 508 PHYDM_INFO_FA_CCK, 509 PHYDM_INFO_FA_TOTAL, 510 PHYDM_INFO_CCA_OFDM, 511 PHYDM_INFO_CCA_CCK, 512 PHYDM_INFO_CCA_ALL, 513 PHYDM_INFO_CRC32_OK_VHT, 514 PHYDM_INFO_CRC32_OK_HT, 515 PHYDM_INFO_CRC32_OK_LEGACY, 516 PHYDM_INFO_CRC32_OK_CCK, 517 PHYDM_INFO_CRC32_ERROR_VHT, 518 PHYDM_INFO_CRC32_ERROR_HT, 519 PHYDM_INFO_CRC32_ERROR_LEGACY, 520 PHYDM_INFO_CRC32_ERROR_CCK, 521 PHYDM_INFO_EDCCA_FLAG, 522 PHYDM_INFO_OFDM_ENABLE, 523 PHYDM_INFO_CCK_ENABLE, 524 PHYDM_INFO_CRC32_OK_HT_AGG, 525 PHYDM_INFO_CRC32_ERROR_HT_AGG, 526 PHYDM_INFO_DBG_PORT_0, 527 PHYDM_INFO_CURR_IGI, 528 PHYDM_INFO_RSSI_MIN, 529 PHYDM_INFO_RSSI_MAX, 530 PHYDM_INFO_CLM_RATIO, 531 PHYDM_INFO_NHM_RATIO, 532 }; 533 534 enum phydm_api { 535 PHYDM_API_NBI = 1, 536 PHYDM_API_CSI_MASK = 2, 537 }; 538 539 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 540 541 F00_DIG = 0, 542 F01_RA_MASK = 1, 543 F02_DYN_TXPWR = 2, 544 F03_FA_CNT = 3, 545 F04_RSSI_MNTR = 4, 546 F05_CCK_PD = 5, 547 F06_ANT_DIV = 6, 548 F07_SMT_ANT = 7, 549 F08_PWR_TRAIN = 8, 550 F09_RA = 9, 551 F10_PATH_DIV = 10, 552 F11_DFS = 11, 553 F12_DYN_ARFR = 12, 554 F13_ADPTVTY = 13, 555 F14_CFO_TRK = 14, 556 F15_ENV_MNTR = 15, 557 F16_PRI_CCA = 16, 558 F17_ADPTV_SOML = 17, 559 F18_LNA_SAT_CHK = 18, 560 }; 561 562 /*@=[PHYDM supportability]==========================================*/ 563 enum odm_ability { 564 ODM_BB_DIG = BIT(F00_DIG), 565 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 566 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 567 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 568 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 569 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 570 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 571 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 572 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 573 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 574 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 575 ODM_BB_DFS = BIT(F11_DFS), 576 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 577 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 578 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 579 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 580 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 581 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 582 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 583 }; 584 585 /*@=[PHYDM Debug Component]=====================================*/ 586 enum phydm_dbg_comp { 587 /*@BB Driver Functions*/ 588 DBG_DIG = BIT(F00_DIG), 589 DBG_RA_MASK = BIT(F01_RA_MASK), 590 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 591 DBG_FA_CNT = BIT(F03_FA_CNT), 592 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 593 DBG_CCKPD = BIT(F05_CCK_PD), 594 DBG_ANT_DIV = BIT(F06_ANT_DIV), 595 DBG_SMT_ANT = BIT(F07_SMT_ANT), 596 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 597 DBG_RA = BIT(F09_RA), 598 DBG_PATH_DIV = BIT(F10_PATH_DIV), 599 DBG_DFS = BIT(F11_DFS), 600 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 601 DBG_ADPTVTY = BIT(F13_ADPTVTY), 602 DBG_CFO_TRK = BIT(F14_CFO_TRK), 603 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 604 DBG_PRI_CCA = BIT(F16_PRI_CCA), 605 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 606 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 607 /*BIT(19)*/ 608 /*Neet to re-arrange*/ 609 DBG_PHY_STATUS = BIT(20), 610 DBG_TMP = BIT(21), 611 DBG_FW_TRACE = BIT(22), 612 DBG_TXBF = BIT(23), 613 DBG_COMMON_FLOW = BIT(24), 614 DBG_COMP_MCC = BIT(25), 615 /*BIT(26)*/ 616 DBG_DM_SUMMARY = BIT(27), 617 ODM_PHY_CONFIG = BIT(28), 618 ODM_COMP_INIT = BIT(29), 619 DBG_CMN = BIT(30),/*@common*/ 620 ODM_COMP_API = BIT(31) 621 }; 622 623 /*@=========================================================*/ 624 625 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 626 enum odm_cca_path { 627 ODM_CCA_2R = 0, 628 ODM_CCA_1R_A = 1, 629 ODM_CCA_1R_B = 2, 630 }; 631 632 enum phy_reg_pg_type { 633 PHY_REG_PG_RELATIVE_VALUE = 0, 634 PHY_REG_PG_EXACT_VALUE = 1 635 }; 636 637 enum phydm_offload_ability { 638 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 639 PHYDM_RF_IQK_OFFLOAD = BIT(1), 640 }; 641 642 struct phydm_pause_lv { 643 s8 lv_dig; 644 s8 lv_cckpd; 645 s8 lv_antdiv; 646 s8 lv_adapt; 647 s8 lv_adsl; 648 }; 649 650 struct phydm_func_poiner { 651 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 652 }; 653 654 struct pkt_process_info { 655 u8 phystatus_smp_mode_en; /*@send phystatus every sampling time*/ 656 u8 pre_ppdu_cnt; 657 u8 lna_idx; 658 u8 vga_idx; 659 }; 660 661 #ifdef ODM_CONFIG_BT_COEXIST 662 struct phydm_bt_info { 663 boolean is_bt_enabled; /*@BT is enabled*/ 664 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 665 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 666 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 667 boolean is_bt_limited_dig; /*@BT is busy.*/ 668 }; 669 #endif 670 671 struct phydm_iot_center { 672 boolean is_linked_cmw500; 673 u8 win_patch_id; /*@Customer ID*/ 674 u32 phydm_patch_id; 675 676 }; 677 678 #if (RTL8822B_SUPPORT) 679 struct drp_rtl8822b_struct { 680 enum bb_path path_judge; 681 u16 path_a_cck_fa; 682 u16 path_b_cck_fa; 683 }; 684 #endif 685 686 #ifdef CONFIG_MCC_DM 687 #define MCC_DM_REG_NUM 32 688 struct _phydm_mcc_dm_ { 689 u8 mcc_pre_status; 690 u8 mcc_reg_id[MCC_DM_REG_NUM]; 691 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 692 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 693 /*mcc DIG*/ 694 u8 mcc_rssi[2]; 695 /*u8 mcc_igi[2];*/ 696 697 /* need to be config by driver*/ 698 u8 mcc_status; 699 u8 sta_macid[2][NUM_STA]; 700 u16 mcc_rf_ch[2]; 701 702 }; 703 #endif 704 705 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT) 706 struct phydm_physts { 707 u8 cck_gi_u_bnd; 708 u8 cck_gi_l_bnd; 709 }; 710 #endif 711 712 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 713 #if (RT_PLATFORM != PLATFORM_LINUX) 714 typedef 715 #endif 716 717 struct dm_struct { 718 #else/*for AP, CE Team*/ 719 struct dm_struct { 720 #endif 721 /*@Add for different team use temporarily*/ 722 void *adapter; /*@For CE/NIC team*/ 723 struct rtl8192cd_priv *priv; /*@For AP team*/ 724 boolean odm_ready; 725 enum phy_reg_pg_type phy_reg_pg_value_type; 726 u8 phy_reg_pg_version; 727 u64 support_ability; /*@PHYDM function Supportability*/ 728 u64 pause_ability; /*@PHYDM function pause Supportability*/ 729 u64 debug_components; 730 u8 cmn_dbg_msg_period; 731 u8 cmn_dbg_msg_cnt; 732 u32 fw_debug_components; 733 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 734 u32 last_num_qry_phy_status_all; 735 u32 rx_pwdb_ave; 736 boolean is_init_hw_info_by_rfe; 737 738 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 739 boolean is_cck_high_power; 740 u8 rf_path_rx_enable; 741 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 742 743 /* @COMMON INFORMATION */ 744 745 /*@Init value*/ 746 /*@-----------HOOK BEFORE REG INIT-----------*/ 747 748 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 749 u8 normal_rx_path; 750 u8 valid_path_set; /*@use for single rx path only*/ 751 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 752 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 753 u32 support_ic_type; /*@PHYDM supported IC*/ 754 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 755 u8 ic_ip_series; /*N/AC/JGR3*/ 756 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 757 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 758 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 759 u8 fw_version; 760 u8 fw_sub_version; 761 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 762 u8 rfe_type; 763 u8 board_type; 764 u8 package_type; 765 u16 type_glna; 766 u16 type_gpa; 767 u16 type_alna; 768 u16 type_apa; 769 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 770 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 771 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 772 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 773 u8 efuse0x3d7; /*@with Efuse number*/ 774 u8 efuse0x3d8; 775 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 776 u8 ext_lna_gain; /*@gain of external lna*/ 777 boolean is_in_hct_test; 778 u8 wifi_test; 779 boolean is_dual_mac_smart_concurrent; 780 u32 bk_support_ability; /*SD4 only*/ 781 u8 with_extenal_ant_switch; 782 /*@cck agc relative*/ 783 boolean cck_new_agc; 784 s8 cck_lna_gain_table[8]; 785 /*@-------------------------------------*/ 786 u32 phydm_sys_up_time; 787 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 788 u32 soft_ap_special_setting; 789 boolean boolean_dummy; 790 s8 s8_dummy; 791 u8 u8_dummy; 792 u16 u16_dummy; 793 u32 u32_dummy; 794 u8 rfe_hwsetting_band; 795 u8 p_advance_ota; 796 boolean hp_hw_id; 797 boolean BOOLEAN_temp; 798 boolean is_dfs_band; 799 u8 is_rx_blocking_en; 800 u16 fw_offload_ability; 801 boolean is_download_fw; 802 boolean en_dis_dpd; 803 u16 dis_dpd_rate; 804 #if (RTL8822C_SUPPORT) 805 u8 txagc_buff[2][NUM_RATE_AC_2SS]; 806 u32 bp_0x9b0; 807 #endif 808 /*@-----------HOOK BEFORE REG INIT-----------*/ 809 /*@===========================================================*/ 810 /*@====[ CALL BY Reference ]=========================================*/ 811 /*@===========================================================*/ 812 813 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 814 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 815 u8 *band_type; /*@2.4G/5G = 0/1*/ 816 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 817 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 818 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 819 u8 *channel; /*@central CH number*/ 820 boolean *is_scan_in_process; 821 boolean *is_power_saving; 822 boolean *is_tdma; 823 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 824 u8 *antenna_test; 825 boolean *is_net_closed; 826 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 827 /*@--------- For 8723B IQK-------------------------------------*/ 828 boolean *is_1_antenna; 829 u8 *rf_default_path; /* @0:S1, 1:S0 */ 830 /*@-----------------------------------------------------------*/ 831 832 u16 *forced_data_rate; 833 u8 *enable_antdiv; 834 u8 *enable_pathdiv; 835 u8 *en_adap_soml; 836 u8 *enable_adaptivity; 837 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 838 boolean *is_fw_dw_rsvd_page_in_progress; 839 u32 *current_tx_tp; 840 u32 *current_rx_tp; 841 u8 *sounding_seq; 842 u32 *soft_ap_mode; 843 u8 *mp_mode; 844 u32 *interrupt_mask; 845 u8 *bb_op_mode; 846 u32 *manual_supportability; 847 /*@===========================================================*/ 848 /*@====[ CALL BY VALUE ]===========================================*/ 849 /*@===========================================================*/ 850 851 u8 disable_phydm_watchdog; 852 boolean is_link_in_process; 853 boolean is_wifi_direct; 854 boolean is_wifi_display; 855 boolean is_linked; 856 boolean pre_is_linked; 857 boolean first_connect; 858 boolean first_disconnect; 859 boolean bsta_state; 860 u8 rssi_min; 861 u8 rssi_min_macid; 862 u8 pre_rssi_min; 863 u8 rssi_max; 864 u8 rssi_max_macid; 865 u8 rssi_min_by_path; 866 boolean is_mp_chip; 867 boolean is_one_entry_only; 868 u32 one_entry_macid; 869 u32 one_entry_tp; 870 u32 pre_one_entry_tp; 871 u8 pre_number_linked_client; 872 u8 number_linked_client; 873 u8 pre_number_active_client; 874 u8 number_active_client; 875 boolean is_disable_phy_api; 876 u8 rssi_a; 877 u8 rssi_b; 878 u8 rssi_c; 879 u8 rssi_d; 880 s8 rxsc_80; 881 s8 rxsc_40; 882 s8 rxsc_20; 883 s8 rxsc_l; 884 u64 rssi_trsw; 885 u64 rssi_trsw_h; 886 u64 rssi_trsw_l; 887 u64 rssi_trsw_iso; 888 u8 tx_ant_status; /*TX path enable*/ 889 u8 rx_ant_status; /*RX path enable*/ 890 #ifdef PHYDM_COMPILE_ABOVE_4SS 891 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 892 #endif 893 #ifdef PHYDM_COMPILE_ABOVE_3SS 894 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 895 #endif 896 #ifdef PHYDM_COMPILE_ABOVE_2SS 897 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 898 #endif 899 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 900 u8 cck_lna_idx; 901 u8 cck_vga_idx; 902 u8 curr_station_id; 903 u8 ofdm_agc_idx[4]; 904 u8 rx_rate; 905 u8 rate_ss; 906 u8 tx_rate; 907 u8 linked_interval; 908 u8 pre_channel; 909 u32 txagc_offset_value_a; 910 boolean is_txagc_offset_positive_a; 911 u32 txagc_offset_value_b; 912 boolean is_txagc_offset_positive_b; 913 u8 ap_total_num; 914 /*@[traffic]*/ 915 u8 traffic_load; 916 u8 pre_traffic_load; 917 u32 tx_tp; /*@Mbps*/ 918 u32 rx_tp; /*@Mbps*/ 919 u32 total_tp; /*@Mbps*/ 920 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 921 u64 cur_tx_ok_cnt; 922 u64 cur_rx_ok_cnt; 923 u64 last_tx_ok_cnt; 924 u64 last_rx_ok_cnt; 925 u16 consecutive_idlel_time; /*@unit: second*/ 926 /*@---------------------------*/ 927 boolean is_bb_swing_offset_positive_a; 928 boolean is_bb_swing_offset_positive_b; 929 930 /*@[DIG]*/ 931 boolean MPDIG_2G; /*off MPDIG*/ 932 u8 times_2g; /*@for MP DIG*/ 933 u8 force_igi; /*@for debug*/ 934 935 /*@[TDMA-DIG]*/ 936 u8 tdma_dig_timer_ms; 937 u8 tdma_dig_state_number; 938 u8 tdma_dig_low_upper_bond; 939 u8 force_tdma_low_igi; 940 u8 force_tdma_high_igi; 941 u8 fix_expire_to_zero; 942 boolean original_dig_restore; 943 /*@---------------------------*/ 944 945 /*@[AntDiv]*/ 946 u8 ant_div_type; 947 u8 antdiv_rssi; 948 u8 fat_comb_a; 949 u8 fat_comb_b; 950 u8 antdiv_intvl; 951 u8 antdiv_delay; 952 u8 ant_type; 953 u8 ant_type2; 954 u8 pre_ant_type; 955 u8 pre_ant_type2; 956 u8 antdiv_period; 957 u8 evm_antdiv_period; 958 u8 antdiv_select; 959 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 960 u8 stop_antdiv_rssi_th; 961 u16 stop_antdiv_tp_diff_th; 962 u16 stop_antdiv_tp_th; 963 u8 antdiv_tp_period; 964 u16 tp_active_th; 965 u8 tp_active_occur; 966 u8 path_select; 967 u8 antdiv_evm_en; 968 u8 bdc_holdstate; 969 u8 antdiv_counter; 970 /*@---------------------------*/ 971 972 u8 ndpa_period; 973 boolean h2c_rarpt_connect; 974 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 975 u8 print_agc; 976 u8 la_mode; 977 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 978 u8 current_rf_set_8821c; 979 u8 default_rf_set_8821c; 980 u8 current_ant_num_8821c; 981 u8 default_ant_num_8821c; 982 u8 rfe_type_expand; 983 /*@-----------------------------------------------------------*/ 984 /*@---For Adaptivtiy---------------------------------------------*/ 985 s8 TH_L2H_default; 986 s8 th_edcca_hl_diff_default; 987 s8 th_l2h_ini; 988 s8 th_edcca_hl_diff; 989 boolean carrier_sense_enable; 990 /*@-----------------------------------------------------------*/ 991 u8 pre_dbg_priority; 992 u8 nbi_set_result; 993 u8 c2h_cmd_start; 994 u8 fw_debug_trace[60]; 995 u8 pre_c2h_seq; 996 boolean fw_buff_is_enpty; 997 u32 data_frame_num; 998 #if (RTL8814B_SUPPORT) 999 /*@--- for spur detection ---------------------------------------*/ 1000 u8 dsde_sel; 1001 u8 nbi_path_sel; 1002 u8 csi_wgt; 1003 /*@------------------------------------------*/ 1004 #endif 1005 /*@--- for noise detection ---------------------------------------*/ 1006 boolean is_noisy_state; 1007 boolean noisy_decision; /*@b_noisy*/ 1008 boolean pre_b_noisy; 1009 u32 noisy_decision_smooth; 1010 /*@-----------------------------------------------------------*/ 1011 1012 /*@--- for MCC ant weighting ------------------------------------*/ 1013 boolean is_stop_dym_ant_weighting; 1014 /*@-----------------------------------------------------------*/ 1015 1016 boolean is_disable_dym_ecs; 1017 boolean is_disable_dym_ant_weighting; 1018 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1019 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1020 1021 #if (RATE_ADAPTIVE_SUPPORT) 1022 u16 currmin_rpt_time; 1023 struct _phydm_txstatistic_ hw_stats; 1024 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1025 /*Use mac_id as array index. STA mac_id=0*/ 1026 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1027 #endif 1028 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1029 /*We need to colelct all support abilit to a proper area.*/ 1030 boolean ra_support88e; 1031 boolean *is_driver_stopped; 1032 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1033 boolean *pinit_adpt_in_progress; 1034 boolean is_user_assign_level; 1035 u8 RSSI_BT; /*@come from BT*/ 1036 1037 /*@---PSD Relative ---------------------------------------------*/ 1038 boolean is_psd_in_process; 1039 boolean is_psd_active; 1040 /*@-----------------------------------------------------------*/ 1041 1042 boolean bsomlenabled; /* @D-SoML control */ 1043 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1044 u32 n_iqk_cnt; 1045 u32 n_iqk_ok_cnt; 1046 u32 n_iqk_fail_cnt; 1047 1048 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1049 boolean config_bbrf; 1050 #endif 1051 boolean is_disable_power_training; 1052 boolean is_bt_continuous_turn; 1053 u8 enhance_pwr_th[3]; 1054 u8 set_pwr_th[3]; 1055 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1056 #ifdef BB_RAM_SUPPORT 1057 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1058 #endif 1059 u8 dynamic_tx_high_power_lvl; 1060 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1061 u8 last_dtp_lvl; 1062 u8 min_power_index; 1063 u32 tx_agc_ofdm_18_6; 1064 /*-------------------------------------------------------------*/ 1065 u8 rx_pkt_type; 1066 1067 #ifdef CONFIG_PHYDM_DFS_MASTER 1068 u8 dfs_region_domain; 1069 u8 *dfs_master_enabled; 1070 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1071 u8 radar_detect_dbg_parm_en; 1072 u32 radar_detect_reg_918; 1073 u32 radar_detect_reg_91c; 1074 u32 radar_detect_reg_920; 1075 u32 radar_detect_reg_924; 1076 1077 u32 radar_detect_reg_a40; 1078 u32 radar_detect_reg_a44; 1079 u32 radar_detect_reg_a48; 1080 u32 radar_detect_reg_a4c; 1081 u32 radar_detect_reg_a50; 1082 u32 radar_detect_reg_a54; 1083 1084 u32 radar_detect_reg_f54; 1085 u32 radar_detect_reg_f58; 1086 u32 radar_detect_reg_f5c; 1087 u32 radar_detect_reg_f70; 1088 u32 radar_detect_reg_f74; 1089 /*@---For zero-wait DFS---------------------------------------*/ 1090 boolean seg1_dfs_flag; 1091 /*@-----------------------------------------------------------*/ 1092 /*@-----------------------------------------------------------*/ 1093 #endif 1094 1095 /*@=== RTL8721D ADC clock 80MHz only for CBW20MHz ===*/ 1096 #if (RTL8721D_SUPPORT) 1097 boolean cbw20_adc80; 1098 #endif 1099 1100 /*@=== PHYDM Timer ========================================== (start)*/ 1101 1102 struct phydm_timer_list mpt_dig_timer; 1103 struct phydm_timer_list fast_ant_training_timer; 1104 #ifdef ODM_EVM_ENHANCE_ANTDIV 1105 struct phydm_timer_list evm_fast_ant_training_timer; 1106 #endif 1107 #ifdef PHYDM_TDMA_DIG_SUPPORT 1108 struct phydm_timer_list tdma_dig_timer; 1109 #endif 1110 struct phydm_timer_list sbdcnt_timer; 1111 1112 /*@=== PHYDM Workitem ======================================= (start)*/ 1113 1114 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1115 #if USE_WORKITEM 1116 RT_WORK_ITEM fast_ant_training_workitem; 1117 RT_WORK_ITEM ra_rpt_workitem; 1118 RT_WORK_ITEM sbdcnt_workitem; 1119 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1120 #endif 1121 #endif 1122 1123 /*@=== PHYDM Structure ======================================== (start)*/ 1124 struct phydm_func_poiner phydm_func_handler; 1125 struct phydm_iot_center iot_table; 1126 1127 #ifdef ODM_CONFIG_BT_COEXIST 1128 struct phydm_bt_info bt_info_table; 1129 #endif 1130 1131 struct pkt_process_info pkt_proc_struct; 1132 struct phydm_adaptivity_struct adaptivity; 1133 struct _DFS_STATISTICS dfs; 1134 struct odm_noise_monitor noise_level; 1135 struct odm_phy_dbg_info phy_dbg_info; 1136 1137 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1138 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1139 #endif 1140 1141 #ifdef CONFIG_ADAPTIVE_SOML 1142 struct adaptive_soml dm_soml_table; 1143 #endif 1144 1145 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1146 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1147 struct _BF_DIV_COEX_ dm_bdc_table; 1148 #endif 1149 1150 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1151 struct smt_ant_honbo dm_sat_table; 1152 #endif 1153 #endif 1154 1155 #if (defined(CONFIG_SMART_ANTENNA)) 1156 struct smt_ant smtant_table; 1157 #endif 1158 1159 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1160 struct dm_rf_calibration_struct rf_calibrate_info; 1161 struct dm_iqk_info IQK_info; 1162 struct dm_dpk_info dpk_info; 1163 1164 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1165 struct phydm_fat_struct dm_fat_table; 1166 struct sw_antenna_switch dm_swat_table; 1167 #endif 1168 struct phydm_dig_struct dm_dig_table; 1169 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1170 struct phydm_lna_sat_t dm_lna_sat_info; 1171 #endif 1172 1173 #ifdef CONFIG_MCC_DM 1174 struct _phydm_mcc_dm_ mcc_dm; 1175 #endif 1176 1177 #ifdef PHYDM_SUPPORT_CCKPD 1178 struct phydm_cckpd_struct dm_cckpd_table; 1179 #endif 1180 1181 #ifdef PHYDM_PRIMARY_CCA 1182 struct phydm_pricca_struct dm_pri_cca; 1183 #endif 1184 1185 struct ra_table dm_ra_table; 1186 struct phydm_fa_struct false_alm_cnt; 1187 #ifdef PHYDM_TDMA_DIG_SUPPORT 1188 struct phydm_fa_acc_struct false_alm_cnt_acc; 1189 #ifdef IS_USE_NEW_TDMA 1190 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1191 #endif 1192 #endif 1193 struct phydm_cfo_track_struct dm_cfo_track; 1194 struct ccx_info dm_ccx_info; 1195 1196 struct odm_power_trim_data power_trim_data; 1197 #if (RTL8822B_SUPPORT) 1198 struct drp_rtl8822b_struct phydm_rtl8822b; 1199 #endif 1200 1201 #ifdef CONFIG_PSD_TOOL 1202 struct psd_info dm_psd_table; 1203 #endif 1204 1205 #if (PHYDM_LA_MODE_SUPPORT) 1206 struct rt_adcsmp adcsmp; 1207 #endif 1208 1209 #if (defined(CONFIG_PATH_DIVERSITY)) 1210 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1211 #endif 1212 1213 #if (defined(CONFIG_ANT_DETECTION)) 1214 struct _ANT_DETECTED_INFO ant_detected_info; 1215 #endif 1216 1217 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1218 #ifdef PHYDM_BEAMFORMING_SUPPORT 1219 struct _RT_BEAMFORMING_INFO beamforming_info; 1220 #endif 1221 #endif 1222 #ifdef PHYDM_AUTO_DEGBUG 1223 struct phydm_auto_dbg_struct auto_dbg_table; 1224 #endif 1225 1226 struct phydm_pause_lv pause_lv_table; 1227 struct phydm_api_stuc api_table; 1228 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1229 struct phydm_pow_train_stuc pow_train_table; 1230 #endif 1231 1232 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1233 struct phydm_pmac_tx dm_pmac_tx_table; 1234 #endif 1235 1236 #ifdef PHYDM_MP_SUPPORT 1237 struct phydm_mp dm_mp_table; 1238 #endif 1239 /*@==========================================================*/ 1240 1241 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT) 1242 /*@-------------------phydm_phystatus report --------------------*/ 1243 struct phydm_physts dm_physts_table; 1244 #endif 1245 1246 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1247 1248 #if (RT_PLATFORM != PLATFORM_LINUX) 1249 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1250 #else 1251 }; 1252 #endif 1253 1254 #else /*@for AP,CE Team*/ 1255 }; 1256 #endif 1257 1258 enum phydm_adv_ota { 1259 PHYDM_PATHB_1RCCA = BIT(0), 1260 PHYDM_HP_OTA_SETTING_A = BIT(1), 1261 PHYDM_HP_OTA_SETTING_B = BIT(2), 1262 PHYDM_ASUS_OTA_SETTING = BIT(3), 1263 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1264 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1265 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1266 1267 }; 1268 1269 enum phydm_bb_op_mode { 1270 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1271 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1272 }; 1273 1274 enum phydm_structure_type { 1275 PHYDM_FALSEALMCNT, 1276 PHYDM_CFOTRACK, 1277 PHYDM_ADAPTIVITY, 1278 PHYDM_DFS, 1279 PHYDM_ROMINFO, 1280 1281 }; 1282 1283 enum odm_bb_config_type { 1284 CONFIG_BB_PHY_REG, 1285 CONFIG_BB_AGC_TAB, 1286 CONFIG_BB_AGC_TAB_2G, 1287 CONFIG_BB_AGC_TAB_5G, 1288 CONFIG_BB_PHY_REG_PG, 1289 CONFIG_BB_PHY_REG_MP, 1290 CONFIG_BB_AGC_TAB_DIFF, 1291 CONFIG_BB_RF_CAL_INIT, 1292 }; 1293 1294 enum odm_rf_config_type { 1295 CONFIG_RF_RADIO, 1296 CONFIG_RF_TXPWR_LMT, 1297 CONFIG_RF_SYN_RADIO, 1298 }; 1299 1300 enum odm_fw_config_type { 1301 CONFIG_FW_NIC, 1302 CONFIG_FW_NIC_2, 1303 CONFIG_FW_AP, 1304 CONFIG_FW_AP_2, 1305 CONFIG_FW_MP, 1306 CONFIG_FW_WOWLAN, 1307 CONFIG_FW_WOWLAN_2, 1308 CONFIG_FW_AP_WOWLAN, 1309 CONFIG_FW_BT, 1310 }; 1311 1312 /*status code*/ 1313 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1314 enum rt_status { 1315 RT_STATUS_SUCCESS, 1316 RT_STATUS_FAILURE, 1317 RT_STATUS_PENDING, 1318 RT_STATUS_RESOURCE, 1319 RT_STATUS_INVALID_CONTEXT, 1320 RT_STATUS_INVALID_PARAMETER, 1321 RT_STATUS_NOT_SUPPORT, 1322 RT_STATUS_OS_API_FAILED, 1323 }; 1324 #endif /*@end of enum rt_status definition*/ 1325 1326 void 1327 phydm_watchdog_lps(struct dm_struct *dm); 1328 1329 void 1330 phydm_watchdog_lps_32k(struct dm_struct *dm); 1331 1332 void 1333 phydm_txcurrentcalibration(struct dm_struct *dm); 1334 1335 void 1336 phydm_dm_early_init(struct dm_struct *dm); 1337 1338 void 1339 odm_dm_init(struct dm_struct *dm); 1340 1341 void 1342 odm_dm_reset(struct dm_struct *dm); 1343 1344 void 1345 phydm_fwoffload_ability_init(struct dm_struct *dm, 1346 enum phydm_offload_ability offload_ability); 1347 1348 void 1349 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1350 enum phydm_offload_ability offload_ability); 1351 1352 void 1353 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1354 char *output, u32 *_out_len); 1355 1356 void 1357 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1358 1359 void 1360 phydm_watchdog(struct dm_struct *dm); 1361 1362 void 1363 phydm_watchdog_mp(struct dm_struct *dm); 1364 1365 u8 1366 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1367 enum phydm_pause_type pause_type, 1368 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1369 1370 void 1371 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1372 char *output, u32 *_out_len); 1373 1374 void 1375 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1376 1377 void 1378 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1379 1380 void 1381 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1382 1383 u32 1384 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1385 1386 void 1387 odm_init_all_timers(struct dm_struct *dm); 1388 1389 void 1390 odm_cancel_all_timers(struct dm_struct *dm); 1391 1392 void 1393 odm_release_all_timers(struct dm_struct *dm); 1394 1395 void * 1396 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1397 1398 void 1399 phydm_dc_cancellation(struct dm_struct *dm); 1400 1401 void 1402 phydm_receiver_blocking(void *dm_void); 1403 1404 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1405 void 1406 odm_init_all_work_items( 1407 struct dm_struct *dm 1408 ); 1409 void 1410 odm_free_all_work_items( 1411 struct dm_struct *dm 1412 ); 1413 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1414 1415 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1416 void 1417 odm_dtc(struct dm_struct *dm); 1418 #endif 1419 1420 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1421 void 1422 odm_init_all_threads( 1423 struct dm_struct *dm 1424 ); 1425 1426 void 1427 odm_stop_all_threads( 1428 struct dm_struct *dm 1429 ); 1430 #endif 1431 1432 #endif 1433