1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16 #define _HAL_MP_C_
17
18 #include <drv_types.h>
19
20 #ifdef CONFIG_MP_INCLUDED
21
22 #ifdef RTW_HALMAC
23 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
24 #else /* !RTW_HALMAC */
25 #ifdef CONFIG_RTL8188E
26 #include <rtl8188e_hal.h>
27 #endif
28 #ifdef CONFIG_RTL8723B
29 #include <rtl8723b_hal.h>
30 #endif
31 #ifdef CONFIG_RTL8192E
32 #include <rtl8192e_hal.h>
33 #endif
34 #ifdef CONFIG_RTL8814A
35 #include <rtl8814a_hal.h>
36 #endif
37 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
38 #include <rtl8812a_hal.h>
39 #endif
40 #ifdef CONFIG_RTL8703B
41 #include <rtl8703b_hal.h>
42 #endif
43 #ifdef CONFIG_RTL8723D
44 #include <rtl8723d_hal.h>
45 #endif
46 #ifdef CONFIG_RTL8710B
47 #include <rtl8710b_hal.h>
48 #endif
49 #ifdef CONFIG_RTL8188F
50 #include <rtl8188f_hal.h>
51 #endif
52 #ifdef CONFIG_RTL8188GTV
53 #include <rtl8188gtv_hal.h>
54 #endif
55 #ifdef CONFIG_RTL8192F
56 #include <rtl8192f_hal.h>
57 #endif
58 #endif /* !RTW_HALMAC */
59
60
MgntQuery_NssTxRate(u16 Rate)61 u8 MgntQuery_NssTxRate(u16 Rate)
62 {
63 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
64
65 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
66 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
67 NssNum = RF_2TX;
68 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
69 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
70 NssNum = RF_3TX;
71 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
72 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
73 NssNum = RF_4TX;
74 else
75 NssNum = RF_1TX;
76
77 return NssNum;
78 }
79
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)80 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
81 {
82 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
83 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
84 u8 ChannelToSw = pMptCtx->MptChannelToSw;
85 u32 ulRateIdx = pMptCtx->mpt_rate_index;
86 u32 ulbandwidth = pMptCtx->MptBandWidth;
87
88 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
89 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
90 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
91 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
92 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
93
94 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
95 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
96 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
97 } else {
98 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
99 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
100 }
101 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
102 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
103 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
104 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
105 } else {
106 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
107 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
108 }
109 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
110 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
111 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
112 }
113 }
114
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)115 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
116 {
117 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
118 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
119
120
121 if (!netif_running(padapter->pnetdev)) {
122 return _FAIL;
123 }
124
125 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
126 return _FAIL;
127 }
128 if (enable)
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
130 else
131 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
132
133 return _SUCCESS;
134 }
135
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)136 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
137 {
138 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
139 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
140
141
142 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
143 }
144
145
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)146 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
147 {
148 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
149 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
150 u8 i;
151 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
152 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
153 u8 u1Channel = pHalData->current_channel;
154 u32 ulRateIdx = pMptCtx->mpt_rate_index;
155 u8 DataRate = 0xFF;
156
157 /* Do not modify CCK TX filter parameters for 8822B*/
158 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
159 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
160 return;
161
162 DataRate = mpt_to_mgnt_rate(ulRateIdx);
163
164 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
165 pHalData->bCCKinCH14 = TRUE;
166 else
167 pHalData->bCCKinCH14 = FALSE;
168
169 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
170 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
171 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
172 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
173 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
174
175 } else {
176 /* Normal setting for 8703B, just recover to the default setting. */
177 /* This hardcore values reference from the parameter which BB team gave. */
178 for (i = 0 ; i < 2 ; ++i)
179 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
180
181 }
182 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
183 /* 2.4G CCK TX DFIR */
184 /* 2016.01.20 Suggest from RS BB mingzhi*/
185 if ((u1Channel == 14)) {
186 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
187 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
188 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
189 } else {
190 for (i = 0 ; i < 3 ; ++i) {
191 phy_set_bb_reg(Adapter,
192 pHalData->RegForRecover[i].offset,
193 bMaskDWord,
194 pHalData->RegForRecover[i].value);
195 }
196 }
197 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
198 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
199 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
200 CCKSwingIndex = 20; /* default index */
201
202 if (!pHalData->bCCKinCH14) {
203 /* Readback the current bb cck swing value and compare with the table to */
204 /* get the current swing index */
205 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
206 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
207 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
208 CCKSwingIndex = i;
209 break;
210 }
211 }
212 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
213 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
214 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
215 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
216 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
217 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
218 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
219 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
220 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
221 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
222 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
223 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
224 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
225 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
226 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
227 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
228 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
229 } else {
230 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
231 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
232 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
233 CCKSwingIndex = i;
234 break;
235 }
236 }
237 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
238 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
239 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
240 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
241 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
242 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
243 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
244 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
245 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
246 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
247 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
248 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
249 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
250 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
251 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
252 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
253 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
254 }
255 } else {
256
257 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
258 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
259
260 if (!pHalData->bCCKinCH14) {
261 /* Readback the current bb cck swing value and compare with the table to */
262 /* get the current swing index */
263 for (i = 0; i < CCK_TABLE_SIZE; i++) {
264 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
265 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
266 CCKSwingIndex = i;
267 break;
268 }
269 }
270
271 /*Write 0xa22 0xa23*/
272 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
273 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
274
275
276 /*Write 0xa24 ~ 0xa27*/
277 TempVal2 = 0;
278 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
280 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
281 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
282
283 /*Write 0xa28 0xa29*/
284 TempVal3 = 0;
285 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
286 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
287 } else {
288 for (i = 0; i < CCK_TABLE_SIZE; i++) {
289 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
290 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
291 CCKSwingIndex = i;
292 break;
293 }
294 }
295
296 /*Write 0xa22 0xa23*/
297 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
298 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
299
300 /*Write 0xa24 ~ 0xa27*/
301 TempVal2 = 0;
302 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
303 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
304 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
305 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
306
307 /*Write 0xa28 0xa29*/
308 TempVal3 = 0;
309 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
310 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
311 }
312
313 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
314 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
315 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
316 }
317
318 }
319
hal_mpt_SetChannel(PADAPTER pAdapter)320 void hal_mpt_SetChannel(PADAPTER pAdapter)
321 {
322 enum rf_path eRFPath;
323 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
324 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
325 struct mp_priv *pmp = &pAdapter->mppriv;
326 u8 channel = pmp->channel;
327 u8 bandwidth = pmp->bandwidth;
328
329 hal_mpt_SwitchRfSetting(pAdapter);
330
331 pHalData->bSwChnl = _TRUE;
332 pHalData->bSetChnlBW = _TRUE;
333
334 if (bandwidth == 2) {
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
336 } else if (bandwidth == 1) {
337 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
338 } else
339 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
340
341 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
342 rtw_btcoex_wifionly_scan_notify(pAdapter);
343
344 }
345
346 /*
347 * Notice
348 * Switch bandwitdth may change center frequency(channel)
349 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)350 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
351 {
352 struct mp_priv *pmp = &pAdapter->mppriv;
353 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
354
355 u8 channel = pmp->channel;
356 u8 bandwidth = pmp->bandwidth;
357
358 pHalData->bSwChnl = _TRUE;
359 pHalData->bSetChnlBW = _TRUE;
360
361 if (bandwidth == 2) {
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
363 } else if (bandwidth == 1) {
364 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
365 } else
366 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
367
368 hal_mpt_SwitchRfSetting(pAdapter);
369 rtw_btcoex_wifionly_scan_notify(pAdapter);
370
371 }
372
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)373 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
374 {
375 switch (Rate) {
376 case MPT_CCK: {
377 u32 TxAGC = 0, pwr = 0;
378 u8 rf;
379
380 pwr = pTxPower[RF_PATH_A];
381 if (pwr < 0x3f) {
382 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
383 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
385 }
386 pwr = pTxPower[RF_PATH_B];
387 if (pwr < 0x3f) {
388 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
389 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
390 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
391 }
392 }
393 break;
394
395 case MPT_OFDM_AND_HT: {
396 u32 TxAGC = 0;
397 u8 pwr = 0, rf;
398
399 pwr = pTxPower[0];
400 if (pwr < 0x3f) {
401 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
402 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
404 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
405 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
406 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
407 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
408 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
409 }
410 TxAGC = 0;
411 pwr = pTxPower[1];
412 if (pwr < 0x3f) {
413 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
414 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
416 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
417 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
418 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
419 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
420 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
421 }
422 }
423 break;
424
425 default:
426 break;
427 }
428 RTW_INFO("<===mpt_SetTxPower_Old()\n");
429 }
430
431 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)432 mpt_SetTxPower(
433 PADAPTER pAdapter,
434 MPT_TXPWR_DEF Rate,
435 u8 *pTxPower
436 )
437 {
438 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
439
440 u8 path = 0 , i = 0, MaxRate = MGN_6M;
441 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
442
443 if (IS_HARDWARE_TYPE_8814A(pAdapter))
444 EndPath = RF_PATH_D;
445 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
446 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
447 EndPath = RF_PATH_A;
448
449 switch (Rate) {
450 case MPT_CCK: {
451 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
452
453 for (path = StartPath; path <= EndPath; path++)
454 for (i = 0; i < sizeof(rate); ++i)
455 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
456 }
457 break;
458 case MPT_OFDM: {
459 u8 rate[] = {
460 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
461 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
462 };
463
464 for (path = StartPath; path <= EndPath; path++)
465 for (i = 0; i < sizeof(rate); ++i)
466 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
467 }
468 break;
469 case MPT_HT: {
470 u8 rate[] = {
471 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
472 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
473 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
474 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
475 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
476 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
477 MGN_MCS30, MGN_MCS31,
478 };
479 if (pHalData->rf_type == RF_3T3R)
480 MaxRate = MGN_MCS23;
481 else if (pHalData->rf_type == RF_2T2R)
482 MaxRate = MGN_MCS15;
483 else
484 MaxRate = MGN_MCS7;
485 for (path = StartPath; path <= EndPath; path++) {
486 for (i = 0; i < sizeof(rate); ++i) {
487 if (rate[i] > MaxRate)
488 break;
489 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
490 }
491 }
492 }
493 break;
494 case MPT_VHT: {
495 u8 rate[] = {
496 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
497 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
498 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
499 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
500 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
501 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
502 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
503 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
504 };
505 if (pHalData->rf_type == RF_3T3R)
506 MaxRate = MGN_VHT3SS_MCS9;
507 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
508 MaxRate = MGN_VHT2SS_MCS9;
509 else
510 MaxRate = MGN_VHT1SS_MCS9;
511
512 for (path = StartPath; path <= EndPath; path++) {
513 for (i = 0; i < sizeof(rate); ++i) {
514 if (rate[i] > MaxRate)
515 break;
516 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
517 }
518 }
519 }
520 break;
521 default:
522 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
523 break;
524 }
525 }
526
hal_mpt_SetTxPower(PADAPTER pAdapter)527 void hal_mpt_SetTxPower(PADAPTER pAdapter)
528 {
529 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
530 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
531 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
532
533 if (pHalData->rf_chip < RF_CHIP_MAX) {
534 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
535 IS_HARDWARE_TYPE_8723B(pAdapter) ||
536 IS_HARDWARE_TYPE_8192E(pAdapter) ||
537 IS_HARDWARE_TYPE_8703B(pAdapter) ||
538 IS_HARDWARE_TYPE_8188F(pAdapter) ||
539 IS_HARDWARE_TYPE_8188GTV(pAdapter)
540 ) {
541 u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
542
543 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
544
545 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
546 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
547
548 } else {
549
550 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
551 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
552 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
553 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
554 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
555 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
556 }
557 }
558
559 rtw_hal_set_txpwr_done(pAdapter);
560 } else
561 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
562
563 odm_clear_txpowertracking_state(pDM_Odm);
564 }
565
hal_mpt_SetDataRate(PADAPTER pAdapter)566 void hal_mpt_SetDataRate(PADAPTER pAdapter)
567 {
568 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
569 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
570 u32 DataRate;
571
572 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
573
574 hal_mpt_SwitchRfSetting(pAdapter);
575
576 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
577 #ifdef CONFIG_RTL8723B
578 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
579 if (IS_CCK_RATE(DataRate)) {
580 if (pMptCtx->mpt_rf_path == RF_PATH_A)
581 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
582 else
583 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
584 } else {
585 if (pMptCtx->mpt_rf_path == RF_PATH_A)
586 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
587 else
588 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
589 }
590 }
591
592 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
593 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
594 if (pMptCtx->mpt_rf_path == RF_PATH_A)
595 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
596 else
597 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
598 }
599 #endif
600 }
601
602 #define RF_PATH_AB 22
603
604 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)605 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
606 {
607 u8 Path;
608 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
609
610 for (Path = 0; Path <= RF_PATH_D; Path++) {
611 switch (Path) {
612 case RF_PATH_B:
613 IGReg = rB_IGI_Jaguar;
614 break;
615 case RF_PATH_C:
616 IGReg = rC_IGI_Jaguar2;
617 break;
618 case RF_PATH_D:
619 IGReg = rD_IGI_Jaguar2;
620 break;
621 default:
622 IGReg = rA_IGI_Jaguar;
623 break;
624 }
625
626 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
627 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
628 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
629 }
630 }
631
mpt_SetRFPath_8814A(PADAPTER pAdapter)632 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
633 {
634
635 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
636 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
637 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
638 R_ANTENNA_SELECT_CCK *p_cck_txrx;
639 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
640 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
641 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
642
643 u32 ulAntennaTx = pHalData->antenna_tx_path;
644 u32 ulAntennaRx = pHalData->AntennaRxPath;
645 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
646
647 if (NssforRate == RF_3TX) {
648 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
649
650 switch (ulAntennaTx) {
651 case ANTENNA_BCD:
652 pMptCtx->mpt_rf_path = RF_PATH_BCD;
653 /*pHalData->ValidTxPath = 0x0e;*/
654 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
655 break;
656
657 case ANTENNA_ABC:
658 default:
659 pMptCtx->mpt_rf_path = RF_PATH_ABC;
660 /*pHalData->ValidTxPath = 0x0d;*/
661 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
662 break;
663 }
664
665 } else { /*/if(NssforRate == RF_1TX)*/
666 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
667 switch (ulAntennaTx) {
668 case ANTENNA_BCD:
669 pMptCtx->mpt_rf_path = RF_PATH_BCD;
670 /*pHalData->ValidTxPath = 0x0e;*/
671 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
672 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
673 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
674 break;
675
676 case ANTENNA_BC:
677 pMptCtx->mpt_rf_path = RF_PATH_BC;
678 /*pHalData->ValidTxPath = 0x06;*/
679 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
680 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
681 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
682 break;
683 case ANTENNA_B:
684 pMptCtx->mpt_rf_path = RF_PATH_B;
685 /*pHalData->ValidTxPath = 0x02;*/
686 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
687 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
688 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
689 break;
690
691 case ANTENNA_C:
692 pMptCtx->mpt_rf_path = RF_PATH_C;
693 /*pHalData->ValidTxPath = 0x04;*/
694 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
695 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
696 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
697 break;
698
699 case ANTENNA_D:
700 pMptCtx->mpt_rf_path = RF_PATH_D;
701 /*pHalData->ValidTxPath = 0x08;*/
702 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
703 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
704 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
705 break;
706
707 case ANTENNA_A:
708 default:
709 pMptCtx->mpt_rf_path = RF_PATH_A;
710 /*pHalData->ValidTxPath = 0x01;*/
711 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
712 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
713 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
714 break;
715 }
716 }
717
718 switch (ulAntennaRx) {
719 case ANTENNA_A:
720 /*pHalData->ValidRxPath = 0x01;*/
721 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
722 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
723 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
724 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
725 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
726 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
727 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
728 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
729 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
730 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
731 /*/ CCA related PD_delay_th*/
732 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
733 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
734 break;
735
736 case ANTENNA_B:
737 /*pHalData->ValidRxPath = 0x02;*/
738 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
739 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
740 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
741 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
742 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
743 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
744 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
745 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
746 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
747 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
748 /*/ CCA related PD_delay_th*/
749 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
750 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
751 break;
752
753 case ANTENNA_C:
754 /*pHalData->ValidRxPath = 0x04;*/
755 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
756 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
757 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
758 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
759 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
760 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
761 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
762 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
763 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
764 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
765 /*/ CCA related PD_delay_th*/
766 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
767 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
768 break;
769
770 case ANTENNA_D:
771 /*pHalData->ValidRxPath = 0x08;*/
772 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
773 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
774 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
775 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
776 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
777 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
778 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
779 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
780 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
781 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
782 /*/ CCA related PD_delay_th*/
783 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
784 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
785 break;
786
787 case ANTENNA_BC:
788 /*pHalData->ValidRxPath = 0x06;*/
789 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
790 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
791 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
792 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
793 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
794 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
795 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
796 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
797 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
798 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
799 /*/ CCA related PD_delay_th*/
800 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
801 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
802 break;
803
804 case ANTENNA_CD:
805 /*pHalData->ValidRxPath = 0x0C;*/
806 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
807 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
808 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
809 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
810 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
811 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
812 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
813 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
814 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
815 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
816 /*/ CCA related PD_delay_th*/
817 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
818 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
819 break;
820
821 case ANTENNA_BCD:
822 /*pHalData->ValidRxPath = 0x0e;*/
823 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
824 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
825 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
826 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
827 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
828 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
829 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
830 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
831 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
832 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
833 /*/ CCA related PD_delay_th*/
834 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
835 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
836 break;
837
838 case ANTENNA_ABCD:
839 /*pHalData->ValidRxPath = 0x0f;*/
840 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
841 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
842 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
843 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
844 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
845 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
846 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
847 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
848 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
849 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
850 /*/ CCA related PD_delay_th*/
851 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
852 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
853 break;
854
855 default:
856 break;
857 }
858
859 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
860
861 mpt_ToggleIG_8814A(pAdapter);
862 }
863 #endif /* CONFIG_RTL8814A */
864 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
865 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)866 mpt_SetSingleTone_8814A(
867 PADAPTER pAdapter,
868 BOOLEAN bSingleTone,
869 BOOLEAN bEnPMacTx)
870 {
871
872 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
873 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
874 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
875
876 if (bSingleTone) {
877 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
878 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
879 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
880 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
881
882 switch (pMptCtx->mpt_rf_path) {
883 case RF_PATH_A:
884 case RF_PATH_B:
885 case RF_PATH_C:
886 case RF_PATH_D:
887 StartPath = pMptCtx->mpt_rf_path;
888 EndPath = pMptCtx->mpt_rf_path;
889 break;
890 case RF_PATH_AB:
891 EndPath = RF_PATH_B;
892 break;
893 case RF_PATH_BC:
894 StartPath = RF_PATH_B;
895 EndPath = RF_PATH_C;
896 break;
897 case RF_PATH_ABC:
898 EndPath = RF_PATH_C;
899 break;
900 case RF_PATH_BCD:
901 StartPath = RF_PATH_B;
902 EndPath = RF_PATH_D;
903 break;
904 case RF_PATH_ABCD:
905 EndPath = RF_PATH_D;
906 break;
907 }
908
909 if (bEnPMacTx == FALSE) {
910 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
911 issue_nulldata(pAdapter, NULL, 1, 3, 500);
912 }
913
914 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
915
916 for (path = StartPath; path <= EndPath; path++) {
917 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
918 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
919
920 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
921 }
922
923 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
924 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
925 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
926 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
927 } else {
928 switch (pMptCtx->mpt_rf_path) {
929 case RF_PATH_A:
930 case RF_PATH_B:
931 case RF_PATH_C:
932 case RF_PATH_D:
933 StartPath = pMptCtx->mpt_rf_path;
934 EndPath = pMptCtx->mpt_rf_path;
935 break;
936 case RF_PATH_AB:
937 EndPath = RF_PATH_B;
938 break;
939 case RF_PATH_BC:
940 StartPath = RF_PATH_B;
941 EndPath = RF_PATH_C;
942 break;
943 case RF_PATH_ABC:
944 EndPath = RF_PATH_C;
945 break;
946 case RF_PATH_BCD:
947 StartPath = RF_PATH_B;
948 EndPath = RF_PATH_D;
949 break;
950 case RF_PATH_ABCD:
951 EndPath = RF_PATH_D;
952 break;
953 }
954 for (path = StartPath; path <= EndPath; path++)
955 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
956
957 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
958
959 if (bEnPMacTx == FALSE)
960 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
961
962 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
963 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
964 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
965 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
966 }
967 }
968
969 #endif
970
971 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)972 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
973 {
974 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
975 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
976 struct mp_priv *pmp = &pAdapter->mppriv;
977 u8 channel = pmp->channel;
978 u8 bandwidth = pmp->bandwidth;
979 u8 eLNA_2g = pHalData->ExternalLNA_2G;
980 u32 ulAntennaTx, ulAntennaRx;
981
982 ulAntennaTx = pHalData->antenna_tx_path;
983 ulAntennaRx = pHalData->AntennaRxPath;
984
985 switch (ulAntennaTx) {
986 case ANTENNA_A:
987 pMptCtx->mpt_rf_path = RF_PATH_A;
988 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
989 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
990 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
991 break;
992 case ANTENNA_B:
993 pMptCtx->mpt_rf_path = RF_PATH_B;
994 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
995 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
996 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
997 break;
998 case ANTENNA_AB:
999 pMptCtx->mpt_rf_path = RF_PATH_AB;
1000 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1001 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1002 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1003 break;
1004 default:
1005 pMptCtx->mpt_rf_path = RF_PATH_AB;
1006 RTW_INFO("Unknown Tx antenna.\n");
1007 break;
1008 }
1009
1010 switch (ulAntennaRx) {
1011 u32 reg0xC50 = 0;
1012 case ANTENNA_A:
1013 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1014 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1015 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1016 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1017
1018 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1019 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1020 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1021 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1022
1023 /* set PWED_TH for BB Yn user guide R29 */
1024 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1025 if (channel <= 14) { /* 2.4G */
1026 if (bandwidth == CHANNEL_WIDTH_20
1027 && eLNA_2g == 0) {
1028 /* 0x830[3:1]=3'b010 */
1029 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1030 } else
1031 /* 0x830[3:1]=3'b100 */
1032 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1033 } else
1034 /* 0x830[3:1]=3'b100 for 5G */
1035 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1036 }
1037 break;
1038 case ANTENNA_B:
1039 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1040 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1041 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1042 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1043
1044 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1045 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1046 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1047 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1048
1049 /* set PWED_TH for BB Yn user guide R29 */
1050 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1051 if (channel <= 14) {
1052 if (bandwidth == CHANNEL_WIDTH_20
1053 && eLNA_2g == 0) {
1054 /* 0x830[3:1]=3'b010 */
1055 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1056 } else
1057 /* 0x830[3:1]=3'b100 */
1058 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1059 } else
1060 /* 0x830[3:1]=3'b100 for 5G */
1061 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1062 }
1063 break;
1064 case ANTENNA_AB:
1065 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1066 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1067 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1068 /* set PWED_TH for BB Yn user guide R29 */
1069 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1070 break;
1071 default:
1072 RTW_INFO("Unknown Rx antenna.\n");
1073 break;
1074 }
1075
1076 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1077 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1078 /* WiFi */
1079 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1080 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1081 } else {
1082 /* BT */
1083 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1084 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1085 }
1086 }
1087 }
1088 #endif
1089
1090 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1091 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1092 {
1093 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1094 u32 ulAntennaTx, ulAntennaRx;
1095 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1096 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1097 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1098
1099 ulAntennaTx = pHalData->antenna_tx_path;
1100 ulAntennaRx = pHalData->AntennaRxPath;
1101
1102 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1103 RTW_INFO("This RF chip ID is not supported\n");
1104 return;
1105 }
1106
1107 switch (pAdapter->mppriv.antenna_tx) {
1108 u8 p = 0, i = 0;
1109 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1110 pMptCtx->mpt_rf_path = RF_PATH_A;
1111 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1112 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1113
1114 for (i = 0; i < 3; ++i) {
1115 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1116 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1117
1118 if (offset != 0) {
1119 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1120 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1121 }
1122 }
1123 for (i = 0; i < 2; ++i) {
1124 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1125 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1126
1127 if (offset != 0) {
1128 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1129 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1130 }
1131 }
1132 }
1133 break;
1134 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1135 u32 offset;
1136 u32 data;
1137
1138 pMptCtx->mpt_rf_path = RF_PATH_B;
1139 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1140 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1141
1142 for (i = 0; i < 3; ++i) {
1143 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1144 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1145 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1146 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1147 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1148 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1149 }
1150 }
1151 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1152 for (i = 0; i < 2; ++i) {
1153 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1154 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1155 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1156 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1157 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1158 }
1159 }
1160 }
1161 break;
1162 default:
1163 pMptCtx->mpt_rf_path = RF_PATH_AB;
1164 break;
1165 }
1166 }
1167 #endif
1168
1169 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1170 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1171 {
1172 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1173 u32 ulAntennaTx, ulAntennaRx;
1174 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1175 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1176 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1177
1178 ulAntennaTx = pHalData->antenna_tx_path;
1179 ulAntennaRx = pHalData->AntennaRxPath;
1180
1181 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1182 RTW_INFO("This RF chip ID is not supported\n");
1183 return;
1184 }
1185
1186 switch (pAdapter->mppriv.antenna_tx) {
1187 u8 p = 0, i = 0;
1188
1189 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1190 pMptCtx->mpt_rf_path = RF_PATH_A;
1191 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1192 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1193
1194 for (i = 0; i < 3; ++i) {
1195 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1196 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1197
1198 if (offset != 0) {
1199 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1200 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1201 }
1202
1203 }
1204 for (i = 0; i < 2; ++i) {
1205 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1206 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1207
1208 if (offset != 0) {
1209 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1210 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1211 }
1212 }
1213 }
1214 break;
1215 case ANTENNA_B: { /* Actually path S0 (BT)*/
1216 pMptCtx->mpt_rf_path = RF_PATH_B;
1217 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1218 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1219
1220 for (i = 0; i < 3; ++i) {
1221 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1222 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1223
1224 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1225 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1226 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1227 }
1228 }
1229 for (i = 0; i < 2; ++i) {
1230 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1231 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1232
1233 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1234 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1235 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1236 }
1237 }
1238 }
1239 break;
1240 default:
1241 pMptCtx->mpt_rf_path = RF_PATH_AB;
1242 break;
1243 }
1244
1245 }
1246 #endif
1247
1248 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1249 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1250 {
1251 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1252 u8 p = 0, i = 0;
1253 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1254 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1255 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1256 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1257
1258 ulAntennaTx = pHalData->antenna_tx_path;
1259 ulAntennaRx = pHalData->AntennaRxPath;
1260
1261 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1262 RTW_INFO("This RF chip ID is not supported\n");
1263 return;
1264 }
1265
1266 switch (pAdapter->mppriv.antenna_tx) {
1267 /* Actually path S1 (Wi-Fi) */
1268 case ANTENNA_A: {
1269 pMptCtx->mpt_rf_path = RF_PATH_A;
1270 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1271 }
1272 break;
1273 /* Actually path S0 (BT) */
1274 case ANTENNA_B: {
1275 pMptCtx->mpt_rf_path = RF_PATH_B;
1276 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1277
1278 }
1279 break;
1280 default:
1281 pMptCtx->mpt_rf_path = RF_PATH_AB;
1282 break;
1283 }
1284 }
1285 #endif
1286
mpt_SetRFPath_819X(PADAPTER pAdapter)1287 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1288 {
1289 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1290 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1291 u32 ulAntennaTx, ulAntennaRx;
1292 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1293 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1294 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1295 u8 chgTx = 0, chgRx = 0;
1296 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1297
1298 ulAntennaTx = pHalData->antenna_tx_path;
1299 ulAntennaRx = pHalData->AntennaRxPath;
1300
1301 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1302 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1303
1304 p_ofdm_tx->r_ant_ht1 = 0x1;
1305 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1306 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1307
1308 switch (ulAntennaTx) {
1309 case ANTENNA_A:
1310 p_ofdm_tx->r_tx_antenna = 0x1;
1311 r_ofdm_tx_en_val = 0x1;
1312 p_ofdm_tx->r_ant_l = 0x1;
1313 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1314 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1315 p_cck_txrx->r_ccktx_enable = 0x8;
1316 chgTx = 1;
1317 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1318 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1319 {
1320 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1321 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1322 r_ofdm_tx_en_val = 0x3;
1323 /*/ Power save*/
1324 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1325 /*/ We need to close RFB by SW control*/
1326 if (pHalData->rf_type == RF_2T2R) {
1327 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1328 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1329 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1330 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1331 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1332 }
1333 }
1334 pMptCtx->mpt_rf_path = RF_PATH_A;
1335 break;
1336 case ANTENNA_B:
1337 p_ofdm_tx->r_tx_antenna = 0x2;
1338 r_ofdm_tx_en_val = 0x2;
1339 p_ofdm_tx->r_ant_l = 0x2;
1340 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1341 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1342 p_cck_txrx->r_ccktx_enable = 0x4;
1343 chgTx = 1;
1344 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1345 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1346 {
1347 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1348 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1349
1350 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1351 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1352 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1353 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1354 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1355 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1356 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1357 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1358 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1359 }
1360 }
1361 pMptCtx->mpt_rf_path = RF_PATH_B;
1362 break;
1363 case ANTENNA_AB:/*/ For 8192S*/
1364 p_ofdm_tx->r_tx_antenna = 0x3;
1365 r_ofdm_tx_en_val = 0x3;
1366 p_ofdm_tx->r_ant_l = 0x3;
1367 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1368 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1369 p_cck_txrx->r_ccktx_enable = 0xC;
1370 chgTx = 1;
1371 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1372 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1373 {
1374 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1375 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1376 /* Disable Power save*/
1377 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1378 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1379 if (pHalData->rf_type == RF_2T2R) {
1380 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1381
1382 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1383 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1384 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1385 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1386 }
1387 }
1388 pMptCtx->mpt_rf_path = RF_PATH_AB;
1389 break;
1390 default:
1391 break;
1392 }
1393 #if 0
1394 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1395 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1396 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1397 #endif
1398 switch (ulAntennaRx) {
1399 case ANTENNA_A:
1400 r_rx_antenna_ofdm = 0x1; /* A*/
1401 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1402 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1403 chgRx = 1;
1404 break;
1405 case ANTENNA_B:
1406 r_rx_antenna_ofdm = 0x2; /*/ B*/
1407 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1408 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1409 chgRx = 1;
1410 break;
1411 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1412 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1413 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1414 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1415 chgRx = 1;
1416 break;
1417 default:
1418 break;
1419 }
1420
1421
1422 if (chgTx && chgRx) {
1423 switch (pHalData->rf_chip) {
1424 case RF_8225:
1425 case RF_8256:
1426 case RF_6052:
1427 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1428 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1429 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1430 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1431 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1432 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1433 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1434 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1435 }
1436 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1437 break;
1438
1439 default:
1440 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1441 break;
1442 }
1443 }
1444 } /* MPT_ProSetRFPath */
1445
1446 #ifdef CONFIG_RTL8192F
1447
mpt_set_rfpath_8192f(PADAPTER pAdapter)1448 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1449 {
1450 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1451 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1452
1453 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1454 u8 NssforRate, odmNssforRate;
1455 u32 ulAntennaTx, ulAntennaRx;
1456 u8 RxAntToPhyDm;
1457 u8 TxAntToPhyDm;
1458
1459 ulAntennaTx = pHalData->antenna_tx_path;
1460 ulAntennaRx = pHalData->AntennaRxPath;
1461 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1462
1463 if (pHalData->rf_chip >= RF_TYPE_MAX)
1464 RTW_INFO("This RF chip ID is not supported\n");
1465
1466 switch (ulAntennaTx) {
1467 case ANTENNA_A:
1468 pMptCtx->mpt_rf_path = RF_PATH_A;
1469 TxAntToPhyDm = BB_PATH_A;
1470 break;
1471 case ANTENNA_B:
1472 pMptCtx->mpt_rf_path = RF_PATH_B;
1473 TxAntToPhyDm = BB_PATH_B;
1474 break;
1475 case ANTENNA_AB:
1476 pMptCtx->mpt_rf_path = RF_PATH_AB;
1477 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1478 break;
1479 default:
1480 pMptCtx->mpt_rf_path = RF_PATH_AB;
1481 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1482 break;
1483 }
1484
1485 switch (ulAntennaRx) {
1486 case ANTENNA_A:
1487 RxAntToPhyDm = BB_PATH_A;
1488 break;
1489 case ANTENNA_B:
1490 RxAntToPhyDm = BB_PATH_B;
1491 break;
1492 case ANTENNA_AB:
1493 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1494 break;
1495 default:
1496 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1497 break;
1498 }
1499
1500 config_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE);
1501
1502 }
1503
1504 #endif
1505
hal_mpt_SetAntenna(PADAPTER pAdapter)1506 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1507
1508 {
1509 RTW_INFO("Do %s\n", __func__);
1510 #ifdef CONFIG_RTL8822C
1511 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1512 rtl8822c_mp_config_rfpath(pAdapter);
1513 return;
1514 }
1515 #endif
1516 #ifdef CONFIG_RTL8814A
1517 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1518 mpt_SetRFPath_8814A(pAdapter);
1519 return;
1520 }
1521 #endif
1522 #ifdef CONFIG_RTL8822B
1523 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1524 rtl8822b_mp_config_rfpath(pAdapter);
1525 return;
1526 }
1527 #endif
1528 #ifdef CONFIG_RTL8821C
1529 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1530 rtl8821c_mp_config_rfpath(pAdapter);
1531 return;
1532 }
1533 #endif
1534 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1535 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1536 mpt_SetRFPath_8812A(pAdapter);
1537 return;
1538 }
1539 #endif
1540 #ifdef CONFIG_RTL8723B
1541 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1542 mpt_SetRFPath_8723B(pAdapter);
1543 return;
1544 }
1545 #endif
1546
1547 #ifdef CONFIG_RTL8703B
1548 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1549 mpt_SetRFPath_8703B(pAdapter);
1550 return;
1551 }
1552 #endif
1553
1554 #ifdef CONFIG_RTL8723D
1555 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1556 mpt_SetRFPath_8723D(pAdapter);
1557 return;
1558 }
1559 #endif
1560
1561 #ifdef CONFIG_RTL8192F
1562 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1563 mpt_set_rfpath_8192f(pAdapter);
1564 return;
1565 }
1566 #endif
1567
1568 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1569 mpt_SetRFPath_8821B(pAdapter);
1570 Prepare for 8822B
1571 else if (IS_HARDWARE_TYPE_8822B(Context))
1572 mpt_SetRFPath_8822B(Context);
1573 */
1574 mpt_SetRFPath_819X(pAdapter);
1575 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1576 }
1577
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1578 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1579 {
1580 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1581
1582 if (!netif_running(pAdapter->pnetdev)) {
1583 return _FAIL;
1584 }
1585
1586
1587 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1588 return _FAIL;
1589 }
1590
1591
1592 target_ther &= 0xff;
1593 if (target_ther < 0x07)
1594 target_ther = 0x07;
1595 else if (target_ther > 0x1d)
1596 target_ther = 0x1d;
1597
1598 pHalData->eeprom_thermal_meter = target_ther;
1599
1600 return _SUCCESS;
1601 }
1602
1603
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1604 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1605 {
1606 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1607 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1608 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1609 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1610 } else
1611 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1612
1613 }
1614
1615
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1616 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1617
1618 {
1619 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1620
1621 u32 ThermalValue = 0;
1622 s32 thermal_value_temp = 0;
1623 s8 thermal_offset = 0;
1624 u32 thermal_reg_mask = 0;
1625
1626 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1627 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1628 else
1629 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1630
1631 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1632
1633 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1634
1635 thermal_value_temp = ThermalValue + thermal_offset;
1636
1637 if (thermal_value_temp > 63)
1638 ThermalValue = 63;
1639 else if (thermal_value_temp < 0)
1640 ThermalValue = 0;
1641 else
1642 ThermalValue = thermal_value_temp;
1643
1644 return (u8)ThermalValue;
1645 }
1646
1647
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1648 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1649 {
1650 #if 0
1651 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1652 rtw_msleep_os(1000);
1653 fw_cmd_data(pAdapter, value, 1);
1654 *value &= 0xFF;
1655 #else
1656 hal_mpt_TriggerRFThermalMeter(pAdapter);
1657 rtw_msleep_os(1000);
1658 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1659 #endif
1660
1661 }
1662
1663
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1664 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1665 {
1666 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1667
1668 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1669
1670 if (bStart) {/*/ Start Single Carrier.*/
1671 /*/ Start Single Carrier.*/
1672 /*/ 1. if OFDM block on?*/
1673 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1674 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1675
1676 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1677 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1678
1679 /*/ 3. turn on scramble setting*/
1680 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1681
1682 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1683 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1684 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1685 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1686 else
1687 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1688 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1689
1690 } else {
1691 /*/ Stop Single Carrier.*/
1692 /*/ Stop Single Carrier.*/
1693 /*/ Turn off all test modes.*/
1694 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1695 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1696 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1697 else
1698 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1699 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1700
1701 rtw_msleep_os(10);
1702 /*/BB Reset*/
1703 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1704 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1705 }
1706 }
1707
1708
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1709 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1710 {
1711 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1712 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1713 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1714 u32 ulAntennaTx = pHalData->antenna_tx_path;
1715 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1716 u8 rfPath;
1717
1718 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1719 #ifdef PHYDM_MP_SUPPORT
1720 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1721 #endif
1722 return;
1723 }
1724
1725 switch (ulAntennaTx) {
1726 case ANTENNA_B:
1727 rfPath = RF_PATH_B;
1728 break;
1729 case ANTENNA_C:
1730 rfPath = RF_PATH_C;
1731 break;
1732 case ANTENNA_D:
1733 rfPath = RF_PATH_D;
1734 break;
1735 case ANTENNA_A:
1736 default:
1737 rfPath = RF_PATH_A;
1738 break;
1739 }
1740
1741 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1742 if (bStart) {
1743 /*/ Start Single Tone.*/
1744 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1745 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1746 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1747 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1748 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1749 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1750 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1751 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1752 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1753 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1754 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1755 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1756 #ifdef CONFIG_RTL8192F
1757 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1758 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1759 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1760 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1761 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1762 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1763 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1764 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1765 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1766 #endif
1767 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1768 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1769 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1770 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1771 } else {
1772 /*/ S0/S1 both use PATH A to configure*/
1773 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1774 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1775 }
1776 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1777 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1778 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1779 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1780 }
1781 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1782 /*Set BB REG 88C: Prevent SingleTone Fail*/
1783 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1784 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1785 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1786
1787 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1788 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1789 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1790 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1791 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1792 } else {/* S0/S1 both use PATH A to configure */
1793 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1794 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1795 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1796 }
1797 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1798 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1799 u8 p = RF_PATH_A;
1800
1801 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1802 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1803 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1804 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1805 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1806
1807 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1808
1809 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1810 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1811 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1812 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1813 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1814 }
1815 } else {
1816 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1817 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1818 #ifdef CONFIG_RTL8821C
1819 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1820 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1821 else
1822 #endif
1823 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1824 }
1825 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1826 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1827 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1828 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1829 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1830 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1831 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1832 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1833 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1834
1835 if (pHalData->external_pa_5g)
1836 {
1837 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1838 }
1839 else if (pHalData->ExternalPA_2G)
1840 {
1841 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1842 }
1843 } else {
1844 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1845 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1846
1847 if (pHalData->external_pa_5g) {
1848 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1849 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1850 } else if (pHalData->ExternalPA_2G) {
1851 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1852 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1853 }
1854 }
1855 #endif
1856 }
1857 #if defined(CONFIG_RTL8814A)
1858 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1859 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1860 #endif
1861 else /*/ Turn On SingleTone and turn off the other test modes.*/
1862 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1863
1864 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1865 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1866
1867 } else {/*/ Stop Single Ton e.*/
1868
1869 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1870 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1871 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1872 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1873 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1874 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1875 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1876 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1877 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1878 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1879 #ifdef CONFIG_RTL8192F
1880 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1881 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1882 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1883 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1884 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1885 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1886 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1887 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1888 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1889 #endif
1890 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1891 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1892 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1893 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1894 } else {
1895 /*/ S0/S1 both use PATH A to configure*/
1896 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1897 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1898 }
1899 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1900 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1901 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1902 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1903 }
1904 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1905 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1906 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1907 /*Set BB REG 88C: Prevent SingleTone Fail*/
1908 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1909 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1910 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1911 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1912 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1913 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1914 } else { /* S0/S1 both use PATH A to configure */
1915 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1916 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1917 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
1918 }
1919 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1920 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1921 u8 p = RF_PATH_A;
1922
1923 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
1924
1925 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1926 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1927 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1928 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1929 }
1930 } else {
1931 p = pMptCtx->mpt_rf_path;
1932 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1933
1934 if (IS_HARDWARE_TYPE_8821C(pAdapter))
1935 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
1936
1937 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1938 }
1939
1940 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1941 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1942 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
1943 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
1944
1945 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1946 RTW_INFO("Restore RFE control Pin cbc\n");
1947 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
1948 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
1949 }
1950 #endif
1951 }
1952 #if defined(CONFIG_RTL8814A)
1953 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1954 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1955
1956 else/*/ Turn off all test modes.*/
1957 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1958 #endif
1959 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1960 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1961
1962 }
1963 }
1964
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1965 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1966 {
1967 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1968 struct dm_struct *pdm_odm = &pHalData->odmpriv;
1969 u8 Rate;
1970
1971 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
1972
1973 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1974 #ifdef PHYDM_MP_SUPPORT
1975 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
1976 #endif
1977 return;
1978 }
1979
1980 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
1981 if (bStart) {/* Start Carrier Suppression.*/
1982 if (Rate <= MPT_RATE_11M) {
1983 /*/ 1. if CCK block on?*/
1984 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1985 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1986
1987 /*/Turn Off All Test Mode*/
1988 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1989 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
1990 else
1991 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1992
1993 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1994 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
1995
1996 /*/Set CCK Tx Test Rate*/
1997 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
1998 }
1999
2000 /*Set for dynamic set Power index*/
2001 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2002 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2003
2004 } else {/* Stop Carrier Suppression.*/
2005
2006 if (Rate <= MPT_RATE_11M) {
2007 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2008 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2009
2010 /*BB Reset*/
2011 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2012 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2013 }
2014 /*Stop for dynamic set Power index*/
2015 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2016 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2017 }
2018 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2019 }
2020
hal_mpt_query_phytxok(PADAPTER pAdapter)2021 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2022 {
2023 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2024 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2025 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2026 u16 count = 0;
2027
2028 #ifdef PHYDM_MP_SUPPORT
2029 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2030 struct phydm_mp *mp = &dm->dm_mp_table;
2031
2032 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2033 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2034 count = mp->tx_phy_ok_cnt;
2035
2036 } else
2037 #endif
2038 {
2039
2040 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2041 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2042 else
2043 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2044 }
2045
2046 if (count > 50000) {
2047 rtw_reset_phy_trx_ok_counters(pAdapter);
2048 pAdapter->mppriv.tx.sended += count;
2049 count = 0;
2050 }
2051
2052 return pAdapter->mppriv.tx.sended + count;
2053
2054 }
2055
mpt_StopCckContTx(PADAPTER pAdapter)2056 static void mpt_StopCckContTx(
2057 PADAPTER pAdapter
2058 )
2059 {
2060 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2061 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2062 u8 u1bReg;
2063
2064 pMptCtx->bCckContTx = FALSE;
2065 pMptCtx->bOfdmContTx = FALSE;
2066
2067 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2068 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2069
2070 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2071 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2072 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2073
2074 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2075 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2076 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2077 }
2078
2079 /*BB Reset*/
2080 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2081 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2082
2083 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2084 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2085 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2086 }
2087
2088 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2089 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2090 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2091 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2092 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2093 }
2094
2095 } /* mpt_StopCckContTx */
2096
2097
mpt_StopOfdmContTx(PADAPTER pAdapter)2098 static void mpt_StopOfdmContTx(
2099 PADAPTER pAdapter
2100 )
2101 {
2102 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2103 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2104 u8 u1bReg;
2105 u32 data;
2106
2107 pMptCtx->bCckContTx = FALSE;
2108 pMptCtx->bOfdmContTx = FALSE;
2109
2110 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2111 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2112 else
2113 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2114
2115 rtw_mdelay_os(10);
2116
2117 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2118 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2119 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2120 }
2121
2122 /*BB Reset*/
2123 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2124 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2125
2126 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2127 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2128 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2129 }
2130 } /* mpt_StopOfdmContTx */
2131
2132
mpt_StartCckContTx(PADAPTER pAdapter)2133 static void mpt_StartCckContTx(
2134 PADAPTER pAdapter
2135 )
2136 {
2137 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2138 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2139 u32 cckrate;
2140
2141 /* 1. if CCK block on */
2142 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2143 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2144
2145 /*Turn Off All Test Mode*/
2146 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2147 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2148 else
2149 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2150
2151 cckrate = pAdapter->mppriv.rateidx;
2152
2153 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2154
2155 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2156 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2157
2158 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2159 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2160 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2161 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2162 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2163 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2164 }
2165
2166 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2167 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2168 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2169 }
2170
2171 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2172 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2173 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2174 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2175 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2176 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2177 else
2178 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2179 }
2180
2181 pMptCtx->bCckContTx = TRUE;
2182 pMptCtx->bOfdmContTx = FALSE;
2183
2184 } /* mpt_StartCckContTx */
2185
2186
mpt_StartOfdmContTx(PADAPTER pAdapter)2187 static void mpt_StartOfdmContTx(
2188 PADAPTER pAdapter
2189 )
2190 {
2191 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2192 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2193
2194 /* 1. if OFDM block on?*/
2195 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2196 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2197
2198 /* 2. set CCK test mode off, set to CCK normal mode*/
2199 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2200
2201 /* 3. turn on scramble setting*/
2202 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2203
2204 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2205 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2206 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2207 }
2208
2209 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2210 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2211 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2212 else
2213 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2214
2215 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2216 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2217 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2218 }
2219
2220 pMptCtx->bCckContTx = FALSE;
2221 pMptCtx->bOfdmContTx = TRUE;
2222 } /* mpt_StartOfdmContTx */
2223
2224 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
2225 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2226 static void mpt_convert_phydm_txinfo_for_jaguar3(
2227 RT_PMAC_TX_INFO pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2228 {
2229 phydmtxinfo->en_pmac_tx = pMacTxInfo.bEnPMacTx;
2230 phydmtxinfo->mode = pMacTxInfo.Mode;
2231 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo.TX_RATE));
2232 phydmtxinfo->tx_sc = pMacTxInfo.TX_SC;
2233 phydmtxinfo->is_short_preamble = pMacTxInfo.bSPreamble;
2234 phydmtxinfo->ndp_sound = pMacTxInfo.NDP_sound;
2235 phydmtxinfo->bw = pMacTxInfo.BandWidth;
2236 phydmtxinfo->m_stbc = pMacTxInfo.m_STBC;
2237 phydmtxinfo->packet_period = pMacTxInfo.PacketPeriod;
2238 phydmtxinfo->packet_count = pMacTxInfo.PacketCount;
2239 phydmtxinfo->packet_pattern = pMacTxInfo.PacketPattern;
2240 phydmtxinfo->sfd = pMacTxInfo.SFD;
2241 phydmtxinfo->signal_field = pMacTxInfo.SignalField;
2242 phydmtxinfo->service_field = pMacTxInfo.ServiceField;
2243 phydmtxinfo->length = pMacTxInfo.LENGTH;
2244 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo.CRC16, 2);
2245 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo.LSIG,3);
2246 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo.HT_SIG,6);
2247 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo.VHT_SIG_A,6);
2248 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo.VHT_SIG_B,4);
2249 phydmtxinfo->vht_sig_b_crc = pMacTxInfo.VHT_SIG_B_CRC;
2250 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo.VHT_Delimiter,4);
2251 }
2252 #endif
2253
2254 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2255 void mpt_ProSetPMacTx(PADAPTER Adapter)
2256 {
2257 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2258 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2259 struct mp_priv *pmppriv = &Adapter->mppriv;
2260 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2261 u32 u4bTmp;
2262 struct dm_struct *p_dm_odm;
2263
2264 p_dm_odm = &pHalData->odmpriv;
2265
2266 #if 0
2267 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2268 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2269 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2270 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2271 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2272 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2273
2274 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2275 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2276 #endif
2277 if (pmppriv->pktInterval != 0)
2278 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2279
2280 if (pmppriv->tx.count != 0)
2281 PMacTxInfo.PacketCount = pmppriv->tx.count;
2282
2283 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2284 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2285 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2286
2287 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2288 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2289 struct phydm_pmac_info phydm_mactxinfo;
2290
2291 if (PMacTxInfo.bEnPMacTx == TRUE) {
2292 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2293 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2294 if (PMacTxInfo.Mode == CONTINUOUS_TX)
2295 hal_mpt_SetTxPower(Adapter);
2296 } else {
2297 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2298 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2299 pMptCtx->HWTxmode = TEST_NONE;
2300 }
2301 mpt_convert_phydm_txinfo_for_jaguar3(PMacTxInfo, &phydm_mactxinfo);
2302 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2303 #endif
2304 return;
2305 }
2306
2307 if (PMacTxInfo.bEnPMacTx == FALSE) {
2308 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2309 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2310 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2311 mpt_StopCckContTx(Adapter);
2312 else
2313 mpt_StopOfdmContTx(Adapter);
2314 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2315 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2316 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2317 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2318 } else
2319 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2320
2321 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2322 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2323 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2324 mpt_StopCckContTx(Adapter);
2325 else
2326 mpt_StopOfdmContTx(Adapter);
2327
2328 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2329 }
2330 pMptCtx->HWTxmode = TEST_NONE;
2331 return;
2332 }
2333
2334 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2335
2336 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2337 pMptCtx->HWTxmode = CONTINUOUS_TX;
2338 PMacTxInfo.PacketCount = 1;
2339
2340 hal_mpt_SetTxPower(Adapter);
2341
2342 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2343 mpt_StartCckContTx(Adapter);
2344 else
2345 mpt_StartOfdmContTx(Adapter);
2346 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2347 /* Continuous TX -> HW TX -> RF Setting */
2348 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2349 PMacTxInfo.PacketCount = 1;
2350
2351 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2352 mpt_StartCckContTx(Adapter);
2353 else
2354 mpt_StartOfdmContTx(Adapter);
2355 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2356 pMptCtx->HWTxmode = PACKETS_TX;
2357 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2358 PMacTxInfo.PacketCount = 0xffff;
2359 }
2360
2361 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2362 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2363 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2364 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2365 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2366 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2367 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2368 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2369 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2370
2371 if (PMacTxInfo.bSPreamble)
2372 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2373 else
2374 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2375 } else {
2376 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2377
2378 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2379 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2380
2381 if (PMacTxInfo.PacketPattern == 0x12)
2382 u4bTmp = 0x3000000;
2383 else
2384 u4bTmp = 0;
2385 }
2386
2387 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2388 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2389 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2390 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2391 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2392 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2393 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2394 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2395 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2396 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2397
2398 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2399 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2400 }
2401
2402 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2403 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2404 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2405
2406 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2407 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2408
2409 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2410 /*& Duration & Frame control*/
2411 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2412
2413 /* Address1 [0:3]*/
2414 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2415 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2416
2417 /* Address3 [3:0]*/
2418 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2419
2420 /* Address2[0:1] & Address1 [5:4]*/
2421 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2422 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2423
2424 /* Address2 [5:2]*/
2425 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2426 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2427
2428 /* Sequence Control & Address3 [5:4]*/
2429 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2430 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2431 } else {
2432 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2433 /* & Duration & Frame control */
2434 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2435
2436 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2437 /* Address1 [0:3]*/
2438 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2439 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2440
2441 /* Address3 [3:0]*/
2442 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2443
2444 /* Address2[0:1] & Address1 [5:4]*/
2445 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2446 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2447
2448 /* Address2 [5:2] */
2449 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2450 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2451
2452 /* Sequence Control & Address3 [5:4]*/
2453 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2454 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2455 }
2456
2457 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2458
2459 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2460 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2461 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2462
2463 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2464 u32 offset = 0xb44;
2465
2466 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2467 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2468 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2469 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2470 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2471 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2472
2473 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2474 u32 offset = 0xb4c;
2475
2476 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2477 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2478 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2479 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2480 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2481 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2482 }
2483
2484 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2485 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2486 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2487 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2488 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2489 } else
2490 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2491
2492 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2493 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2494
2495 }
2496
2497 #endif
2498
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2499 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2500 {
2501 u8 Rate;
2502
2503 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2504 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2505 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2506
2507 if (Rate <= MPT_RATE_11M) {
2508 if (bStart)
2509 mpt_StartCckContTx(pAdapter);
2510 else
2511 mpt_StopCckContTx(pAdapter);
2512
2513 } else if (Rate >= MPT_RATE_6M) {
2514 if (bStart)
2515 mpt_StartOfdmContTx(pAdapter);
2516 else
2517 mpt_StopOfdmContTx(pAdapter);
2518 }
2519 }
2520
2521 #endif /* CONFIG_MP_INCLUDE*/
2522