1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #define _HAL_INTF_C_
18
19 #include <drv_types.h>
20 #include <hal_data.h>
21
22 const u32 _chip_type_to_odm_ic_type[] = {
23 0,
24 ODM_RTL8188E,
25 ODM_RTL8192E,
26 ODM_RTL8812,
27 ODM_RTL8821,
28 ODM_RTL8723B,
29 ODM_RTL8814A,
30 ODM_RTL8703B,
31 ODM_RTL8188F,
32 ODM_RTL8188F,
33 ODM_RTL8822B,
34 ODM_RTL8723D,
35 ODM_RTL8821C,
36 ODM_RTL8710B,
37 ODM_RTL8192F,
38 ODM_RTL8822C,
39 0,
40 };
41
rtw_hal_chip_configure(_adapter * padapter)42 void rtw_hal_chip_configure(_adapter *padapter)
43 {
44 padapter->hal_func.intf_chip_configure(padapter);
45 }
46
47 /*
48 * Description:
49 * Read chip internal ROM data
50 *
51 * Return:
52 * _SUCCESS success
53 * _FAIL fail
54 */
rtw_hal_read_chip_info(_adapter * padapter)55 u8 rtw_hal_read_chip_info(_adapter *padapter)
56 {
57 u8 rtn = _SUCCESS;
58 u8 hci_type = rtw_get_intf_type(padapter);
59 systime start = rtw_get_current_time();
60
61 /* before access eFuse, make sure card enable has been called */
62 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
63 && !rtw_is_hw_init_completed(padapter))
64 rtw_hal_power_on(padapter);
65
66 rtn = padapter->hal_func.read_adapter_info(padapter);
67
68 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
69 && !rtw_is_hw_init_completed(padapter))
70 rtw_hal_power_off(padapter);
71
72 RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
73
74 return rtn;
75 }
76
rtw_hal_read_chip_version(_adapter * padapter)77 void rtw_hal_read_chip_version(_adapter *padapter)
78 {
79 padapter->hal_func.read_chip_version(padapter);
80 rtw_odm_init_ic_type(padapter);
81 }
82
rtw_init_wireless_mode(_adapter * padapter)83 static void rtw_init_wireless_mode(_adapter *padapter)
84 {
85 u8 proto_wireless_mode = 0;
86 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
87 if(hal_spec->proto_cap & PROTO_CAP_11B)
88 proto_wireless_mode |= WIRELESS_11B;
89
90 if(hal_spec->proto_cap & PROTO_CAP_11G)
91 proto_wireless_mode |= WIRELESS_11G;
92 #ifdef CONFIG_80211AC_VHT
93 if(hal_spec->band_cap & BAND_CAP_5G)
94 proto_wireless_mode |= WIRELESS_11A;
95 #endif
96
97 #ifdef CONFIG_80211N_HT
98 if(hal_spec->proto_cap & PROTO_CAP_11N) {
99
100 if(hal_spec->band_cap & BAND_CAP_2G)
101 proto_wireless_mode |= WIRELESS_11_24N;
102 if(hal_spec->band_cap & BAND_CAP_5G)
103 proto_wireless_mode |= WIRELESS_11_5N;
104 }
105 #endif
106
107 #ifdef CONFIG_80211AC_VHT
108 if(hal_spec->proto_cap & PROTO_CAP_11AC)
109 proto_wireless_mode |= WIRELESS_11AC;
110 #endif
111 padapter->registrypriv.wireless_mode &= proto_wireless_mode;
112 }
113
rtw_hal_def_value_init(_adapter * padapter)114 void rtw_hal_def_value_init(_adapter *padapter)
115 {
116 if (is_primary_adapter(padapter)) {
117 /*init fw_psmode_iface_id*/
118 adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
119 /*wireless_mode*/
120 rtw_init_wireless_mode(padapter);
121 padapter->hal_func.init_default_value(padapter);
122
123 rtw_init_hal_com_default_value(padapter);
124
125 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
126 adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
127 adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
128 #endif
129 #ifdef CONFIG_HW_P0_TSF_SYNC
130 adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
131 adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
132 #endif
133
134 GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
135 }
136 }
137
rtw_hal_data_init(_adapter * padapter)138 u8 rtw_hal_data_init(_adapter *padapter)
139 {
140 if (is_primary_adapter(padapter)) {
141 padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
142 padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
143 if (padapter->HalData == NULL) {
144 RTW_INFO("cant not alloc memory for HAL DATA\n");
145 return _FAIL;
146 }
147 rtw_phydm_priv_init(padapter);
148 }
149 return _SUCCESS;
150 }
151
rtw_hal_data_deinit(_adapter * padapter)152 void rtw_hal_data_deinit(_adapter *padapter)
153 {
154 if (is_primary_adapter(padapter)) {
155 if (padapter->HalData) {
156 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
157 phy_free_filebuf(padapter);
158 #endif
159 rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
160 padapter->HalData = NULL;
161 padapter->hal_data_sz = 0;
162 }
163 }
164 }
165
rtw_hal_free_data(_adapter * padapter)166 void rtw_hal_free_data(_adapter *padapter)
167 {
168 /* free HAL Data */
169 rtw_hal_data_deinit(padapter);
170 }
rtw_hal_dm_init(_adapter * padapter)171 void rtw_hal_dm_init(_adapter *padapter)
172 {
173 if (is_primary_adapter(padapter)) {
174 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
175
176 padapter->hal_func.dm_init(padapter);
177
178 _rtw_spinlock_init(&pHalData->IQKSpinLock);
179
180 phy_load_tx_power_ext_info(padapter, 1);
181 }
182 }
rtw_hal_dm_deinit(_adapter * padapter)183 void rtw_hal_dm_deinit(_adapter *padapter)
184 {
185 if (is_primary_adapter(padapter)) {
186 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
187
188 padapter->hal_func.dm_deinit(padapter);
189
190 _rtw_spinlock_free(&pHalData->IQKSpinLock);
191 }
192 }
193
194 #ifdef CONFIG_RTW_SW_LED
rtw_hal_sw_led_init(_adapter * padapter)195 void rtw_hal_sw_led_init(_adapter *padapter)
196 {
197 struct led_priv *ledpriv = adapter_to_led(padapter);
198
199 if (ledpriv->bRegUseLed == _FALSE)
200 return;
201
202 if (!is_primary_adapter(padapter))
203 return;
204
205 if (padapter->hal_func.InitSwLeds) {
206 padapter->hal_func.InitSwLeds(padapter);
207 rtw_led_set_ctl_en_mask_primary(padapter);
208 rtw_led_set_iface_en(padapter, 1);
209 }
210 }
211
rtw_hal_sw_led_deinit(_adapter * padapter)212 void rtw_hal_sw_led_deinit(_adapter *padapter)
213 {
214 struct led_priv *ledpriv = adapter_to_led(padapter);
215
216 if (ledpriv->bRegUseLed == _FALSE)
217 return;
218
219 if (!is_primary_adapter(padapter))
220 return;
221
222 if (padapter->hal_func.DeInitSwLeds)
223 padapter->hal_func.DeInitSwLeds(padapter);
224 }
225 #endif
226
rtw_hal_power_on(_adapter * padapter)227 u32 rtw_hal_power_on(_adapter *padapter)
228 {
229 u32 ret = 0;
230 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
231
232 ret = padapter->hal_func.hal_power_on(padapter);
233
234 #ifdef CONFIG_BT_COEXIST
235 if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
236 rtw_btcoex_PowerOnSetting(padapter);
237 #endif
238
239 return ret;
240 }
rtw_hal_power_off(_adapter * padapter)241 void rtw_hal_power_off(_adapter *padapter)
242 {
243 struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
244
245 _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
246 _rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
247
248 #ifdef CONFIG_LPS_1T1R
249 GET_HAL_DATA(padapter)->lps_1t1r = 0;
250 #endif
251
252 #ifdef CONFIG_BT_COEXIST
253 rtw_btcoex_PowerOffSetting(padapter);
254 #endif
255
256 padapter->hal_func.hal_power_off(padapter);
257 }
258
259
rtw_hal_init_opmode(_adapter * padapter)260 void rtw_hal_init_opmode(_adapter *padapter)
261 {
262 NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
263 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
264 sint fw_state;
265
266 fw_state = get_fwstate(pmlmepriv);
267
268 if (fw_state & WIFI_ADHOC_STATE)
269 networkType = Ndis802_11IBSS;
270 else if (fw_state & WIFI_STATION_STATE)
271 networkType = Ndis802_11Infrastructure;
272 #ifdef CONFIG_AP_MODE
273 else if (fw_state & WIFI_AP_STATE)
274 networkType = Ndis802_11APMode;
275 #endif
276 #ifdef CONFIG_RTW_MESH
277 else if (fw_state & WIFI_MESH_STATE)
278 networkType = Ndis802_11_mesh;
279 #endif
280 else
281 return;
282
283 rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
284 }
285
286 #ifdef CONFIG_NEW_NETDEV_HDL
rtw_hal_iface_init(_adapter * adapter)287 uint rtw_hal_iface_init(_adapter *adapter)
288 {
289 uint status = _SUCCESS;
290
291 rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
292 #ifdef RTW_HALMAC
293 rtw_hal_hw_port_enable(adapter);
294 #endif
295 rtw_sec_restore_wep_key(adapter);
296 rtw_hal_init_opmode(adapter);
297 rtw_hal_start_thread(adapter);
298 return status;
299 }
rtw_hal_init(_adapter * padapter)300 uint rtw_hal_init(_adapter *padapter)
301 {
302 uint status = _SUCCESS;
303
304 halrf_set_rfsupportability(adapter_to_phydm(padapter));
305
306 status = padapter->hal_func.hal_init(padapter);
307
308 if (status == _SUCCESS) {
309 rtw_set_hw_init_completed(padapter, _TRUE);
310 if (padapter->registrypriv.notch_filter == 1)
311 rtw_hal_notch_filter(padapter, 1);
312 rtw_led_control(padapter, LED_CTL_POWER_ON);
313 init_hw_mlme_ext(padapter);
314 #ifdef CONFIG_RF_POWER_TRIM
315 rtw_bb_rf_gain_offset(padapter);
316 #endif /*CONFIG_RF_POWER_TRIM*/
317 GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
318 #ifdef CONFIG_MI_WITH_MBSSID_CAM
319 rtw_mi_set_mbid_cam(padapter);
320 #endif
321 #ifdef CONFIG_SUPPORT_MULTI_BCN
322 rtw_ap_multi_bcn_cfg(padapter);
323 #endif
324 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
325 #ifdef CONFIG_DYNAMIC_SOML
326 rtw_dyn_soml_config(padapter);
327 #endif
328 #endif
329 #ifdef CONFIG_TDMADIG
330 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
331 #endif/*CONFIG_TDMADIG*/
332 #ifdef CONFIG_RTW_TX_2PATH_EN
333 rtw_phydm_tx_2path_en(padapter);
334 #endif
335 } else {
336 rtw_set_hw_init_completed(padapter, _FALSE);
337 RTW_ERR("%s: hal_init fail\n", __func__);
338 }
339 return status;
340 }
341 #else
rtw_hal_init(_adapter * padapter)342 uint rtw_hal_init(_adapter *padapter)
343 {
344 uint status = _SUCCESS;
345 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
346 int i;
347
348 halrf_set_rfsupportability(adapter_to_phydm(padapter));
349
350 status = padapter->hal_func.hal_init(padapter);
351
352 if (status == _SUCCESS) {
353 rtw_set_hw_init_completed(padapter, _TRUE);
354 rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
355 #ifdef RTW_HALMAC
356 rtw_restore_hw_port_cfg(padapter);
357 #endif
358 if (padapter->registrypriv.notch_filter == 1)
359 rtw_hal_notch_filter(padapter, 1);
360
361 for (i = 0; i < dvobj->iface_nums; i++)
362 rtw_sec_restore_wep_key(dvobj->padapters[i]);
363
364 rtw_led_control(padapter, LED_CTL_POWER_ON);
365
366 init_hw_mlme_ext(padapter);
367
368 rtw_hal_init_opmode(padapter);
369
370 #ifdef CONFIG_RF_POWER_TRIM
371 rtw_bb_rf_gain_offset(padapter);
372 #endif /*CONFIG_RF_POWER_TRIM*/
373
374 #ifdef CONFIG_SUPPORT_MULTI_BCN
375 rtw_ap_multi_bcn_cfg(padapter);
376 #endif
377
378 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
379 #ifdef CONFIG_DYNAMIC_SOML
380 rtw_dyn_soml_config(padapter);
381 #endif
382 #endif
383 #ifdef CONFIG_TDMADIG
384 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
385 #endif/*CONFIG_TDMADIG*/
386
387 #ifdef CONFIG_RTW_TX_2PATH_EN
388 rtw_phydm_tx_2path_en(padapter);
389 #endif
390 } else {
391 rtw_set_hw_init_completed(padapter, _FALSE);
392 RTW_ERR("%s: fail\n", __func__);
393 }
394
395
396 return status;
397
398 }
399 #endif
400
rtw_hal_deinit(_adapter * padapter)401 uint rtw_hal_deinit(_adapter *padapter)
402 {
403 uint status = _SUCCESS;
404 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
405 int i;
406
407 status = padapter->hal_func.hal_deinit(padapter);
408
409 if (status == _SUCCESS) {
410 rtw_led_control(padapter, LED_CTL_POWER_OFF);
411 rtw_set_hw_init_completed(padapter, _FALSE);
412 } else
413 RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
414
415
416 return status;
417 }
418
rtw_hal_set_hwreg(_adapter * padapter,u8 variable,u8 * val)419 u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
420 {
421 return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
422 }
423
rtw_hal_get_hwreg(_adapter * padapter,u8 variable,u8 * val)424 void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
425 {
426 padapter->hal_func.GetHwRegHandler(padapter, variable, val);
427 }
428
rtw_hal_set_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)429 u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
430 {
431 return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
432 }
rtw_hal_get_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)433 u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
434 {
435 return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
436 }
437
rtw_hal_set_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)438 void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
439 {
440 padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
441 }
rtw_hal_get_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)442 void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
443 {
444 padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
445 }
446
447 /* FOR SDIO & PCIE */
rtw_hal_enable_interrupt(_adapter * padapter)448 void rtw_hal_enable_interrupt(_adapter *padapter)
449 {
450 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
451 padapter->hal_func.enable_interrupt(padapter);
452 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
453 }
454
455 /* FOR SDIO & PCIE */
rtw_hal_disable_interrupt(_adapter * padapter)456 void rtw_hal_disable_interrupt(_adapter *padapter)
457 {
458 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
459 padapter->hal_func.disable_interrupt(padapter);
460 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
461 }
462
463
rtw_hal_check_ips_status(_adapter * padapter)464 u8 rtw_hal_check_ips_status(_adapter *padapter)
465 {
466 u8 val = _FALSE;
467 if (padapter->hal_func.check_ips_status)
468 val = padapter->hal_func.check_ips_status(padapter);
469 else
470 RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
471
472 return val;
473 }
474
rtw_hal_fw_dl(_adapter * padapter,u8 wowlan)475 s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
476 {
477 s32 ret;
478
479 ret = padapter->hal_func.fw_dl(padapter, wowlan);
480
481 #ifdef CONFIG_LPS_1T1R
482 GET_HAL_DATA(padapter)->lps_1t1r = 0;
483 #endif
484
485 return ret;
486 }
487
488 #ifdef RTW_HALMAC
rtw_hal_fw_mem_dl(_adapter * padapter,enum fw_mem mem)489 s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
490 {
491 systime dlfw_start_time = rtw_get_current_time();
492 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
493 struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
494 s32 rst = _FALSE;
495
496 rst = padapter->hal_func.fw_mem_dl(padapter, mem);
497 RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
498
499 if (rst == _FALSE)
500 pdbgpriv->dbg_fw_mem_dl_error_cnt++;
501 if (1)
502 RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
503 return rst;
504 }
505 #endif
506
507 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
rtw_hal_clear_interrupt(_adapter * padapter)508 void rtw_hal_clear_interrupt(_adapter *padapter)
509 {
510 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
511 padapter->hal_func.clear_interrupt(padapter);
512 #endif
513 }
514 #endif
515
516 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
rtw_hal_inirp_init(_adapter * padapter)517 u32 rtw_hal_inirp_init(_adapter *padapter)
518 {
519 if (is_primary_adapter(padapter))
520 return padapter->hal_func.inirp_init(padapter);
521 return _SUCCESS;
522 }
rtw_hal_inirp_deinit(_adapter * padapter)523 u32 rtw_hal_inirp_deinit(_adapter *padapter)
524 {
525
526 if (is_primary_adapter(padapter))
527 return padapter->hal_func.inirp_deinit(padapter);
528
529 return _SUCCESS;
530 }
531 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
532
533 #if defined(CONFIG_PCI_HCI)
rtw_hal_irp_reset(_adapter * padapter)534 void rtw_hal_irp_reset(_adapter *padapter)
535 {
536 padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
537 }
538
rtw_hal_pci_dbi_write(_adapter * padapter,u16 addr,u8 data)539 void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
540 {
541 u16 cmd[2];
542
543 cmd[0] = addr;
544 cmd[1] = data;
545
546 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
547 }
548
rtw_hal_pci_dbi_read(_adapter * padapter,u16 addr)549 u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
550 {
551 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
552
553 return (u8)addr;
554 }
555
rtw_hal_pci_mdio_write(_adapter * padapter,u8 addr,u16 data)556 void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
557 {
558 u16 cmd[2];
559
560 cmd[0] = (u16)addr;
561 cmd[1] = data;
562
563 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
564 }
565
rtw_hal_pci_mdio_read(_adapter * padapter,u8 addr)566 u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
567 {
568 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
569
570 return (u8)addr;
571 }
572
rtw_hal_pci_l1off_nic_support(_adapter * padapter)573 u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
574 {
575 u8 l1off;
576
577 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
578 return l1off;
579 }
580
rtw_hal_pci_l1off_capability(_adapter * padapter)581 u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
582 {
583 u8 l1off;
584
585 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
586 return l1off;
587 }
588
589
590 #endif /* #if defined(CONFIG_PCI_HCI) */
591
592 /* for USB Auto-suspend */
rtw_hal_intf_ps_func(_adapter * padapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)593 u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
594 {
595 if (padapter->hal_func.interface_ps_func)
596 return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
597 return _FAIL;
598 }
599
rtw_hal_xmitframe_enqueue(_adapter * padapter,struct xmit_frame * pxmitframe)600 s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
601 {
602 return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
603 }
604
rtw_hal_xmit(_adapter * padapter,struct xmit_frame * pxmitframe)605 s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
606 {
607 return padapter->hal_func.hal_xmit(padapter, pxmitframe);
608 }
609
610 /*
611 * [IMPORTANT] This function would be run in interrupt context.
612 */
rtw_hal_mgnt_xmit(_adapter * padapter,struct xmit_frame * pmgntframe)613 s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
614 {
615 s32 ret = _FAIL;
616
617 update_mgntframe_attrib_addr(padapter, pmgntframe);
618
619 #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
620 if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
621 #ifdef CONFIG_RTW_MESH
622 || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
623 #endif
624 )
625 rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
626 #endif
627
628 ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
629 return ret;
630 }
631
rtw_hal_init_xmit_priv(_adapter * padapter)632 s32 rtw_hal_init_xmit_priv(_adapter *padapter)
633 {
634 return padapter->hal_func.init_xmit_priv(padapter);
635 }
rtw_hal_free_xmit_priv(_adapter * padapter)636 void rtw_hal_free_xmit_priv(_adapter *padapter)
637 {
638 padapter->hal_func.free_xmit_priv(padapter);
639 }
640
rtw_hal_init_recv_priv(_adapter * padapter)641 s32 rtw_hal_init_recv_priv(_adapter *padapter)
642 {
643 return padapter->hal_func.init_recv_priv(padapter);
644 }
rtw_hal_free_recv_priv(_adapter * padapter)645 void rtw_hal_free_recv_priv(_adapter *padapter)
646 {
647 padapter->hal_func.free_recv_priv(padapter);
648 }
649
rtw_sta_ra_registed(_adapter * padapter,struct sta_info * psta)650 void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
651 {
652 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
653 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
654
655 if (psta == NULL) {
656 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
657 rtw_warn_on(1);
658 return;
659 }
660
661 #ifdef CONFIG_AP_MODE
662 if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
663 if (psta->cmn.aid > padapter->stapriv.max_aid) {
664 RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
665 rtw_warn_on(1);
666 return;
667 }
668 rtw_ap_update_sta_ra_info(padapter, psta);
669 }
670 #endif
671
672 psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
673 /*set correct initial date rate for each mac_id */
674 hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
675
676 rtw_phydm_ra_registed(padapter, psta);
677 }
678
rtw_hal_update_ra_mask(struct sta_info * psta)679 void rtw_hal_update_ra_mask(struct sta_info *psta)
680 {
681 _adapter *padapter;
682
683 if (!psta)
684 return;
685
686 padapter = psta->padapter;
687 rtw_sta_ra_registed(padapter, psta);
688 }
689
690 /* Start specifical interface thread */
rtw_hal_start_thread(_adapter * padapter)691 void rtw_hal_start_thread(_adapter *padapter)
692 {
693 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
694 #ifndef CONFIG_SDIO_TX_TASKLET
695 padapter->hal_func.run_thread(padapter);
696 #endif
697 #endif
698 }
699 /* Start specifical interface thread */
rtw_hal_stop_thread(_adapter * padapter)700 void rtw_hal_stop_thread(_adapter *padapter)
701 {
702 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
703 #ifndef CONFIG_SDIO_TX_TASKLET
704
705 padapter->hal_func.cancel_thread(padapter);
706
707 #endif
708 #endif
709 }
710
rtw_hal_read_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask)711 u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
712 {
713 u32 data = 0;
714 if (padapter->hal_func.read_bbreg)
715 data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
716 return data;
717 }
rtw_hal_write_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)718 void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
719 {
720 if (padapter->hal_func.write_bbreg)
721 padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
722 }
723
rtw_hal_read_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)724 u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
725 {
726 u32 data = 0;
727
728 if (padapter->hal_func.read_rfreg) {
729 data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
730
731 #ifdef DBG_IO
732 if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
733 RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
734 , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
735 }
736 #endif
737 }
738
739 return data;
740 }
741
rtw_hal_write_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)742 void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
743 {
744 if (padapter->hal_func.write_rfreg) {
745
746 #ifdef DBG_IO
747 if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
748 RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
749 , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
750 }
751 #endif
752
753 padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
754
755 #ifdef CONFIG_PCI_HCI
756 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
757 rtw_udelay_os(2);
758 #endif
759 }
760 }
761
762 #ifdef CONFIG_SYSON_INDIRECT_ACCESS
rtw_hal_read_syson_reg(PADAPTER padapter,u32 RegAddr,u32 BitMask)763 u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
764 {
765 u32 data = 0;
766 if (padapter->hal_func.read_syson_reg)
767 data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
768
769 return data;
770 }
771
rtw_hal_write_syson_reg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)772 void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
773 {
774 if (padapter->hal_func.write_syson_reg)
775 padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
776 }
777 #endif
778
779 #if defined(CONFIG_PCI_HCI)
rtw_hal_interrupt_handler(_adapter * padapter)780 s32 rtw_hal_interrupt_handler(_adapter *padapter)
781 {
782 s32 ret = _FAIL;
783 ret = padapter->hal_func.interrupt_handler(padapter);
784 return ret;
785 }
786
rtw_hal_unmap_beacon_icf(_adapter * padapter)787 void rtw_hal_unmap_beacon_icf(_adapter *padapter)
788 {
789 padapter->hal_func.unmap_beacon_icf(padapter);
790 }
791 #endif
792 #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
rtw_hal_interrupt_handler(_adapter * padapter,u16 pkt_len,u8 * pbuf)793 void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
794 {
795 padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
796 }
797 #endif
798
rtw_hal_set_chnl_bw(_adapter * padapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)799 void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
800 {
801 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
802 u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
803 u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
804 u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
805 u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
806
807 if (rtw_phydm_is_iqk_in_progress(padapter))
808 RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
809
810 #ifdef CONFIG_MP_INCLUDED
811 /* MP mode channel don't use secondary channel */
812 if (rtw_mp_mode_check(padapter) == _FALSE)
813 #endif
814 {
815 #if 0
816 if (cch_160 != 0)
817 cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
818 #endif
819 if (cch_80 != 0)
820 cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
821 if (cch_40 != 0)
822 cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
823 }
824
825 pHalData->cch_80 = cch_80;
826 pHalData->cch_40 = cch_40;
827 pHalData->cch_20 = cch_20;
828
829 if (0)
830 RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
831 , channel, ch_width_str(Bandwidth), Offset40, Offset80
832 , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
833
834 padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
835 }
836
rtw_hal_dm_watchdog(_adapter * padapter)837 void rtw_hal_dm_watchdog(_adapter *padapter)
838 {
839
840 rtw_hal_turbo_edca(padapter);
841 padapter->hal_func.hal_dm_watchdog(padapter);
842
843 #ifdef CONFIG_PCI_DYNAMIC_ASPM
844 rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);
845 #endif
846 }
847
848 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_hal_dm_watchdog_in_lps(_adapter * padapter)849 void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
850 {
851 #if defined(CONFIG_CONCURRENT_MODE)
852 #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
853 if (padapter->hw_port != HW_PORT0)
854 return;
855 #endif
856 #endif
857
858 if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
859 rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
860 }
861 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
862
rtw_hal_bcn_related_reg_setting(_adapter * padapter)863 void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
864 {
865 padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
866 }
867
868 #ifdef CONFIG_HOSTAPD_MLME
rtw_hal_hostap_mgnt_xmit_entry(_adapter * padapter,_pkt * pkt)869 s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
870 {
871 if (padapter->hal_func.hostap_mgnt_xmit_entry)
872 return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
873 return _FAIL;
874 }
875 #endif /* CONFIG_HOSTAPD_MLME */
876
877 #ifdef DBG_CONFIG_ERROR_DETECT
rtw_hal_sreset_init(_adapter * padapter)878 void rtw_hal_sreset_init(_adapter *padapter)
879 {
880 padapter->hal_func.sreset_init_value(padapter);
881 }
rtw_hal_sreset_reset(_adapter * padapter)882 void rtw_hal_sreset_reset(_adapter *padapter)
883 {
884 padapter = GET_PRIMARY_ADAPTER(padapter);
885 padapter->hal_func.silentreset(padapter);
886 }
887
rtw_hal_sreset_reset_value(_adapter * padapter)888 void rtw_hal_sreset_reset_value(_adapter *padapter)
889 {
890 padapter->hal_func.sreset_reset_value(padapter);
891 }
892
rtw_hal_sreset_xmit_status_check(_adapter * padapter)893 void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
894 {
895 padapter->hal_func.sreset_xmit_status_check(padapter);
896 }
rtw_hal_sreset_linked_status_check(_adapter * padapter)897 void rtw_hal_sreset_linked_status_check(_adapter *padapter)
898 {
899 padapter->hal_func.sreset_linked_status_check(padapter);
900 }
rtw_hal_sreset_get_wifi_status(_adapter * padapter)901 u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
902 {
903 return padapter->hal_func.sreset_get_wifi_status(padapter);
904 }
905
rtw_hal_sreset_inprogress(_adapter * padapter)906 bool rtw_hal_sreset_inprogress(_adapter *padapter)
907 {
908 padapter = GET_PRIMARY_ADAPTER(padapter);
909 return padapter->hal_func.sreset_inprogress(padapter);
910 }
911 #endif /* DBG_CONFIG_ERROR_DETECT */
912
913 #ifdef CONFIG_IOL
rtw_hal_iol_cmd(ADAPTER * adapter,struct xmit_frame * xmit_frame,u32 max_waiting_ms,u32 bndy_cnt)914 int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
915 {
916 if (adapter->hal_func.IOL_exec_cmds_sync)
917 return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
918 return _FAIL;
919 }
920 #endif
921
922 #ifdef CONFIG_XMIT_THREAD_MODE
rtw_hal_xmit_thread_handler(_adapter * padapter)923 s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
924 {
925 return padapter->hal_func.xmit_thread_handler(padapter);
926 }
927 #endif
928
929 #ifdef CONFIG_RECV_THREAD_MODE
rtw_hal_recv_hdl(_adapter * adapter)930 s32 rtw_hal_recv_hdl(_adapter *adapter)
931 {
932 return adapter->hal_func.recv_hdl(adapter);
933 }
934 #endif
935
rtw_hal_notch_filter(_adapter * adapter,bool enable)936 void rtw_hal_notch_filter(_adapter *adapter, bool enable)
937 {
938 if (adapter->hal_func.hal_notch_filter)
939 adapter->hal_func.hal_notch_filter(adapter, enable);
940 }
941
942 #ifdef CONFIG_FW_C2H_REG
rtw_hal_c2h_valid(_adapter * adapter,u8 * buf)943 inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
944 {
945 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
946 HAL_VERSION *hal_ver = &HalData->version_id;
947 bool ret = _FAIL;
948
949 ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
950
951 return ret;
952 }
953
rtw_hal_c2h_evt_read(_adapter * adapter,u8 * buf)954 inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
955 {
956 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
957 HAL_VERSION *hal_ver = &HalData->version_id;
958 s32 ret = _FAIL;
959
960 ret = c2h_evt_read_88xx(adapter, buf);
961
962 return ret;
963 }
964
rtw_hal_c2h_reg_hdr_parse(_adapter * adapter,u8 * buf,u8 * id,u8 * seq,u8 * plen,u8 ** payload)965 bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
966 {
967 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
968 HAL_VERSION *hal_ver = &HalData->version_id;
969 bool ret = _FAIL;
970
971 *id = C2H_ID_88XX(buf);
972 *seq = C2H_SEQ_88XX(buf);
973 *plen = C2H_PLEN_88XX(buf);
974 *payload = C2H_PAYLOAD_88XX(buf);
975 ret = _SUCCESS;
976
977 return ret;
978 }
979 #endif /* CONFIG_FW_C2H_REG */
980
981 #ifdef CONFIG_FW_C2H_PKT
rtw_hal_c2h_pkt_hdr_parse(_adapter * adapter,u8 * buf,u16 len,u8 * id,u8 * seq,u8 * plen,u8 ** payload)982 bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
983 {
984 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
985 HAL_VERSION *hal_ver = &HalData->version_id;
986 bool ret = _FAIL;
987
988 if (!buf || len > 256 || len < 3)
989 goto exit;
990
991 *id = C2H_ID_88XX(buf);
992 *seq = C2H_SEQ_88XX(buf);
993 *plen = len - 2;
994 *payload = C2H_PAYLOAD_88XX(buf);
995 ret = _SUCCESS;
996
997 exit:
998 return ret;
999 }
1000 #endif /* CONFIG_FW_C2H_PKT */
1001
1002 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1003 #include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
1004 #endif
c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1005 s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1006 {
1007 u8 sub_id = 0;
1008 s32 ret = _SUCCESS;
1009
1010 switch (id) {
1011 case C2H_FW_SCAN_COMPLETE:
1012 RTW_INFO("[C2H], FW Scan Complete\n");
1013 break;
1014
1015 #ifdef CONFIG_BT_COEXIST
1016 case C2H_BT_INFO:
1017 rtw_btcoex_BtInfoNotify(adapter, plen, payload);
1018 break;
1019 case C2H_BT_MP_INFO:
1020 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1021 MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
1022 #endif
1023 rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
1024 break;
1025 case C2H_MAILBOX_STATUS:
1026 RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
1027 break;
1028 case C2H_WLAN_INFO:
1029 rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
1030 break;
1031 #endif /* CONFIG_BT_COEXIST */
1032
1033 case C2H_IQK_FINISH:
1034 c2h_iqk_offload(adapter, payload, plen);
1035 break;
1036
1037 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1038 case C2H_FW_CHNL_SWITCH_COMPLETE:
1039 rtw_tdls_chsw_oper_done(adapter);
1040 break;
1041 case C2H_BCN_EARLY_RPT:
1042 rtw_tdls_ch_sw_back_to_base_chnl(adapter);
1043 break;
1044 #endif
1045
1046 #ifdef CONFIG_MCC_MODE
1047 case C2H_MCC:
1048 rtw_hal_mcc_c2h_handler(adapter, plen, payload);
1049 break;
1050 #endif
1051
1052 #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
1053 case C2H_MAC_HIDDEN_RPT:
1054 c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
1055 break;
1056 case C2H_MAC_HIDDEN_RPT_2:
1057 c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
1058 break;
1059 #endif
1060
1061 case C2H_DEFEATURE_DBG:
1062 c2h_defeature_dbg_hdl(adapter, payload, plen);
1063 break;
1064
1065 #ifdef CONFIG_RTW_CUSTOMER_STR
1066 case C2H_CUSTOMER_STR_RPT:
1067 c2h_customer_str_rpt_hdl(adapter, payload, plen);
1068 break;
1069 case C2H_CUSTOMER_STR_RPT_2:
1070 c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
1071 break;
1072 #endif
1073 #ifdef RTW_PER_CMD_SUPPORT_FW
1074 case C2H_PER_RATE_RPT:
1075 c2h_per_rate_rpt_hdl(adapter, payload, plen);
1076 break;
1077 #endif
1078 case C2H_EXTEND:
1079 sub_id = payload[0];
1080 /* no handle, goto default */
1081 /* fall through */
1082
1083 default:
1084 if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
1085 ret = _FAIL;
1086 break;
1087 }
1088
1089 if (ret != _SUCCESS) {
1090 if (id == C2H_EXTEND)
1091 RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
1092 else
1093 RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
1094 }
1095
1096 return ret;
1097 }
1098
1099 #ifndef RTW_HALMAC
rtw_hal_c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1100 s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1101 {
1102 s32 ret = _FAIL;
1103
1104 ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
1105 if (ret != _SUCCESS)
1106 ret = c2h_handler(adapter, id, seq, plen, payload);
1107
1108 return ret;
1109 }
1110
rtw_hal_c2h_id_handle_directly(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1111 s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1112 {
1113 switch (id) {
1114 case C2H_CCX_TX_RPT:
1115 case C2H_BT_MP_INFO:
1116 case C2H_FW_CHNL_SWITCH_COMPLETE:
1117 case C2H_IQK_FINISH:
1118 case C2H_MCC:
1119 case C2H_BCN_EARLY_RPT:
1120 case C2H_AP_REQ_TXRPT:
1121 case C2H_SPC_STAT:
1122 return _TRUE;
1123 default:
1124 return _FALSE;
1125 }
1126 }
1127 #endif /* !RTW_HALMAC */
1128
rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)1129 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
1130 {
1131 return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
1132 }
1133
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1134 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1135 {
1136 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1137 u16 reg_sleep;
1138 u8 bit_shift;
1139 u32 val32;
1140 s32 ret = _FAIL;
1141
1142 if (macid >= macid_ctl->num) {
1143 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1144 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1145 goto exit;
1146 }
1147
1148 if (macid < 32) {
1149 reg_sleep = macid_ctl->reg_sleep_m0;
1150 bit_shift = macid;
1151 #if (MACID_NUM_SW_LIMIT > 32)
1152 } else if (macid < 64) {
1153 reg_sleep = macid_ctl->reg_sleep_m1;
1154 bit_shift = macid - 32;
1155 #endif
1156 #if (MACID_NUM_SW_LIMIT > 64)
1157 } else if (macid < 96) {
1158 reg_sleep = macid_ctl->reg_sleep_m2;
1159 bit_shift = macid - 64;
1160 #endif
1161 #if (MACID_NUM_SW_LIMIT > 96)
1162 } else if (macid < 128) {
1163 reg_sleep = macid_ctl->reg_sleep_m3;
1164 bit_shift = macid - 96;
1165 #endif
1166 } else {
1167 rtw_warn_on(1);
1168 goto exit;
1169 }
1170
1171 if (!reg_sleep) {
1172 rtw_warn_on(1);
1173 goto exit;
1174 }
1175
1176 val32 = rtw_read32(adapter, reg_sleep);
1177 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1178 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1179 , macid, reg_sleep, val32);
1180
1181 ret = _SUCCESS;
1182
1183 if (sleep) {
1184 if (val32 & BIT(bit_shift))
1185 goto exit;
1186 val32 |= BIT(bit_shift);
1187 } else {
1188 if (!(val32 & BIT(bit_shift)))
1189 goto exit;
1190 val32 &= ~BIT(bit_shift);
1191 }
1192
1193 rtw_write32(adapter, reg_sleep, val32);
1194
1195 exit:
1196 return ret;
1197 }
1198
rtw_hal_macid_sleep(_adapter * adapter,u8 macid)1199 inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
1200 {
1201 return _rtw_hal_macid_sleep(adapter, macid, 1);
1202 }
1203
rtw_hal_macid_wakeup(_adapter * adapter,u8 macid)1204 inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
1205 {
1206 return _rtw_hal_macid_sleep(adapter, macid, 0);
1207 }
1208
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1209 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1210 {
1211 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1212 u16 reg_sleep;
1213 u32 m;
1214 u8 mid = 0;
1215 u32 val32;
1216
1217 do {
1218 if (mid == 0) {
1219 m = bmp->m0;
1220 reg_sleep = macid_ctl->reg_sleep_m0;
1221 #if (MACID_NUM_SW_LIMIT > 32)
1222 } else if (mid == 1) {
1223 m = bmp->m1;
1224 reg_sleep = macid_ctl->reg_sleep_m1;
1225 #endif
1226 #if (MACID_NUM_SW_LIMIT > 64)
1227 } else if (mid == 2) {
1228 m = bmp->m2;
1229 reg_sleep = macid_ctl->reg_sleep_m2;
1230 #endif
1231 #if (MACID_NUM_SW_LIMIT > 96)
1232 } else if (mid == 3) {
1233 m = bmp->m3;
1234 reg_sleep = macid_ctl->reg_sleep_m3;
1235 #endif
1236 } else {
1237 rtw_warn_on(1);
1238 break;
1239 }
1240
1241 if (m == 0)
1242 goto move_next;
1243
1244 if (!reg_sleep) {
1245 rtw_warn_on(1);
1246 break;
1247 }
1248
1249 val32 = rtw_read32(adapter, reg_sleep);
1250 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1251 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1252 , mid, m, reg_sleep, val32);
1253
1254 if (sleep) {
1255 if ((val32 & m) == m)
1256 goto move_next;
1257 val32 |= m;
1258 } else {
1259 if ((val32 & m) == 0)
1260 goto move_next;
1261 val32 &= ~m;
1262 }
1263
1264 rtw_write32(adapter, reg_sleep, val32);
1265
1266 move_next:
1267 mid++;
1268 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1269
1270 return _SUCCESS;
1271 }
1272
rtw_hal_macid_sleep_all_used(_adapter * adapter)1273 inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
1274 {
1275 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1276
1277 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
1278 }
1279
rtw_hal_macid_wakeup_all_used(_adapter * adapter)1280 inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
1281 {
1282 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1283
1284 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
1285 }
1286
_rtw_hal_macid_drop(_adapter * adapter,u8 macid,u8 drop)1287 static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
1288 {
1289 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1290 #ifndef CONFIG_PROTSEL_MACSLEEP
1291 u16 reg_drop = 0;
1292 #else
1293 u16 reg_drop_info = macid_ctl->reg_drop_info;
1294 u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
1295 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1296 #endif /* CONFIG_PROTSEL_MACSLEEP */
1297 u8 bit_shift;
1298 u32 val32;
1299 s32 ret = _FAIL;
1300 /* some IC doesn't have this register */
1301 #ifndef REG_PKT_BUFF_ACCESS_CTRL
1302 #define REG_PKT_BUFF_ACCESS_CTRL 0
1303 #endif
1304
1305 if (macid >= macid_ctl->num) {
1306 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1307 , ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
1308 goto exit;
1309 }
1310
1311 if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
1312 if (macid < 32) {
1313 #ifndef CONFIG_PROTSEL_MACSLEEP
1314 reg_drop = macid_ctl->reg_drop_m0;
1315 #endif /* CONFIG_PROTSEL_MACSLEEP */
1316 bit_shift = macid;
1317 #if (MACID_NUM_SW_LIMIT > 32)
1318 } else if (macid < 64) {
1319 #ifndef CONFIG_PROTSEL_MACSLEEP
1320 reg_drop = macid_ctl->reg_drop_m1;
1321 #endif /* CONFIG_PROTSEL_MACSLEEP */
1322 bit_shift = macid - 32;
1323 #endif
1324 #if (MACID_NUM_SW_LIMIT > 64)
1325 } else if (macid < 96) {
1326 #ifndef CONFIG_PROTSEL_MACSLEEP
1327 reg_drop = macid_ctl->reg_drop_m2;
1328 #endif /* CONFIG_PROTSEL_MACSLEEP */
1329 bit_shift = macid - 64;
1330 #endif
1331 #if (MACID_NUM_SW_LIMIT > 96)
1332 } else if (macid < 128) {
1333 #ifndef CONFIG_PROTSEL_MACSLEEP
1334 reg_drop = macid_ctl->reg_drop_m3;
1335 #endif /* CONFIG_PROTSEL_MACSLEEP */
1336 bit_shift = macid - 96;
1337 #endif
1338 } else {
1339 rtw_warn_on(1);
1340 goto exit;
1341 }
1342
1343 #ifndef CONFIG_PROTSEL_MACSLEEP
1344 if (!reg_drop) {
1345 rtw_warn_on(1);
1346 goto exit;
1347 }
1348 val32 = rtw_read32(adapter, reg_drop);
1349 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
1350 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1351 , macid, reg_drop, val32);*/
1352 #else
1353 if (!reg_drop_ctrl || !reg_drop_info) {
1354 rtw_warn_on(1);
1355 goto exit;
1356 }
1357
1358 val32 = rtw_read32(adapter, reg_drop_ctrl);
1359 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1360 rtw_write32(adapter, reg_drop_ctrl, val32);
1361
1362 val32 = rtw_read32(adapter, reg_drop_info);
1363 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1364 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1365 , macid, reg_drop_info, val32);*/
1366 #endif /* CONFIG_PROTSEL_MACSLEEP */
1367 ret = _SUCCESS;
1368
1369 if (drop) {
1370 if (val32 & BIT(bit_shift))
1371 goto exit;
1372 val32 |= BIT(bit_shift);
1373 } else {
1374 if (!(val32 & BIT(bit_shift)))
1375 goto exit;
1376 val32 &= ~BIT(bit_shift);
1377 }
1378
1379 #ifndef CONFIG_PROTSEL_MACSLEEP
1380 rtw_write32(adapter, reg_drop, val32);
1381 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1382 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1383 , macid, reg_drop, val32);
1384 #else
1385 rtw_write32(adapter, reg_drop_info, val32);
1386 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1387 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1388 , macid, reg_drop_info, val32);
1389 #endif /* CONFIG_PROTSEL_MACSLEEP */
1390
1391
1392 } else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
1393 u16 start_addr = macid_ctl->macid_txrpt/8;
1394 u32 txrpt_h4b = 0;
1395 u8 i;
1396
1397 /* each address means 1 byte */
1398 start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
1399 /* select tx report buffer */
1400 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
1401 /* set tx report buffer start address for reading */
1402 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1403 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
1404 /* OFFSET5 BIT2 is BIT10 of high 4 bytes */
1405 if (drop) {
1406 if (txrpt_h4b & BIT(10))
1407 goto exit;
1408 txrpt_h4b |= BIT(10);
1409 } else {
1410 if (!(txrpt_h4b & BIT(10)))
1411 goto exit;
1412 txrpt_h4b &= ~BIT(10);
1413 }
1414 /* set to macid drop field */
1415 rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
1416 /* 0x20800000 only write BIT10 of tx report buf */
1417 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
1418 #if 0 /* some ICs doesn't clear the write done bit */
1419 /* checking TX queue status */
1420 for (i = 0 ; i < 50 ; i++) {
1421 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
1422 if (txrpt_h4b & BIT(23)) {
1423 RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
1424 rtw_mdelay_os(10);
1425 } else {
1426 RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
1427 break;
1428 }
1429 }
1430 #endif
1431 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1432 RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
1433 ,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
1434 } else {
1435 RTW_INFO("There is no definition for camctl cap , please correct it\n");
1436 }
1437 exit:
1438 return ret;
1439 }
1440
rtw_hal_macid_drop(_adapter * adapter,u8 macid)1441 inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
1442 {
1443 return _rtw_hal_macid_drop(adapter, macid, 1);
1444 }
1445
rtw_hal_macid_undrop(_adapter * adapter,u8 macid)1446 inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
1447 {
1448 return _rtw_hal_macid_drop(adapter, macid, 0);
1449 }
1450
rtw_hal_fill_h2c_cmd(PADAPTER padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)1451 s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
1452 {
1453 _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
1454
1455 if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
1456 return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
1457 else if (padapter->registrypriv.mp_mode == 0)
1458 RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
1459 , FUNC_ADPT_ARG(padapter), ElementID);
1460 return _FAIL;
1461 }
1462
rtw_hal_fill_fake_txdesc(_adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)1463 void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
1464 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
1465 {
1466 padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
1467
1468 }
1469
rtw_hal_get_txbuff_rsvd_page_num(_adapter * adapter,bool wowlan)1470 u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
1471 {
1472 u8 num = 0;
1473
1474
1475 if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1476 num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
1477 } else {
1478 #ifdef RTW_HALMAC
1479 num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
1480 #endif /* RTW_HALMAC */
1481 }
1482
1483 return num;
1484 }
1485
1486 #ifdef CONFIG_GPIO_API
rtw_hal_update_hisr_hsisr_ind(_adapter * padapter,u32 flag)1487 void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
1488 {
1489 if (padapter->hal_func.update_hisr_hsisr_ind)
1490 padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
1491 }
1492
rtw_hal_gpio_func_check(_adapter * padapter,u8 gpio_num)1493 int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
1494 {
1495 int ret = _SUCCESS;
1496
1497 if (padapter->hal_func.hal_gpio_func_check)
1498 ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
1499
1500 return ret;
1501 }
1502
rtw_hal_gpio_multi_func_reset(_adapter * padapter,u8 gpio_num)1503 void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
1504 {
1505 if (padapter->hal_func.hal_gpio_multi_func_reset)
1506 padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
1507 }
1508 #endif
1509
1510 #ifdef CONFIG_FW_CORRECT_BCN
rtw_hal_fw_correct_bcn(_adapter * padapter)1511 void rtw_hal_fw_correct_bcn(_adapter *padapter)
1512 {
1513 if (padapter->hal_func.fw_correct_bcn)
1514 padapter->hal_func.fw_correct_bcn(padapter);
1515 }
1516 #endif
1517
rtw_hal_set_tx_power_level(_adapter * adapter,u8 channel)1518 void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
1519 {
1520 if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
1521 return;
1522
1523 adapter->hal_func.set_tx_power_level_handler(adapter, channel);
1524 rtw_hal_set_txpwr_done(adapter);
1525 }
1526
rtw_hal_update_txpwr_level(_adapter * adapter)1527 void rtw_hal_update_txpwr_level(_adapter *adapter)
1528 {
1529 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1530
1531 rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
1532 }
1533
rtw_hal_set_txpwr_done(_adapter * adapter)1534 void rtw_hal_set_txpwr_done(_adapter *adapter)
1535 {
1536 if (adapter->hal_func.set_txpwr_done)
1537 adapter->hal_func.set_txpwr_done(adapter);
1538 }
1539
rtw_hal_set_tx_power_index(_adapter * adapter,u32 powerindex,enum rf_path rfpath,u8 rate)1540 void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
1541 , enum rf_path rfpath, u8 rate)
1542 {
1543 adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
1544 }
1545
rtw_hal_get_tx_power_index(_adapter * adapter,enum rf_path rfpath,u8 rate,u8 bandwidth,u8 channel,struct txpwr_idx_comp * tic)1546 u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath, u8 rate
1547 , u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
1548 {
1549 return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath, rate
1550 , bandwidth, channel, tic);
1551 }
1552
1553 #ifdef RTW_HALMAC
1554 /*
1555 * Description:
1556 * Initialize MAC registers
1557 *
1558 * Return:
1559 * _TRUE success
1560 * _FALSE fail
1561 */
rtw_hal_init_mac_register(PADAPTER adapter)1562 u8 rtw_hal_init_mac_register(PADAPTER adapter)
1563 {
1564 return adapter->hal_func.init_mac_register(adapter);
1565 }
1566
1567 /*
1568 * Description:
1569 * Initialize PHY(BB/RF) related functions
1570 *
1571 * Return:
1572 * _TRUE success
1573 * _FALSE fail
1574 */
rtw_hal_init_phy(PADAPTER adapter)1575 u8 rtw_hal_init_phy(PADAPTER adapter)
1576 {
1577 return adapter->hal_func.init_phy(adapter);
1578 }
1579 #endif /* RTW_HALMAC */
1580
1581 #ifdef CONFIG_RFKILL_POLL
rtw_hal_rfkill_poll(_adapter * adapter,u8 * valid)1582 bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
1583 {
1584 bool ret;
1585
1586 if (adapter->hal_func.hal_radio_onoff_check)
1587 ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
1588 else {
1589 *valid = 0;
1590 ret = _FALSE;
1591 }
1592 return ret;
1593 }
1594 #endif
1595
1596 #define rtw_hal_error_msg(ops_fun) \
1597 RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
1598
rtw_hal_ops_check(_adapter * padapter)1599 u8 rtw_hal_ops_check(_adapter *padapter)
1600 {
1601 u8 ret = _SUCCESS;
1602 #if 1
1603 /*** initialize section ***/
1604 if (NULL == padapter->hal_func.read_chip_version) {
1605 rtw_hal_error_msg("read_chip_version");
1606 ret = _FAIL;
1607 }
1608 if (NULL == padapter->hal_func.init_default_value) {
1609 rtw_hal_error_msg("init_default_value");
1610 ret = _FAIL;
1611 }
1612 if (NULL == padapter->hal_func.intf_chip_configure) {
1613 rtw_hal_error_msg("intf_chip_configure");
1614 ret = _FAIL;
1615 }
1616 if (NULL == padapter->hal_func.read_adapter_info) {
1617 rtw_hal_error_msg("read_adapter_info");
1618 ret = _FAIL;
1619 }
1620
1621 if (NULL == padapter->hal_func.hal_power_on) {
1622 rtw_hal_error_msg("hal_power_on");
1623 ret = _FAIL;
1624 }
1625 if (NULL == padapter->hal_func.hal_power_off) {
1626 rtw_hal_error_msg("hal_power_off");
1627 ret = _FAIL;
1628 }
1629
1630 if (NULL == padapter->hal_func.hal_init) {
1631 rtw_hal_error_msg("hal_init");
1632 ret = _FAIL;
1633 }
1634 if (NULL == padapter->hal_func.hal_deinit) {
1635 rtw_hal_error_msg("hal_deinit");
1636 ret = _FAIL;
1637 }
1638
1639 /*** xmit section ***/
1640 if (NULL == padapter->hal_func.init_xmit_priv) {
1641 rtw_hal_error_msg("init_xmit_priv");
1642 ret = _FAIL;
1643 }
1644 if (NULL == padapter->hal_func.free_xmit_priv) {
1645 rtw_hal_error_msg("free_xmit_priv");
1646 ret = _FAIL;
1647 }
1648 if (NULL == padapter->hal_func.hal_xmit) {
1649 rtw_hal_error_msg("hal_xmit");
1650 ret = _FAIL;
1651 }
1652 if (NULL == padapter->hal_func.mgnt_xmit) {
1653 rtw_hal_error_msg("mgnt_xmit");
1654 ret = _FAIL;
1655 }
1656 #ifdef CONFIG_XMIT_THREAD_MODE
1657 if (NULL == padapter->hal_func.xmit_thread_handler) {
1658 rtw_hal_error_msg("xmit_thread_handler");
1659 ret = _FAIL;
1660 }
1661 #endif
1662 if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
1663 rtw_hal_error_msg("hal_xmitframe_enqueue");
1664 ret = _FAIL;
1665 }
1666 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
1667 #ifndef CONFIG_SDIO_TX_TASKLET
1668 if (NULL == padapter->hal_func.run_thread) {
1669 rtw_hal_error_msg("run_thread");
1670 ret = _FAIL;
1671 }
1672 if (NULL == padapter->hal_func.cancel_thread) {
1673 rtw_hal_error_msg("cancel_thread");
1674 ret = _FAIL;
1675 }
1676 #endif
1677 #endif
1678
1679 /*** recv section ***/
1680 if (NULL == padapter->hal_func.init_recv_priv) {
1681 rtw_hal_error_msg("init_recv_priv");
1682 ret = _FAIL;
1683 }
1684 if (NULL == padapter->hal_func.free_recv_priv) {
1685 rtw_hal_error_msg("free_recv_priv");
1686 ret = _FAIL;
1687 }
1688 #ifdef CONFIG_RECV_THREAD_MODE
1689 if (NULL == padapter->hal_func.recv_hdl) {
1690 rtw_hal_error_msg("recv_hdl");
1691 ret = _FAIL;
1692 }
1693 #endif
1694 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
1695 if (NULL == padapter->hal_func.inirp_init) {
1696 rtw_hal_error_msg("inirp_init");
1697 ret = _FAIL;
1698 }
1699 if (NULL == padapter->hal_func.inirp_deinit) {
1700 rtw_hal_error_msg("inirp_deinit");
1701 ret = _FAIL;
1702 }
1703 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
1704
1705
1706 /*** interrupt hdl section ***/
1707 #if defined(CONFIG_PCI_HCI)
1708 if (NULL == padapter->hal_func.irp_reset) {
1709 rtw_hal_error_msg("irp_reset");
1710 ret = _FAIL;
1711 }
1712 #endif/*#if defined(CONFIG_PCI_HCI)*/
1713 #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
1714 if (NULL == padapter->hal_func.interrupt_handler) {
1715 rtw_hal_error_msg("interrupt_handler");
1716 ret = _FAIL;
1717 }
1718 #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
1719
1720 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
1721 if (NULL == padapter->hal_func.enable_interrupt) {
1722 rtw_hal_error_msg("enable_interrupt");
1723 ret = _FAIL;
1724 }
1725 if (NULL == padapter->hal_func.disable_interrupt) {
1726 rtw_hal_error_msg("disable_interrupt");
1727 ret = _FAIL;
1728 }
1729 #endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
1730
1731
1732 /*** DM section ***/
1733 if (NULL == padapter->hal_func.dm_init) {
1734 rtw_hal_error_msg("dm_init");
1735 ret = _FAIL;
1736 }
1737 if (NULL == padapter->hal_func.dm_deinit) {
1738 rtw_hal_error_msg("dm_deinit");
1739 ret = _FAIL;
1740 }
1741 if (NULL == padapter->hal_func.hal_dm_watchdog) {
1742 rtw_hal_error_msg("hal_dm_watchdog");
1743 ret = _FAIL;
1744 }
1745
1746 /*** xxx section ***/
1747 if (NULL == padapter->hal_func.set_chnl_bw_handler) {
1748 rtw_hal_error_msg("set_chnl_bw_handler");
1749 ret = _FAIL;
1750 }
1751
1752 if (NULL == padapter->hal_func.set_hw_reg_handler) {
1753 rtw_hal_error_msg("set_hw_reg_handler");
1754 ret = _FAIL;
1755 }
1756 if (NULL == padapter->hal_func.GetHwRegHandler) {
1757 rtw_hal_error_msg("GetHwRegHandler");
1758 ret = _FAIL;
1759 }
1760 if (NULL == padapter->hal_func.get_hal_def_var_handler) {
1761 rtw_hal_error_msg("get_hal_def_var_handler");
1762 ret = _FAIL;
1763 }
1764 if (NULL == padapter->hal_func.SetHalDefVarHandler) {
1765 rtw_hal_error_msg("SetHalDefVarHandler");
1766 ret = _FAIL;
1767 }
1768 if (NULL == padapter->hal_func.GetHalODMVarHandler) {
1769 rtw_hal_error_msg("GetHalODMVarHandler");
1770 ret = _FAIL;
1771 }
1772 if (NULL == padapter->hal_func.SetHalODMVarHandler) {
1773 rtw_hal_error_msg("SetHalODMVarHandler");
1774 ret = _FAIL;
1775 }
1776
1777 if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
1778 rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
1779 ret = _FAIL;
1780 }
1781
1782 if (NULL == padapter->hal_func.fill_h2c_cmd) {
1783 rtw_hal_error_msg("fill_h2c_cmd");
1784 ret = _FAIL;
1785 }
1786
1787 #ifdef RTW_HALMAC
1788 if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
1789 rtw_hal_error_msg("hal_mac_c2h_handler");
1790 ret = _FAIL;
1791 }
1792 #elif !defined(CONFIG_RTL8188E)
1793 if (NULL == padapter->hal_func.c2h_handler) {
1794 rtw_hal_error_msg("c2h_handler");
1795 ret = _FAIL;
1796 }
1797 #endif
1798
1799 #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1800 if (NULL == padapter->hal_func.fill_fake_txdesc) {
1801 rtw_hal_error_msg("fill_fake_txdesc");
1802 ret = _FAIL;
1803 }
1804 #endif
1805
1806 #ifndef RTW_HALMAC
1807 if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1808 rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
1809 ret = _FAIL;
1810 }
1811 #endif /* !RTW_HALMAC */
1812
1813 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1814 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
1815 if (NULL == padapter->hal_func.clear_interrupt) {
1816 rtw_hal_error_msg("clear_interrupt");
1817 ret = _FAIL;
1818 }
1819 #endif
1820 #endif /* CONFIG_WOWLAN */
1821
1822 if (NULL == padapter->hal_func.fw_dl) {
1823 rtw_hal_error_msg("fw_dl");
1824 ret = _FAIL;
1825 }
1826
1827 #ifdef CONFIG_FW_CORRECT_BCN
1828 if (IS_HARDWARE_TYPE_8814A(padapter)
1829 && NULL == padapter->hal_func.fw_correct_bcn) {
1830 rtw_hal_error_msg("fw_correct_bcn");
1831 ret = _FAIL;
1832 }
1833 #endif
1834
1835 if (!padapter->hal_func.set_tx_power_level_handler) {
1836 rtw_hal_error_msg("set_tx_power_level_handler");
1837 ret = _FAIL;
1838 }
1839 if (!padapter->hal_func.set_tx_power_index_handler) {
1840 rtw_hal_error_msg("set_tx_power_index_handler");
1841 ret = _FAIL;
1842 }
1843 if (!padapter->hal_func.get_tx_power_index_handler) {
1844 rtw_hal_error_msg("get_tx_power_index_handler");
1845 ret = _FAIL;
1846 }
1847
1848 /*** SReset section ***/
1849 #ifdef DBG_CONFIG_ERROR_DETECT
1850 if (NULL == padapter->hal_func.sreset_init_value) {
1851 rtw_hal_error_msg("sreset_init_value");
1852 ret = _FAIL;
1853 }
1854 if (NULL == padapter->hal_func.sreset_reset_value) {
1855 rtw_hal_error_msg("sreset_reset_value");
1856 ret = _FAIL;
1857 }
1858 if (NULL == padapter->hal_func.silentreset) {
1859 rtw_hal_error_msg("silentreset");
1860 ret = _FAIL;
1861 }
1862 if (NULL == padapter->hal_func.sreset_xmit_status_check) {
1863 rtw_hal_error_msg("sreset_xmit_status_check");
1864 ret = _FAIL;
1865 }
1866 if (NULL == padapter->hal_func.sreset_linked_status_check) {
1867 rtw_hal_error_msg("sreset_linked_status_check");
1868 ret = _FAIL;
1869 }
1870 if (NULL == padapter->hal_func.sreset_get_wifi_status) {
1871 rtw_hal_error_msg("sreset_get_wifi_status");
1872 ret = _FAIL;
1873 }
1874 if (NULL == padapter->hal_func.sreset_inprogress) {
1875 rtw_hal_error_msg("sreset_inprogress");
1876 ret = _FAIL;
1877 }
1878 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
1879
1880 #ifdef RTW_HALMAC
1881 if (NULL == padapter->hal_func.init_mac_register) {
1882 rtw_hal_error_msg("init_mac_register");
1883 ret = _FAIL;
1884 }
1885 if (NULL == padapter->hal_func.init_phy) {
1886 rtw_hal_error_msg("init_phy");
1887 ret = _FAIL;
1888 }
1889 #endif /* RTW_HALMAC */
1890
1891 #ifdef CONFIG_RFKILL_POLL
1892 if (padapter->hal_func.hal_radio_onoff_check == NULL) {
1893 rtw_hal_error_msg("hal_radio_onoff_check");
1894 ret = _FAIL;
1895 }
1896 #endif
1897 #endif
1898 return ret;
1899 }
1900