1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2014 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #include <drv_types.h>
18 #include <hal_data.h>
19
20 /* A mapping from HalData to ODM. */
boardType(u8 InterfaceSel)21 enum odm_board_type boardType(u8 InterfaceSel)
22 {
23 enum odm_board_type board = ODM_BOARD_DEFAULT;
24
25 #ifdef CONFIG_PCI_HCI
26 INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
27 switch (pcie) {
28 case INTF_SEL0_SOLO_MINICARD:
29 board |= ODM_BOARD_MINICARD;
30 break;
31 case INTF_SEL1_BT_COMBO_MINICARD:
32 board |= ODM_BOARD_BT;
33 board |= ODM_BOARD_MINICARD;
34 break;
35 default:
36 board = ODM_BOARD_DEFAULT;
37 break;
38 }
39
40 #elif defined(CONFIG_USB_HCI)
41 INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
42 switch (usb) {
43 case INTF_SEL1_USB_High_Power:
44 board |= ODM_BOARD_EXT_LNA;
45 board |= ODM_BOARD_EXT_PA;
46 break;
47 case INTF_SEL2_MINICARD:
48 board |= ODM_BOARD_MINICARD;
49 break;
50 case INTF_SEL4_USB_Combo:
51 board |= ODM_BOARD_BT;
52 break;
53 case INTF_SEL5_USB_Combo_MF:
54 board |= ODM_BOARD_BT;
55 break;
56 case INTF_SEL0_USB:
57 case INTF_SEL3_USB_Solo:
58 default:
59 board = ODM_BOARD_DEFAULT;
60 break;
61 }
62
63 #endif
64 /* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
65
66 return board;
67 }
68
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)69 void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
70 {
71 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
72 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
73
74 if (hal->RegIQKFWOffload) {
75 rtw_sctx_init(&hal->iqk_sctx, 0);
76 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
77 } else
78 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
79
80 RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
81
82 if (rtw_mi_check_status(adapter, MI_LINKED)) {
83 #ifdef CONFIG_LPS
84 LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
85 #endif
86 halrf_iqk_trigger(p_dm_odm, _FALSE);
87 }
88 }
89
90 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
rtw_phydm_iqk_trigger(_adapter * adapter)91 void rtw_phydm_iqk_trigger(_adapter *adapter)
92 {
93 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
94 u8 clear = _TRUE;
95 u8 segment = _FALSE;
96 u8 rfk_forbidden = _FALSE;
97
98 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
99 #if (RTL8822C_SUPPORT == 1)
100 /* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
101 halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
102 #else
103 /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
104 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
105 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
106 #endif
107 }
108 #endif
109
rtw_phydm_iqk_trigger_dbg(_adapter * adapter,bool recovery,bool clear,bool segment)110 void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
111 {
112 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
113
114 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
115 halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
116 #else
117 halrf_iqk_trigger(p_dm_odm, recovery);
118 #endif
119 }
rtw_phydm_lck_trigger(_adapter * adapter)120 void rtw_phydm_lck_trigger(_adapter *adapter)
121 {
122 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
123
124 halrf_lck_trigger(p_dm_odm);
125 }
126 #ifdef CONFIG_DBG_RF_CAL
rtw_hal_iqk_test(_adapter * adapter,bool recovery,bool clear,bool segment)127 void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
128 {
129 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
130
131 rtw_ps_deny(adapter, PS_DENY_IOCTL);
132 LeaveAllPowerSaveModeDirect(adapter);
133
134 rtw_phydm_ability_backup(adapter);
135 rtw_phydm_func_disable_all(adapter);
136
137 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
138
139 rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
140 rtw_phydm_ability_restore(adapter);
141
142 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
143 }
144
rtw_hal_lck_test(_adapter * adapter)145 void rtw_hal_lck_test(_adapter *adapter)
146 {
147 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
148
149 rtw_ps_deny(adapter, PS_DENY_IOCTL);
150 LeaveAllPowerSaveModeDirect(adapter);
151
152 rtw_phydm_ability_backup(adapter);
153 rtw_phydm_func_disable_all(adapter);
154
155 halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
156
157 rtw_phydm_lck_trigger(adapter);
158
159 rtw_phydm_ability_restore(adapter);
160 rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
161 }
162 #endif
163
164 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
rtw_hal_update_param_init_fw_offload_cap(_adapter * adapter)165 void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
166 {
167 struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
168
169 if (adapter->registrypriv.fw_param_init)
170 phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
171 else
172 phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
173
174 RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
175 }
176 #endif
177
record_ra_info(void * p_dm_void,u8 macid,struct cmn_sta_info * p_sta,u64 ra_mask)178 void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
179 {
180 struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
181 _adapter *adapter = p_dm->adapter;
182 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
183 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
184
185 if (p_sta) {
186 rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
187 rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
188 rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
189 rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
190
191 rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
192 }
193 }
194
195 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
rtw_phydm_fill_desc_dpt(void * dm,u8 * desc,u8 dpt_lv)196 void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
197 {
198 struct dm_struct *p_dm = (struct dm_struct *)dm;
199 _adapter *adapter = p_dm->adapter;
200
201 switch (rtw_get_chip_type(adapter)) {
202 /*
203 #ifdef CONFIG_RTL8188F
204 case RTL8188F:
205 break;
206 #endif
207
208 #ifdef CONFIG_RTL8723B
209 case RTL8723B :
210 break;
211 #endif
212
213 #ifdef CONFIG_RTL8703B
214 case RTL8703B :
215 break;
216 #endif
217
218 #ifdef CONFIG_RTL8812A
219 case RTL8812 :
220 break;
221 #endif
222
223 #ifdef CONFIG_RTL8821A
224 case RTL8821:
225 break;
226 #endif
227
228 #ifdef CONFIG_RTL8814A
229 case RTL8814A :
230 break;
231 #endif
232
233 #ifdef CONFIG_RTL8192F
234 case RTL8192F :
235 break;
236 #endif
237 */
238 /*
239 #ifdef CONFIG_RTL8192E
240 case RTL8192E :
241 SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
242 break;
243 #endif
244 */
245
246 #ifdef CONFIG_RTL8821C
247 case RTL8821C :
248 SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
249 break;
250 #endif
251
252 default :
253 RTW_ERR("%s IC not support dynamic tx power\n", __func__);
254 break;
255 }
256 }
rtw_phydm_set_dyntxpwr(_adapter * adapter,u8 * desc,u8 mac_id)257 void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
258 {
259 struct dm_struct *dm = adapter_to_phydm(adapter);
260
261 odm_set_dyntxpwr(dm, desc, mac_id);
262 }
263 #endif
264
265 #ifdef CONFIG_RTW_TX_2PATH_EN
rtw_phydm_tx_2path_en(_adapter * adapter)266 void rtw_phydm_tx_2path_en(_adapter *adapter)
267 {
268 struct dm_struct *dm = adapter_to_phydm(adapter);
269
270 phydm_tx_2path(dm);
271 }
272 #endif
273 #ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(_adapter * adapter,u8 state)274 void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
275 {
276 struct registry_priv *pregistrypriv = &adapter->registrypriv;
277 struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
278 struct dm_struct *dm = adapter_to_phydm(adapter);
279 u8 tdma_dig_en;
280
281 switch (state) {
282 case TDMADIG_INIT:
283 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
284 phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
285 break;
286 case TDMADIG_NON_INIT:
287 if(pregistrypriv->tdmadig_dynamic) {
288 if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
289 tdma_dig_en = 0;
290 else
291 tdma_dig_en = pregistrypriv->tdmadig_en;
292 phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
293 }
294 break;
295 default:
296 break;
297
298 }
299 }
300 #endif/*CONFIG_TDMADIG*/
rtw_phydm_ops_func_init(struct dm_struct * p_phydm)301 void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
302 {
303 struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
304
305 p_ra_t->record_ra_info = record_ra_info;
306 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
307 p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
308 #endif
309 }
rtw_phydm_priv_init(_adapter * adapter)310 void rtw_phydm_priv_init(_adapter *adapter)
311 {
312 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
313 struct dm_struct *phydm = &(hal->odmpriv);
314
315 phydm->adapter = adapter;
316 odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
317 }
318
Init_ODM_ComInfo(_adapter * adapter)319 void Init_ODM_ComInfo(_adapter *adapter)
320 {
321 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
322 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
323 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
324 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
325 int i;
326
327 /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
328 pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
329 rtw_odm_init_ic_type(adapter);
330
331 if (rtw_get_intf_type(adapter) == RTW_GSPI)
332 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
333 else
334 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
335
336 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
337
338 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
339
340 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
341
342 #ifdef CONFIG_ADVANCE_OTA
343 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
344 #endif
345 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
346
347 {
348 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
349 u8 odm_board_type = ODM_BOARD_DEFAULT;
350
351 if (pHalData->ExternalLNA_2G != 0) {
352 odm_board_type |= ODM_BOARD_EXT_LNA;
353 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
354 }
355 if (pHalData->external_lna_5g != 0) {
356 odm_board_type |= ODM_BOARD_EXT_LNA_5G;
357 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
358 }
359 if (pHalData->ExternalPA_2G != 0) {
360 odm_board_type |= ODM_BOARD_EXT_PA;
361 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
362 }
363 if (pHalData->external_pa_5g != 0) {
364 odm_board_type |= ODM_BOARD_EXT_PA_5G;
365 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
366 }
367 if (pHalData->EEPROMBluetoothCoexist)
368 odm_board_type |= ODM_BOARD_BT;
369
370 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
371 /* 1 ============== End of BoardType ============== */
372 }
373
374 rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
375
376 #ifdef CONFIG_DFS_MASTER
377 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
378 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
379 #endif
380
381 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
382 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
383 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
384 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
385
386 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
387 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
388
389 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
390
391 /*Add by YuChen for kfree init*/
392 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
393 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
394
395 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
396 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
397 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
398
399 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
400 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
401 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
402
403 /* waiting for PhyDMV034 support*/
404 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
405 /*Add by YuChen for adaptivity init*/
406 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
407 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
408 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
409 phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
410
411 /*halrf info init*/
412 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
413 halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
414
415 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
416 rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
417
418 #ifdef CONFIG_IQK_PA_OFF
419 odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
420 #endif
421 rtw_hal_update_iqk_fw_offload_cap(adapter);
422 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
423 rtw_hal_update_param_init_fw_offload_cap(adapter);
424 #endif
425
426 /* Pointer reference */
427 /*Antenna diversity relative parameters*/
428 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
429 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
430
431 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
432 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
433 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
434
435 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
436 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
437
438 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
439 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
440 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
441 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
442 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
443
444 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
445 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
446 /*Add by Yuchen for phydm beamforming*/
447 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
448 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
449 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
450 #ifdef CONFIG_RTL8723B
451 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
452 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
453 #endif /*CONFIG_RTL8723B*/
454 #ifdef CONFIG_USB_HCI
455 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
456 #endif
457
458 #ifdef CONFIG_DYNAMIC_SOML
459 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
460 #endif
461
462 odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
463
464 /*halrf info hook*/
465 /* waiting for PhyDMV034 support*/
466 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
467 #ifdef CONFIG_MP_INCLUDED
468 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
469 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
470 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
471 halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
472 #endif/*CONFIG_MP_INCLUDED*/
473 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
474 phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
475
476 rtw_phydm_ops_func_init(pDM_Odm);
477 phydm_dm_early_init(pDM_Odm);
478 /* TODO */
479 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
480 /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
481 }
482
483
484 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
485 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
486 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
487 { 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
488
489 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
490 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
491 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
492 { 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
493
494 static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
495 /*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
496 /*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
497 { 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
498
499
500 struct turbo_edca_setting{
501 u32 edca_ul; /* uplink, tx */
502 u32 edca_dl; /* downlink, rx */
503 };
504
505 #define TURBO_EDCA_ENT(UL, DL) {UL, DL}
506
507 #if 0
508 #define TURBO_EDCA_MODE_NUM 18
509 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
510 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
511 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
512 TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
513
514 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
515 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
516 TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
517
518 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
519 TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
520 TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
521
522 TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
523 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
524 TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
525
526 TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
527 TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
528 TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
529
530 TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
531
532 TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
533
534 TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
535 };
536 #else
537 #define TURBO_EDCA_MODE_NUM 8
538 static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
539 /* { UL, DL } */
540 TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
541
542 TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
543
544 TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
545
546 TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
547
548 TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
549
550 TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
551
552 TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
553
554 TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
555 };
556 #endif
557
rtw_hal_turbo_edca(_adapter * adapter)558 void rtw_hal_turbo_edca(_adapter *adapter)
559 {
560 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
561 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
562 struct recv_priv *precvpriv = &(adapter->recvpriv);
563 struct registry_priv *pregpriv = &adapter->registrypriv;
564 struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
565 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
566
567 /* Parameter suggested by Scott */
568 #if 0
569 u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
570 u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
571 #endif
572 u32 EDCA_BE_UL = 0x5ea42b;
573 u32 EDCA_BE_DL = 0x00a42b;
574 u8 ic_type = rtw_get_chip_type(adapter);
575
576 u8 iot_peer = 0;
577 u8 wireless_mode = 0xFF; /* invalid value */
578 u8 traffic_index;
579 u32 edca_param;
580 u64 cur_tx_bytes = 0;
581 u64 cur_rx_bytes = 0;
582 u8 bbtchange = _TRUE;
583 u8 is_bias_on_rx = _FALSE;
584 u8 is_linked = _FALSE;
585 u8 interface_type;
586
587 if (hal_data->dis_turboedca == 1)
588 return;
589
590 if (rtw_mi_check_status(adapter, MI_ASSOC))
591 is_linked = _TRUE;
592
593 if (is_linked != _TRUE) {
594 precvpriv->is_any_non_be_pkts = _FALSE;
595 return;
596 }
597
598 if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
599 precvpriv->is_any_non_be_pkts = _FALSE;
600 return;
601 }
602
603 interface_type = rtw_get_intf_type(adapter);
604 wireless_mode = pmlmeext->cur_wireless_mode;
605
606 iot_peer = pmlmeinfo->assoc_AP_vendor;
607
608 if (iot_peer >= HT_IOT_PEER_MAX) {
609 precvpriv->is_any_non_be_pkts = _FALSE;
610 return;
611 }
612
613 if (ic_type == RTL8188E) {
614 if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
615 is_bias_on_rx = _TRUE;
616 }
617
618 /* Check if the status needs to be changed. */
619 if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
620 cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
621 cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
622
623 /* traffic, TX or RX */
624 if (is_bias_on_rx) {
625 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
626 /* Uplink TP is present. */
627 traffic_index = UP_LINK;
628 } else {
629 /* Balance TP is present. */
630 traffic_index = DOWN_LINK;
631 }
632 } else {
633 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
634 /* Downlink TP is present. */
635 traffic_index = DOWN_LINK;
636 } else {
637 /* Balance TP is present. */
638 traffic_index = UP_LINK;
639 }
640 }
641 #if 0
642 if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
643 || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
644 #endif
645 {
646 if (interface_type == RTW_PCIE) {
647 EDCA_BE_UL = 0x6ea42b;
648 EDCA_BE_DL = 0x6ea42b;
649 }
650
651 /* 92D txop can't be set to 0x3e for cisco1250 */
652 if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
653 EDCA_BE_DL = edca_setting_DL[iot_peer];
654 EDCA_BE_UL = edca_setting_UL[iot_peer];
655 }
656 /* merge from 92s_92c_merge temp*/
657 else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
658 EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
659 else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
660 EDCA_BE_DL = 0xa630;
661 else if (iot_peer == HT_IOT_PEER_MARVELL) {
662 EDCA_BE_DL = edca_setting_DL[iot_peer];
663 EDCA_BE_UL = edca_setting_UL[iot_peer];
664 } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
665 /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
666 /* Suggested by SD3 Wilson for ASUS TP issue.*/
667 EDCA_BE_DL = edca_setting_DL[iot_peer];
668 }
669
670 if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
671 EDCA_BE_UL = 0x5ea42b;
672 EDCA_BE_DL = 0x5ea42b;
673
674 RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
675 }
676
677 if (interface_type == RTW_PCIE &&
678 ((ic_type == RTL8822B)
679 || (ic_type == RTL8822C)
680 || (ic_type == RTL8814A))) {
681 EDCA_BE_UL = 0x6ea42b;
682 EDCA_BE_DL = 0x6ea42b;
683 }
684
685 if ((ic_type == RTL8822B)
686 && (interface_type == RTW_SDIO))
687 EDCA_BE_DL = 0x00431c;
688
689 #ifdef CONFIG_RTW_TPT_MODE
690 if ( dvobj->tpt_mode > 0 ) {
691 EDCA_BE_UL = dvobj->edca_be_ul;
692 EDCA_BE_DL = dvobj->edca_be_dl;
693 }
694 #endif /* CONFIG_RTW_TPT_MODE */
695
696 /* keep this condition at last check */
697 if (hal_data->dis_turboedca == 2) {
698
699 if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
700
701 struct turbo_edca_setting param;
702
703 param = rtw_turbo_edca[hal_data->edca_param_mode];
704
705 EDCA_BE_UL = param.edca_ul;
706 EDCA_BE_DL = param.edca_dl;
707
708 } else {
709
710 EDCA_BE_UL = hal_data->edca_param_mode;
711 EDCA_BE_DL = hal_data->edca_param_mode;
712 }
713 }
714
715 if (traffic_index == DOWN_LINK)
716 edca_param = EDCA_BE_DL;
717 else
718 edca_param = EDCA_BE_UL;
719
720 #ifdef CONFIG_EXTEND_LOWRATE_TXOP
721 #define TXOP_CCK1M 0x01A6
722 #define TXOP_CCK2M 0x00E6
723 #define TXOP_CCK5M 0x006B
724 #define TXOP_OFD6M 0x0066
725 #define TXOP_MCS6M 0x0061
726 {
727 struct sta_info *psta;
728 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
729 u8 mac_id, role, current_rate_id;
730
731 /* search all used & connect2AP macid */
732 for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
733 if (rtw_macid_is_used(macid_ctl, mac_id)) {
734 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
735 if (role != H2C_MSR_ROLE_AP)
736 continue;
737
738 psta = macid_ctl->sta[mac_id];
739 current_rate_id = rtw_get_current_tx_rate(adapter, psta);
740 /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
741 switch (current_rate_id) {
742 case DESC_RATE1M:
743 edca_param &= 0x0000FFFF;
744 edca_param |= (TXOP_CCK1M<<16);
745 break;
746 case DESC_RATE2M:
747 edca_param &= 0x0000FFFF;
748 edca_param |= (TXOP_CCK2M<<16);
749 break;
750 case DESC_RATE5_5M:
751 edca_param &= 0x0000FFFF;
752 edca_param |= (TXOP_CCK5M<<16);
753 break;
754 case DESC_RATE6M:
755 edca_param &= 0x0000FFFF;
756 edca_param |= (TXOP_OFD6M<<16);
757 break;
758 case DESC_RATEMCS0:
759 edca_param &= 0x0000FFFF;
760 edca_param |= (TXOP_MCS6M<<16);
761 break;
762 default:
763 break;
764 }
765 }
766 }
767 }
768 #endif /* CONFIG_EXTEND_LOWRATE_TXOP */
769
770 #ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
771 edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
772 #endif
773
774 if ( edca_param != hal_data->ac_param_be) {
775
776 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
777
778 RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
779 }
780
781 hal_data->prv_traffic_idx = traffic_index;
782 }
783
784 hal_data->is_turbo_edca = _TRUE;
785 } else {
786 /* */
787 /* Turn Off EDCA turbo here. */
788 /* Restore original EDCA according to the declaration of AP. */
789 /* */
790 if (hal_data->is_turbo_edca) {
791 edca_param = hal_data->ac_param_be;
792 rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
793 hal_data->is_turbo_edca = _FALSE;
794 }
795 }
796
797 }
798
rtw_dm_get_min_rssi(_adapter * adapter)799 s8 rtw_dm_get_min_rssi(_adapter *adapter)
800 {
801 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
802 struct sta_info *sta;
803 s8 min_rssi = 127, rssi;
804 int i;
805
806 for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
807 sta = macid_ctl->sta[i];
808 if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
809 || is_broadcast_mac_addr(sta->cmn.mac_addr))
810 continue;
811 rssi = sta->cmn.rssi_stat.rssi;
812 if (rssi >= 0 && min_rssi > rssi)
813 min_rssi = rssi;
814 }
815
816 return min_rssi == 127 ? 0 : min_rssi;
817 }
818
rtw_phydm_get_min_rssi(_adapter * adapter)819 s8 rtw_phydm_get_min_rssi(_adapter *adapter)
820 {
821 struct dm_struct *phydm = adapter_to_phydm(adapter);
822 s8 rssi_min = 0;
823
824 rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
825 return rssi_min;
826 }
827
rtw_phydm_get_cur_igi(_adapter * adapter)828 u8 rtw_phydm_get_cur_igi(_adapter *adapter)
829 {
830 struct dm_struct *phydm = adapter_to_phydm(adapter);
831 u8 cur_igi = 0;
832
833 cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
834 return cur_igi;
835 }
836
rtw_phydm_get_edcca_flag(_adapter * adapter)837 bool rtw_phydm_get_edcca_flag(_adapter *adapter)
838 {
839 struct dm_struct *phydm = adapter_to_phydm(adapter);
840 bool cur_edcca_flag = 0;
841
842 cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
843 return cur_edcca_flag;
844 }
845
rtw_phydm_get_phy_cnt(_adapter * adapter,enum phy_cnt cnt)846 u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
847 {
848 struct dm_struct *phydm = adapter_to_phydm(adapter);
849
850 if (cnt == FA_OFDM)
851 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
852 else if (cnt == FA_CCK)
853 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
854 else if (cnt == FA_TOTAL)
855 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
856 else if (cnt == CCA_OFDM)
857 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
858 else if (cnt == CCA_CCK)
859 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
860 else if (cnt == CCA_ALL)
861 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
862 else if (cnt == CRC32_OK_VHT)
863 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
864 else if (cnt == CRC32_OK_HT)
865 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
866 else if (cnt == CRC32_OK_LEGACY)
867 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
868 else if (cnt == CRC32_OK_CCK)
869 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
870 else if (cnt == CRC32_ERROR_VHT)
871 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
872 else if (cnt == CRC32_ERROR_HT)
873 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
874 else if (cnt == CRC32_ERROR_LEGACY)
875 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
876 else if (cnt == CRC32_ERROR_CCK)
877 return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
878 else
879 return 0;
880 }
881
rtw_phydm_is_iqk_in_progress(_adapter * adapter)882 u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
883 {
884 u8 rts = _FALSE;
885 struct dm_struct *podmpriv = adapter_to_phydm(adapter);
886
887 odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
888 if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
889 RTW_ERR("IQK InProgress\n");
890 rts = _TRUE;
891 }
892 odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
893
894 return rts;
895 }
896
SetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)897 void SetHalODMVar(
898 PADAPTER Adapter,
899 HAL_ODM_VARIABLE eVariable,
900 void *pValue1,
901 BOOLEAN bSet)
902 {
903 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
904 /* _irqL irqL; */
905 switch (eVariable) {
906 case HAL_ODM_STA_INFO: {
907 struct sta_info *psta = (struct sta_info *)pValue1;
908
909 if (bSet) {
910 RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
911 psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
912 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
913 } else {
914 RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
915 /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
916 psta->cmn.dm_ctrl = 0;
917 phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
918
919 /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
920 }
921 }
922 break;
923 case HAL_ODM_P2P_STATE:
924 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
925 break;
926 case HAL_ODM_WIFI_DISPLAY_STATE:
927 odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
928 break;
929 case HAL_ODM_REGULATION:
930 /* used to auto enable/disable adaptivity by SD7 */
931 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
932 phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
933 break;
934 case HAL_ODM_INITIAL_GAIN: {
935 u8 rx_gain = *((u8 *)(pValue1));
936 /*printk("rx_gain:%x\n",rx_gain);*/
937 if (rx_gain == 0xff) {/*restore rx gain*/
938 /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
939 odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
940 } else {
941 /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
942 /*odm_write_dig(podmpriv,rx_gain);*/
943 odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
944 }
945 }
946 break;
947 case HAL_ODM_RX_INFO_DUMP: {
948 u8 cur_igi = 0;
949 s8 rssi_min;
950 void *sel;
951
952 sel = pValue1;
953 cur_igi = rtw_phydm_get_cur_igi(Adapter);
954 rssi_min = rtw_phydm_get_min_rssi(Adapter);
955
956 _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
957 _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
958 , podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
959 _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
960 rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
961 rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
962 rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
963
964 if (podmpriv->is_linked) {
965 _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
966 if (IS_HARDWARE_TYPE_8814A(Adapter))
967 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
968 podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
969 else
970 _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
971 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
972 rtw_dump_raw_rssi_info(Adapter, sel);
973 #endif
974 }
975 }
976 break;
977 case HAL_ODM_RX_Dframe_INFO: {
978 void *sel;
979
980 sel = pValue1;
981
982 /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
983 #ifdef DBG_RX_DFRAME_RAW_DATA
984 rtw_dump_rx_dframe_info(Adapter, sel);
985 #endif
986 }
987 break;
988
989 #ifdef CONFIG_ANTENNA_DIVERSITY
990 case HAL_ODM_ANTDIV_SELECT: {
991 u8 antenna = (*(u8 *)pValue1);
992 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
993 /*switch antenna*/
994 odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
995 /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
996
997 }
998 break;
999 #endif
1000
1001 default:
1002 break;
1003 }
1004 }
1005
GetHalODMVar(PADAPTER Adapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)1006 void GetHalODMVar(
1007 PADAPTER Adapter,
1008 HAL_ODM_VARIABLE eVariable,
1009 void *pValue1,
1010 void *pValue2)
1011 {
1012 struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
1013
1014 switch (eVariable) {
1015 #ifdef CONFIG_ANTENNA_DIVERSITY
1016 case HAL_ODM_ANTDIV_SELECT: {
1017 struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
1018 *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
1019 }
1020 break;
1021 #endif
1022 case HAL_ODM_INITIAL_GAIN:
1023 *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
1024 break;
1025 default:
1026 break;
1027 }
1028 }
1029
1030 #ifdef RTW_HALMAC
1031 #include "../hal_halmac.h"
1032 #endif
1033
1034 enum hal_status
rtw_phydm_fw_iqk(struct dm_struct * p_dm_odm,u8 clear,u8 segment)1035 rtw_phydm_fw_iqk(
1036 struct dm_struct *p_dm_odm,
1037 u8 clear,
1038 u8 segment
1039 )
1040 {
1041 #ifdef RTW_HALMAC
1042 struct _ADAPTER *adapter = p_dm_odm->adapter;
1043
1044 if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
1045 return HAL_STATUS_SUCCESS;
1046 #endif
1047 return HAL_STATUS_FAILURE;
1048 }
1049
1050 enum hal_status
rtw_phydm_cfg_phy_para(struct dm_struct * p_dm_odm,enum phydm_halmac_param config_type,u32 offset,u32 data,u32 mask,enum rf_path e_rf_path,u32 delay_time)1051 rtw_phydm_cfg_phy_para(
1052 struct dm_struct *p_dm_odm,
1053 enum phydm_halmac_param config_type,
1054 u32 offset,
1055 u32 data,
1056 u32 mask,
1057 enum rf_path e_rf_path,
1058 u32 delay_time)
1059 {
1060 #ifdef RTW_HALMAC
1061 struct _ADAPTER *adapter = p_dm_odm->adapter;
1062 struct rtw_phy_parameter para;
1063
1064 switch (config_type) {
1065 case PHYDM_HALMAC_CMD_MAC_W8:
1066 para.cmd = 0; /* MAC register */
1067 para.data.mac.offset = offset;
1068 para.data.mac.value = data;
1069 para.data.mac.msk = mask;
1070 para.data.mac.msk_en = (mask) ? 1 : 0;
1071 para.data.mac.size = 1;
1072 break;
1073 case PHYDM_HALMAC_CMD_MAC_W16:
1074 para.cmd = 0; /* MAC register */
1075 para.data.mac.offset = offset;
1076 para.data.mac.value = data;
1077 para.data.mac.msk = mask;
1078 para.data.mac.msk_en = (mask) ? 1 : 0;
1079 para.data.mac.size = 2;
1080 break;
1081 case PHYDM_HALMAC_CMD_MAC_W32:
1082 para.cmd = 0; /* MAC register */
1083 para.data.mac.offset = offset;
1084 para.data.mac.value = data;
1085 para.data.mac.msk = mask;
1086 para.data.mac.msk_en = (mask) ? 1 : 0;
1087 para.data.mac.size = 4;
1088 break;
1089 case PHYDM_HALMAC_CMD_BB_W8:
1090 para.cmd = 1; /* BB register */
1091 para.data.bb.offset = offset;
1092 para.data.bb.value = data;
1093 para.data.bb.msk = mask;
1094 para.data.bb.msk_en = (mask) ? 1 : 0;
1095 para.data.bb.size = 1;
1096 break;
1097 case PHYDM_HALMAC_CMD_BB_W16:
1098 para.cmd = 1; /* BB register */
1099 para.data.bb.offset = offset;
1100 para.data.bb.value = data;
1101 para.data.bb.msk = mask;
1102 para.data.bb.msk_en = (mask) ? 1 : 0;
1103 para.data.bb.size = 2;
1104 break;
1105 case PHYDM_HALMAC_CMD_BB_W32:
1106 para.cmd = 1; /* BB register */
1107 para.data.bb.offset = offset;
1108 para.data.bb.value = data;
1109 para.data.bb.msk = mask;
1110 para.data.bb.msk_en = (mask) ? 1 : 0;
1111 para.data.bb.size = 4;
1112 break;
1113 case PHYDM_HALMAC_CMD_RF_W:
1114 para.cmd = 2; /* RF register */
1115 para.data.rf.offset = offset;
1116 para.data.rf.value = data;
1117 para.data.rf.msk = mask;
1118 para.data.rf.msk_en = (mask) ? 1 : 0;
1119 if (e_rf_path == RF_PATH_A)
1120 para.data.rf.path = 0;
1121 else if (e_rf_path == RF_PATH_B)
1122 para.data.rf.path = 1;
1123 else if (e_rf_path == RF_PATH_C)
1124 para.data.rf.path = 2;
1125 else if (e_rf_path == RF_PATH_D)
1126 para.data.rf.path = 3;
1127 else
1128 para.data.rf.path = 0;
1129 break;
1130 case PHYDM_HALMAC_CMD_DELAY_US:
1131 para.cmd = 3; /* Delay */
1132 para.data.delay.unit = 0; /* microsecond */
1133 para.data.delay.value = delay_time;
1134 break;
1135 case PHYDM_HALMAC_CMD_DELAY_MS:
1136 para.cmd = 3; /* Delay */
1137 para.data.delay.unit = 1; /* millisecond */
1138 para.data.delay.value = delay_time;
1139 break;
1140 case PHYDM_HALMAC_CMD_END:
1141 para.cmd = 0xFF; /* End command */
1142 break;
1143 default:
1144 return HAL_STATUS_FAILURE;
1145 }
1146
1147 if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
1148 return HAL_STATUS_FAILURE;
1149 #endif /*RTW_HALMAC*/
1150 return HAL_STATUS_SUCCESS;
1151 }
1152
1153
1154 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_phydm_wd_lps_lclk_hdl(_adapter * adapter)1155 void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
1156 {
1157 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1158 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1159 struct dm_struct *podmpriv = &(pHalData->odmpriv);
1160 struct sta_priv *pstapriv = &adapter->stapriv;
1161 struct sta_info *psta = NULL;
1162 u8 rssi_min = 0;
1163 u32 rssi_rpt = 0;
1164 bool is_linked = _FALSE;
1165
1166 if (!rtw_is_hw_init_completed(adapter))
1167 return;
1168
1169 if (rtw_mi_check_status(adapter, MI_ASSOC))
1170 is_linked = _TRUE;
1171
1172 if (is_linked == _FALSE)
1173 return;
1174
1175 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1176 if (psta == NULL)
1177 return;
1178
1179 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
1180
1181 phydm_watchdog_lps_32k(&pHalData->odmpriv);
1182 }
1183
rtw_phydm_watchdog_in_lps_lclk(_adapter * adapter)1184 void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
1185 {
1186 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1187 struct sta_priv *pstapriv = &adapter->stapriv;
1188 u8 cur_igi = 0;
1189 s8 min_rssi = 0;
1190
1191 if (!rtw_is_hw_init_completed(adapter))
1192 return;
1193
1194 cur_igi = rtw_phydm_get_cur_igi(adapter);
1195 min_rssi = rtw_dm_get_min_rssi(adapter);
1196 /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
1197
1198 if (min_rssi <= 0)
1199 return;
1200
1201 if ((cur_igi > min_rssi + 5) ||
1202 (cur_igi < min_rssi - 5)) {
1203 #ifdef CONFIG_LPS
1204 rtw_dm_in_lps_wk_cmd(adapter);
1205 #endif
1206 }
1207 }
1208 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1209
dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)1210 void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
1211 {
1212 struct ra_sta_info *ra_info;
1213 u8 curr_sgi = _FALSE;
1214 u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
1215
1216 if (!psta)
1217 return;
1218 RTW_PRINT_SEL(sel, "\n");
1219 RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
1220 psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
1221
1222 if (is_client_associated_to_ap(psta->padapter))
1223 RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
1224 rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
1225
1226 ra_info = &psta->cmn.ra_info;
1227 curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
1228 RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
1229 , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
1230 , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
1231 );
1232
1233 if (0) {
1234 RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
1235 , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
1236 , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
1237 );
1238 RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
1239 , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
1240 , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
1241 );
1242 RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
1243 , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
1244 , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
1245 );
1246 RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
1247 , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
1248 , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
1249 );
1250 }
1251
1252 _RTW_PRINT_SEL(sel, "RTW: [TP] ");
1253 tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
1254 rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
1255 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1256
1257 if (tx_tp_mbips)
1258 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1259 else
1260 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
1261
1262 if (rx_tp_mbips)
1263 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1264 else
1265 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
1266
1267 if (bi_tp_mbips)
1268 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1269 else
1270 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1271
1272
1273 _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
1274 tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
1275 rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
1276 bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
1277 if (tx_tp_mbips)
1278 _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
1279 else
1280 _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
1281
1282 if (rx_tp_mbips)
1283 _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
1284 else
1285 _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
1286
1287 if (bi_tp_mbips)
1288 _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
1289 else
1290 _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
1291
1292 #if 0
1293 RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
1294 (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
1295 (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
1296 #endif
1297 }
1298
dump_sta_info(void * sel,struct sta_info * psta)1299 void dump_sta_info(void *sel, struct sta_info *psta)
1300 {
1301 struct ra_sta_info *ra_info;
1302 u8 curr_tx_sgi = _FALSE;
1303 u8 curr_tx_rate = 0;
1304
1305 if (!psta)
1306 return;
1307
1308 ra_info = &psta->cmn.ra_info;
1309
1310 RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
1311 MAC_ARG(psta->cmn.mac_addr));
1312 RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
1313 RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
1314 RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
1315 RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
1316 RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
1317 ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
1318 RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
1319 RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
1320 RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
1321 (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
1322 RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
1323 (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
1324 RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
1325 RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
1326
1327 curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
1328 curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
1329 RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
1330 HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
1331 RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
1332 RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
1333 RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
1334 }
1335
rtw_phydm_ra_registed(_adapter * adapter,struct sta_info * psta)1336 void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
1337 {
1338 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1339 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1340 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
1341
1342 if (psta == NULL) {
1343 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
1344 rtw_warn_on(1);
1345 return;
1346 }
1347
1348 if (psta->cmn.mac_id >= macid_ctl->num)
1349 return;
1350
1351 phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
1352 dump_sta_info(RTW_DBGDUMP, psta);
1353 }
1354
init_phydm_info(_adapter * adapter)1355 static void init_phydm_info(_adapter *adapter)
1356 {
1357 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1358 struct dm_struct *phydm = &(hal_data->odmpriv);
1359
1360 odm_cmn_info_update(phydm, ODM_CMNINFO_IS_DOWNLOAD_FW, hal_data->bFWReady);
1361 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
1362 odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
1363 }
rtw_phydm_init(_adapter * adapter)1364 void rtw_phydm_init(_adapter *adapter)
1365 {
1366 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1367 struct dm_struct *phydm = &(hal_data->odmpriv);
1368
1369 init_phydm_info(adapter);
1370 odm_dm_init(phydm);
1371 #ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
1372 phydm_pathb_q_matrix_rotate_en(phydm);
1373 #endif
1374 }
1375
rtw_phydm_set_crystal_cap(_adapter * adapter,u8 crystal_cap)1376 bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
1377 {
1378 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1379 struct dm_struct *phydm = &(hal_data->odmpriv);
1380
1381 return phydm_set_crystal_cap_reg(phydm, crystal_cap);
1382 }
1383
1384 #ifdef CONFIG_LPS_PG
1385 /*
1386 static void _lps_pg_state_update(_adapter *adapter)
1387 {
1388 u8 is_in_lpspg = _FALSE;
1389 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1390 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1391 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1392 struct sta_priv *pstapriv = &adapter->stapriv;
1393 struct sta_info *psta = NULL;
1394
1395 if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
1396 is_in_lpspg = _TRUE;
1397 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
1398
1399 if (psta)
1400 psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
1401 }
1402 */
rtw_phydm_lps_pg_hdl(_adapter * adapter,struct sta_info * sta,bool in_lpspg)1403 void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
1404 {
1405 struct dm_struct *phydm = adapter_to_phydm(adapter);
1406 /*u8 rate_id;*/
1407
1408 if(sta == NULL) {
1409 RTW_ERR("%s sta is null\n", __func__);
1410 rtw_warn_on(1);
1411 return;
1412 }
1413
1414 if (in_lpspg) {
1415 sta->cmn.ra_info.disable_ra = _TRUE;
1416 sta->cmn.ra_info.disable_pt = _TRUE;
1417 /*TODO : DRV fix tx rate*/
1418 /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
1419 } else {
1420 sta->cmn.ra_info.disable_ra = _FALSE;
1421 sta->cmn.ra_info.disable_pt = _FALSE;
1422 }
1423
1424 rtw_phydm_ra_registed(adapter, sta);
1425 }
1426 #endif
1427
1428 /*#define DBG_PHYDM_STATE_CHK*/
1429
1430
_rtw_phydm_rfk_condition_check(_adapter * adapter,u8 is_scaning,u8 ifs_linked)1431 static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
1432 {
1433 u8 rfk_allowed = _TRUE;
1434
1435 #ifdef CONFIG_SKIP_RFK_IN_DM
1436 rfk_allowed = _FALSE;
1437 if (0)
1438 RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
1439 return rfk_allowed;
1440 #endif
1441
1442 #ifdef CONFIG_MCC_MODE
1443 /*not in MCC State*/
1444 if (MCC_EN(adapter) &&
1445 rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
1446 rfk_allowed = _FALSE;
1447 if (0)
1448 RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
1449 return rfk_allowed;
1450 }
1451 #endif
1452
1453 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1454
1455 #endif
1456
1457 if (ifs_linked) {
1458 if (is_scaning) {
1459 rfk_allowed = _FALSE;
1460 RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
1461 }
1462 else {
1463 rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
1464 if (rfk_allowed == _FALSE)
1465 RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
1466 }
1467 }
1468
1469 return rfk_allowed;
1470 }
1471
1472 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
_rtw_phydm_iqk_segment_chk(_adapter * adapter,u8 ifs_linked)1473 static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
1474 {
1475 u8 iqk_sgt = _FALSE;
1476
1477 #if 0
1478 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1479 if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
1480 rst = _TRUE;
1481 #else
1482 if (ifs_linked)
1483 iqk_sgt = _TRUE;
1484 #endif
1485 return iqk_sgt;
1486 }
1487 #endif
1488
1489 /*check the tx low rate while unlinked to any AP;for pwr tracking */
_rtw_phydm_pwr_tracking_rate_check(_adapter * adapter)1490 static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
1491 {
1492 int i;
1493 _adapter *iface;
1494 u8 if_tx_rate = 0xFF;
1495 u8 tx_rate = 0xFF;
1496 struct mlme_ext_priv *pmlmeext = NULL;
1497 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1498
1499 for (i = 0; i < dvobj->iface_nums; i++) {
1500 iface = dvobj->padapters[i];
1501 pmlmeext = &(iface->mlmeextpriv);
1502 if ((iface) && rtw_is_adapter_up(iface)) {
1503 #ifdef CONFIG_P2P
1504 if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
1505 if_tx_rate = IEEE80211_OFDM_RATE_6MB;
1506 else
1507 #endif
1508 if_tx_rate = pmlmeext->tx_rate;
1509 if(if_tx_rate < tx_rate)
1510 tx_rate = if_tx_rate;
1511
1512 RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate);
1513 }
1514 }
1515 RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
1516 return tx_rate;
1517 }
1518
1519 #ifdef CONFIG_DYNAMIC_SOML
rtw_dyn_soml_byte_update(_adapter * adapter,u8 data_rate,u32 size)1520 void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
1521 {
1522 struct dm_struct *phydm = adapter_to_phydm(adapter);
1523
1524 phydm_soml_bytes_acq(phydm, data_rate, size);
1525 }
1526
rtw_dyn_soml_para_set(_adapter * adapter,u8 train_num,u8 intvl,u8 period,u8 delay)1527 void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
1528 u8 period, u8 delay)
1529 {
1530 struct dm_struct *phydm = adapter_to_phydm(adapter);
1531
1532 phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
1533 RTW_INFO("%s.\n", __func__);
1534 }
1535
rtw_dyn_soml_config(_adapter * adapter)1536 void rtw_dyn_soml_config(_adapter *adapter)
1537 {
1538 RTW_INFO("%s.\n", __func__);
1539
1540 if (adapter->registrypriv.dyn_soml_en == 1) {
1541 /* Must after phydm_adaptive_soml_init() */
1542 rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
1543 RTW_INFO("dyn_soml_en = 1\n");
1544 } else {
1545 if (adapter->registrypriv.dyn_soml_en == 2) {
1546 rtw_dyn_soml_para_set(adapter,
1547 adapter->registrypriv.dyn_soml_train_num,
1548 adapter->registrypriv.dyn_soml_interval,
1549 adapter->registrypriv.dyn_soml_period,
1550 adapter->registrypriv.dyn_soml_delay);
1551 RTW_INFO("dyn_soml_en = 2\n");
1552 RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
1553 adapter->registrypriv.dyn_soml_train_num,
1554 adapter->registrypriv.dyn_soml_interval,
1555 adapter->registrypriv.dyn_soml_period,
1556 adapter->registrypriv.dyn_soml_delay);
1557 } else if (adapter->registrypriv.dyn_soml_en == 0) {
1558 RTW_INFO("dyn_soml_en = 0\n");
1559 } else
1560 RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
1561 adapter->registrypriv.dyn_soml_en);
1562 }
1563 }
1564 #endif
1565
1566 #ifdef RTW_DYNAMIC_RRSR
rtw_phydm_set_rrsr(_adapter * adapter,u32 rrsr_value,bool write_rrsr)1567 void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
1568 {
1569
1570 struct dm_struct *phydm = adapter_to_phydm(adapter);
1571
1572 odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, rrsr_value);
1573 if(write_rrsr)
1574 phydm_rrsr_set_register(phydm, rrsr_value);
1575 }
1576 #endif/*RTW_DYNAMIC_RRSR*/
rtw_phydm_read_efuse(_adapter * adapter)1577 void rtw_phydm_read_efuse(_adapter *adapter)
1578 {
1579 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1580 struct dm_struct *phydm = &(hal_data->odmpriv);
1581
1582 /*PHYDM API - thermal trim*/
1583 phydm_get_thermal_trim_offset(phydm);
1584 /*PHYDM API - power trim*/
1585 phydm_get_power_trim_offset(phydm);
1586 }
1587
1588 #ifdef CONFIG_LPS_PWR_TRACKING
rtw_phydm_pwr_tracking_directly(_adapter * adapter)1589 void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
1590 {
1591 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
1592 u8 rfk_forbidden = _TRUE;
1593 u8 is_linked = _FALSE;
1594
1595 if (rtw_mi_check_status(adapter, MI_ASSOC))
1596 is_linked = _TRUE;
1597
1598 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
1599 halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1600
1601 odm_txpowertracking_direct_ce(&hal_data->odmpriv);
1602 }
1603 #endif
1604
rtw_phydm_watchdog(_adapter * adapter,bool in_lps)1605 void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
1606 {
1607 u8 bLinked = _FALSE;
1608 u8 bsta_state = _FALSE;
1609 u8 bBtDisabled = _TRUE;
1610 u8 rfk_forbidden = _FALSE;
1611 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1612 u8 segment_iqk = _FALSE;
1613 #endif
1614 u8 tx_unlinked_low_rate = 0xFF;
1615 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
1616
1617 if (!rtw_is_hw_init_completed(adapter)) {
1618 RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
1619 return;
1620 }
1621 if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY))
1622 pHalData->bScanInProcess = _TRUE;
1623 else
1624 pHalData->bScanInProcess = _FALSE;
1625
1626 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
1627 bLinked = _TRUE;
1628 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
1629 bsta_state = _TRUE;
1630 }
1631
1632 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
1633 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
1634
1635 #ifdef CONFIG_BT_COEXIST
1636 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
1637 #endif /* CONFIG_BT_COEXIST */
1638 odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
1639 (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
1640
1641 rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
1642 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
1643
1644 #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
1645 segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
1646 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
1647 #endif
1648 #ifdef DBG_PHYDM_STATE_CHK
1649 RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
1650 __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
1651 #endif
1652
1653 if (bLinked == _FALSE) {
1654 tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
1655 halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
1656 }
1657
1658 /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
1659 #ifdef DBG_PHYDM_STATE_CHK
1660 RTW_ERR("Not stay in union band, skip phydm\n");
1661 #endif
1662 goto _exit;
1663 }*/
1664
1665 #ifdef CONFIG_TDMADIG
1666 rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
1667 #endif/*CONFIG_TDMADIG*/
1668
1669 if (in_lps)
1670 phydm_watchdog_lps(&pHalData->odmpriv);
1671 else
1672 phydm_watchdog(&pHalData->odmpriv);
1673
1674 #ifdef CONFIG_RTW_ACS
1675 rtw_acs_update_current_info(adapter);
1676 #endif
1677
1678 return;
1679 }
1680
1681 #ifdef CONFIG_CTRL_TXSS_BY_TP
rtw_phydm_trx_cfg(_adapter * adapter,bool tx_1ss)1682 void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
1683 {
1684 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1685 enum bb_path txpath = BB_PATH_AB;
1686 enum bb_path rxpath = BB_PATH_AB;
1687 /*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
1688 enum bb_path txpath_1ss = BB_PATH_A;
1689
1690 rtw_hal_get_rf_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
1691 txpath = (tx_1ss) ? BB_PATH_A : txpath;
1692
1693 if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
1694 RTW_ERR("%s failed\n", __func__);
1695 }
1696 #endif
1697
1698