1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 *******************************************************************************/ 19 #ifndef __RTL8814A_SPEC_H__ 20 #define __RTL8814A_SPEC_H__ 21 22 #include <drv_conf.h> 23 24 25 //============================================================ 26 // 27 //============================================================ 28 29 //----------------------------------------------------- 30 // 31 // 0x0000h ~ 0x00FFh System Configuration 32 // 33 //----------------------------------------------------- 34 #define REG_SYS_ISO_CTRL_8814A 0x0000 // 2 Byte 35 #define REG_SYS_FUNC_EN_8814A 0x0002 // 2 Byte 36 #define REG_SYS_PW_CTRL_8814A 0x0004 // 4 Byte 37 #define REG_SYS_CLKR_8814A 0x0008 // 2 Byte 38 #define REG_SYS_EEPROM_CTRL_8814A 0x000A // 2 Byte 39 #define REG_EE_VPD_8814A 0x000C // 2 Byte 40 #define REG_SYS_SWR_CTRL1_8814A 0x0010 // 1 Byte 41 #define REG_SPS0_CTRL_8814A 0x0011 // 7 Byte 42 #define REG_SYS_SWR_CTRL3_8814A 0x0018 // 4 Byte 43 #define REG_RSV_CTRL_8814A 0x001C // 3 Byte 44 #define REG_RF_CTRL0_8814A 0x001F // 1 Byte 45 #define REG_RF_CTRL1_8814A 0x0020 // 1 Byte 46 #define REG_RF_CTRL2_8814A 0x0021 // 1 Byte 47 #define REG_LPLDO_CTRL_8814A 0x0023 // 1 Byte 48 #define REG_AFE_CTRL1_8814A 0x0024 // 4 Byte 49 #define REG_AFE_CTRL2_8814A 0x0028 // 4 Byte 50 #define REG_AFE_CTRL3_8814A 0x002c // 4 Byte 51 #define REG_EFUSE_CTRL_8814A 0x0030 52 #define REG_LDO_EFUSE_CTRL_8814A 0x0034 53 #define REG_PWR_DATA_8814A 0x0038 54 #define REG_CAL_TIMER_8814A 0x003C 55 #define REG_ACLK_MON_8814A 0x003E 56 #define REG_GPIO_MUXCFG_8814A 0x0040 57 #define REG_GPIO_IO_SEL_8814A 0x0042 58 #define REG_MAC_PINMUX_CFG_8814A 0x0043 59 #define REG_GPIO_PIN_CTRL_8814A 0x0044 60 #define REG_GPIO_INTM_8814A 0x0048 61 #define REG_LEDCFG0_8814A 0x004C 62 #define REG_LEDCFG1_8814A 0x004D 63 #define REG_LEDCFG2_8814A 0x004E 64 #define REG_LEDCFG3_8814A 0x004F 65 #define REG_FSIMR_8814A 0x0050 66 #define REG_FSISR_8814A 0x0054 67 #define REG_HSIMR_8814A 0x0058 68 #define REG_HSISR_8814A 0x005c 69 #define REG_GPIO_EXT_CTRL_8814A 0x0060 70 #define REG_GPIO_STATUS_8814A 0x006C 71 #define REG_SDIO_CTRL_8814A 0x0070 72 #define REG_HCI_OPT_CTRL_8814A 0x0074 73 #define REG_RF_CTRL3_8814A 0x0076 // 1 Byte 74 #define REG_AFE_CTRL4_8814A 0x0078 75 #define REG_8051FW_CTRL_8814A 0x0080 76 #define REG_HIMR0_8814A 0x00B0 77 #define REG_HISR0_8814A 0x00B4 78 #define REG_HIMR1_8814A 0x00B8 79 #define REG_HISR1_8814A 0x00BC 80 #define REG_SYS_CFG1_8814A 0x00F0 81 #define REG_SYS_CFG2_8814A 0x00FC 82 83 //----------------------------------------------------- 84 // 85 // 0x0100h ~ 0x01FFh MACTOP General Configuration 86 // 87 //----------------------------------------------------- 88 #define REG_CR_8814A 0x0100 89 #define REG_PBP_8814A 0x0104 90 #define REG_PKT_BUFF_ACCESS_CTRL_8814A 0x0106 91 #define REG_TRXDMA_CTRL_8814A 0x010C 92 #define REG_TRXFF_BNDY_8814A 0x0114 93 #define REG_TRXFF_STATUS_8814A 0x0118 94 #define REG_RXFF_PTR_8814A 0x011C 95 #define REG_CPWM_8814A 0x012F 96 #define REG_FWIMR_8814A 0x0130 97 #define REG_FWISR_8814A 0x0134 98 #define REG_FTIMR_8814A 0x0138 99 #define REG_PKTBUF_DBG_CTRL_8814A 0x0140 100 #define REG_RXPKTBUF_CTRL_8814A 0x0142 101 #define REG_PKTBUF_DBG_DATA_L_8814A 0x0144 102 #define REG_PKTBUF_DBG_DATA_H_8814A 0x0148 103 104 #define REG_TC0_CTRL_8814A 0x0150 105 #define REG_TC1_CTRL_8814A 0x0154 106 #define REG_TC2_CTRL_8814A 0x0158 107 #define REG_TC3_CTRL_8814A 0x015C 108 #define REG_TC4_CTRL_8814A 0x0160 109 #define REG_TCUNIT_BASE_8814A 0x0164 110 #define REG_RSVD3_8814A 0x0168 111 #define REG_C2HEVT_MSG_NORMAL_8814A 0x01A0 112 #define REG_C2HEVT_CLEAR_8814A 0x01AF 113 #define REG_MCUTST_1_8814A 0x01C0 114 #define REG_MCUTST_WOWLAN_8814A 0x01C7 115 #define REG_FMETHR_8814A 0x01C8 116 #define REG_HMETFR_8814A 0x01CC 117 #define REG_HMEBOX_0_8814A 0x01D0 118 #define REG_HMEBOX_1_8814A 0x01D4 119 #define REG_HMEBOX_2_8814A 0x01D8 120 #define REG_HMEBOX_3_8814A 0x01DC 121 #define REG_LLT_INIT_8814A 0x01E0 122 #define REG_LLT_ADDR_8814A 0x01E4 //20130415 KaiYuan add for 8814 123 #define REG_HMEBOX_EXT0_8814A 0x01F0 124 #define REG_HMEBOX_EXT1_8814A 0x01F4 125 #define REG_HMEBOX_EXT2_8814A 0x01F8 126 #define REG_HMEBOX_EXT3_8814A 0x01FC 127 128 //----------------------------------------------------- 129 // 130 // 0x0200h ~ 0x027Fh TXDMA Configuration 131 // 132 //----------------------------------------------------- 133 #define REG_FIFOPAGE_CTRL_1_8814A 0x0200 134 #define REG_FIFOPAGE_CTRL_2_8814A 0x0204 135 #define REG_AUTO_LLT_8814A 0x0208 136 #define REG_TXDMA_OFFSET_CHK_8814A 0x020C 137 #define REG_TXDMA_STATUS_8814A 0x0210 138 #define REG_RQPN_NPQ_8814A 0x0214 139 #define REG_TQPNT1_8814A 0x0218 140 #define REG_TQPNT2_8814A 0x021C 141 #define REG_TQPNT3_8814A 0x0220 142 #define REG_TQPNT4_8814A 0x0224 143 #define REG_RQPN_CTRL_1_8814A 0x0228 144 #define REG_RQPN_CTRL_2_8814A 0x022C 145 #define REG_FIFOPAGE_INFO_1_8814A 0x0230 146 #define REG_FIFOPAGE_INFO_2_8814A 0x0234 147 #define REG_FIFOPAGE_INFO_3_8814A 0x0238 148 #define REG_FIFOPAGE_INFO_4_8814A 0x023C 149 #define REG_FIFOPAGE_INFO_5_8814A 0x0240 150 151 152 //----------------------------------------------------- 153 // 154 // 0x0280h ~ 0x02FFh RXDMA Configuration 155 // 156 //----------------------------------------------------- 157 #define REG_RXDMA_AGG_PG_TH_8814A 0x0280 158 #define REG_RXPKT_NUM_8814A 0x0284 // The number of packets in RXPKTBUF. 159 #define REG_RXDMA_CONTROL_8814A 0x0286 // ?????? Control the RX DMA. 160 #define REG_RXDMA_STATUS_8814A 0x0288 161 #define REG_RXDMA_MODE_8814A 0x0290 // ?????? 162 #define REG_EARLY_MODE_CONTROL_8814A 0x02BC // ?????? 163 #define REG_RSVD5_8814A 0x02F0 // ?????? 164 165 166 //----------------------------------------------------- 167 // 168 // 0x0300h ~ 0x03FFh PCIe 169 // 170 //----------------------------------------------------- 171 #define REG_PCIE_CTRL_REG_8814A 0x0300 172 #define REG_INT_MIG_8814A 0x0304 // Interrupt Migration 173 #define REG_BCNQ_TXBD_DESA_8814A 0x0308 // TX Beacon Descriptor Address 174 #define REG_MGQ_TXBD_DESA_8814A 0x0310 // TX Manage Queue Descriptor Address 175 #define REG_VOQ_TXBD_DESA_8814A 0x0318 // TX VO Queue Descriptor Address 176 #define REG_VIQ_TXBD_DESA_8814A 0x0320 // TX VI Queue Descriptor Address 177 #define REG_BEQ_TXBD_DESA_8814A 0x0328 // TX BE Queue Descriptor Address 178 #define REG_BKQ_TXBD_DESA_8814A 0x0330 // TX BK Queue Descriptor Address 179 #define REG_RXQ_RXBD_DESA_8814A 0x0338 // RX Queue Descriptor Address 180 #define REG_HI0Q_TXBD_DESA_8814A 0x0340 181 #define REG_HI1Q_TXBD_DESA_8814A 0x0348 182 #define REG_HI2Q_TXBD_DESA_8814A 0x0350 183 #define REG_HI3Q_TXBD_DESA_8814A 0x0358 184 #define REG_HI4Q_TXBD_DESA_8814A 0x0360 185 #define REG_HI5Q_TXBD_DESA_8814A 0x0368 186 #define REG_HI6Q_TXBD_DESA_8814A 0x0370 187 #define REG_HI7Q_TXBD_DESA_8814A 0x0378 188 #define REG_MGQ_TXBD_NUM_8814A 0x0380 189 #define REG_RX_RXBD_NUM_8814A 0x0382 190 #define REG_VOQ_TXBD_NUM_8814A 0x0384 191 #define REG_VIQ_TXBD_NUM_8814A 0x0386 192 #define REG_BEQ_TXBD_NUM_8814A 0x0388 193 #define REG_BKQ_TXBD_NUM_8814A 0x038A 194 #define REG_HI0Q_TXBD_NUM_8814A 0x038C 195 #define REG_HI1Q_TXBD_NUM_8814A 0x038E 196 #define REG_HI2Q_TXBD_NUM_8814A 0x0390 197 #define REG_HI3Q_TXBD_NUM_8814A 0x0392 198 #define REG_HI4Q_TXBD_NUM_8814A 0x0394 199 #define REG_HI5Q_TXBD_NUM_8814A 0x0396 200 #define REG_HI6Q_TXBD_NUM_8814A 0x0398 201 #define REG_HI7Q_TXBD_NUM_8814A 0x039A 202 #define REG_TSFTIMER_HCI_8814A 0x039C 203 204 //Read Write Point 205 #define REG_VOQ_TXBD_IDX_8814A 0x03A0 206 #define REG_VIQ_TXBD_IDX_8814A 0x03A4 207 #define REG_BEQ_TXBD_IDX_8814A 0x03A8 208 #define REG_BKQ_TXBD_IDX_8814A 0x03AC 209 #define REG_MGQ_TXBD_IDX_8814A 0x03B0 210 #define REG_RXQ_TXBD_IDX_8814A 0x03B4 211 #define REG_HI0Q_TXBD_IDX_8814A 0x03B8 212 #define REG_HI1Q_TXBD_IDX_8814A 0x03BC 213 #define REG_HI2Q_TXBD_IDX_8814A 0x03C0 214 #define REG_HI3Q_TXBD_IDX_8814A 0x03C4 215 #define REG_HI4Q_TXBD_IDX_8814A 0x03C8 216 #define REG_HI5Q_TXBD_IDX_8814A 0x03CC 217 #define REG_HI6Q_TXBD_IDX_8814A 0x03D0 218 #define REG_HI7Q_TXBD_IDX_8814A 0x03D4 219 #define REG_DBG_SEL_V1_8814A 0x03D8 220 #define REG_PCIE_HRPWM1_V1_8814A 0x03D9 221 #define REG_PCIE_HCPWM1_V1_8814A 0x03DA 222 #define REG_PCIE_CTRL2_8814A 0x03DB 223 #define REG_PCIE_HRPWM2_V1_8814A 0x03DC 224 #define REG_PCIE_HCPWM2_V1_8814A 0x03DE 225 #define REG_PCIE_H2C_MSG_V1_8814A 0x03E0 226 #define REG_PCIE_C2H_MSG_V1_8814A 0x03E4 227 #define REG_DBI_WDATA_V1_8814A 0x03E8 228 #define REG_DBI_RDATA_V1_8814A 0x03EC 229 #define REG_DBI_FLAG_V1_8814A 0x03F0 230 #define REG_MDIO_V1_8814A 0x03F4 231 #define REG_PCIE_MIX_CFG_8814A 0x03F8 232 #define REG_DBG_8814A 0x03FC 233 //----------------------------------------------------- 234 // 235 // 0x0400h ~ 0x047Fh Protocol Configuration 236 // 237 //----------------------------------------------------- 238 #define REG_VOQ_INFORMATION_8814A 0x0400 239 #define REG_VIQ_INFORMATION_8814A 0x0404 240 #define REG_BEQ_INFORMATION_8814A 0x0408 241 #define REG_BKQ_INFORMATION_8814A 0x040C 242 #define REG_MGQ_INFORMATION_8814A 0x0410 243 #define REG_HGQ_INFORMATION_8814A 0x0414 244 #define REG_BCNQ_INFORMATION_8814A 0x0418 245 #define REG_TXPKT_EMPTY_8814A 0x041A 246 #define REG_CPU_MGQ_INFORMATION_8814A 0x041C 247 #define REG_FWHW_TXQ_CTRL_8814A 0x0420 248 #define REG_HWSEQ_CTRL_8814A 0x0423 249 #define REG_TXPKTBUF_BCNQ_BDNY_8814A 0x0424 250 //#define REG_MGQ_BDNY_8814A 0x0425 251 #define REG_LIFETIME_EN_8814A 0x0426 252 //#define REG_FW_FREE_TAIL_8814A 0x0427 253 #define REG_SPEC_SIFS_8814A 0x0428 254 #define REG_RETRY_LIMIT_8814A 0x042A 255 #define REG_TXBF_CTRL_8814A 0x042C 256 #define REG_DARFRC_8814A 0x0430 257 #define REG_RARFRC_8814A 0x0438 258 #define REG_RRSR_8814A 0x0440 259 #define REG_ARFR0_8814A 0x0444 260 #define REG_ARFR1_8814A 0x044C 261 #define REG_CCK_CHECK_8814A 0x0454 262 #define REG_AMPDU_MAX_TIME_8814A 0x0455 263 #define REG_TXPKTBUF_BCNQ1_BDNY_8814A 0x0456 264 #define REG_AMPDU_MAX_LENGTH_8814A 0x0458 265 #define REG_ACQ_STOP_8814A 0x045C 266 #define REG_NDPA_RATE_8814A 0x045D 267 #define REG_TX_HANG_CTRL_8814A 0x045E 268 #define REG_NDPA_OPT_CTRL_8814A 0x045F 269 #define REG_FAST_EDCA_CTRL_8814A 0x0460 270 #define REG_RD_RESP_PKT_TH_8814A 0x0463 271 #define REG_CMDQ_INFO_8814A 0x0464 272 #define REG_Q4_INFO_8814A 0x0468 273 #define REG_Q5_INFO_8814A 0x046C 274 #define REG_Q6_INFO_8814A 0x0470 275 #define REG_Q7_INFO_8814A 0x0474 276 #define REG_WMAC_LBK_BUF_HD_8814A 0x0478 277 #define REG_MGQ_PGBNDY_8814A 0x047A 278 #define REG_INIRTS_RATE_SEL_8814A 0x0480 279 #define REG_BASIC_CFEND_RATE_8814A 0x0481 280 #define REG_STBC_CFEND_RATE_8814A 0x0482 281 #define REG_DATA_SC_8814A 0x0483 282 #define REG_MACID_SLEEP3_8814A 0x0484 283 #define REG_MACID_SLEEP1_8814A 0x0488 284 #define REG_ARFR2_8814A 0x048C 285 #define REG_ARFR3_8814A 0x0494 286 #define REG_ARFR4_8814A 0x049C 287 #define REG_ARFR5_8814A 0x04A4 288 #define REG_TXRPT_START_OFFSET_8814A 0x04AC 289 #define REG_TRYING_CNT_TH_8814A 0x04B0 290 #define REG_POWER_STAGE1_8814A 0x04B4 291 #define REG_POWER_STAGE2_8814A 0x04B8 292 #define REG_SW_AMPDU_BURST_MODE_CTRL_8814A 0x04BC 293 #define REG_PKT_LIFE_TIME_8814A 0x04C0 294 #define REG_PKT_BE_BK_LIFE_TIME_8814A 0x04C2 // ?????? 295 #define REG_STBC_SETTING_8814A 0x04C4 296 #define REG_STBC_8814A 0x04C5 297 #define REG_QUEUE_CTRL_8814A 0x04C6 298 #define REG_SINGLE_AMPDU_CTRL_8814A 0x04C7 299 #define REG_PROT_MODE_CTRL_8814A 0x04C8 300 #define REG_MAX_AGGR_NUM_8814A 0x04CA 301 #define REG_RTS_MAX_AGGR_NUM_8814A 0x04CB 302 #define REG_BAR_MODE_CTRL_8814A 0x04CC 303 #define REG_RA_TRY_RATE_AGG_LMT_8814A 0x04CF 304 #define REG_MACID_SLEEP2_8814A 0x04D0 305 #define REG_MACID_SLEEP0_8814A 0x04D4 306 #define REG_HW_SEQ0_8814A 0x04D8 307 #define REG_HW_SEQ1_8814A 0x04DA 308 #define REG_HW_SEQ2_8814A 0x04DC 309 #define REG_HW_SEQ3_8814A 0x04DE 310 #define REG_NULL_PKT_STATUS_8814A 0x04E0 311 #define REG_PTCL_ERR_STATUS_8814A 0x04E2 312 #define REG_DROP_PKT_NUM_8814A 0x04EC 313 #define REG_PTCL_TX_RPT_8814A 0x04F0 314 #define REG_Dummy_8814A 0x04FC 315 316 317 //----------------------------------------------------- 318 // 319 // 0x0500h ~ 0x05FFh EDCA Configuration 320 // 321 //----------------------------------------------------- 322 #define REG_EDCA_VO_PARAM_8814A 0x0500 323 #define REG_EDCA_VI_PARAM_8814A 0x0504 324 #define REG_EDCA_BE_PARAM_8814A 0x0508 325 #define REG_EDCA_BK_PARAM_8814A 0x050C 326 #define REG_BCNTCFG_8814A 0x0510 327 #define REG_PIFS_8814A 0x0512 328 #define REG_RDG_PIFS_8814A 0x0513 329 #define REG_SIFS_CTX_8814A 0x0514 330 #define REG_SIFS_TRX_8814A 0x0516 331 #define REG_AGGR_BREAK_TIME_8814A 0x051A 332 #define REG_SLOT_8814A 0x051B 333 #define REG_TX_PTCL_CTRL_8814A 0x0520 334 #define REG_TXPAUSE_8814A 0x0522 335 #define REG_DIS_TXREQ_CLR_8814A 0x0523 336 #define REG_RD_CTRL_8814A 0x0524 337 // 338 // Format for offset 540h-542h: 339 // [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 340 // [7:4]: Reserved. 341 // [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 342 // [23:20]: Reserved 343 // Description: 344 // | 345 // |<--Setup--|--Hold------------>| 346 // --------------|---------------------- 347 // | 348 // TBTT 349 // Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 350 // Described by Designer Tim and Bruce, 2011-01-14. 351 // 352 #define REG_TBTT_PROHIBIT_8814A 0x0540 353 #define REG_RD_NAV_NXT_8814A 0x0544 354 #define REG_NAV_PROT_LEN_8814A 0x0546 355 #define REG_BCN_CTRL_8814A 0x0550 356 #define REG_BCN_CTRL_1_8814A 0x0551 357 #define REG_MBID_NUM_8814A 0x0552 358 #define REG_DUAL_TSF_RST_8814A 0x0553 359 #define REG_MBSSID_BCN_SPACE_8814A 0x0554 360 #define REG_DRVERLYINT_8814A 0x0558 361 #define REG_BCNDMATIM_8814A 0x0559 362 #define REG_ATIMWND_8814A 0x055A 363 #define REG_USTIME_TSF_8814A 0x055C 364 #define REG_BCN_MAX_ERR_8814A 0x055D 365 #define REG_RXTSF_OFFSET_CCK_8814A 0x055E 366 #define REG_RXTSF_OFFSET_OFDM_8814A 0x055F 367 #define REG_TSFTR_8814A 0x0560 368 #define REG_CTWND_8814A 0x0572 369 #define REG_SECONDARY_CCA_CTRL_8814A 0x0577 // ?????? 370 #define REG_PSTIMER_8814A 0x0580 371 #define REG_TIMER0_8814A 0x0584 372 #define REG_TIMER1_8814A 0x0588 373 #define REG_BCN_PREDL_ITV_8814A 0x058F //Pre download beacon interval 374 #define REG_ACMHWCTRL_8814A 0x05C0 375 376 //----------------------------------------------------- 377 // 378 // 0x0600h ~ 0x07FFh WMAC Configuration 379 // 380 //----------------------------------------------------- 381 #define REG_MAC_CR_8814A 0x0600 382 #define REG_TCR_8814A 0x0604 383 #define REG_RCR_8814A 0x0608 384 #define REG_RX_PKT_LIMIT_8814A 0x060C 385 #define REG_RX_DLK_TIME_8814A 0x060D 386 #define REG_RX_DRVINFO_SZ_8814A 0x060F 387 388 #define REG_MACID_8814A 0x0610 389 #define REG_BSSID_8814A 0x0618 390 #define REG_MAR_8814A 0x0620 391 #define REG_MBIDCAMCFG_8814A 0x0628 392 393 #define REG_USTIME_EDCA_8814A 0x0638 394 #define REG_MAC_SPEC_SIFS_8814A 0x063A 395 #define REG_RESP_SIFP_CCK_8814A 0x063C 396 #define REG_RESP_SIFS_OFDM_8814A 0x063E 397 #define REG_ACKTO_8814A 0x0640 398 #define REG_CTS2TO_8814A 0x0641 399 #define REG_EIFS_8814A 0x0642 400 401 #define REG_NAV_UPPER_8814A 0x0652 // unit of 128 402 #define REG_TRXPTCL_CTL_8814A 0x0668 403 404 // Security 405 #define REG_CAMCMD_8814A 0x0670 406 #define REG_CAMWRITE_8814A 0x0674 407 #define REG_CAMREAD_8814A 0x0678 408 #define REG_CAMDBG_8814A 0x067C 409 #define REG_SECCFG_8814A 0x0680 410 411 // Power 412 #define REG_WOW_CTRL_8814A 0x0690 413 #define REG_PS_RX_INFO_8814A 0x0692 414 #define REG_UAPSD_TID_8814A 0x0693 415 #define REG_WKFMCAM_NUM_8814A 0x0698 416 #define REG_RXFLTMAP0_8814A 0x06A0 417 #define REG_RXFLTMAP1_8814A 0x06A2 418 #define REG_RXFLTMAP2_8814A 0x06A4 419 #define REG_BCN_PSR_RPT_8814A 0x06A8 420 #define REG_BT_COEX_TABLE_8814A 0x06C0 421 #define REG_TX_DATA_RSP_RATE_8814A 0x06DE 422 #define REG_ASSOCIATED_BFMER0_INFO_8814A 0x06E4 423 #define REG_ASSOCIATED_BFMER1_INFO_8814A 0x06EC 424 #define REG_CSI_RPT_PARAM_BW20_8814A 0x06F4 425 #define REG_CSI_RPT_PARAM_BW40_8814A 0x06F8 426 #define REG_CSI_RPT_PARAM_BW80_8814A 0x06FC 427 428 // Hardware Port 2 429 #define REG_MACID1_8814A 0x0700 430 #define REG_BSSID1_8814A 0x0708 431 // Hardware Port 3 432 #define REG_MACID2_8814A 0x1620 433 #define REG_BSSID2_8814A 0x1628 434 // Hardware Port 4 435 #define REG_MACID3_8814A 0x1630 436 #define REG_BSSID3_8814A 0x1638 437 // Hardware Port 5 438 #define REG_MACID4_8814A 0x1640 439 #define REG_BSSID4_8814A 0x1648 440 441 #define REG_ASSOCIATED_BFMEE_SEL_8814A 0x0714 442 #define REG_SND_PTCL_CTRL_8814A 0x0718 443 #define REG_IQ_DUMP_8814A 0x07C0 444 445 /**** page 19 ****/ 446 //TX BeamForming 447 #define REG_BB_TXBF_ANT_SET_BF1 0x19ac 448 #define REG_BB_TXBF_ANT_SET_BF0 0x19b4 449 450 // 0x1200h ~ 0x12FFh DDMA CTRL 451 // 452 //----------------------------------------------------- 453 #define REG_DDMA_CH0SA 0x1200 454 #define REG_DDMA_CH0DA 0x1204 455 #define REG_DDMA_CH0CTRL 0x1208 456 #define REG_DDMA_CH1SA 0x1210 457 #define REG_DDMA_CH1DA 0x1214 458 #define REG_DDMA_CH1CTRL 0x1218 459 #define REG_DDMA_CH2SA 0x1220 460 #define REG_DDMA_CH2DA 0x1224 461 #define REG_DDMA_CH2CTRL 0x1228 462 #define REG_DDMA_CH3SA 0x1230 463 #define REG_DDMA_CH3DA 0x1234 464 #define REG_DDMA_CH3CTRL 0x1238 465 #define REG_DDMA_CH4SA 0x1240 466 #define REG_DDMA_CH4DA 0x1244 467 #define REG_DDMA_CH4CTRL 0x1248 468 #define REG_DDMA_CH5SA 0x1250 469 #define REG_DDMA_CH5DA 0x1254 470 #define REG_DDMA_CH5CTRL 0x1258 471 #define REG_DDMA_INT_MSK 0x12E0 472 #define REG_DDMA_CHSTATUS 0x12E8 473 #define REG_DDMA_CHKSUM 0x12F0 474 #define REG_DDMA_MONITER 0x12FC 475 476 #define DDMA_LEN_MASK 0x0001FFFF 477 #define FW_CHKSUM_DUMMY_SZ 8 478 #define DDMA_CH_CHKSUM_CNT BIT(24) 479 #define DDMA_RST_CHKSUM_STS BIT(25) 480 #define DDMA_MODE_BLOCK_CPU BIT(26) 481 #define DDMA_CHKSUM_FAIL BIT(27) 482 #define DDMA_DA_W_DISABLE BIT(28) 483 #define DDMA_CHKSUM_EN BIT(29) 484 #define DDMA_CH_OWN BIT(31) 485 486 487 //3081 FWDL 488 #define FWDL_EN BIT0 489 #define IMEM_BOOT_DL_RDY BIT1 490 #define IMEM_BOOT_CHKSUM_FAIL BIT2 491 #define IMEM_DL_RDY BIT3 492 #define IMEM_CHKSUM_OK BIT4 493 #define DMEM_DL_RDY BIT5 494 #define DMEM_CHKSUM_OK BIT6 495 #define EMEM_DL_RDY BIT7 496 #define EMEM_CHKSUM_FAIL BIT8 497 #define EMEM_TXBUF_DL_RDY BIT9 498 #define EMEM_TXBUF_CHKSUM_FAIL BIT10 499 #define CPU_CLK_SWITCH_BUSY BIT11 500 #define CPU_CLK_SEL (BIT12|BIT13) 501 #define FWDL_OK BIT14 502 #define FW_INIT_RDY BIT15 503 #define R_EN_BOOT_FLASH BIT20 504 505 #define OCPBASE_IMEM_3081 0x00000000 506 #define OCPBASE_DMEM_3081 0x00200000 507 #define OCPBASE_RPTBUF_3081 0x18660000 508 #define OCPBASE_RXBUF2_3081 0x18680000 509 #define OCPBASE_RXBUF_3081 0x18700000 510 #define OCPBASE_TXBUF_3081 0x18780000 511 512 513 #define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448 514 #define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C 515 516 517 //----------------------------------------------------- 518 // 519 520 521 //----------------------------------------------------- 522 // 523 // Redifine 8192C register definition for compatibility 524 // 525 //----------------------------------------------------- 526 527 // TODO: use these definition when using REG_xxx naming rule. 528 // NOTE: DO NOT Remove these definition. Use later. 529 #define EFUSE_CTRL_8814A REG_EFUSE_CTRL_8814A // E-Fuse Control. 530 #define EFUSE_TEST_8814A REG_LDO_EFUSE_CTRL_8814A // E-Fuse Test. 531 #define MSR_8814A (REG_CR_8814A + 2) // Media Status register 532 #define ISR_8814A REG_HISR0_8814A 533 #define TSFR_8814A REG_TSFTR_8814A // Timing Sync Function Timer Register. 534 535 #define PBP_8814A REG_PBP_8814A 536 537 // Redifine MACID register, to compatible prior ICs. 538 #define IDR0_8814A REG_MACID_8814A // MAC ID Register, Offset 0x0050-0x0053 539 #define IDR4_8814A (REG_MACID_8814A + 4) // MAC ID Register, Offset 0x0054-0x0055 540 541 542 // 543 // 9. Security Control Registers (Offset: ) 544 // 545 #define RWCAM_8814A REG_CAMCMD_8814A //IN 8190 Data Sheet is called CAMcmd 546 #define WCAMI_8814A REG_CAMWRITE_8814A // Software write CAM input content 547 #define RCAMO_8814A REG_CAMREAD_8814A // Software read/write CAM config 548 #define CAMDBG_8814A REG_CAMDBG_8814A 549 #define SECR_8814A REG_SECCFG_8814A //Security Configuration Register 550 551 552 //---------------------------------------------------------------------------- 553 // 8195 IMR/ISR bits (offset 0xB0, 8bits) 554 //---------------------------------------------------------------------------- 555 #define IMR_DISABLED_8814A 0 556 // IMR DW0(0x00B0-00B3) Bit 0-31 557 #define IMR_TIMER2_8814A BIT31 // Timeout interrupt 2 558 #define IMR_TIMER1_8814A BIT30 // Timeout interrupt 1 559 #define IMR_PSTIMEOUT_8814A BIT29 // Power Save Time Out Interrupt 560 #define IMR_GTINT4_8814A BIT28 // When GTIMER4 expires, this bit is set to 1 561 #define IMR_GTINT3_8814A BIT27 // When GTIMER3 expires, this bit is set to 1 562 #define IMR_TXBCN0ERR_8814A BIT26 // Transmit Beacon0 Error 563 #define IMR_TXBCN0OK_8814A BIT25 // Transmit Beacon0 OK 564 #define IMR_TSF_BIT32_TOGGLE_8814A BIT24 // TSF Timer BIT32 toggle indication interrupt 565 #define IMR_BCNDMAINT0_8814A BIT20 // Beacon DMA Interrupt 0 566 #define IMR_BCNDERR0_8814A BIT16 // Beacon Queue DMA OK0 567 #define IMR_HSISR_IND_ON_INT_8814A BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) 568 #define IMR_BCNDMAINT_E_8814A BIT14 // Beacon DMA Interrupt Extension for Win7 569 #define IMR_ATIMEND_8814A BIT12 // CTWidnow End or ATIM Window End 570 #define IMR_C2HCMD_8814A BIT10 // CPU to Host Command INT Status, Write 1 clear 571 #define IMR_CPWM2_8814A BIT9 // CPU power Mode exchange INT Status, Write 1 clear 572 #define IMR_CPWM_8814A BIT8 // CPU power Mode exchange INT Status, Write 1 clear 573 #define IMR_HIGHDOK_8814A BIT7 // High Queue DMA OK 574 #define IMR_MGNTDOK_8814A BIT6 // Management Queue DMA OK 575 #define IMR_BKDOK_8814A BIT5 // AC_BK DMA OK 576 #define IMR_BEDOK_8814A BIT4 // AC_BE DMA OK 577 #define IMR_VIDOK_8814A BIT3 // AC_VI DMA OK 578 #define IMR_VODOK_8814A BIT2 // AC_VO DMA OK 579 #define IMR_RDU_8814A BIT1 // Rx Descriptor Unavailable 580 #define IMR_ROK_8814A BIT0 // Receive DMA OK 581 582 // IMR DW1(0x00B4-00B7) Bit 0-31 583 #define IMR_MCUERR_8814A BIT28 // Beacon DMA Interrupt 7 584 #define IMR_BCNDMAINT7_8814A BIT27 // Beacon DMA Interrupt 7 585 #define IMR_BCNDMAINT6_8814A BIT26 // Beacon DMA Interrupt 6 586 #define IMR_BCNDMAINT5_8814A BIT25 // Beacon DMA Interrupt 5 587 #define IMR_BCNDMAINT4_8814A BIT24 // Beacon DMA Interrupt 4 588 #define IMR_BCNDMAINT3_8814A BIT23 // Beacon DMA Interrupt 3 589 #define IMR_BCNDMAINT2_8814A BIT22 // Beacon DMA Interrupt 2 590 #define IMR_BCNDMAINT1_8814A BIT21 // Beacon DMA Interrupt 1 591 #define IMR_BCNDOK7_8814A BIT20 // Beacon Queue DMA OK Interrup 7 592 #define IMR_BCNDOK6_8814A BIT19 // Beacon Queue DMA OK Interrup 6 593 #define IMR_BCNDOK5_8814A BIT18 // Beacon Queue DMA OK Interrup 5 594 #define IMR_BCNDOK4_8814A BIT17 // Beacon Queue DMA OK Interrup 4 595 #define IMR_BCNDOK3_8814A BIT16 // Beacon Queue DMA OK Interrup 3 596 #define IMR_BCNDOK2_8814A BIT15 // Beacon Queue DMA OK Interrup 2 597 #define IMR_BCNDOK1_8814A BIT14 // Beacon Queue DMA OK Interrup 1 598 #define IMR_ATIMEND_E_8814A BIT13 // ATIM Window End Extension for Win7 599 #define IMR_TXERR_8814A BIT11 // Tx Error Flag Interrupt Status, write 1 clear. 600 #define IMR_RXERR_8814A BIT10 // Rx Error Flag INT Status, Write 1 clear 601 #define IMR_TXFOVW_8814A BIT9 // Transmit FIFO Overflow 602 #define IMR_RXFOVW_8814A BIT8 // Receive FIFO Overflow 603 604 605 #ifdef CONFIG_PCI_HCI 606 #define IMR_TX_MASK (IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A) 607 608 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A) 609 610 #define RT_AC_INT_MASKS (IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A) 611 #endif 612 613 614 /*=================================================================== 615 ===================================================================== 616 Here the register defines are for 92C. When the define is as same with 92C, 617 we will use the 92C's define for the consistency 618 So the following defines for 92C is not entire!!!!!! 619 ===================================================================== 620 =====================================================================*/ 621 622 623 //----------------------------------------------------- 624 // 625 // 0xFE00h ~ 0xFE55h USB Configuration 626 // 627 //----------------------------------------------------- 628 629 //2 Special Option 630 #define USB_AGG_EN_8814A BIT(7) 631 #define REG_USB_HRPWM_U3 0xF052 632 633 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A 2048-1 //20130415 KaiYuan add for 8814 634 635 #define MACID_NUM_8814A 128 636 #define CAM_ENTRY_NUM_8814A 64 637 638 #endif //__RTL8814A_SPEC_H__ 639