1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #ifndef __HAL_COMMON_H__
21 #define __HAL_COMMON_H__
22
23 #include "HalVerDef.h"
24 #include "hal_pg.h"
25 #include "hal_phy.h"
26 #include "hal_phy_reg.h"
27 #include "hal_com_reg.h"
28 #include "hal_com_phycfg.h"
29
30 /*------------------------------ Tx Desc definition Macro ------------------------*/
31 //#pragma mark -- Tx Desc related definition. --
32 //----------------------------------------------------------------------------
33 //-----------------------------------------------------------
34 // Rate
35 //-----------------------------------------------------------
36 // CCK Rates, TxHT = 0
37 #define DESC_RATE1M 0x00
38 #define DESC_RATE2M 0x01
39 #define DESC_RATE5_5M 0x02
40 #define DESC_RATE11M 0x03
41
42 // OFDM Rates, TxHT = 0
43 #define DESC_RATE6M 0x04
44 #define DESC_RATE9M 0x05
45 #define DESC_RATE12M 0x06
46 #define DESC_RATE18M 0x07
47 #define DESC_RATE24M 0x08
48 #define DESC_RATE36M 0x09
49 #define DESC_RATE48M 0x0a
50 #define DESC_RATE54M 0x0b
51
52 // MCS Rates, TxHT = 1
53 #define DESC_RATEMCS0 0x0c
54 #define DESC_RATEMCS1 0x0d
55 #define DESC_RATEMCS2 0x0e
56 #define DESC_RATEMCS3 0x0f
57 #define DESC_RATEMCS4 0x10
58 #define DESC_RATEMCS5 0x11
59 #define DESC_RATEMCS6 0x12
60 #define DESC_RATEMCS7 0x13
61 #define DESC_RATEMCS8 0x14
62 #define DESC_RATEMCS9 0x15
63 #define DESC_RATEMCS10 0x16
64 #define DESC_RATEMCS11 0x17
65 #define DESC_RATEMCS12 0x18
66 #define DESC_RATEMCS13 0x19
67 #define DESC_RATEMCS14 0x1a
68 #define DESC_RATEMCS15 0x1b
69 #define DESC_RATEMCS16 0x1C
70 #define DESC_RATEMCS17 0x1D
71 #define DESC_RATEMCS18 0x1E
72 #define DESC_RATEMCS19 0x1F
73 #define DESC_RATEMCS20 0x20
74 #define DESC_RATEMCS21 0x21
75 #define DESC_RATEMCS22 0x22
76 #define DESC_RATEMCS23 0x23
77 #define DESC_RATEMCS24 0x24
78 #define DESC_RATEMCS25 0x25
79 #define DESC_RATEMCS26 0x26
80 #define DESC_RATEMCS27 0x27
81 #define DESC_RATEMCS28 0x28
82 #define DESC_RATEMCS29 0x29
83 #define DESC_RATEMCS30 0x2A
84 #define DESC_RATEMCS31 0x2B
85 #define DESC_RATEVHTSS1MCS0 0x2C
86 #define DESC_RATEVHTSS1MCS1 0x2D
87 #define DESC_RATEVHTSS1MCS2 0x2E
88 #define DESC_RATEVHTSS1MCS3 0x2F
89 #define DESC_RATEVHTSS1MCS4 0x30
90 #define DESC_RATEVHTSS1MCS5 0x31
91 #define DESC_RATEVHTSS1MCS6 0x32
92 #define DESC_RATEVHTSS1MCS7 0x33
93 #define DESC_RATEVHTSS1MCS8 0x34
94 #define DESC_RATEVHTSS1MCS9 0x35
95 #define DESC_RATEVHTSS2MCS0 0x36
96 #define DESC_RATEVHTSS2MCS1 0x37
97 #define DESC_RATEVHTSS2MCS2 0x38
98 #define DESC_RATEVHTSS2MCS3 0x39
99 #define DESC_RATEVHTSS2MCS4 0x3A
100 #define DESC_RATEVHTSS2MCS5 0x3B
101 #define DESC_RATEVHTSS2MCS6 0x3C
102 #define DESC_RATEVHTSS2MCS7 0x3D
103 #define DESC_RATEVHTSS2MCS8 0x3E
104 #define DESC_RATEVHTSS2MCS9 0x3F
105 #define DESC_RATEVHTSS3MCS0 0x40
106 #define DESC_RATEVHTSS3MCS1 0x41
107 #define DESC_RATEVHTSS3MCS2 0x42
108 #define DESC_RATEVHTSS3MCS3 0x43
109 #define DESC_RATEVHTSS3MCS4 0x44
110 #define DESC_RATEVHTSS3MCS5 0x45
111 #define DESC_RATEVHTSS3MCS6 0x46
112 #define DESC_RATEVHTSS3MCS7 0x47
113 #define DESC_RATEVHTSS3MCS8 0x48
114 #define DESC_RATEVHTSS3MCS9 0x49
115 #define DESC_RATEVHTSS4MCS0 0x4A
116 #define DESC_RATEVHTSS4MCS1 0x4B
117 #define DESC_RATEVHTSS4MCS2 0x4C
118 #define DESC_RATEVHTSS4MCS3 0x4D
119 #define DESC_RATEVHTSS4MCS4 0x4E
120 #define DESC_RATEVHTSS4MCS5 0x4F
121 #define DESC_RATEVHTSS4MCS6 0x50
122 #define DESC_RATEVHTSS4MCS7 0x51
123 #define DESC_RATEVHTSS4MCS8 0x52
124 #define DESC_RATEVHTSS4MCS9 0x53
125
126 #define HDATA_RATE(rate)\
127 (rate==DESC_RATE1M)?"CCK_1M":\
128 (rate==DESC_RATE2M)?"CCK_2M":\
129 (rate==DESC_RATE5_5M)?"CCK5_5M":\
130 (rate==DESC_RATE11M)?"CCK_11M":\
131 (rate==DESC_RATE6M)?"OFDM_6M":\
132 (rate==DESC_RATE9M)?"OFDM_9M":\
133 (rate==DESC_RATE12M)?"OFDM_12M":\
134 (rate==DESC_RATE18M)?"OFDM_18M":\
135 (rate==DESC_RATE24M)?"OFDM_24M":\
136 (rate==DESC_RATE36M)?"OFDM_36M":\
137 (rate==DESC_RATE48M)?"OFDM_48M":\
138 (rate==DESC_RATE54M)?"OFDM_54M":\
139 (rate==DESC_RATEMCS0)?"MCS0":\
140 (rate==DESC_RATEMCS1)?"MCS1":\
141 (rate==DESC_RATEMCS2)?"MCS2":\
142 (rate==DESC_RATEMCS3)?"MCS3":\
143 (rate==DESC_RATEMCS4)?"MCS4":\
144 (rate==DESC_RATEMCS5)?"MCS5":\
145 (rate==DESC_RATEMCS6)?"MCS6":\
146 (rate==DESC_RATEMCS7)?"MCS7":\
147 (rate==DESC_RATEMCS8)?"MCS8":\
148 (rate==DESC_RATEMCS9)?"MCS9":\
149 (rate==DESC_RATEMCS10)?"MCS10":\
150 (rate==DESC_RATEMCS11)?"MCS11":\
151 (rate==DESC_RATEMCS12)?"MCS12":\
152 (rate==DESC_RATEMCS13)?"MCS13":\
153 (rate==DESC_RATEMCS14)?"MCS14":\
154 (rate==DESC_RATEMCS15)?"MCS15":\
155 (rate==DESC_RATEVHTSS1MCS0)?"VHTSS1MCS0":\
156 (rate==DESC_RATEVHTSS1MCS1)?"VHTSS1MCS1":\
157 (rate==DESC_RATEVHTSS1MCS2)?"VHTSS1MCS2":\
158 (rate==DESC_RATEVHTSS1MCS3)?"VHTSS1MCS3":\
159 (rate==DESC_RATEVHTSS1MCS4)?"VHTSS1MCS4":\
160 (rate==DESC_RATEVHTSS1MCS5)?"VHTSS1MCS5":\
161 (rate==DESC_RATEVHTSS1MCS6)?"VHTSS1MCS6":\
162 (rate==DESC_RATEVHTSS1MCS7)?"VHTSS1MCS7":\
163 (rate==DESC_RATEVHTSS1MCS8)?"VHTSS1MCS8":\
164 (rate==DESC_RATEVHTSS1MCS9)?"VHTSS1MCS9":\
165 (rate==DESC_RATEVHTSS2MCS0)?"VHTSS2MCS0":\
166 (rate==DESC_RATEVHTSS2MCS1)?"VHTSS2MCS1":\
167 (rate==DESC_RATEVHTSS2MCS2)?"VHTSS2MCS2":\
168 (rate==DESC_RATEVHTSS2MCS3)?"VHTSS2MCS3":\
169 (rate==DESC_RATEVHTSS2MCS4)?"VHTSS2MCS4":\
170 (rate==DESC_RATEVHTSS2MCS5)?"VHTSS2MCS5":\
171 (rate==DESC_RATEVHTSS2MCS6)?"VHTSS2MCS6":\
172 (rate==DESC_RATEVHTSS2MCS7)?"VHTSS2MCS7":\
173 (rate==DESC_RATEVHTSS2MCS8)?"VHTSS2MCS8":\
174 (rate==DESC_RATEVHTSS2MCS9)?"VHTSS2MCS9":"UNKNOW"
175
176
177 enum{
178 UP_LINK,
179 DOWN_LINK,
180 BI_LINK,
181 };
182 typedef enum _RT_MEDIA_STATUS {
183 RT_MEDIA_DISCONNECT = 0,
184 RT_MEDIA_CONNECT = 1
185 } RT_MEDIA_STATUS;
186
187 #define MAX_DLFW_PAGE_SIZE 4096 // @ page : 4k bytes
188 typedef enum _FIRMWARE_SOURCE {
189 FW_SOURCE_IMG_FILE = 0,
190 FW_SOURCE_HEADER_FILE = 1, //from header file
191 } FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
192
193 //
194 // Queue Select Value in TxDesc
195 //
196 #define QSLT_BK 0x2//0x01
197 #define QSLT_BE 0x0
198 #define QSLT_VI 0x5//0x4
199 #define QSLT_VO 0x7//0x6
200 #define QSLT_BEACON 0x10
201 #define QSLT_HIGH 0x11
202 #define QSLT_MGNT 0x12
203 #define QSLT_CMD 0x13
204
205 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
206 //#define MAX_TX_QUEUE 9
207
208 #define TX_SELE_HQ BIT(0) // High Queue
209 #define TX_SELE_LQ BIT(1) // Low Queue
210 #define TX_SELE_NQ BIT(2) // Normal Queue
211 #define TX_SELE_EQ BIT(3) // Extern Queue
212
213 #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
214 #define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len)&0xFF ? 1:0))
215 #define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0))
216 #define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0))
217
218 struct dbg_rx_counter
219 {
220 u32 rx_pkt_ok;
221 u32 rx_pkt_crc_error;
222 u32 rx_pkt_drop;
223 u32 rx_ofdm_fa;
224 u32 rx_cck_fa;
225 u32 rx_ht_fa;
226 };
227 void rtw_dump_mac_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
228 void rtw_dump_phy_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
229 void rtw_reset_mac_rx_counters(_adapter* padapter);
230 void rtw_reset_phy_rx_counters(_adapter* padapter);
231
232 #ifdef DBG_RX_COUNTER_DUMP
233 #define DUMP_DRV_RX_COUNTER BIT0
234 #define DUMP_MAC_RX_COUNTER BIT1
235 #define DUMP_PHY_RX_COUNTER BIT2
236 #define DUMP_DRV_TRX_COUNTER_DATA BIT3
237
238 void rtw_dump_phy_rxcnts_preprocess(_adapter* padapter,u8 rx_cnt_mode);
239 void rtw_dump_rx_counters(_adapter* padapter);
240 #endif
241
242 void dump_chip_info(HAL_VERSION ChipVersion);
243 void rtw_hal_config_rftype(PADAPTER padapter);
244
245 u8 //return the final channel plan decision
246 hal_com_config_channel_plan(
247 IN PADAPTER padapter,
248 IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
249 IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
250 IN u8 def_channel_plan, //channel plan used when the former two is invalid
251 IN BOOLEAN AutoLoadFail
252 );
253
254 int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
255
256 BOOLEAN
257 HAL_IsLegalChannel(
258 IN PADAPTER Adapter,
259 IN u32 Channel
260 );
261
262 u8 MRateToHwRate(u8 rate);
263
264 u8 HwRateToMRate(u8 rate);
265
266 void HalSetBrateCfg(
267 IN PADAPTER Adapter,
268 IN u8 *mBratesOS,
269 OUT u16 *pBrateCfg);
270
271 BOOLEAN
272 Hal_MappingOutPipe(
273 IN PADAPTER pAdapter,
274 IN u8 NumOutPipe
275 );
276
277 void hal_init_macaddr(_adapter *adapter);
278
279 void rtw_init_hal_com_default_value(PADAPTER Adapter);
280
281 void c2h_evt_clear(_adapter *adapter);
282 s32 c2h_evt_read(_adapter *adapter, u8 *buf);
283 s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
284
285 u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta);
286 u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type);
287 void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta);
288
289 void hw_var_port_switch(_adapter *adapter);
290
291 void SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
292 void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
293 void rtw_hal_check_rxfifo_full(_adapter *adapter);
294
295 u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
296 u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
297
298 BOOLEAN
299 eqNByte(
300 u8* str1,
301 u8* str2,
302 u32 num
303 );
304
305 BOOLEAN
306 IsHexDigit(
307 IN char chTmp
308 );
309
310 u32
311 MapCharToHexDigit(
312 IN char chTmp
313 );
314
315 BOOLEAN
316 GetHexValueFromString(
317 IN char* szStr,
318 IN OUT u32* pu4bVal,
319 IN OUT u32* pu4bMove
320 );
321
322 BOOLEAN
323 GetFractionValueFromString(
324 IN char* szStr,
325 IN OUT u8* pInteger,
326 IN OUT u8* pFraction,
327 IN OUT u32* pu4bMove
328 );
329
330 BOOLEAN
331 IsCommentString(
332 IN char* szStr
333 );
334
335 BOOLEAN
336 ParseQualifiedString(
337 IN char* In,
338 IN OUT u32* Start,
339 OUT char* Out,
340 IN char LeftQualifier,
341 IN char RightQualifier
342 );
343
344 BOOLEAN
345 GetU1ByteIntegerFromStringInDecimal(
346 IN char* Str,
347 IN OUT u8* pInt
348 );
349
350 BOOLEAN
351 isAllSpaceOrTab(
352 u8* data,
353 u8 size
354 );
355
356 void linked_info_dump(_adapter *padapter,u8 benable);
357 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
358 void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
359 void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
360 void rtw_dump_raw_rssi_info(_adapter *padapter);
361 #endif
362
363 #define HWSET_MAX_SIZE 512
364 #ifdef CONFIG_EFUSE_CONFIG_FILE
365 #define EFUSE_FILE_COLUMN_NUM 16
366 u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
367 u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
368 #endif /* CONFIG_EFUSE_CONFIG_FILE */
369
370 int check_phy_efuse_tx_power_info_valid(PADAPTER padapter);
371 int hal_efuse_macaddr_offset(_adapter *adapter);
372 int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
373
374 #ifdef CONFIG_RF_GAIN_OFFSET
375 void rtw_bb_rf_gain_offset(_adapter *padapter);
376 #endif //CONFIG_RF_GAIN_OFFSET
377
378 void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
379 u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel);
380 void GetHalODMVar(
381 PADAPTER Adapter,
382 HAL_ODM_VARIABLE eVariable,
383 PVOID pValue1,
384 PVOID pValue2);
385 void SetHalODMVar(
386 PADAPTER Adapter,
387 HAL_ODM_VARIABLE eVariable,
388 PVOID pValue1,
389 BOOLEAN bSet);
390
391 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
392 struct noise_info
393 {
394 u8 bPauseDIG;
395 u8 IGIValue;
396 u32 max_time;//ms
397 u8 chan;
398 };
399 #endif
400
401 void rtw_get_noise(_adapter* padapter);
402
403 void rtw_hal_set_fw_rsvd_page(_adapter* adapter, bool finished);
404
405 #ifdef CONFIG_GPIO_API
406 u8 rtw_hal_get_gpio(_adapter* adapter, u8 gpio_num);
407 int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, bool isHigh);
408 int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, bool isOutput);
409 int rtw_hal_register_gpio_interrupt(_adapter* adapter, int gpio_num, void(*callback)(u8 level));
410 int rtw_hal_disable_gpio_interrupt(_adapter* adapter, int gpio_num);
411 #endif
412
413 #ifdef CONFIG_GPIO_WAKEUP
414 void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
415 #endif
416
417 typedef enum _HAL_PHYDM_OPS {
418 HAL_PHYDM_DIS_ALL_FUNC,
419 HAL_PHYDM_FUNC_SET,
420 HAL_PHYDM_FUNC_CLR,
421 HAL_PHYDM_ABILITY_BK,
422 HAL_PHYDM_ABILITY_RESTORE,
423 HAL_PHYDM_ABILITY_SET,
424 HAL_PHYDM_ABILITY_GET,
425 } HAL_PHYDM_OPS;
426
427
428 #define DYNAMIC_FUNC_DISABLE (0x0)
429 u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
430
431 #define rtw_phydm_func_disable_all(adapter) \
432 rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
433
434 #define rtw_phydm_func_for_offchannel(adapter) \
435 do { \
436 rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
437 if (rtw_odm_adaptivity_needed(adapter)) \
438 rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
439 } while (0)
440
441 #define rtw_phydm_func_set(adapter, ability) \
442 rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability)
443
444 #define rtw_phydm_func_clr(adapter, ability) \
445 rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
446
447 #define rtw_phydm_ability_backup(adapter) \
448 rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
449
450 #define rtw_phydm_ability_restore(adapter) \
451 rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
452
453 #define rtw_phydm_ability_set(adapter, ability) \
454 rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, 0)
455
rtw_phydm_ability_get(_adapter * adapter)456 static inline u32 rtw_phydm_ability_get(_adapter *adapter)
457 {
458 return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
459 }
460
461 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
462 extern char *rtw_phy_file_path;
463 extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
464 #define GetLineFromBuffer(buffer) strsep(&buffer, "\n")
465 #endif
466
467 #ifdef CONFIG_FW_C2H_DEBUG
468 void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len);
469 #endif
470 /*CONFIG_FW_C2H_DEBUG*/
471
472 void update_IOT_info(_adapter *padapter);
473
474 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
475 void rtw_acs_start(_adapter *padapter, bool bStart);
476 #endif
477
478 #endif //__HAL_COMMON_H__
479
480