1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __INC_HAL8723BPHYREG_H__ 21 #define __INC_HAL8723BPHYREG_H__ 22 23 #define rSYM_WLBT_PAPE_SEL 0x64 24 // 25 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 26 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 27 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 28 // 3. RF register 0x00-2E 29 // 4. Bit Mask for BB/RF register 30 // 5. Other defintion for BB/RF R/W 31 // 32 33 34 // 35 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 36 // 1. Page1(0x100) 37 // 38 #define rPMAC_Reset 0x100 39 #define rPMAC_TxStart 0x104 40 #define rPMAC_TxLegacySIG 0x108 41 #define rPMAC_TxHTSIG1 0x10c 42 #define rPMAC_TxHTSIG2 0x110 43 #define rPMAC_PHYDebug 0x114 44 #define rPMAC_TxPacketNum 0x118 45 #define rPMAC_TxIdle 0x11c 46 #define rPMAC_TxMACHeader0 0x120 47 #define rPMAC_TxMACHeader1 0x124 48 #define rPMAC_TxMACHeader2 0x128 49 #define rPMAC_TxMACHeader3 0x12c 50 #define rPMAC_TxMACHeader4 0x130 51 #define rPMAC_TxMACHeader5 0x134 52 #define rPMAC_TxDataType 0x138 53 #define rPMAC_TxRandomSeed 0x13c 54 #define rPMAC_CCKPLCPPreamble 0x140 55 #define rPMAC_CCKPLCPHeader 0x144 56 #define rPMAC_CCKCRC16 0x148 57 #define rPMAC_OFDMRxCRC32OK 0x170 58 #define rPMAC_OFDMRxCRC32Er 0x174 59 #define rPMAC_OFDMRxParityEr 0x178 60 #define rPMAC_OFDMRxCRC8Er 0x17c 61 #define rPMAC_CCKCRxRC16Er 0x180 62 #define rPMAC_CCKCRxRC32Er 0x184 63 #define rPMAC_CCKCRxRC32OK 0x188 64 #define rPMAC_TxStatus 0x18c 65 66 // 67 // 2. Page2(0x200) 68 // 69 // The following two definition are only used for USB interface. 70 #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. 71 #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. 72 73 // 74 // 3. Page8(0x800) 75 // 76 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? 77 78 #define rFPGA0_TxInfo 0x804 // Status report?? 79 #define rFPGA0_PSDFunction 0x808 80 81 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? 82 83 #define rFPGA0_RFTiming1 0x810 // Useless now 84 #define rFPGA0_RFTiming2 0x814 85 86 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register 87 #define rFPGA0_XA_HSSIParameter2 0x824 88 #define rFPGA0_XB_HSSIParameter1 0x828 89 #define rFPGA0_XB_HSSIParameter2 0x82c 90 #define rTxAGC_B_Rate18_06 0x830 91 #define rTxAGC_B_Rate54_24 0x834 92 #define rTxAGC_B_CCK1_55_Mcs32 0x838 93 #define rTxAGC_B_Mcs03_Mcs00 0x83c 94 95 #define rTxAGC_B_Mcs07_Mcs04 0x848 96 #define rTxAGC_B_Mcs11_Mcs08 0x84c 97 98 #define rFPGA0_XA_LSSIParameter 0x840 99 #define rFPGA0_XB_LSSIParameter 0x844 100 101 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now 102 #define rFPGA0_RFSleepUpParameter 0x854 103 104 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch 105 #define rFPGA0_XCD_SwitchControl 0x85c 106 107 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch 108 #define rFPGA0_XB_RFInterfaceOE 0x864 109 110 #define rTxAGC_B_Mcs15_Mcs12 0x868 111 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 112 113 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control 114 #define rFPGA0_XCD_RFInterfaceSW 0x874 115 116 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter 117 #define rFPGA0_XCD_RFParameter 0x87c 118 119 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? 120 #define rFPGA0_AnalogParameter2 0x884 121 #define rFPGA0_AnalogParameter3 0x888 // Useless now 122 #define rFPGA0_AnalogParameter4 0x88c 123 124 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback 125 #define rFPGA0_XB_LSSIReadBack 0x8a4 126 #define rFPGA0_XC_LSSIReadBack 0x8a8 127 #define rFPGA0_XD_LSSIReadBack 0x8ac 128 129 #define rFPGA0_PSDReport 0x8b4 // Useless now 130 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback 131 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback 132 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value 133 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now 134 135 // 136 // 4. Page9(0x900) 137 // 138 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? 139 #define rFPGA1_TxBlock 0x904 // Useless now 140 #define rFPGA1_DebugSelect 0x908 // Useless now 141 #define rFPGA1_TxInfo 0x90c // Useless now // Status report?? 142 #define rDPDT_control 0x92c 143 #define rfe_ctrl_anta_src 0x930 144 #define rS0S1_PathSwitch 0x948 145 146 // 147 // 5. PageA(0xA00) 148 // 149 // Set Control channel to upper or lower. These settings are required only for 40MHz 150 #define rCCK0_System 0xa00 151 152 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI 153 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain 154 155 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series 156 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC 157 158 #define rCCK0_RxHP 0xa14 159 160 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold 161 #define rCCK0_DSPParameter2 0xa1c //SQ threshold 162 163 #define rCCK0_TxFilter1 0xa20 164 #define rCCK0_TxFilter2 0xa24 165 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 166 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report 167 #define rCCK0_TRSSIReport 0xa50 168 #define rCCK0_RxReport 0xa54 //0xa57 169 #define rCCK0_FACounterLower 0xa5c //0xa5b 170 #define rCCK0_FACounterUpper 0xa58 //0xa5c 171 172 // 173 // PageB(0xB00) 174 // 175 #define rPdp_AntA 0xb00 176 #define rPdp_AntA_4 0xb04 177 #define rPdp_AntA_8 0xb08 178 #define rPdp_AntA_C 0xb0c 179 #define rPdp_AntA_10 0xb10 180 #define rPdp_AntA_14 0xb14 181 #define rPdp_AntA_18 0xb18 182 #define rPdp_AntA_1C 0xb1c 183 #define rPdp_AntA_20 0xb20 184 #define rPdp_AntA_24 0xb24 185 186 #define rConfig_Pmpd_AntA 0xb28 187 #define rConfig_ram64x16 0xb2c 188 189 #define rBndA 0xb30 190 #define rHssiPar 0xb34 191 192 #define rConfig_AntA 0xb68 193 #define rConfig_AntB 0xb6c 194 195 #define rPdp_AntB 0xb70 196 #define rPdp_AntB_4 0xb74 197 #define rPdp_AntB_8 0xb78 198 #define rPdp_AntB_C 0xb7c 199 #define rPdp_AntB_10 0xb80 200 #define rPdp_AntB_14 0xb84 201 #define rPdp_AntB_18 0xb88 202 #define rPdp_AntB_1C 0xb8c 203 #define rPdp_AntB_20 0xb90 204 #define rPdp_AntB_24 0xb94 205 206 #define rConfig_Pmpd_AntB 0xb98 207 208 #define rBndB 0xba0 209 210 #define rAPK 0xbd8 211 #define rPm_Rx0_AntA 0xbdc 212 #define rPm_Rx1_AntA 0xbe0 213 #define rPm_Rx2_AntA 0xbe4 214 #define rPm_Rx3_AntA 0xbe8 215 #define rPm_Rx0_AntB 0xbec 216 #define rPm_Rx1_AntB 0xbf0 217 #define rPm_Rx2_AntB 0xbf4 218 #define rPm_Rx3_AntB 0xbf8 219 // 220 // 6. PageC(0xC00) 221 // 222 #define rOFDM0_LSTF 0xc00 223 224 #define rOFDM0_TRxPathEnable 0xc04 225 #define rOFDM0_TRMuxPar 0xc08 226 #define rOFDM0_TRSWIsolation 0xc0c 227 228 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter 229 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix 230 #define rOFDM0_XBRxAFE 0xc18 231 #define rOFDM0_XBRxIQImbalance 0xc1c 232 #define rOFDM0_XCRxAFE 0xc20 233 #define rOFDM0_XCRxIQImbalance 0xc24 234 #define rOFDM0_XDRxAFE 0xc28 235 #define rOFDM0_XDRxIQImbalance 0xc2c 236 237 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain 238 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. 239 #define rOFDM0_RxDetector3 0xc38 //Frame Sync. 240 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI 241 242 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path 243 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC 244 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold 245 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA 246 247 #define rOFDM0_XAAGCCore1 0xc50 // DIG 248 #define rOFDM0_XAAGCCore2 0xc54 249 #define rOFDM0_XBAGCCore1 0xc58 250 #define rOFDM0_XBAGCCore2 0xc5c 251 #define rOFDM0_XCAGCCore1 0xc60 252 #define rOFDM0_XCAGCCore2 0xc64 253 #define rOFDM0_XDAGCCore1 0xc68 254 #define rOFDM0_XDAGCCore2 0xc6c 255 256 #define rOFDM0_AGCParameter1 0xc70 257 #define rOFDM0_AGCParameter2 0xc74 258 #define rOFDM0_AGCRSSITable 0xc78 259 #define rOFDM0_HTSTFAGC 0xc7c 260 261 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG 262 #define rOFDM0_XATxAFE 0xc84 263 #define rOFDM0_XBTxIQImbalance 0xc88 264 #define rOFDM0_XBTxAFE 0xc8c 265 #define rOFDM0_XCTxIQImbalance 0xc90 266 #define rOFDM0_XCTxAFE 0xc94 267 #define rOFDM0_XDTxIQImbalance 0xc98 268 #define rOFDM0_XDTxAFE 0xc9c 269 270 #define rOFDM0_RxIQExtAnta 0xca0 271 #define rOFDM0_TxCoeff1 0xca4 272 #define rOFDM0_TxCoeff2 0xca8 273 #define rOFDM0_TxCoeff3 0xcac 274 #define rOFDM0_TxCoeff4 0xcb0 275 #define rOFDM0_TxCoeff5 0xcb4 276 #define rOFDM0_TxCoeff6 0xcb8 277 #define rOFDM0_RxHPParameter 0xce0 278 #define rOFDM0_TxPseudoNoiseWgt 0xce4 279 #define rOFDM0_FrameSync 0xcf0 280 #define rOFDM0_DFSReport 0xcf4 281 282 // 283 // 7. PageD(0xD00) 284 // 285 #define rOFDM1_LSTF 0xd00 286 #define rOFDM1_TRxPathEnable 0xd04 287 288 #define rOFDM1_CFO 0xd08 // No setting now 289 #define rOFDM1_CSI1 0xd10 290 #define rOFDM1_SBD 0xd14 291 #define rOFDM1_CSI2 0xd18 292 #define rOFDM1_CFOTracking 0xd2c 293 #define rOFDM1_TRxMesaure1 0xd34 294 #define rOFDM1_IntfDet 0xd3c 295 #define rOFDM1_PseudoNoiseStateAB 0xd50 296 #define rOFDM1_PseudoNoiseStateCD 0xd54 297 #define rOFDM1_RxPseudoNoiseWgt 0xd58 298 299 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail 300 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail 301 #define rOFDM_PHYCounter3 0xda8 //MCS not support 302 303 #define rOFDM_ShortCFOAB 0xdac // No setting now 304 #define rOFDM_ShortCFOCD 0xdb0 305 #define rOFDM_LongCFOAB 0xdb4 306 #define rOFDM_LongCFOCD 0xdb8 307 #define rOFDM_TailCFOAB 0xdbc 308 #define rOFDM_TailCFOCD 0xdc0 309 #define rOFDM_PWMeasure1 0xdc4 310 #define rOFDM_PWMeasure2 0xdc8 311 #define rOFDM_BWReport 0xdcc 312 #define rOFDM_AGCReport 0xdd0 313 #define rOFDM_RxSNR 0xdd4 314 #define rOFDM_RxEVMCSI 0xdd8 315 #define rOFDM_SIGReport 0xddc 316 317 318 // 319 // 8. PageE(0xE00) 320 // 321 #define rTxAGC_A_Rate18_06 0xe00 322 #define rTxAGC_A_Rate54_24 0xe04 323 #define rTxAGC_A_CCK1_Mcs32 0xe08 324 #define rTxAGC_A_Mcs03_Mcs00 0xe10 325 #define rTxAGC_A_Mcs07_Mcs04 0xe14 326 #define rTxAGC_A_Mcs11_Mcs08 0xe18 327 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 328 329 #define rFPGA0_IQK 0xe28 330 #define rTx_IQK_Tone_A 0xe30 331 #define rRx_IQK_Tone_A 0xe34 332 #define rTx_IQK_PI_A 0xe38 333 #define rRx_IQK_PI_A 0xe3c 334 335 #define rTx_IQK 0xe40 336 #define rRx_IQK 0xe44 337 #define rIQK_AGC_Pts 0xe48 338 #define rIQK_AGC_Rsp 0xe4c 339 #define rTx_IQK_Tone_B 0xe50 340 #define rRx_IQK_Tone_B 0xe54 341 #define rTx_IQK_PI_B 0xe58 342 #define rRx_IQK_PI_B 0xe5c 343 #define rIQK_AGC_Cont 0xe60 344 345 #define rBlue_Tooth 0xe6c 346 #define rRx_Wait_CCA 0xe70 347 #define rTx_CCK_RFON 0xe74 348 #define rTx_CCK_BBON 0xe78 349 #define rTx_OFDM_RFON 0xe7c 350 #define rTx_OFDM_BBON 0xe80 351 #define rTx_To_Rx 0xe84 352 #define rTx_To_Tx 0xe88 353 #define rRx_CCK 0xe8c 354 355 #define rTx_Power_Before_IQK_A 0xe94 356 #define rTx_Power_After_IQK_A 0xe9c 357 358 #define rRx_Power_Before_IQK_A 0xea0 359 #define rRx_Power_Before_IQK_A_2 0xea4 360 #define rRx_Power_After_IQK_A 0xea8 361 #define rRx_Power_After_IQK_A_2 0xeac 362 363 #define rTx_Power_Before_IQK_B 0xeb4 364 #define rTx_Power_After_IQK_B 0xebc 365 366 #define rRx_Power_Before_IQK_B 0xec0 367 #define rRx_Power_Before_IQK_B_2 0xec4 368 #define rRx_Power_After_IQK_B 0xec8 369 #define rRx_Power_After_IQK_B_2 0xecc 370 371 #define rRx_OFDM 0xed0 372 #define rRx_Wait_RIFS 0xed4 373 #define rRx_TO_Rx 0xed8 374 #define rStandby 0xedc 375 #define rSleep 0xee0 376 #define rPMPD_ANAEN 0xeec 377 378 // 379 // 7. RF Register 0x00-0x2E (RF 8256) 380 // RF-0222D 0x00-3F 381 // 382 //Zebra1 383 #define rZebra1_HSSIEnable 0x0 // Useless now 384 #define rZebra1_TRxEnable1 0x1 385 #define rZebra1_TRxEnable2 0x2 386 #define rZebra1_AGC 0x4 387 #define rZebra1_ChargePump 0x5 388 #define rZebra1_Channel 0x7 // RF channel switch 389 390 //#endif 391 #define rZebra1_TxGain 0x8 // Useless now 392 #define rZebra1_TxLPF 0x9 393 #define rZebra1_RxLPF 0xb 394 #define rZebra1_RxHPFCorner 0xc 395 396 //Zebra4 397 #define rGlobalCtrl 0 // Useless now 398 #define rRTL8256_TxLPF 19 399 #define rRTL8256_RxLPF 11 400 401 //RTL8258 402 #define rRTL8258_TxLPF 0x11 // Useless now 403 #define rRTL8258_RxLPF 0x13 404 #define rRTL8258_RSSILPF 0xa 405 406 // 407 // RL6052 Register definition 408 // 409 #define RF_AC 0x00 // 410 411 #define RF_IQADJ_G1 0x01 // 412 #define RF_IQADJ_G2 0x02 // 413 #define RF_BS_PA_APSET_G1_G4 0x03 414 #define RF_BS_PA_APSET_G5_G8 0x04 415 #define RF_POW_TRSW 0x05 // 416 417 #define RF_GAIN_RX 0x06 // 418 #define RF_GAIN_TX 0x07 // 419 420 #define RF_TXM_IDAC 0x08 // 421 #define RF_IPA_G 0x09 // 422 #define RF_TXBIAS_G 0x0A 423 #define RF_TXPA_AG 0x0B 424 #define RF_IPA_A 0x0C // 425 #define RF_TXBIAS_A 0x0D 426 #define RF_BS_PA_APSET_G9_G11 0x0E 427 #define RF_BS_IQGEN 0x0F // 428 429 #define RF_MODE1 0x10 // 430 #define RF_MODE2 0x11 // 431 432 #define RF_RX_AGC_HP 0x12 // 433 #define RF_TX_AGC 0x13 // 434 #define RF_BIAS 0x14 // 435 #define RF_IPA 0x15 // 436 #define RF_TXBIAS 0x16 // 437 #define RF_POW_ABILITY 0x17 // 438 #define RF_MODE_AG 0x18 // 439 #define rRfChannel 0x18 // RF channel and BW switch 440 #define RF_CHNLBW 0x18 // RF channel and BW switch 441 #define RF_TOP 0x19 // 442 443 #define RF_RX_G1 0x1A // 444 #define RF_RX_G2 0x1B // 445 446 #define RF_RX_BB2 0x1C // 447 #define RF_RX_BB1 0x1D // 448 449 #define RF_RCK1 0x1E // 450 #define RF_RCK2 0x1F // 451 452 #define RF_TX_G1 0x20 // 453 #define RF_TX_G2 0x21 // 454 #define RF_TX_G3 0x22 // 455 456 #define RF_TX_BB1 0x23 // 457 458 #define RF_T_METER 0x24 // 459 460 #define RF_SYN_G1 0x25 // RF TX Power control 461 #define RF_SYN_G2 0x26 // RF TX Power control 462 #define RF_SYN_G3 0x27 // RF TX Power control 463 #define RF_SYN_G4 0x28 // RF TX Power control 464 #define RF_SYN_G5 0x29 // RF TX Power control 465 #define RF_SYN_G6 0x2A // RF TX Power control 466 #define RF_SYN_G7 0x2B // RF TX Power control 467 #define RF_SYN_G8 0x2C // RF TX Power control 468 469 #define RF_RCK_OS 0x30 // RF TX PA control 470 471 #define RF_TXPA_G1 0x31 // RF TX PA control 472 #define RF_TXPA_G2 0x32 // RF TX PA control 473 #define RF_TXPA_G3 0x33 // RF TX PA control 474 #define RF_TX_BIAS_A 0x35 475 #define RF_TX_BIAS_D 0x36 476 #define RF_LOBF_9 0x38 477 #define RF_RXRF_A3 0x3C // 478 #define RF_TRSW 0x3F 479 480 #define RF_TXRF_A2 0x41 481 #define RF_TXPA_G4 0x46 482 #define RF_TXPA_A4 0x4B 483 #define RF_0x52 0x52 484 #define RF_WE_LUT 0xEF 485 #define RF_S0S1 0xB0 486 487 // 488 //Bit Mask 489 // 490 // 1. Page1(0x100) 491 #define bBBResetB 0x100 // Useless now? 492 #define bGlobalResetB 0x200 493 #define bOFDMTxStart 0x4 494 #define bCCKTxStart 0x8 495 #define bCRC32Debug 0x100 496 #define bPMACLoopback 0x10 497 #define bTxLSIG 0xffffff 498 #define bOFDMTxRate 0xf 499 #define bOFDMTxReserved 0x10 500 #define bOFDMTxLength 0x1ffe0 501 #define bOFDMTxParity 0x20000 502 #define bTxHTSIG1 0xffffff 503 #define bTxHTMCSRate 0x7f 504 #define bTxHTBW 0x80 505 #define bTxHTLength 0xffff00 506 #define bTxHTSIG2 0xffffff 507 #define bTxHTSmoothing 0x1 508 #define bTxHTSounding 0x2 509 #define bTxHTReserved 0x4 510 #define bTxHTAggreation 0x8 511 #define bTxHTSTBC 0x30 512 #define bTxHTAdvanceCoding 0x40 513 #define bTxHTShortGI 0x80 514 #define bTxHTNumberHT_LTF 0x300 515 #define bTxHTCRC8 0x3fc00 516 #define bCounterReset 0x10000 517 #define bNumOfOFDMTx 0xffff 518 #define bNumOfCCKTx 0xffff0000 519 #define bTxIdleInterval 0xffff 520 #define bOFDMService 0xffff0000 521 #define bTxMACHeader 0xffffffff 522 #define bTxDataInit 0xff 523 #define bTxHTMode 0x100 524 #define bTxDataType 0x30000 525 #define bTxRandomSeed 0xffffffff 526 #define bCCKTxPreamble 0x1 527 #define bCCKTxSFD 0xffff0000 528 #define bCCKTxSIG 0xff 529 #define bCCKTxService 0xff00 530 #define bCCKLengthExt 0x8000 531 #define bCCKTxLength 0xffff0000 532 #define bCCKTxCRC16 0xffff 533 #define bCCKTxStatus 0x1 534 #define bOFDMTxStatus 0x2 535 536 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 537 538 // 2. Page8(0x800) 539 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD 540 #define bJapanMode 0x2 541 #define bCCKTxSC 0x30 542 #define bCCKEn 0x1000000 543 #define bOFDMEn 0x2000000 544 545 #define bOFDMRxADCPhase 0x10000 // Useless now 546 #define bOFDMTxDACPhase 0x40000 547 #define bXATxAGC 0x3f 548 549 #define bAntennaSelect 0x0300 550 551 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage 552 #define bXCTxAGC 0xf000 553 #define bXDTxAGC 0xf0000 554 555 #define bPAStart 0xf0000000 // Useless now 556 #define bTRStart 0x00f00000 557 #define bRFStart 0x0000f000 558 #define bBBStart 0x000000f0 559 #define bBBCCKStart 0x0000000f 560 #define bPAEnd 0xf //Reg0x814 561 #define bTREnd 0x0f000000 562 #define bRFEnd 0x000f0000 563 #define bCCAMask 0x000000f0 //T2R 564 #define bR2RCCAMask 0x00000f00 565 #define bHSSI_R2TDelay 0xf8000000 566 #define bHSSI_T2RDelay 0xf80000 567 #define bContTxHSSI 0x400 //chane gain at continue Tx 568 #define bIGFromCCK 0x200 569 #define bAGCAddress 0x3f 570 #define bRxHPTx 0x7000 571 #define bRxHPT2R 0x38000 572 #define bRxHPCCKIni 0xc0000 573 #define bAGCTxCode 0xc00000 574 #define bAGCRxCode 0x300000 575 576 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 577 #define b3WireAddressLength 0x400 578 579 #define b3WireRFPowerDown 0x1 // Useless now 580 //#define bHWSISelect 0x8 581 #define b5GPAPEPolarity 0x40000000 582 #define b2GPAPEPolarity 0x80000000 583 #define bRFSW_TxDefaultAnt 0x3 584 #define bRFSW_TxOptionAnt 0x30 585 #define bRFSW_RxDefaultAnt 0x300 586 #define bRFSW_RxOptionAnt 0x3000 587 #define bRFSI_3WireData 0x1 588 #define bRFSI_3WireClock 0x2 589 #define bRFSI_3WireLoad 0x4 590 #define bRFSI_3WireRW 0x8 591 #define bRFSI_3Wire 0xf 592 593 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW 594 595 #define bRFSI_TRSW 0x20 // Useless now 596 #define bRFSI_TRSWB 0x40 597 #define bRFSI_ANTSW 0x100 598 #define bRFSI_ANTSWB 0x200 599 #define bRFSI_PAPE 0x400 600 #define bRFSI_PAPE5G 0x800 601 #define bBandSelect 0x1 602 #define bHTSIG2_GI 0x80 603 #define bHTSIG2_Smoothing 0x01 604 #define bHTSIG2_Sounding 0x02 605 #define bHTSIG2_Aggreaton 0x08 606 #define bHTSIG2_STBC 0x30 607 #define bHTSIG2_AdvCoding 0x40 608 #define bHTSIG2_NumOfHTLTF 0x300 609 #define bHTSIG2_CRC8 0x3fc 610 #define bHTSIG1_MCS 0x7f 611 #define bHTSIG1_BandWidth 0x80 612 #define bHTSIG1_HTLength 0xffff 613 #define bLSIG_Rate 0xf 614 #define bLSIG_Reserved 0x10 615 #define bLSIG_Length 0x1fffe 616 #define bLSIG_Parity 0x20 617 #define bCCKRxPhase 0x4 618 619 #define bLSSIReadAddress 0x7f800000 // T65 RF 620 621 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal 622 623 #define bLSSIReadBackData 0xfffff // T65 RF 624 625 #define bLSSIReadOKFlag 0x1000 // Useless now 626 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz 627 #define bRegulator0Standby 0x1 628 #define bRegulatorPLLStandby 0x2 629 #define bRegulator1Standby 0x4 630 #define bPLLPowerUp 0x8 631 #define bDPLLPowerUp 0x10 632 #define bDA10PowerUp 0x20 633 #define bAD7PowerUp 0x200 634 #define bDA6PowerUp 0x2000 635 #define bXtalPowerUp 0x4000 636 #define b40MDClkPowerUP 0x8000 637 #define bDA6DebugMode 0x20000 638 #define bDA6Swing 0x380000 639 640 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ 641 642 #define b80MClkDelay 0x18000000 // Useless 643 #define bAFEWatchDogEnable 0x20000000 644 645 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap 646 #define bXtalCap23 0x3 647 #define bXtalCap92x 0x0f000000 648 #define bXtalCap 0x0f000000 649 650 #define bIntDifClkEnable 0x400 // Useless 651 #define bExtSigClkEnable 0x800 652 #define bBandgapMbiasPowerUp 0x10000 653 #define bAD11SHGain 0xc0000 654 #define bAD11InputRange 0x700000 655 #define bAD11OPCurrent 0x3800000 656 #define bIPathLoopback 0x4000000 657 #define bQPathLoopback 0x8000000 658 #define bAFELoopback 0x10000000 659 #define bDA10Swing 0x7e0 660 #define bDA10Reverse 0x800 661 #define bDAClkSource 0x1000 662 #define bAD7InputRange 0x6000 663 #define bAD7Gain 0x38000 664 #define bAD7OutputCMMode 0x40000 665 #define bAD7InputCMMode 0x380000 666 #define bAD7Current 0xc00000 667 #define bRegulatorAdjust 0x7000000 668 #define bAD11PowerUpAtTx 0x1 669 #define bDA10PSAtTx 0x10 670 #define bAD11PowerUpAtRx 0x100 671 #define bDA10PSAtRx 0x1000 672 #define bCCKRxAGCFormat 0x200 673 #define bPSDFFTSamplepPoint 0xc000 674 #define bPSDAverageNum 0x3000 675 #define bIQPathControl 0xc00 676 #define bPSDFreq 0x3ff 677 #define bPSDAntennaPath 0x30 678 #define bPSDIQSwitch 0x40 679 #define bPSDRxTrigger 0x400000 680 #define bPSDTxTrigger 0x80000000 681 #define bPSDSineToneScale 0x7f000000 682 #define bPSDReport 0xffff 683 684 // 3. Page9(0x900) 685 #define bOFDMTxSC 0x30000000 // Useless 686 #define bCCKTxOn 0x1 687 #define bOFDMTxOn 0x2 688 #define bDebugPage 0xfff //reset debug page and also HWord, LWord 689 #define bDebugItem 0xff //reset debug page and LWord 690 #define bAntL 0x10 691 #define bAntNonHT 0x100 692 #define bAntHT1 0x1000 693 #define bAntHT2 0x10000 694 #define bAntHT1S1 0x100000 695 #define bAntNonHTS1 0x1000000 696 697 // 4. PageA(0xA00) 698 #define bCCKBBMode 0x3 // Useless 699 #define bCCKTxPowerSaving 0x80 700 #define bCCKRxPowerSaving 0x40 701 702 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch 703 704 #define bCCKScramble 0x8 // Useless 705 #define bCCKAntDiversity 0x8000 706 #define bCCKCarrierRecovery 0x4000 707 #define bCCKTxRate 0x3000 708 #define bCCKDCCancel 0x0800 709 #define bCCKISICancel 0x0400 710 #define bCCKMatchFilter 0x0200 711 #define bCCKEqualizer 0x0100 712 #define bCCKPreambleDetect 0x800000 713 #define bCCKFastFalseCCA 0x400000 714 #define bCCKChEstStart 0x300000 715 #define bCCKCCACount 0x080000 716 #define bCCKcs_lim 0x070000 717 #define bCCKBistMode 0x80000000 718 #define bCCKCCAMask 0x40000000 719 #define bCCKTxDACPhase 0x4 720 #define bCCKRxADCPhase 0x20000000 //r_rx_clk 721 #define bCCKr_cp_mode0 0x0100 722 #define bCCKTxDCOffset 0xf0 723 #define bCCKRxDCOffset 0xf 724 #define bCCKCCAMode 0xc000 725 #define bCCKFalseCS_lim 0x3f00 726 #define bCCKCS_ratio 0xc00000 727 #define bCCKCorgBit_sel 0x300000 728 #define bCCKPD_lim 0x0f0000 729 #define bCCKNewCCA 0x80000000 730 #define bCCKRxHPofIG 0x8000 731 #define bCCKRxIG 0x7f00 732 #define bCCKLNAPolarity 0x800000 733 #define bCCKRx1stGain 0x7f0000 734 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity 735 #define bCCKRxAGCSatLevel 0x1f000000 736 #define bCCKRxAGCSatCount 0xe0 737 #define bCCKRxRFSettle 0x1f //AGCsamp_dly 738 #define bCCKFixedRxAGC 0x8000 739 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 740 #define bCCKAntennaPolarity 0x2000 741 #define bCCKTxFilterType 0x0c00 742 #define bCCKRxAGCReportType 0x0300 743 #define bCCKRxDAGCEn 0x80000000 744 #define bCCKRxDAGCPeriod 0x20000000 745 #define bCCKRxDAGCSatLevel 0x1f000000 746 #define bCCKTimingRecovery 0x800000 747 #define bCCKTxC0 0x3f0000 748 #define bCCKTxC1 0x3f000000 749 #define bCCKTxC2 0x3f 750 #define bCCKTxC3 0x3f00 751 #define bCCKTxC4 0x3f0000 752 #define bCCKTxC5 0x3f000000 753 #define bCCKTxC6 0x3f 754 #define bCCKTxC7 0x3f00 755 #define bCCKDebugPort 0xff0000 756 #define bCCKDACDebug 0x0f000000 757 #define bCCKFalseAlarmEnable 0x8000 758 #define bCCKFalseAlarmRead 0x4000 759 #define bCCKTRSSI 0x7f 760 #define bCCKRxAGCReport 0xfe 761 #define bCCKRxReport_AntSel 0x80000000 762 #define bCCKRxReport_MFOff 0x40000000 763 #define bCCKRxRxReport_SQLoss 0x20000000 764 #define bCCKRxReport_Pktloss 0x10000000 765 #define bCCKRxReport_Lockedbit 0x08000000 766 #define bCCKRxReport_RateError 0x04000000 767 #define bCCKRxReport_RxRate 0x03000000 768 #define bCCKRxFACounterLower 0xff 769 #define bCCKRxFACounterUpper 0xff000000 770 #define bCCKRxHPAGCStart 0xe000 771 #define bCCKRxHPAGCFinal 0x1c00 772 #define bCCKRxFalseAlarmEnable 0x8000 773 #define bCCKFACounterFreeze 0x4000 774 #define bCCKTxPathSel 0x10000000 775 #define bCCKDefaultRxPath 0xc000000 776 #define bCCKOptionRxPath 0x3000000 777 778 // 5. PageC(0xC00) 779 #define bNumOfSTF 0x3 // Useless 780 #define bShift_L 0xc0 781 #define bGI_TH 0xc 782 #define bRxPathA 0x1 783 #define bRxPathB 0x2 784 #define bRxPathC 0x4 785 #define bRxPathD 0x8 786 #define bTxPathA 0x1 787 #define bTxPathB 0x2 788 #define bTxPathC 0x4 789 #define bTxPathD 0x8 790 #define bTRSSIFreq 0x200 791 #define bADCBackoff 0x3000 792 #define bDFIRBackoff 0xc000 793 #define bTRSSILatchPhase 0x10000 794 #define bRxIDCOffset 0xff 795 #define bRxQDCOffset 0xff00 796 #define bRxDFIRMode 0x1800000 797 #define bRxDCNFType 0xe000000 798 #define bRXIQImb_A 0x3ff 799 #define bRXIQImb_B 0xfc00 800 #define bRXIQImb_C 0x3f0000 801 #define bRXIQImb_D 0xffc00000 802 #define bDC_dc_Notch 0x60000 803 #define bRxNBINotch 0x1f000000 804 #define bPD_TH 0xf 805 #define bPD_TH_Opt2 0xc000 806 #define bPWED_TH 0x700 807 #define bIfMF_Win_L 0x800 808 #define bPD_Option 0x1000 809 #define bMF_Win_L 0xe000 810 #define bBW_Search_L 0x30000 811 #define bwin_enh_L 0xc0000 812 #define bBW_TH 0x700000 813 #define bED_TH2 0x3800000 814 #define bBW_option 0x4000000 815 #define bRatio_TH 0x18000000 816 #define bWindow_L 0xe0000000 817 #define bSBD_Option 0x1 818 #define bFrame_TH 0x1c 819 #define bFS_Option 0x60 820 #define bDC_Slope_check 0x80 821 #define bFGuard_Counter_DC_L 0xe00 822 #define bFrame_Weight_Short 0x7000 823 #define bSub_Tune 0xe00000 824 #define bFrame_DC_Length 0xe000000 825 #define bSBD_start_offset 0x30000000 826 #define bFrame_TH_2 0x7 827 #define bFrame_GI2_TH 0x38 828 #define bGI2_Sync_en 0x40 829 #define bSarch_Short_Early 0x300 830 #define bSarch_Short_Late 0xc00 831 #define bSarch_GI2_Late 0x70000 832 #define bCFOAntSum 0x1 833 #define bCFOAcc 0x2 834 #define bCFOStartOffset 0xc 835 #define bCFOLookBack 0x70 836 #define bCFOSumWeight 0x80 837 #define bDAGCEnable 0x10000 838 #define bTXIQImb_A 0x3ff 839 #define bTXIQImb_B 0xfc00 840 #define bTXIQImb_C 0x3f0000 841 #define bTXIQImb_D 0xffc00000 842 #define bTxIDCOffset 0xff 843 #define bTxQDCOffset 0xff00 844 #define bTxDFIRMode 0x10000 845 #define bTxPesudoNoiseOn 0x4000000 846 #define bTxPesudoNoise_A 0xff 847 #define bTxPesudoNoise_B 0xff00 848 #define bTxPesudoNoise_C 0xff0000 849 #define bTxPesudoNoise_D 0xff000000 850 #define bCCADropOption 0x20000 851 #define bCCADropThres 0xfff00000 852 #define bEDCCA_H 0xf 853 #define bEDCCA_L 0xf0 854 #define bLambda_ED 0x300 855 #define bRxInitialGain 0x7f 856 #define bRxAntDivEn 0x80 857 #define bRxAGCAddressForLNA 0x7f00 858 #define bRxHighPowerFlow 0x8000 859 #define bRxAGCFreezeThres 0xc0000 860 #define bRxFreezeStep_AGC1 0x300000 861 #define bRxFreezeStep_AGC2 0xc00000 862 #define bRxFreezeStep_AGC3 0x3000000 863 #define bRxFreezeStep_AGC0 0xc000000 864 #define bRxRssi_Cmp_En 0x10000000 865 #define bRxQuickAGCEn 0x20000000 866 #define bRxAGCFreezeThresMode 0x40000000 867 #define bRxOverFlowCheckType 0x80000000 868 #define bRxAGCShift 0x7f 869 #define bTRSW_Tri_Only 0x80 870 #define bPowerThres 0x300 871 #define bRxAGCEn 0x1 872 #define bRxAGCTogetherEn 0x2 873 #define bRxAGCMin 0x4 874 #define bRxHP_Ini 0x7 875 #define bRxHP_TRLNA 0x70 876 #define bRxHP_RSSI 0x700 877 #define bRxHP_BBP1 0x7000 878 #define bRxHP_BBP2 0x70000 879 #define bRxHP_BBP3 0x700000 880 #define bRSSI_H 0x7f0000 //the threshold for high power 881 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity 882 #define bRxSettle_TRSW 0x7 883 #define bRxSettle_LNA 0x38 884 #define bRxSettle_RSSI 0x1c0 885 #define bRxSettle_BBP 0xe00 886 #define bRxSettle_RxHP 0x7000 887 #define bRxSettle_AntSW_RSSI 0x38000 888 #define bRxSettle_AntSW 0xc0000 889 #define bRxProcessTime_DAGC 0x300000 890 #define bRxSettle_HSSI 0x400000 891 #define bRxProcessTime_BBPPW 0x800000 892 #define bRxAntennaPowerShift 0x3000000 893 #define bRSSITableSelect 0xc000000 894 #define bRxHP_Final 0x7000000 895 #define bRxHTSettle_BBP 0x7 896 #define bRxHTSettle_HSSI 0x8 897 #define bRxHTSettle_RxHP 0x70 898 #define bRxHTSettle_BBPPW 0x80 899 #define bRxHTSettle_Idle 0x300 900 #define bRxHTSettle_Reserved 0x1c00 901 #define bRxHTRxHPEn 0x8000 902 #define bRxHTAGCFreezeThres 0x30000 903 #define bRxHTAGCTogetherEn 0x40000 904 #define bRxHTAGCMin 0x80000 905 #define bRxHTAGCEn 0x100000 906 #define bRxHTDAGCEn 0x200000 907 #define bRxHTRxHP_BBP 0x1c00000 908 #define bRxHTRxHP_Final 0xe0000000 909 #define bRxPWRatioTH 0x3 910 #define bRxPWRatioEn 0x4 911 #define bRxMFHold 0x3800 912 #define bRxPD_Delay_TH1 0x38 913 #define bRxPD_Delay_TH2 0x1c0 914 #define bRxPD_DC_COUNT_MAX 0x600 915 //#define bRxMF_Hold 0x3800 916 #define bRxPD_Delay_TH 0x8000 917 #define bRxProcess_Delay 0xf0000 918 #define bRxSearchrange_GI2_Early 0x700000 919 #define bRxFrame_Guard_Counter_L 0x3800000 920 #define bRxSGI_Guard_L 0xc000000 921 #define bRxSGI_Search_L 0x30000000 922 #define bRxSGI_TH 0xc0000000 923 #define bDFSCnt0 0xff 924 #define bDFSCnt1 0xff00 925 #define bDFSFlag 0xf0000 926 #define bMFWeightSum 0x300000 927 #define bMinIdxTH 0x7f000000 928 #define bDAFormat 0x40000 929 #define bTxChEmuEnable 0x01000000 930 #define bTRSWIsolation_A 0x7f 931 #define bTRSWIsolation_B 0x7f00 932 #define bTRSWIsolation_C 0x7f0000 933 #define bTRSWIsolation_D 0x7f000000 934 #define bExtLNAGain 0x7c00 935 936 // 6. PageE(0xE00) 937 #define bSTBCEn 0x4 // Useless 938 #define bAntennaMapping 0x10 939 #define bNss 0x20 940 #define bCFOAntSumD 0x200 941 #define bPHYCounterReset 0x8000000 942 #define bCFOReportGet 0x4000000 943 #define bOFDMContinueTx 0x10000000 944 #define bOFDMSingleCarrier 0x20000000 945 #define bOFDMSingleTone 0x40000000 946 //#define bRxPath1 0x01 947 //#define bRxPath2 0x02 948 //#define bRxPath3 0x04 949 //#define bRxPath4 0x08 950 //#define bTxPath1 0x10 951 //#define bTxPath2 0x20 952 #define bHTDetect 0x100 953 #define bCFOEn 0x10000 954 #define bCFOValue 0xfff00000 955 #define bSigTone_Re 0x3f 956 #define bSigTone_Im 0x7f00 957 #define bCounter_CCA 0xffff 958 #define bCounter_ParityFail 0xffff0000 959 #define bCounter_RateIllegal 0xffff 960 #define bCounter_CRC8Fail 0xffff0000 961 #define bCounter_MCSNoSupport 0xffff 962 #define bCounter_FastSync 0xffff 963 #define bShortCFO 0xfff 964 #define bShortCFOTLength 12 //total 965 #define bShortCFOFLength 11 //fraction 966 #define bLongCFO 0x7ff 967 #define bLongCFOTLength 11 968 #define bLongCFOFLength 11 969 #define bTailCFO 0x1fff 970 #define bTailCFOTLength 13 971 #define bTailCFOFLength 12 972 #define bmax_en_pwdB 0xffff 973 #define bCC_power_dB 0xffff0000 974 #define bnoise_pwdB 0xffff 975 #define bPowerMeasTLength 10 976 #define bPowerMeasFLength 3 977 #define bRx_HT_BW 0x1 978 #define bRxSC 0x6 979 #define bRx_HT 0x8 980 #define bNB_intf_det_on 0x1 981 #define bIntf_win_len_cfg 0x30 982 #define bNB_Intf_TH_cfg 0x1c0 983 #define bRFGain 0x3f 984 #define bTableSel 0x40 985 #define bTRSW 0x80 986 #define bRxSNR_A 0xff 987 #define bRxSNR_B 0xff00 988 #define bRxSNR_C 0xff0000 989 #define bRxSNR_D 0xff000000 990 #define bSNREVMTLength 8 991 #define bSNREVMFLength 1 992 #define bCSI1st 0xff 993 #define bCSI2nd 0xff00 994 #define bRxEVM1st 0xff0000 995 #define bRxEVM2nd 0xff000000 996 #define bSIGEVM 0xff 997 #define bPWDB 0xff00 998 #define bSGIEN 0x10000 999 1000 #define bSFactorQAM1 0xf // Useless 1001 #define bSFactorQAM2 0xf0 1002 #define bSFactorQAM3 0xf00 1003 #define bSFactorQAM4 0xf000 1004 #define bSFactorQAM5 0xf0000 1005 #define bSFactorQAM6 0xf0000 1006 #define bSFactorQAM7 0xf00000 1007 #define bSFactorQAM8 0xf000000 1008 #define bSFactorQAM9 0xf0000000 1009 #define bCSIScheme 0x100000 1010 1011 #define bNoiseLvlTopSet 0x3 // Useless 1012 #define bChSmooth 0x4 1013 #define bChSmoothCfg1 0x38 1014 #define bChSmoothCfg2 0x1c0 1015 #define bChSmoothCfg3 0xe00 1016 #define bChSmoothCfg4 0x7000 1017 #define bMRCMode 0x800000 1018 #define bTHEVMCfg 0x7000000 1019 1020 #define bLoopFitType 0x1 // Useless 1021 #define bUpdCFO 0x40 1022 #define bUpdCFOOffData 0x80 1023 #define bAdvUpdCFO 0x100 1024 #define bAdvTimeCtrl 0x800 1025 #define bUpdClko 0x1000 1026 #define bFC 0x6000 1027 #define bTrackingMode 0x8000 1028 #define bPhCmpEnable 0x10000 1029 #define bUpdClkoLTF 0x20000 1030 #define bComChCFO 0x40000 1031 #define bCSIEstiMode 0x80000 1032 #define bAdvUpdEqz 0x100000 1033 #define bUChCfg 0x7000000 1034 #define bUpdEqz 0x8000000 1035 1036 //Rx Pseduo noise 1037 #define bRxPesudoNoiseOn 0x20000000 // Useless 1038 #define bRxPesudoNoise_A 0xff 1039 #define bRxPesudoNoise_B 0xff00 1040 #define bRxPesudoNoise_C 0xff0000 1041 #define bRxPesudoNoise_D 0xff000000 1042 #define bPesudoNoiseState_A 0xffff 1043 #define bPesudoNoiseState_B 0xffff0000 1044 #define bPesudoNoiseState_C 0xffff 1045 #define bPesudoNoiseState_D 0xffff0000 1046 1047 //7. RF Register 1048 //Zebra1 1049 #define bZebra1_HSSIEnable 0x8 // Useless 1050 #define bZebra1_TRxControl 0xc00 1051 #define bZebra1_TRxGainSetting 0x07f 1052 #define bZebra1_RxCorner 0xc00 1053 #define bZebra1_TxChargePump 0x38 1054 #define bZebra1_RxChargePump 0x7 1055 #define bZebra1_ChannelNum 0xf80 1056 #define bZebra1_TxLPFBW 0x400 1057 #define bZebra1_RxLPFBW 0x600 1058 1059 //Zebra4 1060 #define bRTL8256RegModeCtrl1 0x100 // Useless 1061 #define bRTL8256RegModeCtrl0 0x40 1062 #define bRTL8256_TxLPFBW 0x18 1063 #define bRTL8256_RxLPFBW 0x600 1064 1065 //RTL8258 1066 #define bRTL8258_TxLPFBW 0xc // Useless 1067 #define bRTL8258_RxLPFBW 0xc00 1068 #define bRTL8258_RSSILPFBW 0xc0 1069 1070 1071 // 1072 // Other Definition 1073 // 1074 1075 //byte endable for sb_write 1076 #define bByte0 0x1 // Useless 1077 #define bByte1 0x2 1078 #define bByte2 0x4 1079 #define bByte3 0x8 1080 #define bWord0 0x3 1081 #define bWord1 0xc 1082 #define bDWord 0xf 1083 1084 //for PutRegsetting & GetRegSetting BitMask 1085 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f 1086 #define bMaskByte1 0xff00 1087 #define bMaskByte2 0xff0000 1088 #define bMaskByte3 0xff000000 1089 #define bMaskHWord 0xffff0000 1090 #define bMaskLWord 0x0000ffff 1091 #define bMaskDWord 0xffffffff 1092 #define bMaskH3Bytes 0xffffff00 1093 #define bMask12Bits 0xfff 1094 #define bMaskH4Bits 0xf0000000 1095 #define bMaskOFDM_D 0xffc00000 1096 #define bMaskCCK 0x3f3f3f3f 1097 1098 1099 #define bEnable 0x1 // Useless 1100 #define bDisable 0x0 1101 1102 #define LeftAntenna 0x0 // Useless 1103 #define RightAntenna 0x1 1104 1105 #define tCheckTxStatus 500 //500ms // Useless 1106 #define tUpdateRxCounter 100 //100ms 1107 1108 #define rateCCK 0 // Useless 1109 #define rateOFDM 1 1110 #define rateHT 2 1111 1112 //define Register-End 1113 #define bPMAC_End 0x1ff // Useless 1114 #define bFPGAPHY0_End 0x8ff 1115 #define bFPGAPHY1_End 0x9ff 1116 #define bCCKPHY0_End 0xaff 1117 #define bOFDMPHY0_End 0xcff 1118 #define bOFDMPHY1_End 0xdff 1119 1120 //define max debug item in each debug page 1121 //#define bMaxItem_FPGA_PHY0 0x9 1122 //#define bMaxItem_FPGA_PHY1 0x3 1123 //#define bMaxItem_PHY_11B 0x16 1124 //#define bMaxItem_OFDM_PHY0 0x29 1125 //#define bMaxItem_OFDM_PHY1 0x0 1126 1127 #define bPMACControl 0x0 // Useless 1128 #define bWMACControl 0x1 1129 #define bWNICControl 0x2 1130 1131 #define PathA 0x0 // Useless 1132 #define PathB 0x1 1133 #define PathC 0x2 1134 #define PathD 0x3 1135 1136 #endif 1137 1138