1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HAL_MP_C_
21 #ifdef CONFIG_MP_INCLUDED
22
23 #ifdef CONFIG_RTL8188E
24 #include <rtl8188e_hal.h>
25 #endif
26 #ifdef CONFIG_RTL8723B
27 #include <rtl8723b_hal.h>
28 #endif
29 #ifdef CONFIG_RTL8192E
30 #include <rtl8192e_hal.h>
31 #endif
32 #ifdef CONFIG_RTL8814A
33 #include <rtl8814a_hal.h>
34 #endif
35 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
36 #include <rtl8812a_hal.h>
37 #endif
38 #ifdef CONFIG_RTL8703B
39 #include <rtl8703b_hal.h>
40 #endif
41 #ifdef CONFIG_RTL8188F
42 #include <rtl8188f_hal.h>
43 #endif
44
45
MgntQuery_NssTxRate(u16 Rate)46 u8 MgntQuery_NssTxRate(u16 Rate)
47 {
48 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
49
50 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
51 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
52 NssNum = RF_2TX;
53 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
54 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
55 NssNum = RF_3TX;
56 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
57 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
58 NssNum = RF_4TX;
59 else
60 NssNum = RF_1TX;
61
62 return NssNum;
63 }
64
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)65 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
66 {
67 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
68 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
69 u8 ChannelToSw = pMptCtx->MptChannelToSw;
70 ULONG ulRateIdx = pMptCtx->MptRateIndex;
71 ULONG ulbandwidth = pMptCtx->MptBandWidth;
72
73 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
74 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
75 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
76 pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
77 pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
78
79 if ((PlatformEFIORead4Byte(pAdapter, 0xF4)&BIT29) == BIT29) {
80 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
81 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
82 } else {
83 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
84 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
85 }
86 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
87
88 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
89 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
90 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
91 } else {
92 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
93 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
94 }
95
96 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
97 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
98 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
99 }
100 }
101
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)102 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
103 {
104 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
105 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
106
107
108 if (!netif_running(padapter->pnetdev)) {
109 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
110 return _FAIL;
111 }
112
113 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
114 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
115 return _FAIL;
116 }
117 if (enable)
118 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
119 else
120 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
121
122 return _SUCCESS;
123 }
124
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)125 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
126 {
127 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
128 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
129
130
131 *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
132 }
133
134
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)135 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
136 {
137 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
138 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
139 u8 i;
140 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
141
142 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
143 u1Byte u1Channel = pHalData->CurrentChannel;
144 ULONG ulRateIdx = pMptCtx->MptRateIndex;
145 u1Byte DataRate = 0xFF;
146
147 DataRate = MptToMgntRate(ulRateIdx);
148
149 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
150 pHalData->bCCKinCH14 = TRUE;
151 else
152 pHalData->bCCKinCH14 = FALSE;
153
154 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
155 if ((u1Channel == 12 || u1Channel == 13) && IS_CCK_RATE(DataRate)) {/* Channel 12, 13 in CCK, need to set 0xA22~0xA29, OxA9A~0xA9D, 0xAA0~0xAA3 for 8703B */
156 PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0xD1D80000);
157 PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x5A7DA0BD);
158 PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x0000223B);
159
160 PHY_SetBBReg(Adapter, 0xA98, bMaskDWord, 0x05100000);
161 PHY_SetBBReg(Adapter, 0xA9C, bMaskDWord, 0);
162 PHY_SetBBReg(Adapter, 0xAA0, bMaskDWord, 0);
163
164 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));
165 } else if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) { /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
166 PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
167 PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
168
169 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));
170 } else { /* Normal setting for 8703B, just recover to the default setting.*/
171 /* This hardcore values reference from the parameter which BB team gave.*/
172 for (i = 0 ; i < 6 ; ++i)
173 PHY_SetBBReg(Adapter, pHalData->BBRegForRecover[i].offset, bMaskDWord, pHalData->BBRegForRecover[i].value);
174
175 RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel));
176 }
177 } else {
178
179 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
180 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
181
182 if (!pHalData->bCCKinCH14) {
183 /* Readback the current bb cck swing value and compare with the table to */
184 /* get the current swing index */
185 for (i = 0; i < CCK_TABLE_SIZE; i++) {
186 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
187 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
188 CCKSwingIndex = i;
189 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
190 (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
191 break;
192 }
193 }
194
195 /*Write 0xa22 0xa23*/
196 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
197 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
198
199
200 /*Write 0xa24 ~ 0xa27*/
201 TempVal2 = 0;
202 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
203 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
204 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16) +
205 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
206
207 /*Write 0xa28 0xa29*/
208 TempVal3 = 0;
209 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
210 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
211 } else {
212 for (i = 0; i < CCK_TABLE_SIZE; i++) {
213 if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
214 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
215 CCKSwingIndex = i;
216 RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
217 (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
218 break;
219 }
220 }
221
222 /*Write 0xa22 0xa23*/
223 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
224 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
225
226 /*Write 0xa24 ~ 0xa27*/
227 TempVal2 = 0;
228 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
229 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
230 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16) +
231 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
232
233 /*Write 0xa28 0xa29*/
234 TempVal3 = 0;
235 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
236 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
237 }
238
239 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
240 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
241 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
242
243 }
244
245 }
246
hal_mpt_SetChannel(PADAPTER pAdapter)247 void hal_mpt_SetChannel(PADAPTER pAdapter)
248 {
249 u8 eRFPath;
250 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
251 PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
252 struct mp_priv *pmp = &pAdapter->mppriv;
253 u8 channel = pmp->channel;
254 u8 bandwidth = pmp->bandwidth;
255 u8 rate = pmp->rateidx;
256
257 hal_mpt_SwitchRfSetting(pAdapter);
258
259 SelectChannel(pAdapter, channel);
260
261 pHalData->bSwChnl = _TRUE;
262 pHalData->bSetChnlBW = _TRUE;
263 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
264
265 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
266
267 }
268
269 /*
270 * Notice
271 * Switch bandwitdth may change center frequency(channel)
272 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)273 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
274 {
275 struct mp_priv *pmp = &pAdapter->mppriv;
276 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
277
278 u8 channel = pmp->channel;
279 u8 bandwidth = pmp->bandwidth;
280
281 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
282 pHalData->bSwChnl = _TRUE;
283 pHalData->bSetChnlBW = _TRUE;
284 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
285
286 hal_mpt_SwitchRfSetting(pAdapter);
287 }
288
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)289 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
290 {
291 RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate));
292 switch (Rate) {
293 case MPT_CCK:
294 {
295 u4Byte TxAGC = 0, pwr = 0;
296 u1Byte rf;
297
298 pwr = pTxPower[ODM_RF_PATH_A];
299 if (pwr < 0x3f) {
300 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
301 PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
302 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
303 }
304 pwr = pTxPower[ODM_RF_PATH_B];
305 if (pwr < 0x3f) {
306 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
307 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
308 PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
309 }
310
311 } break;
312
313 case MPT_OFDM_AND_HT:
314 {
315 u4Byte TxAGC = 0;
316 u1Byte pwr = 0, rf;
317
318 pwr = pTxPower[0];
319 if (pwr < 0x3f) {
320 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
321 DBG_871X("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
322
323 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
324 PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
325 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
326 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
327 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
328 PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
329 }
330 TxAGC = 0;
331 pwr = pTxPower[1];
332 if (pwr < 0x3f) {
333 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
334 DBG_871X("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
335
336 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
337 PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
338 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
339 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
340 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
341 PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
342 }
343 } break;
344
345 default:
346 break;
347 }
348 DBG_871X("<===mpt_SetTxPower_Old()\n");
349 }
350
351
352
353 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,pu1Byte pTxPower)354 mpt_SetTxPower(
355 PADAPTER pAdapter,
356 MPT_TXPWR_DEF Rate,
357 pu1Byte pTxPower
358 )
359 {
360 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
361
362 u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
363 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
364
365 if (IS_HARDWARE_TYPE_8814A(pAdapter))
366 EndPath = ODM_RF_PATH_D;
367
368 switch (Rate) {
369 case MPT_CCK:
370 {
371 u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
372
373 for (path = StartPath; path <= EndPath; path++)
374 for (i = 0; i < sizeof(rate); ++i)
375 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
376 }
377 break;
378
379 case MPT_OFDM:
380 {
381 u1Byte rate[] = {
382 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
383 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
384 };
385
386 for (path = StartPath; path <= EndPath; path++)
387 for (i = 0; i < sizeof(rate); ++i)
388 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
389 } break;
390
391 case MPT_HT:
392 {
393 u1Byte rate[] = {
394 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
395 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
396 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
397 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
398 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
399 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
400 MGN_MCS30, MGN_MCS31,
401 };
402 if (pHalData->rf_type == RF_3T3R)
403 MaxRate = MGN_MCS23;
404 else if (pHalData->rf_type == RF_2T2R)
405 MaxRate = MGN_MCS15;
406 else
407 MaxRate = MGN_MCS7;
408
409 for (path = StartPath; path <= EndPath; path++) {
410 for (i = 0; i < sizeof(rate); ++i) {
411 if (rate[i] > MaxRate)
412 break;
413 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
414 }
415 }
416 } break;
417
418 case MPT_VHT:
419 {
420 u1Byte rate[] = {
421 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
422 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
423 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
424 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
425 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
426 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
427 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
428 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
429 };
430
431 if (pHalData->rf_type == RF_3T3R)
432 MaxRate = MGN_VHT3SS_MCS9;
433 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
434 MaxRate = MGN_VHT2SS_MCS9;
435 else
436 MaxRate = MGN_VHT1SS_MCS9;
437
438 for (path = StartPath; path <= EndPath; path++) {
439 for (i = 0; i < sizeof(rate); ++i) {
440 if (rate[i] > MaxRate)
441 break;
442 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
443 }
444 }
445 } break;
446
447 default:
448 DBG_871X("<===mpt_SetTxPower: Illegal channel!!\n");
449 break;
450 }
451
452 }
453
454
hal_mpt_SetTxPower(PADAPTER pAdapter)455 void hal_mpt_SetTxPower(PADAPTER pAdapter)
456 {
457 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
458 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
459 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
460
461 if (pHalData->rf_chip < RF_TYPE_MAX) {
462 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
463 IS_HARDWARE_TYPE_8723B(pAdapter) ||
464 IS_HARDWARE_TYPE_8192E(pAdapter) ||
465 IS_HARDWARE_TYPE_8703B(pAdapter) ||
466 IS_HARDWARE_TYPE_8188F(pAdapter)) {
467 u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
468
469 DBG_8192C("===> MPT_ProSetTxPower: Old\n");
470
471 RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n"));
472 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
473 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
474
475 } else {
476 DBG_871X("===> MPT_ProSetTxPower: Jaguar\n");
477 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
478 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
479 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
480 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
481
482 }
483 } else
484 DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
485
486 ODM_ClearTxPowerTrackingState(pDM_Odm);
487
488 }
489
490
hal_mpt_SetDataRate(PADAPTER pAdapter)491 void hal_mpt_SetDataRate(PADAPTER pAdapter)
492 {
493 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
494 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
495 u32 DataRate;
496
497 DataRate = MptToMgntRate(pAdapter->mppriv.rateidx);
498
499 hal_mpt_SwitchRfSetting(pAdapter);
500
501 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
502 #ifdef CONFIG_RTL8723B
503 if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
504 if (IS_CCK_RATE(DataRate)) {
505 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
506 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
507 else
508 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
509 } else {
510 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
511 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
512 else
513 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
514 }
515 }
516
517 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
518 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
519 if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
520 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
521 else
522 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
523 }
524 #endif
525 }
526
527
528 #define RF_PATH_AB 22
529
530 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)531 VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
532 {
533 u1Byte Path = 0;
534 u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
535
536 for (Path; Path <= ODM_RF_PATH_D; Path++) {
537 switch (Path) {
538 case ODM_RF_PATH_B:
539 IGReg = rB_IGI_Jaguar;
540 break;
541 case ODM_RF_PATH_C:
542 IGReg = rC_IGI_Jaguar2;
543 break;
544 case ODM_RF_PATH_D:
545 IGReg = rD_IGI_Jaguar2;
546 break;
547 default:
548 IGReg = rA_IGI_Jaguar;
549 break;
550 }
551
552 IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);
553 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue+2);
554 PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);
555 }
556 }
557
mpt_SetRFPath_8814A(PADAPTER pAdapter)558 VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
559 {
560
561 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
562 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
563 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
564 R_ANTENNA_SELECT_CCK *p_cck_txrx;
565
566 u8 ForcedDataRate = HwRateToMRate(pAdapter->mppriv.rateidx);
567 u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
568 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
569 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
570
571 u32 ulAntennaTx = pHalData->AntennaTxPath;
572 u32 ulAntennaRx = pHalData->AntennaRxPath;
573 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
574
575 if (NssforRate == RF_2TX) {
576 DBG_871X("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
577
578 switch (ulAntennaTx) {
579 case ANTENNA_BC:
580 pMptCtx->MptRfPath = ODM_RF_PATH_BC;
581 /*pHalData->ValidTxPath = 0x06; linux no use */
582 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/
583 break;
584
585 case ANTENNA_CD:
586 pMptCtx->MptRfPath = ODM_RF_PATH_CD;
587 /*pHalData->ValidTxPath = 0x0C;*/
588 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/
589 break;
590 case ANTENNA_AB: default:
591 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
592 /*pHalData->ValidTxPath = 0x03;*/
593 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/
594 break;
595 }
596
597 } else if (NssforRate == RF_3TX) {
598 DBG_871X("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
599
600 switch (ulAntennaTx) {
601 case ANTENNA_BCD:
602 pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
603 /*pHalData->ValidTxPath = 0x0e;*/
604 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
605 break;
606
607 case ANTENNA_ABC: default:
608 pMptCtx->MptRfPath = ODM_RF_PATH_ABC;
609 /*pHalData->ValidTxPath = 0x0d;*/
610 PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
611 break;
612 }
613
614 } else { /*/if(NssforRate == RF_1TX)*/
615 DBG_871X("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
616 switch (ulAntennaTx) {
617 case ANTENNA_B:
618 pMptCtx->MptRfPath = ODM_RF_PATH_B;
619 /*pHalData->ValidTxPath = 0x02;*/
620 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
621 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
622 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
623 break;
624
625 case ANTENNA_C:
626 pMptCtx->MptRfPath = ODM_RF_PATH_C;
627 /*pHalData->ValidTxPath = 0x04;*/
628 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
629 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
630 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
631 break;
632
633 case ANTENNA_D:
634 pMptCtx->MptRfPath = ODM_RF_PATH_D;
635 /*pHalData->ValidTxPath = 0x08;*/
636 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
637 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
638 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
639 break;
640
641 case ANTENNA_A: default:
642 pMptCtx->MptRfPath = ODM_RF_PATH_A;
643 /*pHalData->ValidTxPath = 0x01;*/
644 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
645 PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
646 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
647 break;
648 }
649 }
650
651 switch (ulAntennaRx) {
652 case ANTENNA_A:
653 /*pHalData->ValidRxPath = 0x01;*/
654 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
655 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
656 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
657 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
658 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
659 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
660 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
661 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
662 /*/ CCA related PD_delay_th*/
663 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
664 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
665 break;
666
667 case ANTENNA_B:
668 /*pHalData->ValidRxPath = 0x02;*/
669 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
670 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
671 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
672 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
673 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
674 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
675 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
676 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
677 /*/ CCA related PD_delay_th*/
678 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
679 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
680 break;
681
682 case ANTENNA_C:
683 /*pHalData->ValidRxPath = 0x04;*/
684 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
685 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
686 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
687 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
688 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
689 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
690 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
691 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
692 /*/ CCA related PD_delay_th*/
693 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
694 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
695 break;
696
697 case ANTENNA_D:
698 /*pHalData->ValidRxPath = 0x08;*/
699 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
700 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
701 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
702 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
703 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
704 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
705 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
706 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
707 /*/ CCA related PD_delay_th*/
708 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
709 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
710 break;
711
712 case ANTENNA_BC:
713 /*pHalData->ValidRxPath = 0x06;*/
714 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
715 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
716 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
717 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
718 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
719 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
720 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
721 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
722 /*/ CCA related PD_delay_th*/
723 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
724 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
725 break;
726
727 case ANTENNA_CD:
728 /*pHalData->ValidRxPath = 0x0C;*/
729 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
730 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
731 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
732 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
733 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
734 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
735 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
736 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
737 /*/ CCA related PD_delay_th*/
738 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
739 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
740 break;
741
742 case ANTENNA_BCD:
743 /*pHalData->ValidRxPath = 0x0e;*/
744 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
745 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
746 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
747 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
748 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
749 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
750 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
751 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
752 /*/ CCA related PD_delay_th*/
753 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
754 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
755 break;
756
757 case ANTENNA_ABCD:
758 /*pHalData->ValidRxPath = 0x0f;*/
759 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
760 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
761 PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
762 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
763 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
764 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
765 PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
766 PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
767 /*/ CCA related PD_delay_th*/
768 PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
769 PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
770 break;
771
772 default:
773 RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n"));
774 break;
775 }
776
777 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
778
779 mpt_ToggleIG_8814A(pAdapter);
780 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
781 }
782
783 VOID
mpt_SetSingleTone_8814A(IN PADAPTER pAdapter,IN BOOLEAN bSingleTone,IN BOOLEAN bEnPMacTx)784 mpt_SetSingleTone_8814A(
785 IN PADAPTER pAdapter,
786 IN BOOLEAN bSingleTone,
787 IN BOOLEAN bEnPMacTx)
788 {
789
790 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
791 u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A;
792 static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
793
794 if (bSingleTone) {
795 regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
796 regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
797 regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
798 regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
799
800 switch (pMptCtx->MptRfPath) {
801 case ODM_RF_PATH_A: case ODM_RF_PATH_B:
802 case ODM_RF_PATH_C: case ODM_RF_PATH_D:
803 StartPath = pMptCtx->MptRfPath;
804 EndPath = pMptCtx->MptRfPath;
805 break;
806 case ODM_RF_PATH_AB:
807 EndPath = ODM_RF_PATH_B;
808 break;
809 case ODM_RF_PATH_BC:
810 StartPath = ODM_RF_PATH_B;
811 EndPath = ODM_RF_PATH_C;
812 break;
813 case ODM_RF_PATH_ABC:
814 EndPath = ODM_RF_PATH_C;
815 break;
816 case ODM_RF_PATH_BCD:
817 StartPath = ODM_RF_PATH_B;
818 EndPath = ODM_RF_PATH_D;
819 break;
820 case ODM_RF_PATH_ABCD:
821 EndPath = ODM_RF_PATH_D;
822 break;
823 }
824
825 if (bEnPMacTx == FALSE) {
826 hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);
827 issue_nulldata(pAdapter, NULL, 1, 3, 500);
828 }
829
830 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
831
832 for (StartPath; StartPath <= EndPath; StartPath++) {
833 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
834 PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
835
836 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
837 }
838
839 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
840 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
841 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
842 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
843
844 } else {
845
846 switch (pMptCtx->MptRfPath) {
847 case ODM_RF_PATH_A: case ODM_RF_PATH_B:
848 case ODM_RF_PATH_C: case ODM_RF_PATH_D:
849 StartPath = pMptCtx->MptRfPath;
850 EndPath = pMptCtx->MptRfPath;
851 break;
852 case ODM_RF_PATH_AB:
853 EndPath = ODM_RF_PATH_B;
854 break;
855 case ODM_RF_PATH_BC:
856 StartPath = ODM_RF_PATH_B;
857 EndPath = ODM_RF_PATH_C;
858 break;
859 case ODM_RF_PATH_ABC:
860 EndPath = ODM_RF_PATH_C;
861 break;
862 case ODM_RF_PATH_BCD:
863 StartPath = ODM_RF_PATH_B;
864 EndPath = ODM_RF_PATH_D;
865 break;
866 case ODM_RF_PATH_ABCD:
867 EndPath = ODM_RF_PATH_D;
868 break;
869 }
870
871 for (StartPath; StartPath <= EndPath; StartPath++)
872 PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /*// RF LO disabled*/
873
874
875 PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
876
877 if (bEnPMacTx == FALSE)
878 hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);
879
880 PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
881 PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
882 PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
883 PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
884 }
885 }
886
887 #endif
888
889 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)890 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
891 {
892 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
893 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
894 u32 ulAntennaTx, ulAntennaRx;
895
896 ulAntennaTx = pHalData->AntennaTxPath;
897 ulAntennaRx = pHalData->AntennaRxPath;
898
899 switch (ulAntennaTx) {
900 case ANTENNA_A:
901 pMptCtx->MptRfPath = ODM_RF_PATH_A;
902 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
903 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
904 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
905 break;
906 case ANTENNA_B:
907 pMptCtx->MptRfPath = ODM_RF_PATH_B;
908 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
909 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
910 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
911 break;
912 case ANTENNA_AB:
913 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
914 PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
915 if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
916 PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
917 break;
918 default:
919 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
920 DBG_871X("Unknown Tx antenna.\n");
921 break;
922 }
923
924 switch (ulAntennaRx) {
925 u32 reg0xC50 = 0;
926 case ANTENNA_A:
927 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
928 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
929 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
930 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3);
931
932 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
933 reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
934 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50+2);
935 PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
936 break;
937 case ANTENNA_B:
938 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
939 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
940 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
941 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3);
942
943 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
944 reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
945 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50+2);
946 PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
947 break;
948 case ANTENNA_AB:
949 PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
950 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
951 PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
952 break;
953 default:
954 DBG_871X("Unknown Rx antenna.\n");
955 break;
956 }
957 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
958 }
959 #endif
960
961 #ifdef CONFIG_RTL8188F
962
mpt_SetRFPath_8188F(PADAPTER pAdapter)963 void mpt_SetRFPath_8188F(PADAPTER pAdapter)
964 {
965 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
966 u32 ulAntennaTx, ulAntennaRx;
967 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
968 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
969 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
970
971 ulAntennaTx = pHalData->AntennaTxPath;
972 ulAntennaRx = pHalData->AntennaRxPath;
973
974 if (pHalData->rf_chip >= RF_TYPE_MAX) {
975 DBG_8192C("This RF chip ID is not supported\n");
976 return;
977 }
978
979 switch (pAdapter->mppriv.antenna_tx) {
980 u8 p = 0, i = 0;
981 case ANTENNA_A: /*/ Actually path S1 (Wi-Fi)*/
982 {
983 pMptCtx->MptRfPath = ODM_RF_PATH_A;
984 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);
985 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
986
987 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
988 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
989 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
990 else
991 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
992
993
994 for (i = 0; i < 3; ++i) {
995 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
996 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
997
998 if (offset != 0) {
999 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1000 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1001 }
1002
1003 }
1004 for (i = 0; i < 2; ++i) {
1005 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1006 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
1007
1008 if (offset != 0) {
1009 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1010 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1011 }
1012 }
1013 }
1014 break;
1015 case ANTENNA_B: /*/ Actually path S0 (BT)*/
1016 {
1017 u4Byte offset;
1018 u4Byte data;
1019
1020 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1021 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);
1022 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1023
1024 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1025 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1026 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1027 else
1028 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1029
1030 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1031 for (i = 0; i < 3; ++i) {
1032 offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1033 data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
1034
1035 if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1036 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1037 DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1038 }
1039 }
1040 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1041 for (i = 0; i < 2; ++i) {
1042 offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1043 data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
1044 if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1045 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1046 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1047 }
1048 }
1049
1050 }
1051 break;
1052 default:
1053 pMptCtx->MptRfPath = RF_PATH_AB;
1054 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1055 break;
1056 }
1057 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1058 }
1059 #endif
1060
1061
1062 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1063 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1064 {
1065 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1066 u32 ulAntennaTx, ulAntennaRx;
1067 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1068 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1069 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1070
1071 ulAntennaTx = pHalData->AntennaTxPath;
1072 ulAntennaRx = pHalData->AntennaRxPath;
1073
1074 if (pHalData->rf_chip >= RF_TYPE_MAX) {
1075 DBG_8192C("This RF chip ID is not supported\n");
1076 return;
1077 }
1078
1079 switch (pAdapter->mppriv.antenna_tx) {
1080 u8 p = 0, i = 0;
1081 case ANTENNA_A: /*/ Actually path S1 (Wi-Fi)*/
1082 {
1083 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1084 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0);
1085 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1086
1087 /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1088 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1089 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1090 else
1091 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1092
1093
1094 for (i = 0; i < 3; ++i) {
1095 u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1096 u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
1097
1098 if (offset != 0) {
1099 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1100 DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1101 }
1102
1103 }
1104 for (i = 0; i < 2; ++i) {
1105 u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1106 u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
1107
1108 if (offset != 0) {
1109 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1110 DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1111 }
1112 }
1113 }
1114 break;
1115 case ANTENNA_B: /*/ Actually path S0 (BT)*/
1116 {
1117 u4Byte offset;
1118 u4Byte data;
1119
1120 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1121 PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5);
1122 PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1123
1124 /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
1125 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
1126 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
1127 else
1128 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
1129
1130 for (i = 0; i < 3; ++i) {
1131 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1132 offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
1133 data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
1134 if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1135 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1136 DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1137 }
1138 }
1139 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1140 for (i = 0; i < 2; ++i) {
1141 offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
1142 data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
1143
1144 if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
1145 PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
1146 DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1147 }
1148 }
1149 }
1150 break;
1151 default:
1152 pMptCtx->MptRfPath = RF_PATH_AB;
1153 RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
1154 break;
1155 }
1156 RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
1157 }
1158 #endif
1159
mpt_SetRFPath_819X(PADAPTER pAdapter)1160 VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
1161 {
1162 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1163 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1164 u4Byte ulAntennaTx, ulAntennaRx;
1165 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1166 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1167 u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1168 u1Byte chgTx = 0, chgRx = 0;
1169 u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1170
1171 ulAntennaTx = pHalData->AntennaTxPath;
1172 ulAntennaRx = pHalData->AntennaRxPath;
1173
1174 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1175 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1176
1177 p_ofdm_tx->r_ant_ht1 = 0x1;
1178 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1179 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1180
1181 switch (ulAntennaTx) {
1182 case ANTENNA_A:
1183 p_ofdm_tx->r_tx_antenna = 0x1;
1184 r_ofdm_tx_en_val = 0x1;
1185 p_ofdm_tx->r_ant_l = 0x1;
1186 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1187 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1188 p_cck_txrx->r_ccktx_enable = 0x8;
1189 chgTx = 1;
1190 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1191 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1192 {
1193 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1194 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1195 r_ofdm_tx_en_val = 0x3;
1196 /*/ Power save*/
1197 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1198 /*/ We need to close RFB by SW control*/
1199 if (pHalData->rf_type == RF_2T2R) {
1200 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1201 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1202 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1203 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1204 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1205 }
1206 }
1207 pMptCtx->MptRfPath = ODM_RF_PATH_A;
1208 break;
1209 case ANTENNA_B:
1210 p_ofdm_tx->r_tx_antenna = 0x2;
1211 r_ofdm_tx_en_val = 0x2;
1212 p_ofdm_tx->r_ant_l = 0x2;
1213 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1214 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1215 p_cck_txrx->r_ccktx_enable = 0x4;
1216 chgTx = 1;
1217 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1218 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1219 {
1220 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1221 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1222
1223 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1224 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1225 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1226 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1227 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1228 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1229 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1230 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1231 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1232 }
1233 }
1234 pMptCtx->MptRfPath = ODM_RF_PATH_B;
1235 break;
1236 case ANTENNA_AB:/*/ For 8192S*/
1237 p_ofdm_tx->r_tx_antenna = 0x3;
1238 r_ofdm_tx_en_val = 0x3;
1239 p_ofdm_tx->r_ant_l = 0x3;
1240 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1241 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1242 p_cck_txrx->r_ccktx_enable = 0xC;
1243 chgTx = 1;
1244 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1245 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1246 {
1247 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1248 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1249 /* Disable Power save*/
1250 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1251 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1252 if (pHalData->rf_type == RF_2T2R) {
1253 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1254
1255 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1256 /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1257 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1258 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1259 }
1260 }
1261 pMptCtx->MptRfPath = ODM_RF_PATH_AB;
1262 break;
1263 default:
1264 break;
1265 }
1266
1267
1268
1269 /*// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
1270 // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
1271 // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1272 switch (ulAntennaRx) {
1273 case ANTENNA_A:
1274 r_rx_antenna_ofdm = 0x1; /* A*/
1275 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1276 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1277 chgRx = 1;
1278 break;
1279 case ANTENNA_B:
1280 r_rx_antenna_ofdm = 0x2; /*/ B*/
1281 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1282 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1283 chgRx = 1;
1284 break;
1285 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1286 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1287 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1288 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1289 chgRx = 1;
1290 break;
1291 default:
1292 break;
1293 }
1294
1295
1296 if (chgTx && chgRx) {
1297 switch (pHalData->rf_chip) {
1298 case RF_8225:
1299 case RF_8256:
1300 case RF_6052:
1301 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1302 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1303 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1304 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1305 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1306 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1307 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1308 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1309 }
1310 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1311 break;
1312
1313 default:
1314 DBG_871X("Unsupported RFChipID for switching antenna.\n");
1315 break;
1316 }
1317 }
1318 } /* MPT_ProSetRFPath */
1319
1320
hal_mpt_SetAntenna(PADAPTER pAdapter)1321 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1322
1323 {
1324 DBG_871X("Do %s\n", __func__);
1325 #ifdef CONFIG_RTL8814A
1326 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1327 mpt_SetRFPath_8814A(pAdapter);
1328 return;
1329 }
1330 #endif
1331 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1332 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1333 mpt_SetRFPath_8812A(pAdapter);
1334 return;
1335 }
1336 #endif
1337 #ifdef CONFIG_RTL8723B
1338 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1339 mpt_SetRFPath_8723B(pAdapter);
1340 return;
1341 }
1342 #endif
1343 #ifdef CONFIG_RTL8188F
1344 if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
1345 mpt_SetRFPath_8188F(pAdapter);
1346 return;
1347 }
1348 #endif
1349 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1350 mpt_SetRFPath_8821B(pAdapter);
1351 Prepare for 8822B
1352 else if (IS_HARDWARE_TYPE_8822B(Context))
1353 mpt_SetRFPath_8822B(Context);
1354 */ mpt_SetRFPath_819X(pAdapter);
1355 DBG_871X("mpt_SetRFPath_819X Do %s\n", __func__);
1356
1357 }
1358
1359
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1360 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1361 {
1362 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1363
1364 if (!netif_running(pAdapter->pnetdev)) {
1365 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
1366 return _FAIL;
1367 }
1368
1369
1370 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1371 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
1372 return _FAIL;
1373 }
1374
1375
1376 target_ther &= 0xff;
1377 if (target_ther < 0x07)
1378 target_ther = 0x07;
1379 else if (target_ther > 0x1d)
1380 target_ther = 0x1d;
1381
1382 pHalData->EEPROMThermalMeter = target_ther;
1383
1384 return _SUCCESS;
1385 }
1386
1387
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1388 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1389 {
1390 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1391
1392 }
1393
1394
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)1395 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
1396
1397 {
1398 u32 ThermalValue = 0;
1399
1400 ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
1401 return (u8)ThermalValue;
1402
1403 }
1404
1405
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 * value)1406 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
1407 {
1408 #if 0
1409 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1410 rtw_msleep_os(1000);
1411 fw_cmd_data(pAdapter, value, 1);
1412 *value &= 0xFF;
1413 #else
1414 hal_mpt_TriggerRFThermalMeter(pAdapter);
1415 rtw_msleep_os(1000);
1416 *value = hal_mpt_ReadRFThermalMeter(pAdapter);
1417 #endif
1418
1419 }
1420
1421
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1422 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1423 {
1424 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1425
1426 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
1427
1428 if (bStart) {/*/ Start Single Carrier.*/
1429 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
1430 /*/ Start Single Carrier.*/
1431 /*/ 1. if OFDM block on?*/
1432 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1433 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1434
1435 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1436 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1437
1438 /*/ 3. turn on scramble setting*/
1439 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1440
1441 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1442 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
1443 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1444 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier);
1445 else
1446 #endif
1447 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier);
1448
1449 } else {
1450 /*/ Stop Single Carrier.*/
1451 /*/ Stop Single Carrier.*/
1452 /*/ Turn off all test modes.*/
1453 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
1454 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1455 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1456 else
1457 #endif
1458
1459 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1460
1461 rtw_msleep_os(10);
1462 /*/BB Reset*/
1463 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1464 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1465 }
1466 }
1467
1468
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1469 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1470 {
1471 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1472 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1473 u4Byte ulAntennaTx = pHalData->AntennaTxPath;
1474 static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1475 u8 rfPath;
1476
1477 switch (ulAntennaTx) {
1478 case ANTENNA_B:
1479 rfPath = ODM_RF_PATH_B;
1480 break;
1481 case ANTENNA_C:
1482 rfPath = ODM_RF_PATH_C;
1483 break;
1484 case ANTENNA_D:
1485 rfPath = ODM_RF_PATH_D;
1486 break;
1487 case ANTENNA_A:
1488 default:
1489 rfPath = ODM_RF_PATH_A;
1490 break;
1491 }
1492
1493 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
1494 if (bStart) {
1495 /*/ Start Single Tone.*/
1496 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1497 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1498 regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
1499
1500 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1501 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1502 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1503 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1504 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1505 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);
1506 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1507 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1508 } else if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
1509 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1510 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1511 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1512 } else {
1513 /*/ S0/S1 both use PATH A to configure*/
1514 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1515 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1516 }
1517 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1518 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1519 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1520 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1521 } else {
1522 /*/ S0/S1 both use PATH A to configure*/
1523 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1524 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1525 }
1526 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1527 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1528 u1Byte p = ODM_RF_PATH_A;
1529
1530 regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1531 regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1532 regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1533 regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord);
1534 regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord);
1535
1536 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); /*/ Disable CCK and OFDM*/
1537
1538 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1539 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1540 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1541 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1542 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1543 }
1544 } else {
1545 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1546 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1547 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1548 }
1549
1550 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1551 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1552
1553 if (pHalData->ExternalPA_5G) {
1554 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1555 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1556 } else if (pHalData->ExternalPA_2G) {
1557 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1558 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1559 }
1560 #endif
1561 }
1562 #ifdef CONFIG_RTL8814A
1563 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1564 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1565 #endif
1566 else /*/ Turn On SingleTone and turn off the other test modes.*/
1567 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone);
1568
1569 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1570 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1571
1572 } else {/*/ Stop Single Ton e.*/
1573
1574 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1575 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);
1576 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1577 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1578 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1579 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1580 PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */
1581 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1582 PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);
1583 } else if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
1584 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1585
1586 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1587 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1588 } else {
1589 /*/ S0/S1 both use PATH A to configure*/
1590 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1591 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1592 }
1593 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1594
1595 if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
1596 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1597 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1598 } else {
1599 /*/ S0/S1 both use PATH A to configure*/
1600 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1601 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1602 }
1603 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1604 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1605 u1Byte p = ODM_RF_PATH_A;
1606
1607 PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); /*/ Disable CCK and OFDM*/
1608
1609 if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
1610 for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
1611 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1612 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1613 }
1614 } else {
1615 PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
1616 PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
1617 }
1618
1619 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
1620 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
1621 PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB2);
1622 PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB3);
1623 #endif
1624 }
1625 #ifdef CONFIG_RTL8814A
1626 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1627 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
1628
1629 else/*/ Turn off all test modes.*/
1630 PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1631 #endif
1632 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1633 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1634
1635 }
1636 }
1637
1638
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1639 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1640 {
1641 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
1642 if (bStart) {/* Start Carrier Suppression.*/
1643 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
1644 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
1645 /*/ 1. if CCK block on?*/
1646 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1647 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1648
1649 /*/Turn Off All Test Mode*/
1650 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1651 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/* rSingleTone_ContTx_Jaguar*/
1652 else
1653 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1654
1655 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1656 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
1657
1658 /*/Set CCK Tx Test Rate*/
1659 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
1660 }
1661
1662 /*Set for dynamic set Power index*/
1663 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1664 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1665
1666 } else {/* Stop Carrier Suppression.*/
1667 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
1668
1669 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
1670 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
1671 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
1672
1673 /*BB Reset*/
1674 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1675 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1676 }
1677 /*Stop for dynamic set Power index*/
1678 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1679 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1680 }
1681 DBG_871X("\n MPT_ProSetCarrierSupp() is finished.\n");
1682 }
1683
hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter,u8 bStart)1684 void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
1685 {
1686 u32 cckrate;
1687
1688 if (bStart) {
1689 RT_TRACE(_module_mp_, _drv_alert_,
1690 ("SetCCKContinuousTx: test start\n"));
1691
1692 /*/ 1. if CCK block on?*/
1693 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
1694 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
1695
1696 /*/Turn Off All Test Mode*/
1697 if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
1698 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/*rSingleTone_ContTx_Jaguar*/
1699 else
1700 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1701
1702 /*/Set CCK Tx Test Rate*/
1703
1704 cckrate = pAdapter->mppriv.rateidx;
1705
1706 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
1707 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
1708 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1709
1710 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
1711 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/
1712 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
1713 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
1714 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
1715 }
1716
1717 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1718 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1719
1720 } else {
1721 RT_TRACE(_module_mp_, _drv_info_,
1722 ("SetCCKContinuousTx: test stop\n"));
1723
1724 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/
1725 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
1726
1727 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {
1728 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/
1729 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/
1730
1731 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
1732 PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
1733 }
1734
1735 /*/BB Reset*/
1736 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1737 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1738
1739 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1740 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1741 }
1742
1743 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
1744 pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
1745 }
1746
hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter,u8 bStart)1747 void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
1748 {
1749 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1750
1751 if (bStart) {
1752 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/
1753 if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1754 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/
1755
1756 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1757 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1758
1759 /*/ 3. turn on scramble setting*/
1760 PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
1761
1762 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1763 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/
1764 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
1765 }
1766
1767 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1768 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1769 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);/*rSingleTone_ContTx_Jaguar*/
1770 else
1771 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx);
1772
1773 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1774 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1775
1776 } else {
1777 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
1778 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
1779 PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);
1780 else
1781 PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF);
1782 /*/Delay 10 ms*/
1783 rtw_msleep_os(10);
1784
1785 if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
1786 PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/
1787 PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/
1788 }
1789
1790 /*/BB Reset*/
1791 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1792 PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1793
1794 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
1795 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
1796 }
1797
1798 pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
1799 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
1800 }
1801
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)1802 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1803 {
1804 RT_TRACE(_module_mp_, _drv_info_,
1805 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
1806
1807 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
1808
1809 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
1810 hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
1811 else if (pAdapter->mppriv.rateidx >= MPT_RATE_6M)
1812 hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
1813 }
1814
1815 #endif /* CONFIG_MP_INCLUDE*/
1816
1817