1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8188EPHYREG_H__ 17 #define __INC_HAL8188EPHYREG_H__ 18 /*--------------------------Define Parameters-------------------------------*/ 19 /* 20 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 21 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 22 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 23 * 3. RF register 0x00-2E 24 * 4. Bit Mask for BB/RF register 25 * 5. Other defintion for BB/RF R/W 26 * */ 27 28 29 /* 30 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 31 * 1. Page1(0x100) 32 * */ 33 #define rPMAC_Reset 0x100 34 #define rPMAC_TxStart 0x104 35 #define rPMAC_TxLegacySIG 0x108 36 #define rPMAC_TxHTSIG1 0x10c 37 #define rPMAC_TxHTSIG2 0x110 38 #define rPMAC_PHYDebug 0x114 39 #define rPMAC_TxPacketNum 0x118 40 #define rPMAC_TxIdle 0x11c 41 #define rPMAC_TxMACHeader0 0x120 42 #define rPMAC_TxMACHeader1 0x124 43 #define rPMAC_TxMACHeader2 0x128 44 #define rPMAC_TxMACHeader3 0x12c 45 #define rPMAC_TxMACHeader4 0x130 46 #define rPMAC_TxMACHeader5 0x134 47 #define rPMAC_TxDataType 0x138 48 #define rPMAC_TxRandomSeed 0x13c 49 #define rPMAC_CCKPLCPPreamble 0x140 50 #define rPMAC_CCKPLCPHeader 0x144 51 #define rPMAC_CCKCRC16 0x148 52 #define rPMAC_OFDMRxCRC32OK 0x170 53 #define rPMAC_OFDMRxCRC32Er 0x174 54 #define rPMAC_OFDMRxParityEr 0x178 55 #define rPMAC_OFDMRxCRC8Er 0x17c 56 #define rPMAC_CCKCRxRC16Er 0x180 57 #define rPMAC_CCKCRxRC32Er 0x184 58 #define rPMAC_CCKCRxRC32OK 0x188 59 #define rPMAC_TxStatus 0x18c 60 61 /* 62 * 2. Page2(0x200) 63 * 64 * The following two definition are only used for USB interface. */ 65 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 66 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 67 68 /* 69 * 3. Page8(0x800) 70 * */ 71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 72 73 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 74 #define rFPGA0_PSDFunction 0x808 75 76 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 77 78 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 79 #define rFPGA0_RFTiming2 0x814 80 81 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 82 #define rFPGA0_XA_HSSIParameter2 0x824 83 #define rFPGA0_XB_HSSIParameter1 0x828 84 #define rFPGA0_XB_HSSIParameter2 0x82c 85 86 #define rFPGA0_XA_LSSIParameter 0x840 87 #define rFPGA0_XB_LSSIParameter 0x844 88 89 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 90 #define rFPGA0_RFSleepUpParameter 0x854 91 92 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 93 #define rFPGA0_XCD_SwitchControl 0x85c 94 95 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 96 #define rFPGA0_XB_RFInterfaceOE 0x864 97 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 98 #define rFPGA0_XCD_RFInterfaceSW 0x874 99 100 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 101 #define rFPGA0_XCD_RFParameter 0x87c 102 103 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 104 #define rFPGA0_AnalogParameter2 0x884 105 #define rFPGA0_AnalogParameter3 0x888 106 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ 107 #define rFPGA0_AnalogParameter4 0x88c 108 109 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 110 #define rFPGA0_XB_LSSIReadBack 0x8a4 111 #define rFPGA0_XC_LSSIReadBack 0x8a8 112 #define rFPGA0_XD_LSSIReadBack 0x8ac 113 114 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 115 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 116 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 117 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 118 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 119 120 /* 121 * 4. Page9(0x900) 122 * */ 123 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 124 125 #define rFPGA1_TxBlock 0x904 /* Useless now */ 126 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 127 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 128 129 /* 130 * 5. PageA(0xA00) 131 * 132 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 133 #define rCCK0_System 0xa00 134 135 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 136 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 137 138 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 139 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 140 141 #define rCCK0_RxHP 0xa14 142 143 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 144 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 145 146 #define rCCK0_TxFilter1 0xa20 147 #define rCCK0_TxFilter2 0xa24 148 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 149 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 150 #define rCCK0_TRSSIReport 0xa50 151 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 152 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 153 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 154 155 /* 156 * PageB(0xB00) 157 * */ 158 #define rPdp_AntA 0xb00 159 #define rPdp_AntA_4 0xb04 160 #define rConfig_Pmpd_AntA 0xb28 161 #define rConfig_ram64x16 0xb2c 162 #define rConfig_AntA 0xb68 163 #define rConfig_AntB 0xb6c 164 #define rPdp_AntB 0xb70 165 #define rPdp_AntB_4 0xb74 166 #define rConfig_Pmpd_AntB 0xb98 167 #define rAPK 0xbd8 168 169 170 171 /* 172 * 6. PageC(0xC00) 173 * */ 174 #define rOFDM0_LSTF 0xc00 175 176 #define rOFDM0_TRxPathEnable 0xc04 177 #define rOFDM0_TRMuxPar 0xc08 178 #define rOFDM0_TRSWIsolation 0xc0c 179 180 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 181 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 182 #define rOFDM0_XBRxAFE 0xc18 183 #define rOFDM0_XBRxIQImbalance 0xc1c 184 #define rOFDM0_XCRxAFE 0xc20 185 #define rOFDM0_XCRxIQImbalance 0xc24 186 #define rOFDM0_XDRxAFE 0xc28 187 #define rOFDM0_XDRxIQImbalance 0xc2c 188 189 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 190 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 191 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 192 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 193 194 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 195 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 196 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 197 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 198 199 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 200 #define rOFDM0_XAAGCCore2 0xc54 201 #define rOFDM0_XBAGCCore1 0xc58 202 #define rOFDM0_XBAGCCore2 0xc5c 203 #define rOFDM0_XCAGCCore1 0xc60 204 #define rOFDM0_XCAGCCore2 0xc64 205 #define rOFDM0_XDAGCCore1 0xc68 206 #define rOFDM0_XDAGCCore2 0xc6c 207 208 #define rOFDM0_AGCParameter1 0xc70 209 #define rOFDM0_AGCParameter2 0xc74 210 #define rOFDM0_AGCRSSITable 0xc78 211 #define rOFDM0_HTSTFAGC 0xc7c 212 213 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 214 #define rOFDM0_XATxAFE 0xc84 215 #define rOFDM0_XBTxIQImbalance 0xc88 216 #define rOFDM0_XBTxAFE 0xc8c 217 #define rOFDM0_XCTxIQImbalance 0xc90 218 #define rOFDM0_XCTxAFE 0xc94 219 #define rOFDM0_XDTxIQImbalance 0xc98 220 #define rOFDM0_XDTxAFE 0xc9c 221 222 #define rOFDM0_RxIQExtAnta 0xca0 223 #define rOFDM0_TxCoeff1 0xca4 224 #define rOFDM0_TxCoeff2 0xca8 225 #define rOFDM0_TxCoeff3 0xcac 226 #define rOFDM0_TxCoeff4 0xcb0 227 #define rOFDM0_TxCoeff5 0xcb4 228 #define rOFDM0_TxCoeff6 0xcb8 229 #define rOFDM0_RxHPParameter 0xce0 230 #define rOFDM0_TxPseudoNoiseWgt 0xce4 231 #define rOFDM0_FrameSync 0xcf0 232 #define rOFDM0_DFSReport 0xcf4 233 234 235 /* 236 * 7. PageD(0xD00) 237 * */ 238 #define rOFDM1_LSTF 0xd00 239 #define rOFDM1_TRxPathEnable 0xd04 240 241 #define rOFDM1_CFO 0xd08 /* No setting now */ 242 #define rOFDM1_CSI1 0xd10 243 #define rOFDM1_SBD 0xd14 244 #define rOFDM1_CSI2 0xd18 245 #define rOFDM1_CFOTracking 0xd2c 246 #define rOFDM1_TRxMesaure1 0xd34 247 #define rOFDM1_IntfDet 0xd3c 248 #define rOFDM1_csi_fix_mask1 0xd40 249 #define rOFDM1_csi_fix_mask2 0xd44 250 #define rOFDM1_PseudoNoiseStateAB 0xd50 251 #define rOFDM1_PseudoNoiseStateCD 0xd54 252 #define rOFDM1_RxPseudoNoiseWgt 0xd58 253 254 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 255 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 256 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 257 258 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 259 #define rOFDM_ShortCFOCD 0xdb0 260 #define rOFDM_LongCFOAB 0xdb4 261 #define rOFDM_LongCFOCD 0xdb8 262 #define rOFDM_TailCFOAB 0xdbc 263 #define rOFDM_TailCFOCD 0xdc0 264 #define rOFDM_PWMeasure1 0xdc4 265 #define rOFDM_PWMeasure2 0xdc8 266 #define rOFDM_BWReport 0xdcc 267 #define rOFDM_AGCReport 0xdd0 268 #define rOFDM_RxSNR 0xdd4 269 #define rOFDM_RxEVMCSI 0xdd8 270 #define rOFDM_SIGReport 0xddc 271 272 273 /* 274 * 8. PageE(0xE00) 275 * */ 276 #define rTxAGC_A_Rate18_06 0xe00 277 #define rTxAGC_A_Rate54_24 0xe04 278 #define rTxAGC_A_CCK1_Mcs32 0xe08 279 #define rTxAGC_A_Mcs03_Mcs00 0xe10 280 #define rTxAGC_A_Mcs07_Mcs04 0xe14 281 #define rTxAGC_A_Mcs11_Mcs08 0xe18 282 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 283 284 #define rTxAGC_B_Rate18_06 0x830 285 #define rTxAGC_B_Rate54_24 0x834 286 #define rTxAGC_B_CCK1_55_Mcs32 0x838 287 #define rTxAGC_B_Mcs03_Mcs00 0x83c 288 #define rTxAGC_B_Mcs07_Mcs04 0x848 289 #define rTxAGC_B_Mcs11_Mcs08 0x84c 290 #define rTxAGC_B_Mcs15_Mcs12 0x868 291 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 292 293 #define rFPGA0_IQK 0xe28 294 #define rTx_IQK_Tone_A 0xe30 295 #define rRx_IQK_Tone_A 0xe34 296 #define rTx_IQK_PI_A 0xe38 297 #define rRx_IQK_PI_A 0xe3c 298 299 #define rTx_IQK 0xe40 300 #define rRx_IQK 0xe44 301 #define rIQK_AGC_Pts 0xe48 302 #define rIQK_AGC_Rsp 0xe4c 303 #define rTx_IQK_Tone_B 0xe50 304 #define rRx_IQK_Tone_B 0xe54 305 #define rTx_IQK_PI_B 0xe58 306 #define rRx_IQK_PI_B 0xe5c 307 #define rIQK_AGC_Cont 0xe60 308 309 #define rBlue_Tooth 0xe6c 310 #define rRx_Wait_CCA 0xe70 311 #define rTx_CCK_RFON 0xe74 312 #define rTx_CCK_BBON 0xe78 313 #define rTx_OFDM_RFON 0xe7c 314 #define rTx_OFDM_BBON 0xe80 315 #define rTx_To_Rx 0xe84 316 #define rTx_To_Tx 0xe88 317 #define rRx_CCK 0xe8c 318 319 #define rTx_Power_Before_IQK_A 0xe94 320 #define rTx_Power_After_IQK_A 0xe9c 321 322 #define rRx_Power_Before_IQK_A 0xea0 323 #define rRx_Power_Before_IQK_A_2 0xea4 324 #define rRx_Power_After_IQK_A 0xea8 325 #define rRx_Power_After_IQK_A_2 0xeac 326 327 #define rTx_Power_Before_IQK_B 0xeb4 328 #define rTx_Power_After_IQK_B 0xebc 329 330 #define rRx_Power_Before_IQK_B 0xec0 331 #define rRx_Power_Before_IQK_B_2 0xec4 332 #define rRx_Power_After_IQK_B 0xec8 333 #define rRx_Power_After_IQK_B_2 0xecc 334 335 #define rRx_OFDM 0xed0 336 #define rRx_Wait_RIFS 0xed4 337 #define rRx_TO_Rx 0xed8 338 #define rStandby 0xedc 339 #define rSleep 0xee0 340 #define rPMPD_ANAEN 0xeec 341 342 /* 343 * 7. RF Register 0x00-0x2E (RF 8256) 344 * RF-0222D 0x00-3F 345 * 346 * Zebra1 */ 347 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 348 #define rZebra1_TRxEnable1 0x1 349 #define rZebra1_TRxEnable2 0x2 350 #define rZebra1_AGC 0x4 351 #define rZebra1_ChargePump 0x5 352 #define rZebra1_Channel 0x7 /* RF channel switch */ 353 354 /* #endif */ 355 #define rZebra1_TxGain 0x8 /* Useless now */ 356 #define rZebra1_TxLPF 0x9 357 #define rZebra1_RxLPF 0xb 358 #define rZebra1_RxHPFCorner 0xc 359 360 /* Zebra4 */ 361 #define rGlobalCtrl 0 /* Useless now */ 362 #define rRTL8256_TxLPF 19 363 #define rRTL8256_RxLPF 11 364 365 /* RTL8258 */ 366 #define rRTL8258_TxLPF 0x11 /* Useless now */ 367 #define rRTL8258_RxLPF 0x13 368 #define rRTL8258_RSSILPF 0xa 369 370 /* 371 * RL6052 Register definition 372 * */ 373 #define RF_AC 0x00 /* */ 374 375 #define RF_IQADJ_G1 0x01 /* */ 376 #define RF_IQADJ_G2 0x02 /* */ 377 378 #define RF_POW_TRSW 0x05 /* */ 379 380 #define RF_GAIN_RX 0x06 /* */ 381 #define RF_GAIN_TX 0x07 /* */ 382 383 #define RF_TXM_IDAC 0x08 /* */ 384 #define RF_IPA_G 0x09 /* */ 385 #define RF_TXBIAS_G 0x0A 386 #define RF_TXPA_AG 0x0B 387 #define RF_IPA_A 0x0C /* */ 388 #define RF_TXBIAS_A 0x0D 389 #define RF_BS_PA_APSET_G9_G11 0x0E 390 #define RF_BS_IQGEN 0x0F /* */ 391 392 #define RF_MODE1 0x10 /* */ 393 #define RF_MODE2 0x11 /* */ 394 395 #define RF_RX_AGC_HP 0x12 /* */ 396 #define RF_TX_AGC 0x13 /* */ 397 #define RF_BIAS 0x14 /* */ 398 #define RF_IPA 0x15 /* */ 399 #define RF_TXBIAS 0x16 400 #define RF_POW_ABILITY 0x17 /* */ 401 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 402 #define RF_TOP 0x19 /* */ 403 404 #define RF_RX_G1 0x1A /* */ 405 #define RF_RX_G2 0x1B /* */ 406 407 #define RF_RX_BB2 0x1C /* */ 408 #define RF_RX_BB1 0x1D /* */ 409 410 #define RF_RCK1 0x1E /* */ 411 #define RF_RCK2 0x1F /* */ 412 413 #define RF_TX_G1 0x20 /* */ 414 #define RF_TX_G2 0x21 /* */ 415 #define RF_TX_G3 0x22 /* */ 416 417 #define RF_TX_BB1 0x23 /* */ 418 419 #define RF_T_METER_88E 0x42 /* */ 420 #define RF_T_METER 0x24 /* */ 421 422 #define RF_SYN_G1 0x25 /* RF TX Power control */ 423 #define RF_SYN_G2 0x26 /* RF TX Power control */ 424 #define RF_SYN_G3 0x27 /* RF TX Power control */ 425 #define RF_SYN_G4 0x28 /* RF TX Power control */ 426 #define RF_SYN_G5 0x29 /* RF TX Power control */ 427 #define RF_SYN_G6 0x2A /* RF TX Power control */ 428 #define RF_SYN_G7 0x2B /* RF TX Power control */ 429 #define RF_SYN_G8 0x2C /* RF TX Power control */ 430 431 #define RF_RCK_OS 0x30 /* RF TX PA control */ 432 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 433 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 434 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 435 #define RF_TX_BIAS_A 0x35 436 #define RF_TX_BIAS_D 0x36 437 #define RF_LOBF_9 0x38 438 #define RF_RXRF_A3 0x3C /* */ 439 #define RF_TRSW 0x3F 440 441 #define RF_TXRF_A2 0x41 442 #define RF_TXPA_G4 0x46 443 #define RF_TXPA_A4 0x4B 444 #define RF_0x52 0x52 445 #define RF_WE_LUT 0xEF 446 447 448 /* 449 * Bit Mask 450 * 451 * 1. Page1(0x100) */ 452 #define bBBResetB 0x100 /* Useless now? */ 453 #define bGlobalResetB 0x200 454 #define bOFDMTxStart 0x4 455 #define bCCKTxStart 0x8 456 #define bCRC32Debug 0x100 457 #define bPMACLoopback 0x10 458 #define bTxLSIG 0xffffff 459 #define bOFDMTxRate 0xf 460 #define bOFDMTxReserved 0x10 461 #define bOFDMTxLength 0x1ffe0 462 #define bOFDMTxParity 0x20000 463 #define bTxHTSIG1 0xffffff 464 #define bTxHTMCSRate 0x7f 465 #define bTxHTBW 0x80 466 #define bTxHTLength 0xffff00 467 #define bTxHTSIG2 0xffffff 468 #define bTxHTSmoothing 0x1 469 #define bTxHTSounding 0x2 470 #define bTxHTReserved 0x4 471 #define bTxHTAggreation 0x8 472 #define bTxHTSTBC 0x30 473 #define bTxHTAdvanceCoding 0x40 474 #define bTxHTShortGI 0x80 475 #define bTxHTNumberHT_LTF 0x300 476 #define bTxHTCRC8 0x3fc00 477 #define bCounterReset 0x10000 478 #define bNumOfOFDMTx 0xffff 479 #define bNumOfCCKTx 0xffff0000 480 #define bTxIdleInterval 0xffff 481 #define bOFDMService 0xffff0000 482 #define bTxMACHeader 0xffffffff 483 #define bTxDataInit 0xff 484 #define bTxHTMode 0x100 485 #define bTxDataType 0x30000 486 #define bTxRandomSeed 0xffffffff 487 #define bCCKTxPreamble 0x1 488 #define bCCKTxSFD 0xffff0000 489 #define bCCKTxSIG 0xff 490 #define bCCKTxService 0xff00 491 #define bCCKLengthExt 0x8000 492 #define bCCKTxLength 0xffff0000 493 #define bCCKTxCRC16 0xffff 494 #define bCCKTxStatus 0x1 495 #define bOFDMTxStatus 0x2 496 497 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 498 499 /* 2. Page8(0x800) */ 500 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 501 #define bJapanMode 0x2 502 #define bCCKTxSC 0x30 503 #define bCCKEn 0x1000000 504 #define bOFDMEn 0x2000000 505 506 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 507 #define bOFDMTxDACPhase 0x40000 508 #define bXATxAGC 0x3f 509 510 #define bAntennaSelect 0x0300 511 512 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 513 #define bXCTxAGC 0xf000 514 #define bXDTxAGC 0xf0000 515 516 #define bPAStart 0xf0000000 /* Useless now */ 517 #define bTRStart 0x00f00000 518 #define bRFStart 0x0000f000 519 #define bBBStart 0x000000f0 520 #define bBBCCKStart 0x0000000f 521 #define bPAEnd 0xf /* Reg0x814 */ 522 #define bTREnd 0x0f000000 523 #define bRFEnd 0x000f0000 524 #define bCCAMask 0x000000f0 /* T2R */ 525 #define bR2RCCAMask 0x00000f00 526 #define bHSSI_R2TDelay 0xf8000000 527 #define bHSSI_T2RDelay 0xf80000 528 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 529 #define bIGFromCCK 0x200 530 #define bAGCAddress 0x3f 531 #define bRxHPTx 0x7000 532 #define bRxHPT2R 0x38000 533 #define bRxHPCCKIni 0xc0000 534 #define bAGCTxCode 0xc00000 535 #define bAGCRxCode 0x300000 536 537 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 538 #define b3WireAddressLength 0x400 539 540 #define b3WireRFPowerDown 0x1 /* Useless now 541 * #define bHWSISelect 0x8 */ 542 #define b5GPAPEPolarity 0x40000000 543 #define b2GPAPEPolarity 0x80000000 544 #define bRFSW_TxDefaultAnt 0x3 545 #define bRFSW_TxOptionAnt 0x30 546 #define bRFSW_RxDefaultAnt 0x300 547 #define bRFSW_RxOptionAnt 0x3000 548 #define bRFSI_3WireData 0x1 549 #define bRFSI_3WireClock 0x2 550 #define bRFSI_3WireLoad 0x4 551 #define bRFSI_3WireRW 0x8 552 #define bRFSI_3Wire 0xf 553 554 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 555 556 #define bRFSI_TRSW 0x20 /* Useless now */ 557 #define bRFSI_TRSWB 0x40 558 #define bRFSI_ANTSW 0x100 559 #define bRFSI_ANTSWB 0x200 560 #define bRFSI_PAPE 0x400 561 #define bRFSI_PAPE5G 0x800 562 #define bBandSelect 0x1 563 #define bHTSIG2_GI 0x80 564 #define bHTSIG2_Smoothing 0x01 565 #define bHTSIG2_Sounding 0x02 566 #define bHTSIG2_Aggreaton 0x08 567 #define bHTSIG2_STBC 0x30 568 #define bHTSIG2_AdvCoding 0x40 569 #define bHTSIG2_NumOfHTLTF 0x300 570 #define bHTSIG2_CRC8 0x3fc 571 #define bHTSIG1_MCS 0x7f 572 #define bHTSIG1_BandWidth 0x80 573 #define bHTSIG1_HTLength 0xffff 574 #define bLSIG_Rate 0xf 575 #define bLSIG_Reserved 0x10 576 #define bLSIG_Length 0x1fffe 577 #define bLSIG_Parity 0x20 578 #define bCCKRxPhase 0x4 579 580 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 581 582 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 583 584 #define bLSSIReadBackData 0xfffff /* T65 RF */ 585 586 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 587 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 588 #define bRegulator0Standby 0x1 589 #define bRegulatorPLLStandby 0x2 590 #define bRegulator1Standby 0x4 591 #define bPLLPowerUp 0x8 592 #define bDPLLPowerUp 0x10 593 #define bDA10PowerUp 0x20 594 #define bAD7PowerUp 0x200 595 #define bDA6PowerUp 0x2000 596 #define bXtalPowerUp 0x4000 597 #define b40MDClkPowerUP 0x8000 598 #define bDA6DebugMode 0x20000 599 #define bDA6Swing 0x380000 600 601 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 602 603 #define b80MClkDelay 0x18000000 /* Useless */ 604 #define bAFEWatchDogEnable 0x20000000 605 606 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 607 #define bXtalCap23 0x3 608 #define bXtalCap92x 0x0f000000 609 #define bXtalCap 0x0f000000 610 611 #define bIntDifClkEnable 0x400 /* Useless */ 612 #define bExtSigClkEnable 0x800 613 #define bBandgapMbiasPowerUp 0x10000 614 #define bAD11SHGain 0xc0000 615 #define bAD11InputRange 0x700000 616 #define bAD11OPCurrent 0x3800000 617 #define bIPathLoopback 0x4000000 618 #define bQPathLoopback 0x8000000 619 #define bAFELoopback 0x10000000 620 #define bDA10Swing 0x7e0 621 #define bDA10Reverse 0x800 622 #define bDAClkSource 0x1000 623 #define bAD7InputRange 0x6000 624 #define bAD7Gain 0x38000 625 #define bAD7OutputCMMode 0x40000 626 #define bAD7InputCMMode 0x380000 627 #define bAD7Current 0xc00000 628 #define bRegulatorAdjust 0x7000000 629 #define bAD11PowerUpAtTx 0x1 630 #define bDA10PSAtTx 0x10 631 #define bAD11PowerUpAtRx 0x100 632 #define bDA10PSAtRx 0x1000 633 #define bCCKRxAGCFormat 0x200 634 #define bPSDFFTSamplepPoint 0xc000 635 #define bPSDAverageNum 0x3000 636 #define bIQPathControl 0xc00 637 #define bPSDFreq 0x3ff 638 #define bPSDAntennaPath 0x30 639 #define bPSDIQSwitch 0x40 640 #define bPSDRxTrigger 0x400000 641 #define bPSDTxTrigger 0x80000000 642 #define bPSDSineToneScale 0x7f000000 643 #define bPSDReport 0xffff 644 645 /* 3. Page9(0x900) */ 646 #define bOFDMTxSC 0x30000000 /* Useless */ 647 #define bCCKTxOn 0x1 648 #define bOFDMTxOn 0x2 649 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 650 #define bDebugItem 0xff /* reset debug page and LWord */ 651 #define bAntL 0x10 652 #define bAntNonHT 0x100 653 #define bAntHT1 0x1000 654 #define bAntHT2 0x10000 655 #define bAntHT1S1 0x100000 656 #define bAntNonHTS1 0x1000000 657 658 /* 4. PageA(0xA00) */ 659 #define bCCKBBMode 0x3 /* Useless */ 660 #define bCCKTxPowerSaving 0x80 661 #define bCCKRxPowerSaving 0x40 662 663 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 664 665 #define bCCKScramble 0x8 /* Useless */ 666 #define bCCKAntDiversity 0x8000 667 #define bCCKCarrierRecovery 0x4000 668 #define bCCKTxRate 0x3000 669 #define bCCKDCCancel 0x0800 670 #define bCCKISICancel 0x0400 671 #define bCCKMatchFilter 0x0200 672 #define bCCKEqualizer 0x0100 673 #define bCCKPreambleDetect 0x800000 674 #define bCCKFastFalseCCA 0x400000 675 #define bCCKChEstStart 0x300000 676 #define bCCKCCACount 0x080000 677 #define bCCKcs_lim 0x070000 678 #define bCCKBistMode 0x80000000 679 #define bCCKCCAMask 0x40000000 680 #define bCCKTxDACPhase 0x4 681 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 682 #define bCCKr_cp_mode0 0x0100 683 #define bCCKTxDCOffset 0xf0 684 #define bCCKRxDCOffset 0xf 685 #define bCCKCCAMode 0xc000 686 #define bCCKFalseCS_lim 0x3f00 687 #define bCCKCS_ratio 0xc00000 688 #define bCCKCorgBit_sel 0x300000 689 #define bCCKPD_lim 0x0f0000 690 #define bCCKNewCCA 0x80000000 691 #define bCCKRxHPofIG 0x8000 692 #define bCCKRxIG 0x7f00 693 #define bCCKLNAPolarity 0x800000 694 #define bCCKRx1stGain 0x7f0000 695 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 696 #define bCCKRxAGCSatLevel 0x1f000000 697 #define bCCKRxAGCSatCount 0xe0 698 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 699 #define bCCKFixedRxAGC 0x8000 700 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 701 #define bCCKAntennaPolarity 0x2000 702 #define bCCKTxFilterType 0x0c00 703 #define bCCKRxAGCReportType 0x0300 704 #define bCCKRxDAGCEn 0x80000000 705 #define bCCKRxDAGCPeriod 0x20000000 706 #define bCCKRxDAGCSatLevel 0x1f000000 707 #define bCCKTimingRecovery 0x800000 708 #define bCCKTxC0 0x3f0000 709 #define bCCKTxC1 0x3f000000 710 #define bCCKTxC2 0x3f 711 #define bCCKTxC3 0x3f00 712 #define bCCKTxC4 0x3f0000 713 #define bCCKTxC5 0x3f000000 714 #define bCCKTxC6 0x3f 715 #define bCCKTxC7 0x3f00 716 #define bCCKDebugPort 0xff0000 717 #define bCCKDACDebug 0x0f000000 718 #define bCCKFalseAlarmEnable 0x8000 719 #define bCCKFalseAlarmRead 0x4000 720 #define bCCKTRSSI 0x7f 721 #define bCCKRxAGCReport 0xfe 722 #define bCCKRxReport_AntSel 0x80000000 723 #define bCCKRxReport_MFOff 0x40000000 724 #define bCCKRxRxReport_SQLoss 0x20000000 725 #define bCCKRxReport_Pktloss 0x10000000 726 #define bCCKRxReport_Lockedbit 0x08000000 727 #define bCCKRxReport_RateError 0x04000000 728 #define bCCKRxReport_RxRate 0x03000000 729 #define bCCKRxFACounterLower 0xff 730 #define bCCKRxFACounterUpper 0xff000000 731 #define bCCKRxHPAGCStart 0xe000 732 #define bCCKRxHPAGCFinal 0x1c00 733 #define bCCKRxFalseAlarmEnable 0x8000 734 #define bCCKFACounterFreeze 0x4000 735 #define bCCKTxPathSel 0x10000000 736 #define bCCKDefaultRxPath 0xc000000 737 #define bCCKOptionRxPath 0x3000000 738 739 /* 5. PageC(0xC00) */ 740 #define bNumOfSTF 0x3 /* Useless */ 741 #define bShift_L 0xc0 742 #define bGI_TH 0xc 743 #define bRxPathA 0x1 744 #define bRxPathB 0x2 745 #define bRxPathC 0x4 746 #define bRxPathD 0x8 747 #define bTxPathA 0x1 748 #define bTxPathB 0x2 749 #define bTxPathC 0x4 750 #define bTxPathD 0x8 751 #define bTRSSIFreq 0x200 752 #define bADCBackoff 0x3000 753 #define bDFIRBackoff 0xc000 754 #define bTRSSILatchPhase 0x10000 755 #define bRxIDCOffset 0xff 756 #define bRxQDCOffset 0xff00 757 #define bRxDFIRMode 0x1800000 758 #define bRxDCNFType 0xe000000 759 #define bRXIQImb_A 0x3ff 760 #define bRXIQImb_B 0xfc00 761 #define bRXIQImb_C 0x3f0000 762 #define bRXIQImb_D 0xffc00000 763 #define bDC_dc_Notch 0x60000 764 #define bRxNBINotch 0x1f000000 765 #define bPD_TH 0xf 766 #define bPD_TH_Opt2 0xc000 767 #define bPWED_TH 0x700 768 #define bIfMF_Win_L 0x800 769 #define bPD_Option 0x1000 770 #define bMF_Win_L 0xe000 771 #define bBW_Search_L 0x30000 772 #define bwin_enh_L 0xc0000 773 #define bBW_TH 0x700000 774 #define bED_TH2 0x3800000 775 #define bBW_option 0x4000000 776 #define bRatio_TH 0x18000000 777 #define bWindow_L 0xe0000000 778 #define bSBD_Option 0x1 779 #define bFrame_TH 0x1c 780 #define bFS_Option 0x60 781 #define bDC_Slope_check 0x80 782 #define bFGuard_Counter_DC_L 0xe00 783 #define bFrame_Weight_Short 0x7000 784 #define bSub_Tune 0xe00000 785 #define bFrame_DC_Length 0xe000000 786 #define bSBD_start_offset 0x30000000 787 #define bFrame_TH_2 0x7 788 #define bFrame_GI2_TH 0x38 789 #define bGI2_Sync_en 0x40 790 #define bSarch_Short_Early 0x300 791 #define bSarch_Short_Late 0xc00 792 #define bSarch_GI2_Late 0x70000 793 #define bCFOAntSum 0x1 794 #define bCFOAcc 0x2 795 #define bCFOStartOffset 0xc 796 #define bCFOLookBack 0x70 797 #define bCFOSumWeight 0x80 798 #define bDAGCEnable 0x10000 799 #define bTXIQImb_A 0x3ff 800 #define bTXIQImb_B 0xfc00 801 #define bTXIQImb_C 0x3f0000 802 #define bTXIQImb_D 0xffc00000 803 #define bTxIDCOffset 0xff 804 #define bTxQDCOffset 0xff00 805 #define bTxDFIRMode 0x10000 806 #define bTxPesudoNoiseOn 0x4000000 807 #define bTxPesudoNoise_A 0xff 808 #define bTxPesudoNoise_B 0xff00 809 #define bTxPesudoNoise_C 0xff0000 810 #define bTxPesudoNoise_D 0xff000000 811 #define bCCADropOption 0x20000 812 #define bCCADropThres 0xfff00000 813 #define bEDCCA_H 0xf 814 #define bEDCCA_L 0xf0 815 #define bLambda_ED 0x300 816 #define bRxInitialGain 0x7f 817 #define bRxAntDivEn 0x80 818 #define bRxAGCAddressForLNA 0x7f00 819 #define bRxHighPowerFlow 0x8000 820 #define bRxAGCFreezeThres 0xc0000 821 #define bRxFreezeStep_AGC1 0x300000 822 #define bRxFreezeStep_AGC2 0xc00000 823 #define bRxFreezeStep_AGC3 0x3000000 824 #define bRxFreezeStep_AGC0 0xc000000 825 #define bRxRssi_Cmp_En 0x10000000 826 #define bRxQuickAGCEn 0x20000000 827 #define bRxAGCFreezeThresMode 0x40000000 828 #define bRxOverFlowCheckType 0x80000000 829 #define bRxAGCShift 0x7f 830 #define bTRSW_Tri_Only 0x80 831 #define bPowerThres 0x300 832 #define bRxAGCEn 0x1 833 #define bRxAGCTogetherEn 0x2 834 #define bRxAGCMin 0x4 835 #define bRxHP_Ini 0x7 836 #define bRxHP_TRLNA 0x70 837 #define bRxHP_RSSI 0x700 838 #define bRxHP_BBP1 0x7000 839 #define bRxHP_BBP2 0x70000 840 #define bRxHP_BBP3 0x700000 841 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 842 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 843 #define bRxSettle_TRSW 0x7 844 #define bRxSettle_LNA 0x38 845 #define bRxSettle_RSSI 0x1c0 846 #define bRxSettle_BBP 0xe00 847 #define bRxSettle_RxHP 0x7000 848 #define bRxSettle_AntSW_RSSI 0x38000 849 #define bRxSettle_AntSW 0xc0000 850 #define bRxProcessTime_DAGC 0x300000 851 #define bRxSettle_HSSI 0x400000 852 #define bRxProcessTime_BBPPW 0x800000 853 #define bRxAntennaPowerShift 0x3000000 854 #define bRSSITableSelect 0xc000000 855 #define bRxHP_Final 0x7000000 856 #define bRxHTSettle_BBP 0x7 857 #define bRxHTSettle_HSSI 0x8 858 #define bRxHTSettle_RxHP 0x70 859 #define bRxHTSettle_BBPPW 0x80 860 #define bRxHTSettle_Idle 0x300 861 #define bRxHTSettle_Reserved 0x1c00 862 #define bRxHTRxHPEn 0x8000 863 #define bRxHTAGCFreezeThres 0x30000 864 #define bRxHTAGCTogetherEn 0x40000 865 #define bRxHTAGCMin 0x80000 866 #define bRxHTAGCEn 0x100000 867 #define bRxHTDAGCEn 0x200000 868 #define bRxHTRxHP_BBP 0x1c00000 869 #define bRxHTRxHP_Final 0xe0000000 870 #define bRxPWRatioTH 0x3 871 #define bRxPWRatioEn 0x4 872 #define bRxMFHold 0x3800 873 #define bRxPD_Delay_TH1 0x38 874 #define bRxPD_Delay_TH2 0x1c0 875 #define bRxPD_DC_COUNT_MAX 0x600 876 /* #define bRxMF_Hold 0x3800 */ 877 #define bRxPD_Delay_TH 0x8000 878 #define bRxProcess_Delay 0xf0000 879 #define bRxSearchrange_GI2_Early 0x700000 880 #define bRxFrame_Guard_Counter_L 0x3800000 881 #define bRxSGI_Guard_L 0xc000000 882 #define bRxSGI_Search_L 0x30000000 883 #define bRxSGI_TH 0xc0000000 884 #define bDFSCnt0 0xff 885 #define bDFSCnt1 0xff00 886 #define bDFSFlag 0xf0000 887 #define bMFWeightSum 0x300000 888 #define bMinIdxTH 0x7f000000 889 #define bDAFormat 0x40000 890 #define bTxChEmuEnable 0x01000000 891 #define bTRSWIsolation_A 0x7f 892 #define bTRSWIsolation_B 0x7f00 893 #define bTRSWIsolation_C 0x7f0000 894 #define bTRSWIsolation_D 0x7f000000 895 #define bExtLNAGain 0x7c00 896 897 /* 6. PageE(0xE00) */ 898 #define bSTBCEn 0x4 /* Useless */ 899 #define bAntennaMapping 0x10 900 #define bNss 0x20 901 #define bCFOAntSumD 0x200 902 #define bPHYCounterReset 0x8000000 903 #define bCFOReportGet 0x4000000 904 #define bOFDMContinueTx 0x10000000 905 #define bOFDMSingleCarrier 0x20000000 906 #define bOFDMSingleTone 0x40000000 907 /* #define bRxPath1 0x01 */ 908 /* #define bRxPath2 0x02 */ 909 /* #define bRxPath3 0x04 */ 910 /* #define bRxPath4 0x08 */ 911 /* #define bTxPath1 0x10 */ 912 /* #define bTxPath2 0x20 */ 913 #define bHTDetect 0x100 914 #define bCFOEn 0x10000 915 #define bCFOValue 0xfff00000 916 #define bSigTone_Re 0x3f 917 #define bSigTone_Im 0x7f00 918 #define bCounter_CCA 0xffff 919 #define bCounter_ParityFail 0xffff0000 920 #define bCounter_RateIllegal 0xffff 921 #define bCounter_CRC8Fail 0xffff0000 922 #define bCounter_MCSNoSupport 0xffff 923 #define bCounter_FastSync 0xffff 924 #define bShortCFO 0xfff 925 #define bShortCFOTLength 12 /* total */ 926 #define bShortCFOFLength 11 /* fraction */ 927 #define bLongCFO 0x7ff 928 #define bLongCFOTLength 11 929 #define bLongCFOFLength 11 930 #define bTailCFO 0x1fff 931 #define bTailCFOTLength 13 932 #define bTailCFOFLength 12 933 #define bmax_en_pwdB 0xffff 934 #define bCC_power_dB 0xffff0000 935 #define bnoise_pwdB 0xffff 936 #define bPowerMeasTLength 10 937 #define bPowerMeasFLength 3 938 #define bRx_HT_BW 0x1 939 #define bRxSC 0x6 940 #define bRx_HT 0x8 941 #define bNB_intf_det_on 0x1 942 #define bIntf_win_len_cfg 0x30 943 #define bNB_Intf_TH_cfg 0x1c0 944 #define bRFGain 0x3f 945 #define bTableSel 0x40 946 #define bTRSW 0x80 947 #define bRxSNR_A 0xff 948 #define bRxSNR_B 0xff00 949 #define bRxSNR_C 0xff0000 950 #define bRxSNR_D 0xff000000 951 #define bSNREVMTLength 8 952 #define bSNREVMFLength 1 953 #define bCSI1st 0xff 954 #define bCSI2nd 0xff00 955 #define bRxEVM1st 0xff0000 956 #define bRxEVM2nd 0xff000000 957 #define bSIGEVM 0xff 958 #define bPWDB 0xff00 959 #define bSGIEN 0x10000 960 961 #define bSFactorQAM1 0xf /* Useless */ 962 #define bSFactorQAM2 0xf0 963 #define bSFactorQAM3 0xf00 964 #define bSFactorQAM4 0xf000 965 #define bSFactorQAM5 0xf0000 966 #define bSFactorQAM6 0xf0000 967 #define bSFactorQAM7 0xf00000 968 #define bSFactorQAM8 0xf000000 969 #define bSFactorQAM9 0xf0000000 970 #define bCSIScheme 0x100000 971 972 #define bNoiseLvlTopSet 0x3 /* Useless */ 973 #define bChSmooth 0x4 974 #define bChSmoothCfg1 0x38 975 #define bChSmoothCfg2 0x1c0 976 #define bChSmoothCfg3 0xe00 977 #define bChSmoothCfg4 0x7000 978 #define bMRCMode 0x800000 979 #define bTHEVMCfg 0x7000000 980 981 #define bLoopFitType 0x1 /* Useless */ 982 #define bUpdCFO 0x40 983 #define bUpdCFOOffData 0x80 984 #define bAdvUpdCFO 0x100 985 #define bAdvTimeCtrl 0x800 986 #define bUpdClko 0x1000 987 #define bFC 0x6000 988 #define bTrackingMode 0x8000 989 #define bPhCmpEnable 0x10000 990 #define bUpdClkoLTF 0x20000 991 #define bComChCFO 0x40000 992 #define bCSIEstiMode 0x80000 993 #define bAdvUpdEqz 0x100000 994 #define bUChCfg 0x7000000 995 #define bUpdEqz 0x8000000 996 997 /* Rx Pseduo noise */ 998 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 999 #define bRxPesudoNoise_A 0xff 1000 #define bRxPesudoNoise_B 0xff00 1001 #define bRxPesudoNoise_C 0xff0000 1002 #define bRxPesudoNoise_D 0xff000000 1003 #define bPesudoNoiseState_A 0xffff 1004 #define bPesudoNoiseState_B 0xffff0000 1005 #define bPesudoNoiseState_C 0xffff 1006 #define bPesudoNoiseState_D 0xffff0000 1007 1008 /* 7. RF Register 1009 * Zebra1 */ 1010 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1011 #define bZebra1_TRxControl 0xc00 1012 #define bZebra1_TRxGainSetting 0x07f 1013 #define bZebra1_RxCorner 0xc00 1014 #define bZebra1_TxChargePump 0x38 1015 #define bZebra1_RxChargePump 0x7 1016 #define bZebra1_ChannelNum 0xf80 1017 #define bZebra1_TxLPFBW 0x400 1018 #define bZebra1_RxLPFBW 0x600 1019 1020 /* Zebra4 */ 1021 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1022 #define bRTL8256RegModeCtrl0 0x40 1023 #define bRTL8256_TxLPFBW 0x18 1024 #define bRTL8256_RxLPFBW 0x600 1025 1026 /* RTL8258 */ 1027 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1028 #define bRTL8258_RxLPFBW 0xc00 1029 #define bRTL8258_RSSILPFBW 0xc0 1030 1031 1032 /* 1033 * Other Definition 1034 * */ 1035 1036 /* byte endable for sb_write */ 1037 #define bByte0 0x1 /* Useless */ 1038 #define bByte1 0x2 1039 #define bByte2 0x4 1040 #define bByte3 0x8 1041 #define bWord0 0x3 1042 #define bWord1 0xc 1043 #define bDWord 0xf 1044 1045 /* for PutRegsetting & GetRegSetting BitMask */ 1046 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1047 #define bMaskByte1 0xff00 1048 #define bMaskByte2 0xff0000 1049 #define bMaskByte3 0xff000000 1050 #define bMaskHWord 0xffff0000 1051 #define bMaskLWord 0x0000ffff 1052 #define bMaskDWord 0xffffffff 1053 #define bMaskH3Bytes 0xffffff00 1054 #define bMask12Bits 0xfff 1055 #define bMaskH4Bits 0xf0000000 1056 #define bMaskOFDM_D 0xffc00000 1057 #define bMaskCCK 0x3f3f3f3f 1058 1059 1060 1061 #define bEnable 0x1 /* Useless */ 1062 #define bDisable 0x0 1063 1064 #define LeftAntenna 0x0 /* Useless */ 1065 #define RightAntenna 0x1 1066 1067 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1068 #define tUpdateRxCounter 100 /* 100ms */ 1069 1070 #define rateCCK 0 /* Useless */ 1071 #define rateOFDM 1 1072 #define rateHT 2 1073 1074 /* define Register-End */ 1075 #define bPMAC_End 0x1ff /* Useless */ 1076 #define bFPGAPHY0_End 0x8ff 1077 #define bFPGAPHY1_End 0x9ff 1078 #define bCCKPHY0_End 0xaff 1079 #define bOFDMPHY0_End 0xcff 1080 #define bOFDMPHY1_End 0xdff 1081 1082 /* define max debug item in each debug page 1083 * #define bMaxItem_FPGA_PHY0 0x9 1084 * #define bMaxItem_FPGA_PHY1 0x3 1085 * #define bMaxItem_PHY_11B 0x16 1086 * #define bMaxItem_OFDM_PHY0 0x29 1087 * #define bMaxItem_OFDM_PHY1 0x0 */ 1088 1089 #define bPMACControl 0x0 /* Useless */ 1090 #define bWMACControl 0x1 1091 #define bWNICControl 0x2 1092 1093 #define PathA 0x0 /* Useless */ 1094 #define PathB 0x1 1095 #define PathC 0x2 1096 #define PathD 0x3 1097 1098 /*--------------------------Define Parameters-------------------------------*/ 1099 1100 1101 #endif 1102