1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in the
16 * file called LICENSE.
17 *
18 * Contact Information:
19 * wlanfae <wlanfae@realtek.com>
20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
21 * Hsinchu 300, Taiwan.
22 *
23 * Larry Finger <Larry.Finger@lwfinger.net>
24 *
25 *****************************************************************************/
26
27 /*@************************************************************
28 * include files
29 ************************************************************/
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 const u16 phy_rate_table[] = {
35 /*@20M*/
36 1, 2, 5, 11,
37 6, 9, 12, 18, 24, 36, 48, 54,
38 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
39 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
40 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
41 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
42 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
43 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
44 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
45 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
46 };
47
phydm_traffic_load_decision(void * dm_void)48 void phydm_traffic_load_decision(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51 u8 shift = 0;
52
53 /*@---TP & Trafic-load calculation---*/
54
55 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
56 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
57
58 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
59 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
60
61 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
62 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
63 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
64 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
65
66 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
67 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
68 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
69
70 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
71 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
72
73 dm->total_tp = dm->tx_tp + dm->rx_tp;
74
75 /*@[Calculate TX/RX state]*/
76 if (dm->tx_tp > (dm->rx_tp << 1))
77 dm->txrx_state_all = TX_STATE;
78 else if (dm->rx_tp > (dm->tx_tp << 1))
79 dm->txrx_state_all = RX_STATE;
80 else
81 dm->txrx_state_all = BI_DIRECTION_STATE;
82
83 /*@[Traffic load decision]*/
84 dm->pre_traffic_load = dm->traffic_load;
85
86 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
87 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
88 dm->traffic_load = TRAFFIC_HIGH;
89 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
90 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
91 dm->traffic_load = TRAFFIC_MID;
92 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
93 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
94 dm->traffic_load = TRAFFIC_LOW;
95 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
96 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
97 dm->traffic_load = TRAFFIC_ULTRA_LOW;
98 } else {
99 dm->traffic_load = TRAFFIC_NO_TP;
100 }
101
102 /*@[Calculate consecutive idlel time]*/
103 if (dm->traffic_load == 0)
104 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
105 else
106 dm->consecutive_idlel_time = 0;
107
108 #if 0
109 PHYDM_DBG(dm, DBG_COMMON_FLOW,
110 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
111 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
112 dm->last_rx_ok_cnt);
113
114 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
115 dm->rx_tp);
116 #endif
117 }
118
phydm_cck_new_agc_chk(struct dm_struct * dm)119 void phydm_cck_new_agc_chk(struct dm_struct *dm)
120 {
121 dm->cck_new_agc = 0;
122
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT)
127 if (dm->support_ic_type &
128 (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F |
129 ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B | ODM_RTL8721D)) {
130 /*@1: new agc 0: old agc*/
131 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17));
132 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
133 /*@1: new agc 0: old agc*/
134 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c,
135 BIT(17));
136 }
137 #endif
138 }
139
140 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)141 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
142 {
143 boolean report_type = 0;
144 #if (RTL8192E_SUPPORT)
145 u32 value_824, value_82c;
146 #endif
147
148 #if (RTL8192E_SUPPORT)
149 if (dm->support_ic_type & (ODM_RTL8192E)) {
150 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
151 * should be equal or CCK RSSI report may be incorrect
152 */
153 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
154 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
155
156 if (value_824 != value_82c)
157 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
158 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
159 report_type = (boolean)value_824;
160 }
161 #endif
162
163 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
164 if (dm->support_ic_type &
165 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
166 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
167
168 if (report_type != 1)
169 pr_debug("[Warning] CCK should be 4bit LNA\n");
170 }
171 #endif
172
173 #if (RTL8821C_SUPPORT)
174 if (dm->support_ic_type & ODM_RTL8821C) {
175 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
176 report_type = 1;
177 }
178 #endif
179
180 dm->cck_agc_report_type = report_type;
181
182 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
183 dm->cck_agc_report_type);
184 }
185
phydm_init_cck_setting(struct dm_struct * dm)186 void phydm_init_cck_setting(struct dm_struct *dm)
187 {
188 u32 reg_tmp = 0;
189 u32 mask_tmp = 0;
190
191 phydm_cck_new_agc_chk(dm);
192
193 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
194 return;
195
196 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
197 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
198 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
199
200 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
201
202 phydm_config_cck_rx_antenna_init(dm);
203
204 if (dm->support_ic_type & ODM_RTL8192F)
205 phydm_config_cck_rx_path(dm, BB_PATH_AB);
206 else if (dm->valid_path_set == BB_PATH_A)
207 phydm_config_cck_rx_path(dm, BB_PATH_A);
208 else if (dm->valid_path_set == BB_PATH_B)
209 phydm_config_cck_rx_path(dm, BB_PATH_B);
210
211 phydm_cck_lna_bit_num_chk(dm);
212 phydm_get_cck_rssi_table_from_reg(dm);
213 }
214
phydm_init_hw_info_by_rfe(struct dm_struct * dm)215 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
216 {
217 #if (RTL8822B_SUPPORT)
218 /*@if (dm->support_ic_type & ODM_RTL8822B)*/
219 /*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/
220 #endif
221 #if (RTL8821C_SUPPORT)
222 if (dm->support_ic_type & ODM_RTL8821C)
223 phydm_init_hw_info_by_rfe_type_8821c(dm);
224 #endif
225 #if (RTL8197F_SUPPORT)
226 if (dm->support_ic_type & ODM_RTL8197F)
227 phydm_init_hw_info_by_rfe_type_8197f(dm);
228 #endif
229 }
230
phydm_common_info_self_init(struct dm_struct * dm)231 void phydm_common_info_self_init(struct dm_struct *dm)
232 {
233 u32 reg_tmp = 0;
234 u32 mask_tmp = 0;
235
236 dm->run_in_drv_fw = RUN_IN_DRIVER;
237
238 /*@BB IP Generation*/
239 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
240 dm->ic_ip_series = PHYDM_IC_JGR3;
241 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
242 dm->ic_ip_series = PHYDM_IC_AC;
243 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
244 dm->ic_ip_series = PHYDM_IC_N;
245
246 /*@BB phy-status Generation*/
247 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
248 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
249 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
250 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
251 else
252 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
253
254 phydm_init_cck_setting(dm);
255
256 reg_tmp = ODM_REG(BB_RX_PATH, dm);
257 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
258 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
259 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
260 dm->is_net_closed = &dm->BOOLEAN_temp;
261
262 phydm_init_debug_setting(dm);
263 #endif
264 phydm_init_soft_ml_setting(dm);
265
266 dm->phydm_sys_up_time = 0;
267
268 if (dm->support_ic_type & ODM_IC_1SS)
269 dm->num_rf_path = 1;
270 else if (dm->support_ic_type & ODM_IC_2SS)
271 dm->num_rf_path = 2;
272 #if 0
273 /* @RTK do not has IC which is equipped with 3 RF paths,
274 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
275 */
276 else if (dm->support_ic_type & ODM_IC_3SS)
277 dm->num_rf_path = 3;
278 #endif
279 else if (dm->support_ic_type & ODM_IC_4SS)
280 dm->num_rf_path = 4;
281 else
282 dm->num_rf_path = 1;
283
284 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
285
286 dm->tx_rate = 0xFF;
287 dm->rssi_min_by_path = 0xFF;
288
289 dm->number_linked_client = 0;
290 dm->pre_number_linked_client = 0;
291 dm->number_active_client = 0;
292 dm->pre_number_active_client = 0;
293
294 dm->last_tx_ok_cnt = 0;
295 dm->last_rx_ok_cnt = 0;
296 dm->tx_tp = 0;
297 dm->rx_tp = 0;
298 dm->total_tp = 0;
299 dm->traffic_load = TRAFFIC_LOW;
300
301 dm->nbi_set_result = 0;
302 dm->is_init_hw_info_by_rfe = false;
303 dm->pre_dbg_priority = DBGPORT_RELEASE;
304 dm->tp_active_th = 5;
305 dm->disable_phydm_watchdog = 0;
306
307 dm->u8_dummy = 0xf;
308 dm->u16_dummy = 0xffff;
309 dm->u32_dummy = 0xffffffff;
310
311 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
312 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
313 dm->pre_is_linked = false;
314 dm->is_linked = false;
315
316 if (!(dm->is_fcs_mode_enable)) {
317 dm->is_fcs_mode_enable = &dm->boolean_dummy;
318 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
319 }
320 }
321
phydm_cmn_sta_info_update(void * dm_void,u8 macid)322 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
323 {
324 struct dm_struct *dm = (struct dm_struct *)dm_void;
325 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
326 struct ra_sta_info *ra = NULL;
327
328 if (is_sta_active(sta)) {
329 ra = &sta->ra_info;
330 } else {
331 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
332 __func__);
333 return;
334 }
335
336 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
337 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
338
339 /*@[Calculate TX/RX state]*/
340 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
341 ra->txrx_state = TX_STATE;
342 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
343 ra->txrx_state = RX_STATE;
344 else
345 ra->txrx_state = BI_DIRECTION_STATE;
346
347 ra->is_noisy = dm->noisy_decision;
348 }
349
phydm_common_info_self_update(struct dm_struct * dm)350 void phydm_common_info_self_update(struct dm_struct *dm)
351 {
352 u8 sta_cnt = 0, num_active_client = 0;
353 u32 i, one_entry_macid = 0;
354 u32 ma_rx_tp = 0;
355 u32 tp_diff = 0;
356 struct cmn_sta_info *sta;
357 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
358 PADAPTER adapter = (PADAPTER)dm->adapter;
359 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
360
361 sta = dm->phydm_sta_info[0];
362 if (mgnt_info->mAssoc) {
363 sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
364 for (i = 0; i < 6; i++)
365 sta->mac_addr[i] = mgnt_info->Bssid[i];
366 } else if (GetFirstClientPort(adapter)) {
367 struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
368
369 sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
370 for (i = 0; i < 6; i++)
371 sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
372 } else {
373 sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
374 for (i = 0; i < 6; i++)
375 sta->mac_addr[i] = 0;
376 }
377
378 /* STA mode is linked to AP */
379 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
380 dm->bsta_state = true;
381 else
382 dm->bsta_state = false;
383 #endif
384
385 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
386 sta = dm->phydm_sta_info[i];
387 if (is_sta_active(sta)) {
388 sta_cnt++;
389
390 if (sta_cnt == 1)
391 one_entry_macid = i;
392
393 phydm_cmn_sta_info_update(dm, (u8)i);
394 #ifdef PHYDM_BEAMFORMING_SUPPORT
395 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
396 #endif
397
398 ma_rx_tp = sta->rx_moving_average_tp +
399 sta->tx_moving_average_tp;
400
401 PHYDM_DBG(dm, DBG_COMMON_FLOW,
402 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
403
404 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
405 num_active_client++;
406 }
407 }
408
409 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
410 dm->is_linked = (sta_cnt != 0) ? true : false;
411 #endif
412
413 if (sta_cnt == 1) {
414 dm->is_one_entry_only = true;
415 dm->one_entry_macid = one_entry_macid;
416 dm->one_entry_tp = ma_rx_tp;
417
418 dm->tp_active_occur = 0;
419
420 PHYDM_DBG(dm, DBG_COMMON_FLOW,
421 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
422 dm->one_entry_tp, dm->pre_one_entry_tp);
423
424 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
425 dm->pre_one_entry_tp <= 2) {
426 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
427
428 if (tp_diff > dm->tp_active_th)
429 dm->tp_active_occur = 1;
430 }
431 dm->pre_one_entry_tp = dm->one_entry_tp;
432 } else {
433 dm->is_one_entry_only = false;
434 }
435
436 dm->pre_number_linked_client = dm->number_linked_client;
437 dm->pre_number_active_client = dm->number_active_client;
438
439 dm->number_linked_client = sta_cnt;
440 dm->number_active_client = num_active_client;
441
442 /*Traffic load information update*/
443 phydm_traffic_load_decision(dm);
444
445 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
446
447 dm->is_dfs_band = phydm_is_dfs_band(dm);
448 dm->phy_dbg_info.show_phy_sts_cnt = 0;
449
450 /*[Link Status Check]*/
451 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
452 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
453 dm->pre_is_linked = dm->is_linked;
454 }
455
phydm_common_info_self_reset(struct dm_struct * dm)456 void phydm_common_info_self_reset(struct dm_struct *dm)
457 {
458 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
459
460 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
461 dbg_t->num_qry_beacon_pkt = 0;
462
463 dm->rxsc_l = 0xff;
464 dm->rxsc_20 = 0xff;
465 dm->rxsc_40 = 0xff;
466 dm->rxsc_80 = 0xff;
467 }
468
469 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)470 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
471
472 {
473 void *structure = NULL;
474
475 switch (structure_type) {
476 case PHYDM_FALSEALMCNT:
477 structure = &dm->false_alm_cnt;
478 break;
479
480 case PHYDM_CFOTRACK:
481 structure = &dm->dm_cfo_track;
482 break;
483
484 case PHYDM_ADAPTIVITY:
485 structure = &dm->adaptivity;
486 break;
487
488 case PHYDM_DFS:
489 structure = &dm->dfs;
490 break;
491
492 default:
493 break;
494 }
495
496 return structure;
497 }
498
phydm_phy_info_update(struct dm_struct * dm)499 void phydm_phy_info_update(struct dm_struct *dm)
500 {
501 #if (RTL8822B_SUPPORT == 1)
502 if (dm->support_ic_type == ODM_RTL8822B)
503 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
504 #endif
505 }
506
phydm_hw_setting(struct dm_struct * dm)507 void phydm_hw_setting(struct dm_struct *dm)
508 {
509 #if (RTL8821A_SUPPORT == 1)
510 if (dm->support_ic_type & ODM_RTL8821)
511 odm_hw_setting_8821a(dm);
512 #endif
513
514 #if (RTL8814A_SUPPORT == 1)
515 if (dm->support_ic_type & ODM_RTL8814A)
516 phydm_hwsetting_8814a(dm);
517 #endif
518
519 #if (RTL8822B_SUPPORT == 1)
520 if (dm->support_ic_type & ODM_RTL8822B)
521 phydm_hwsetting_8822b(dm);
522 #endif
523
524 #if (RTL8812A_SUPPORT == 1)
525 if (dm->support_ic_type & ODM_RTL8812)
526 phydm_hwsetting_8812a(dm);
527 #endif
528
529 #if (RTL8197F_SUPPORT == 1)
530 if (dm->support_ic_type & ODM_RTL8197F)
531 phydm_hwsetting_8197f(dm);
532 #endif
533
534 #if (RTL8192F_SUPPORT == 1)
535 if (dm->support_ic_type & ODM_RTL8192F)
536 phydm_hwsetting_8192f(dm);
537 #endif
538 }
539
540 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)541 u64 phydm_supportability_init_win(
542 void *dm_void)
543 {
544 struct dm_struct *dm = (struct dm_struct *)dm_void;
545 u64 support_ability = 0;
546
547 switch (dm->support_ic_type) {
548 /*@---------------N Series--------------------*/
549 #if (RTL8188E_SUPPORT)
550 case ODM_RTL8188E:
551 support_ability |=
552 ODM_BB_DIG |
553 ODM_BB_RA_MASK |
554 /*ODM_BB_DYNAMIC_TXPWR |*/
555 ODM_BB_FA_CNT |
556 ODM_BB_RSSI_MONITOR |
557 ODM_BB_CCK_PD |
558 /*ODM_BB_PWR_TRAIN |*/
559 ODM_BB_RATE_ADAPTIVE |
560 ODM_BB_CFO_TRACKING |
561 ODM_BB_ENV_MONITOR |
562 ODM_BB_PRIMARY_CCA;
563 break;
564 #endif
565
566 #if (RTL8192E_SUPPORT)
567 case ODM_RTL8192E:
568 support_ability |=
569 ODM_BB_DIG |
570 ODM_BB_RA_MASK |
571 /*ODM_BB_DYNAMIC_TXPWR |*/
572 ODM_BB_FA_CNT |
573 ODM_BB_RSSI_MONITOR |
574 ODM_BB_CCK_PD |
575 /*ODM_BB_PWR_TRAIN |*/
576 ODM_BB_RATE_ADAPTIVE |
577 ODM_BB_CFO_TRACKING |
578 ODM_BB_ENV_MONITOR |
579 ODM_BB_PRIMARY_CCA;
580 break;
581 #endif
582
583 #if (RTL8723B_SUPPORT)
584 case ODM_RTL8723B:
585 support_ability |=
586 ODM_BB_DIG |
587 ODM_BB_RA_MASK |
588 /*ODM_BB_DYNAMIC_TXPWR |*/
589 ODM_BB_FA_CNT |
590 ODM_BB_RSSI_MONITOR |
591 ODM_BB_CCK_PD |
592 /*ODM_BB_PWR_TRAIN |*/
593 ODM_BB_RATE_ADAPTIVE |
594 ODM_BB_CFO_TRACKING |
595 ODM_BB_ENV_MONITOR |
596 ODM_BB_PRIMARY_CCA;
597 break;
598 #endif
599
600 #if (RTL8703B_SUPPORT)
601 case ODM_RTL8703B:
602 support_ability |=
603 ODM_BB_DIG |
604 ODM_BB_RA_MASK |
605 /*ODM_BB_DYNAMIC_TXPWR |*/
606 ODM_BB_FA_CNT |
607 ODM_BB_RSSI_MONITOR |
608 ODM_BB_CCK_PD |
609 /*ODM_BB_PWR_TRAIN |*/
610 ODM_BB_RATE_ADAPTIVE |
611 ODM_BB_CFO_TRACKING |
612 ODM_BB_ENV_MONITOR;
613 break;
614 #endif
615
616 #if (RTL8723D_SUPPORT)
617 case ODM_RTL8723D:
618 support_ability |=
619 ODM_BB_DIG |
620 ODM_BB_RA_MASK |
621 /*ODM_BB_DYNAMIC_TXPWR |*/
622 ODM_BB_FA_CNT |
623 ODM_BB_RSSI_MONITOR |
624 ODM_BB_CCK_PD |
625 ODM_BB_PWR_TRAIN |
626 ODM_BB_RATE_ADAPTIVE |
627 ODM_BB_CFO_TRACKING |
628 ODM_BB_ENV_MONITOR;
629 break;
630 #endif
631
632 #if (RTL8710B_SUPPORT)
633 case ODM_RTL8710B:
634 support_ability |=
635 ODM_BB_DIG |
636 ODM_BB_RA_MASK |
637 /*ODM_BB_DYNAMIC_TXPWR |*/
638 ODM_BB_FA_CNT |
639 ODM_BB_RSSI_MONITOR |
640 ODM_BB_CCK_PD |
641 ODM_BB_PWR_TRAIN |
642 ODM_BB_RATE_ADAPTIVE |
643 ODM_BB_CFO_TRACKING |
644 ODM_BB_ENV_MONITOR;
645 break;
646 #endif
647
648 #if (RTL8188F_SUPPORT)
649 case ODM_RTL8188F:
650 support_ability |=
651 ODM_BB_DIG |
652 ODM_BB_RA_MASK |
653 /*ODM_BB_DYNAMIC_TXPWR |*/
654 ODM_BB_FA_CNT |
655 ODM_BB_RSSI_MONITOR |
656 ODM_BB_CCK_PD |
657 /*ODM_BB_PWR_TRAIN |*/
658 ODM_BB_RATE_ADAPTIVE |
659 ODM_BB_CFO_TRACKING |
660 ODM_BB_ENV_MONITOR;
661 break;
662 #endif
663
664 #if (RTL8192F_SUPPORT)
665 case ODM_RTL8192F:
666 support_ability |=
667 ODM_BB_DIG |
668 ODM_BB_RA_MASK |
669 ODM_BB_FA_CNT |
670 ODM_BB_RSSI_MONITOR |
671 ODM_BB_CCK_PD |
672 ODM_BB_PWR_TRAIN |
673 ODM_BB_RATE_ADAPTIVE |
674 ODM_BB_CFO_TRACKING |
675 ODM_BB_ADAPTIVE_SOML |
676 ODM_BB_ENV_MONITOR;
677 /*ODM_BB_LNA_SAT_CHK |*/
678 /*ODM_BB_PRIMARY_CCA*/
679
680 break;
681 #endif
682
683 /*@---------------AC Series-------------------*/
684
685 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
686 case ODM_RTL8812:
687 case ODM_RTL8821:
688 support_ability |=
689 ODM_BB_DIG |
690 ODM_BB_RA_MASK |
691 ODM_BB_DYNAMIC_TXPWR |
692 ODM_BB_FA_CNT |
693 ODM_BB_RSSI_MONITOR |
694 ODM_BB_CCK_PD |
695 /*ODM_BB_PWR_TRAIN |*/
696 ODM_BB_RATE_ADAPTIVE |
697 ODM_BB_CFO_TRACKING |
698 ODM_BB_ENV_MONITOR;
699 break;
700 #endif
701
702 #if (RTL8814A_SUPPORT)
703 case ODM_RTL8814A:
704 support_ability |=
705 ODM_BB_DIG |
706 ODM_BB_RA_MASK |
707 ODM_BB_DYNAMIC_TXPWR |
708 ODM_BB_FA_CNT |
709 ODM_BB_RSSI_MONITOR |
710 ODM_BB_CCK_PD |
711 /*ODM_BB_PWR_TRAIN |*/
712 ODM_BB_RATE_ADAPTIVE |
713 ODM_BB_CFO_TRACKING |
714 ODM_BB_ENV_MONITOR;
715 break;
716 #endif
717
718 #if (RTL8822B_SUPPORT)
719 case ODM_RTL8822B:
720 support_ability |=
721 ODM_BB_DIG |
722 ODM_BB_RA_MASK |
723 /*ODM_BB_DYNAMIC_TXPWR |*/
724 ODM_BB_FA_CNT |
725 ODM_BB_RSSI_MONITOR |
726 ODM_BB_CCK_PD |
727 /*ODM_BB_PWR_TRAIN |*/
728 /*ODM_BB_ADAPTIVE_SOML |*/
729 ODM_BB_RATE_ADAPTIVE |
730 /*ODM_BB_PATH_DIV |*/
731 ODM_BB_CFO_TRACKING |
732 ODM_BB_ENV_MONITOR;
733 break;
734 #endif
735
736 #if (RTL8821C_SUPPORT)
737 case ODM_RTL8821C:
738 support_ability |=
739 ODM_BB_DIG |
740 ODM_BB_RA_MASK |
741 /*ODM_BB_DYNAMIC_TXPWR |*/
742 ODM_BB_FA_CNT |
743 ODM_BB_RSSI_MONITOR |
744 ODM_BB_CCK_PD |
745 /*ODM_BB_PWR_TRAIN |*/
746 ODM_BB_RATE_ADAPTIVE |
747 ODM_BB_CFO_TRACKING |
748 ODM_BB_ENV_MONITOR;
749 break;
750 #endif
751
752 /*@---------------JGR3 Series-------------------*/
753
754 #if (RTL8822C_SUPPORT)
755 case ODM_RTL8822C:
756 support_ability |=
757 ODM_BB_DIG |
758 ODM_BB_RA_MASK |
759 /* ODM_BB_DYNAMIC_TXPWR |*/
760 ODM_BB_FA_CNT |
761 ODM_BB_RSSI_MONITOR |
762 ODM_BB_CCK_PD |
763 ODM_BB_RATE_ADAPTIVE |
764 ODM_BB_PATH_DIV |
765 ODM_BB_CFO_TRACKING |
766 ODM_BB_ENV_MONITOR;
767 break;
768 #endif
769
770 #if (RTL8814B_SUPPORT)
771 case ODM_RTL8814B:
772 support_ability |=
773 ODM_BB_DIG |
774 ODM_BB_RA_MASK |
775 /*ODM_BB_DYNAMIC_TXPWR |*/
776 ODM_BB_FA_CNT |
777 ODM_BB_RSSI_MONITOR |
778 /*ODM_BB_CCK_PD |*/
779 /*ODM_BB_PWR_TRAIN |*/
780 ODM_BB_RATE_ADAPTIVE |
781 ODM_BB_CFO_TRACKING;
782 /*ODM_BB_ENV_MONITOR;*/
783 break;
784 #endif
785
786 default:
787 support_ability |=
788 ODM_BB_DIG |
789 ODM_BB_RA_MASK |
790 /*ODM_BB_DYNAMIC_TXPWR |*/
791 ODM_BB_FA_CNT |
792 ODM_BB_RSSI_MONITOR |
793 ODM_BB_CCK_PD |
794 /*ODM_BB_PWR_TRAIN |*/
795 ODM_BB_RATE_ADAPTIVE |
796 ODM_BB_CFO_TRACKING |
797 ODM_BB_ENV_MONITOR;
798
799 pr_debug("[Warning] Supportability Init Warning !!!\n");
800 break;
801 }
802
803 return support_ability;
804 }
805 #endif
806
807 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)808 u64 phydm_supportability_init_ce(void *dm_void)
809 {
810 struct dm_struct *dm = (struct dm_struct *)dm_void;
811 u64 support_ability = 0;
812
813 switch (dm->support_ic_type) {
814 /*@---------------N Series--------------------*/
815 #if (RTL8188E_SUPPORT)
816 case ODM_RTL8188E:
817 support_ability |=
818 ODM_BB_DIG |
819 ODM_BB_RA_MASK |
820 /*@ODM_BB_DYNAMIC_TXPWR |*/
821 ODM_BB_FA_CNT |
822 ODM_BB_RSSI_MONITOR |
823 ODM_BB_CCK_PD |
824 /*@ODM_BB_PWR_TRAIN |*/
825 ODM_BB_RATE_ADAPTIVE |
826 ODM_BB_CFO_TRACKING |
827 ODM_BB_ENV_MONITOR |
828 ODM_BB_PRIMARY_CCA;
829 break;
830 #endif
831
832 #if (RTL8192E_SUPPORT)
833 case ODM_RTL8192E:
834 support_ability |=
835 ODM_BB_DIG |
836 ODM_BB_RA_MASK |
837 /*@ODM_BB_DYNAMIC_TXPWR |*/
838 ODM_BB_FA_CNT |
839 ODM_BB_RSSI_MONITOR |
840 ODM_BB_CCK_PD |
841 /*@ODM_BB_PWR_TRAIN |*/
842 ODM_BB_RATE_ADAPTIVE |
843 ODM_BB_CFO_TRACKING |
844 ODM_BB_ENV_MONITOR |
845 ODM_BB_PRIMARY_CCA;
846 break;
847 #endif
848
849 #if (RTL8723B_SUPPORT)
850 case ODM_RTL8723B:
851 support_ability |=
852 ODM_BB_DIG |
853 ODM_BB_RA_MASK |
854 /*@ODM_BB_DYNAMIC_TXPWR |*/
855 ODM_BB_FA_CNT |
856 ODM_BB_RSSI_MONITOR |
857 ODM_BB_CCK_PD |
858 /*@ODM_BB_PWR_TRAIN |*/
859 ODM_BB_RATE_ADAPTIVE |
860 ODM_BB_CFO_TRACKING |
861 ODM_BB_ENV_MONITOR |
862 ODM_BB_PRIMARY_CCA;
863 break;
864 #endif
865
866 #if (RTL8703B_SUPPORT)
867 case ODM_RTL8703B:
868 support_ability |=
869 ODM_BB_DIG |
870 ODM_BB_RA_MASK |
871 /*@ODM_BB_DYNAMIC_TXPWR |*/
872 ODM_BB_FA_CNT |
873 ODM_BB_RSSI_MONITOR |
874 ODM_BB_CCK_PD |
875 /*@ODM_BB_PWR_TRAIN |*/
876 ODM_BB_RATE_ADAPTIVE |
877 ODM_BB_CFO_TRACKING |
878 ODM_BB_ENV_MONITOR;
879 break;
880 #endif
881
882 #if (RTL8723D_SUPPORT)
883 case ODM_RTL8723D:
884 support_ability |=
885 ODM_BB_DIG |
886 ODM_BB_RA_MASK |
887 /*@ODM_BB_DYNAMIC_TXPWR |*/
888 ODM_BB_FA_CNT |
889 ODM_BB_RSSI_MONITOR |
890 ODM_BB_CCK_PD |
891 ODM_BB_PWR_TRAIN |
892 ODM_BB_RATE_ADAPTIVE |
893 ODM_BB_CFO_TRACKING |
894 ODM_BB_ENV_MONITOR;
895 break;
896 #endif
897
898 #if (RTL8710B_SUPPORT)
899 case ODM_RTL8710B:
900 support_ability |=
901 ODM_BB_DIG |
902 ODM_BB_RA_MASK |
903 /*@ODM_BB_DYNAMIC_TXPWR |*/
904 ODM_BB_FA_CNT |
905 ODM_BB_RSSI_MONITOR |
906 ODM_BB_CCK_PD |
907 /*@ODM_BB_PWR_TRAIN |*/
908 ODM_BB_RATE_ADAPTIVE |
909 ODM_BB_CFO_TRACKING |
910 ODM_BB_ENV_MONITOR;
911 break;
912 #endif
913
914 #if (RTL8188F_SUPPORT)
915 case ODM_RTL8188F:
916 support_ability |=
917 ODM_BB_DIG |
918 ODM_BB_RA_MASK |
919 /*@ODM_BB_DYNAMIC_TXPWR |*/
920 ODM_BB_FA_CNT |
921 ODM_BB_RSSI_MONITOR |
922 ODM_BB_CCK_PD |
923 /*@ODM_BB_PWR_TRAIN |*/
924 ODM_BB_RATE_ADAPTIVE |
925 ODM_BB_CFO_TRACKING |
926 ODM_BB_ENV_MONITOR;
927 break;
928 #endif
929
930 #if (RTL8192F_SUPPORT)
931 case ODM_RTL8192F:
932 support_ability |=
933 ODM_BB_DIG |
934 ODM_BB_RA_MASK |
935 ODM_BB_FA_CNT |
936 ODM_BB_RSSI_MONITOR |
937 ODM_BB_CCK_PD |
938 ODM_BB_PWR_TRAIN |
939 ODM_BB_RATE_ADAPTIVE |
940 ODM_BB_CFO_TRACKING |
941 /*@ODM_BB_ADAPTIVE_SOML |*/
942 ODM_BB_ENV_MONITOR;
943 /*@ODM_BB_LNA_SAT_CHK |*/
944 /*@ODM_BB_PRIMARY_CCA*/
945 break;
946 #endif
947 /*@---------------AC Series-------------------*/
948
949 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
950 case ODM_RTL8812:
951 case ODM_RTL8821:
952 support_ability |=
953 ODM_BB_DIG |
954 ODM_BB_RA_MASK |
955 /*@ODM_BB_DYNAMIC_TXPWR |*/
956 ODM_BB_FA_CNT |
957 ODM_BB_RSSI_MONITOR |
958 ODM_BB_CCK_PD |
959 /*@ODM_BB_PWR_TRAIN |*/
960 ODM_BB_RATE_ADAPTIVE |
961 ODM_BB_CFO_TRACKING |
962 ODM_BB_ENV_MONITOR;
963 break;
964 #endif
965
966 #if (RTL8814A_SUPPORT)
967 case ODM_RTL8814A:
968 support_ability |=
969 ODM_BB_DIG |
970 ODM_BB_RA_MASK |
971 /*@ODM_BB_DYNAMIC_TXPWR |*/
972 ODM_BB_FA_CNT |
973 ODM_BB_RSSI_MONITOR |
974 ODM_BB_CCK_PD |
975 /*@ODM_BB_PWR_TRAIN |*/
976 ODM_BB_RATE_ADAPTIVE |
977 ODM_BB_CFO_TRACKING |
978 ODM_BB_ENV_MONITOR;
979 break;
980 #endif
981
982 #if (RTL8822B_SUPPORT)
983 case ODM_RTL8822B:
984 support_ability |=
985 ODM_BB_DIG |
986 ODM_BB_RA_MASK |
987 /*@ODM_BB_DYNAMIC_TXPWR |*/
988 ODM_BB_FA_CNT |
989 ODM_BB_RSSI_MONITOR |
990 ODM_BB_CCK_PD |
991 /*@ODM_BB_PWR_TRAIN |*/
992 ODM_BB_RATE_ADAPTIVE |
993 /*ODM_BB_PATH_DIV |*/
994 ODM_BB_CFO_TRACKING |
995 ODM_BB_ENV_MONITOR;
996 break;
997 #endif
998
999 #if (RTL8821C_SUPPORT)
1000 case ODM_RTL8821C:
1001 support_ability |=
1002 ODM_BB_DIG |
1003 ODM_BB_RA_MASK |
1004 /*@ODM_BB_DYNAMIC_TXPWR |*/
1005 ODM_BB_FA_CNT |
1006 ODM_BB_RSSI_MONITOR |
1007 ODM_BB_CCK_PD |
1008 /*@ODM_BB_PWR_TRAIN |*/
1009 ODM_BB_RATE_ADAPTIVE |
1010 ODM_BB_CFO_TRACKING |
1011 ODM_BB_ENV_MONITOR;
1012 break;
1013 #endif
1014
1015 /*@---------------JGR3 Series-------------------*/
1016
1017 #if (RTL8822C_SUPPORT)
1018 case ODM_RTL8822C:
1019 support_ability |=
1020 ODM_BB_DIG |
1021 ODM_BB_RA_MASK |
1022 /* ODM_BB_DYNAMIC_TXPWR |*/
1023 ODM_BB_FA_CNT |
1024 ODM_BB_RSSI_MONITOR |
1025 ODM_BB_CCK_PD |
1026 ODM_BB_RATE_ADAPTIVE |
1027 ODM_BB_PATH_DIV |
1028 ODM_BB_CFO_TRACKING |
1029 ODM_BB_ENV_MONITOR;
1030 break;
1031 #endif
1032
1033 #if (RTL8814B_SUPPORT)
1034 case ODM_RTL8814B:
1035 support_ability |=
1036 ODM_BB_DIG |
1037 ODM_BB_RA_MASK |
1038 /*@ODM_BB_DYNAMIC_TXPWR |*/
1039 ODM_BB_FA_CNT |
1040 ODM_BB_RSSI_MONITOR;
1041 /*ODM_BB_CCK_PD |*/
1042 /*@ODM_BB_PWR_TRAIN |*/
1043 /*ODM_BB_RATE_ADAPTIVE |*/
1044 /*ODM_BB_CFO_TRACKING |*/
1045 /*ODM_BB_ENV_MONITOR;*/
1046 break;
1047 #endif
1048
1049 default:
1050 support_ability |=
1051 ODM_BB_DIG |
1052 ODM_BB_RA_MASK |
1053 /*@ODM_BB_DYNAMIC_TXPWR |*/
1054 ODM_BB_FA_CNT |
1055 ODM_BB_RSSI_MONITOR |
1056 ODM_BB_CCK_PD |
1057 /*@ODM_BB_PWR_TRAIN |*/
1058 ODM_BB_RATE_ADAPTIVE |
1059 ODM_BB_CFO_TRACKING |
1060 ODM_BB_ENV_MONITOR;
1061
1062 pr_debug("[Warning] Supportability Init Warning !!!\n");
1063 break;
1064 }
1065
1066 return support_ability;
1067 }
1068 #endif
1069
1070 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1071 u64 phydm_supportability_init_ap(
1072 void *dm_void)
1073 {
1074 struct dm_struct *dm = (struct dm_struct *)dm_void;
1075 u64 support_ability = 0;
1076
1077 switch (dm->support_ic_type) {
1078 /*@---------------N Series--------------------*/
1079 #if (RTL8188E_SUPPORT)
1080 case ODM_RTL8188E:
1081 support_ability |=
1082 ODM_BB_DIG |
1083 ODM_BB_RA_MASK |
1084 ODM_BB_FA_CNT |
1085 ODM_BB_RSSI_MONITOR |
1086 ODM_BB_CCK_PD |
1087 /*ODM_BB_PWR_TRAIN |*/
1088 ODM_BB_RATE_ADAPTIVE |
1089 ODM_BB_CFO_TRACKING |
1090 ODM_BB_ENV_MONITOR |
1091 ODM_BB_PRIMARY_CCA;
1092 break;
1093 #endif
1094
1095 #if (RTL8192E_SUPPORT)
1096 case ODM_RTL8192E:
1097 support_ability |=
1098 ODM_BB_DIG |
1099 ODM_BB_RA_MASK |
1100 ODM_BB_FA_CNT |
1101 ODM_BB_RSSI_MONITOR |
1102 ODM_BB_CCK_PD |
1103 /*ODM_BB_PWR_TRAIN |*/
1104 ODM_BB_RATE_ADAPTIVE |
1105 ODM_BB_CFO_TRACKING |
1106 ODM_BB_ENV_MONITOR |
1107 ODM_BB_PRIMARY_CCA;
1108 break;
1109 #endif
1110
1111 #if (RTL8723B_SUPPORT)
1112 case ODM_RTL8723B:
1113 support_ability |=
1114 ODM_BB_DIG |
1115 ODM_BB_RA_MASK |
1116 ODM_BB_FA_CNT |
1117 ODM_BB_RSSI_MONITOR |
1118 ODM_BB_CCK_PD |
1119 /*ODM_BB_PWR_TRAIN |*/
1120 ODM_BB_RATE_ADAPTIVE |
1121 ODM_BB_CFO_TRACKING |
1122 ODM_BB_ENV_MONITOR;
1123 break;
1124 #endif
1125
1126 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1127 case ODM_RTL8198F:
1128 support_ability |=
1129 /*ODM_BB_DIG |*/
1130 ODM_BB_RA_MASK |
1131 ODM_BB_FA_CNT |
1132 ODM_BB_RSSI_MONITOR;
1133 /*ODM_BB_CCK_PD |*/
1134 /*ODM_BB_PWR_TRAIN |*/
1135 /*ODM_BB_RATE_ADAPTIVE |*/
1136 /*ODM_BB_CFO_TRACKING |*/
1137 /*ODM_BB_ADAPTIVE_SOML |*/
1138 /*ODM_BB_ENV_MONITOR |*/
1139 /*ODM_BB_LNA_SAT_CHK |*/
1140 /*ODM_BB_PRIMARY_CCA;*/
1141 break;
1142 case ODM_RTL8197F:
1143 support_ability |=
1144 ODM_BB_DIG |
1145 ODM_BB_RA_MASK |
1146 ODM_BB_FA_CNT |
1147 ODM_BB_RSSI_MONITOR |
1148 ODM_BB_CCK_PD |
1149 /*ODM_BB_PWR_TRAIN |*/
1150 ODM_BB_RATE_ADAPTIVE |
1151 ODM_BB_CFO_TRACKING |
1152 ODM_BB_ADAPTIVE_SOML |
1153 ODM_BB_ENV_MONITOR |
1154 ODM_BB_LNA_SAT_CHK |
1155 ODM_BB_PRIMARY_CCA;
1156 break;
1157 #endif
1158
1159 #if (RTL8192F_SUPPORT)
1160 case ODM_RTL8192F:
1161 support_ability |=
1162 ODM_BB_DIG |
1163 ODM_BB_RA_MASK |
1164 ODM_BB_FA_CNT |
1165 ODM_BB_RSSI_MONITOR |
1166 ODM_BB_CCK_PD |
1167 /*ODM_BB_PWR_TRAIN |*/
1168 ODM_BB_RATE_ADAPTIVE |
1169 /*ODM_BB_CFO_TRACKING |*/
1170 ODM_BB_ADAPTIVE_SOML |
1171 ODM_BB_ENV_MONITOR |
1172 /*ODM_BB_LNA_SAT_CHK |*/
1173 /*ODM_BB_PRIMARY_CCA |*/
1174 0;
1175 break;
1176 #endif
1177
1178 /*@---------------AC Series-------------------*/
1179
1180 #if (RTL8881A_SUPPORT)
1181 case ODM_RTL8881A:
1182 support_ability |=
1183 ODM_BB_DIG |
1184 ODM_BB_RA_MASK |
1185 ODM_BB_FA_CNT |
1186 ODM_BB_RSSI_MONITOR |
1187 ODM_BB_CCK_PD |
1188 /*ODM_BB_PWR_TRAIN |*/
1189 ODM_BB_RATE_ADAPTIVE |
1190 ODM_BB_CFO_TRACKING |
1191 ODM_BB_ENV_MONITOR;
1192 break;
1193 #endif
1194
1195 #if (RTL8814A_SUPPORT)
1196 case ODM_RTL8814A:
1197 support_ability |=
1198 ODM_BB_DIG |
1199 ODM_BB_RA_MASK |
1200 ODM_BB_FA_CNT |
1201 ODM_BB_RSSI_MONITOR |
1202 ODM_BB_CCK_PD |
1203 /*ODM_BB_PWR_TRAIN |*/
1204 ODM_BB_RATE_ADAPTIVE |
1205 ODM_BB_CFO_TRACKING |
1206 ODM_BB_ENV_MONITOR;
1207 break;
1208 #endif
1209
1210 #if (RTL8822B_SUPPORT)
1211 case ODM_RTL8822B:
1212 support_ability |=
1213 ODM_BB_DIG |
1214 ODM_BB_RA_MASK |
1215 ODM_BB_FA_CNT |
1216 ODM_BB_RSSI_MONITOR |
1217 ODM_BB_CCK_PD |
1218 /*ODM_BB_PWR_TRAIN |*/
1219 /*ODM_BB_ADAPTIVE_SOML |*/
1220 ODM_BB_RATE_ADAPTIVE |
1221 ODM_BB_CFO_TRACKING |
1222 ODM_BB_ENV_MONITOR;
1223 break;
1224 #endif
1225
1226 #if (RTL8821C_SUPPORT)
1227 case ODM_RTL8821C:
1228 support_ability |=
1229 ODM_BB_DIG |
1230 ODM_BB_RA_MASK |
1231 ODM_BB_FA_CNT |
1232 ODM_BB_RSSI_MONITOR |
1233 ODM_BB_CCK_PD |
1234 /*ODM_BB_PWR_TRAIN |*/
1235 ODM_BB_RATE_ADAPTIVE |
1236 ODM_BB_CFO_TRACKING |
1237 ODM_BB_ENV_MONITOR;
1238
1239 break;
1240 #endif
1241
1242 /*@---------------JGR3 Series-------------------*/
1243
1244 #if (RTL8814B_SUPPORT)
1245 case ODM_RTL8814B:
1246 support_ability |=
1247 ODM_BB_DIG |
1248 ODM_BB_RA_MASK |
1249 ODM_BB_FA_CNT |
1250 ODM_BB_RSSI_MONITOR;
1251 /*ODM_BB_CCK_PD |*/
1252 /*ODM_BB_PWR_TRAIN |*/
1253 /*ODM_BB_RATE_ADAPTIVE |*/
1254 /*ODM_BB_CFO_TRACKING |*/
1255 /*ODM_BB_ENV_MONITOR;*/
1256 break;
1257 #endif
1258
1259 default:
1260 support_ability |=
1261 ODM_BB_DIG |
1262 ODM_BB_RA_MASK |
1263 ODM_BB_FA_CNT |
1264 ODM_BB_RSSI_MONITOR |
1265 ODM_BB_CCK_PD |
1266 /*ODM_BB_PWR_TRAIN |*/
1267 ODM_BB_RATE_ADAPTIVE |
1268 ODM_BB_CFO_TRACKING |
1269 ODM_BB_ENV_MONITOR;
1270
1271 pr_debug("[Warning] Supportability Init Warning !!!\n");
1272 break;
1273 }
1274
1275 #if 0
1276 /*@[Config Antenna Diveristy]*/
1277 if (*dm->enable_antdiv)
1278 support_ability |= ODM_BB_ANT_DIV;
1279
1280 /*@[Config Adaptivity]*/
1281 if (*dm->enable_adaptivity)
1282 support_ability |= ODM_BB_ADAPTIVITY;
1283 #endif
1284
1285 return support_ability;
1286 }
1287 #endif
1288
1289 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1290 u64 phydm_supportability_init_iot(
1291 void *dm_void)
1292 {
1293 struct dm_struct *dm = (struct dm_struct *)dm_void;
1294 u64 support_ability = 0;
1295
1296 switch (dm->support_ic_type) {
1297 #if (RTL8710B_SUPPORT)
1298 case ODM_RTL8710B:
1299 support_ability |=
1300 ODM_BB_DIG |
1301 ODM_BB_RA_MASK |
1302 /*ODM_BB_DYNAMIC_TXPWR |*/
1303 ODM_BB_FA_CNT |
1304 ODM_BB_RSSI_MONITOR |
1305 ODM_BB_CCK_PD |
1306 /*ODM_BB_PWR_TRAIN |*/
1307 ODM_BB_RATE_ADAPTIVE |
1308 ODM_BB_CFO_TRACKING |
1309 ODM_BB_ENV_MONITOR;
1310 break;
1311 #endif
1312
1313 #if (RTL8195A_SUPPORT)
1314 case ODM_RTL8195A:
1315 support_ability |=
1316 ODM_BB_DIG |
1317 ODM_BB_RA_MASK |
1318 /*ODM_BB_DYNAMIC_TXPWR |*/
1319 ODM_BB_FA_CNT |
1320 ODM_BB_RSSI_MONITOR |
1321 ODM_BB_CCK_PD |
1322 /*ODM_BB_PWR_TRAIN |*/
1323 ODM_BB_RATE_ADAPTIVE |
1324 ODM_BB_CFO_TRACKING |
1325 ODM_BB_ENV_MONITOR;
1326 break;
1327 #endif
1328
1329 #if (RTL8195B_SUPPORT)
1330 case ODM_RTL8195B:
1331 support_ability |=
1332 ODM_BB_DIG |
1333 ODM_BB_RA_MASK |
1334 /*ODM_BB_DYNAMIC_TXPWR |*/
1335 ODM_BB_FA_CNT |
1336 ODM_BB_RSSI_MONITOR |
1337 ODM_BB_CCK_PD |
1338 /*ODM_BB_PWR_TRAIN |*/
1339 ODM_BB_RATE_ADAPTIVE |
1340 ODM_BB_CFO_TRACKING;
1341 /*ODM_BB_ENV_MONITOR*/
1342 break;
1343 #endif
1344
1345 #if (RTL8721D_SUPPORT)
1346 case ODM_RTL8721D:
1347 support_ability |=
1348 ODM_BB_DIG |
1349 ODM_BB_RA_MASK |
1350 /*ODM_BB_DYNAMIC_TXPWR |*/
1351 ODM_BB_FA_CNT |
1352 ODM_BB_RSSI_MONITOR |
1353 ODM_BB_CCK_PD |
1354 /*ODM_BB_PWR_TRAIN |*/
1355 ODM_BB_RATE_ADAPTIVE |
1356 ODM_BB_CFO_TRACKING |
1357 ODM_BB_ENV_MONITOR;
1358 break;
1359 #endif
1360
1361 default:
1362 support_ability |=
1363 ODM_BB_DIG |
1364 ODM_BB_RA_MASK |
1365 /*ODM_BB_DYNAMIC_TXPWR |*/
1366 ODM_BB_FA_CNT |
1367 ODM_BB_RSSI_MONITOR |
1368 ODM_BB_CCK_PD |
1369 /*ODM_BB_PWR_TRAIN |*/
1370 ODM_BB_RATE_ADAPTIVE |
1371 ODM_BB_CFO_TRACKING |
1372 ODM_BB_ENV_MONITOR;
1373
1374 pr_debug("[Warning] Supportability Init Warning !!!\n");
1375 break;
1376 }
1377
1378 return support_ability;
1379 }
1380 #endif
1381
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1382 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1383 enum phydm_offload_ability offload_ability)
1384 {
1385 switch (offload_ability) {
1386 case PHYDM_PHY_PARAM_OFFLOAD:
1387 if (dm->support_ic_type &
1388 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1389 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1390 break;
1391
1392 case PHYDM_RF_IQK_OFFLOAD:
1393 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1394 break;
1395
1396 default:
1397 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1398 break;
1399 }
1400
1401 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1402 dm->fw_offload_ability);
1403 }
1404
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1405 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1406 enum phydm_offload_ability offload_ability)
1407 {
1408 switch (offload_ability) {
1409 case PHYDM_PHY_PARAM_OFFLOAD:
1410 if (dm->support_ic_type &
1411 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
1412 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1413 break;
1414
1415 case PHYDM_RF_IQK_OFFLOAD:
1416 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1417 break;
1418
1419 default:
1420 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1421 break;
1422 }
1423
1424 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1425 dm->fw_offload_ability);
1426 }
1427
phydm_supportability_init(void * dm_void)1428 void phydm_supportability_init(void *dm_void)
1429 {
1430 struct dm_struct *dm = (struct dm_struct *)dm_void;
1431 u64 support_ability;
1432
1433 if (dm->manual_supportability &&
1434 *dm->manual_supportability != 0xffffffff) {
1435 support_ability = *dm->manual_supportability;
1436 } else if (*dm->mp_mode) {
1437 support_ability = 0;
1438 } else {
1439 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1440 support_ability = phydm_supportability_init_win(dm);
1441 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1442 support_ability = phydm_supportability_init_ap(dm);
1443 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1444 support_ability = phydm_supportability_init_ce(dm);
1445 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1446 support_ability = phydm_supportability_init_iot(dm);
1447 #endif
1448
1449 /*@[Config Antenna Diversity]*/
1450 if (IS_FUNC_EN(dm->enable_antdiv))
1451 support_ability |= ODM_BB_ANT_DIV;
1452
1453 /*@[Config TXpath Diversity]*/
1454 if (IS_FUNC_EN(dm->enable_pathdiv))
1455 support_ability |= ODM_BB_PATH_DIV;
1456
1457 /*@[Config Adaptive SOML]*/
1458 if (IS_FUNC_EN(dm->en_adap_soml))
1459 support_ability |= ODM_BB_ADAPTIVE_SOML;
1460
1461 /* @[Config Adaptivity]*/
1462 if (IS_FUNC_EN(dm->enable_adaptivity))
1463 support_ability |= ODM_BB_ADAPTIVITY;
1464 }
1465 dm->support_ability = support_ability;
1466 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1467 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1468 }
1469
phydm_rfe_init(void * dm_void)1470 void phydm_rfe_init(void *dm_void)
1471 {
1472 struct dm_struct *dm = (struct dm_struct *)dm_void;
1473
1474 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1475 #if (RTL8822B_SUPPORT == 1)
1476 if (dm->support_ic_type == ODM_RTL8822B)
1477 phydm_rfe_8822b_init(dm);
1478 #endif
1479 }
1480
phydm_dm_early_init(struct dm_struct * dm)1481 void phydm_dm_early_init(struct dm_struct *dm)
1482 {
1483 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1484 phydm_init_debug_setting(dm);
1485 #endif
1486 }
1487
odm_dm_init(struct dm_struct * dm)1488 void odm_dm_init(struct dm_struct *dm)
1489 {
1490 halrf_init(dm);
1491 phydm_supportability_init(dm);
1492 phydm_rfe_init(dm);
1493 phydm_common_info_self_init(dm);
1494 phydm_rx_phy_status_init(dm);
1495 #ifdef PHYDM_AUTO_DEGBUG
1496 phydm_auto_dbg_engine_init(dm);
1497 #endif
1498 phydm_dig_init(dm);
1499 #ifdef PHYDM_SUPPORT_CCKPD
1500 phydm_cck_pd_init(dm);
1501 #endif
1502 phydm_env_monitor_init(dm);
1503 phydm_adaptivity_init(dm);
1504 phydm_ra_info_init(dm);
1505 phydm_rssi_monitor_init(dm);
1506 phydm_cfo_tracking_init(dm);
1507 phydm_rf_init(dm);
1508 phydm_dc_cancellation(dm);
1509 #ifdef PHYDM_TXA_CALIBRATION
1510 phydm_txcurrentcalibration(dm);
1511 phydm_get_pa_bias_offset(dm);
1512 #endif
1513 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1514 odm_antenna_diversity_init(dm);
1515 #endif
1516 #ifdef CONFIG_ADAPTIVE_SOML
1517 phydm_adaptive_soml_init(dm);
1518 #endif
1519 #ifdef CONFIG_PATH_DIVERSITY
1520 phydm_tx_path_diversity_init(dm);
1521 #endif
1522 #ifdef CONFIG_DYNAMIC_TX_TWR
1523 phydm_dynamic_tx_power_init(dm);
1524 #endif
1525 #if (PHYDM_LA_MODE_SUPPORT == 1)
1526 phydm_la_init(dm);
1527 #endif
1528
1529 #ifdef PHYDM_BEAMFORMING_VERSION1
1530 phydm_beamforming_init(dm);
1531 #endif
1532
1533 #if (RTL8188E_SUPPORT == 1)
1534 odm_ra_info_init_all(dm);
1535 #endif
1536 #ifdef PHYDM_PRIMARY_CCA
1537 phydm_primary_cca_init(dm);
1538 #endif
1539 #ifdef CONFIG_PSD_TOOL
1540 phydm_psd_init(dm);
1541 #endif
1542
1543 #ifdef CONFIG_SMART_ANTENNA
1544 phydm_smt_ant_init(dm);
1545 #endif
1546 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1547 phydm_lna_sat_check_init(dm);
1548 #endif
1549 #ifdef CONFIG_MCC_DM
1550 phydm_mcc_init(dm);
1551 #endif
1552
1553 #ifdef CONFIG_MU_RSOML
1554 phydm_mu_rsoml_init(dm);
1555 #endif
1556 }
1557
odm_dm_reset(struct dm_struct * dm)1558 void odm_dm_reset(struct dm_struct *dm)
1559 {
1560 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1561
1562 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1563 odm_ant_div_reset(dm);
1564 #endif
1565 phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);
1566 }
1567
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1568 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1569 char *output, u32 *_out_len)
1570 {
1571 struct dm_struct *dm = (struct dm_struct *)dm_void;
1572 u32 dm_value[10] = {0};
1573 u64 pre_support_ability, one = 1;
1574 u64 comp = 0;
1575 u32 used = *_used;
1576 u32 out_len = *_out_len;
1577 u8 i;
1578
1579 for (i = 0; i < 5; i++) {
1580 if (input[i + 1])
1581 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1582 }
1583
1584 pre_support_ability = dm->support_ability;
1585 comp = dm->support_ability;
1586
1587 PDM_SNPF(out_len, used, output + used, out_len - used,
1588 "\n================================\n");
1589
1590 if (dm_value[0] == 100) {
1591 PDM_SNPF(out_len, used, output + used, out_len - used,
1592 "[Supportability] PhyDM Selection\n");
1593 PDM_SNPF(out_len, used, output + used, out_len - used,
1594 "================================\n");
1595 PDM_SNPF(out_len, used, output + used, out_len - used,
1596 "00. (( %s ))DIG\n",
1597 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1598 PDM_SNPF(out_len, used, output + used, out_len - used,
1599 "01. (( %s ))RA_MASK\n",
1600 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1601 PDM_SNPF(out_len, used, output + used, out_len - used,
1602 "02. (( %s ))DYN_TXPWR\n",
1603 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1604 PDM_SNPF(out_len, used, output + used, out_len - used,
1605 "03. (( %s ))FA_CNT\n",
1606 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1607 PDM_SNPF(out_len, used, output + used, out_len - used,
1608 "04. (( %s ))RSSI_MNTR\n",
1609 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1610 PDM_SNPF(out_len, used, output + used, out_len - used,
1611 "05. (( %s ))CCK_PD\n",
1612 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1613 PDM_SNPF(out_len, used, output + used, out_len - used,
1614 "06. (( %s ))ANT_DIV\n",
1615 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1616 PDM_SNPF(out_len, used, output + used, out_len - used,
1617 "07. (( %s ))SMT_ANT\n",
1618 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1619 PDM_SNPF(out_len, used, output + used, out_len - used,
1620 "08. (( %s ))PWR_TRAIN\n",
1621 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1622 PDM_SNPF(out_len, used, output + used, out_len - used,
1623 "09. (( %s ))RA\n",
1624 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1625 PDM_SNPF(out_len, used, output + used, out_len - used,
1626 "10. (( %s ))PATH_DIV\n",
1627 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1628 PDM_SNPF(out_len, used, output + used, out_len - used,
1629 "11. (( %s ))DFS\n",
1630 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1631 PDM_SNPF(out_len, used, output + used, out_len - used,
1632 "12. (( %s ))DYN_ARFR\n",
1633 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1634 PDM_SNPF(out_len, used, output + used, out_len - used,
1635 "13. (( %s ))ADAPTIVITY\n",
1636 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1637 PDM_SNPF(out_len, used, output + used, out_len - used,
1638 "14. (( %s ))CFO_TRACK\n",
1639 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1640 PDM_SNPF(out_len, used, output + used, out_len - used,
1641 "15. (( %s ))ENV_MONITOR\n",
1642 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1643 PDM_SNPF(out_len, used, output + used, out_len - used,
1644 "16. (( %s ))PRI_CCA\n",
1645 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1646 PDM_SNPF(out_len, used, output + used, out_len - used,
1647 "17. (( %s ))ADPTV_SOML\n",
1648 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1649 PDM_SNPF(out_len, used, output + used, out_len - used,
1650 "18. (( %s ))LNA_SAT_CHK\n",
1651 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1652
1653 PDM_SNPF(out_len, used, output + used, out_len - used,
1654 "================================\n");
1655 PDM_SNPF(out_len, used, output + used, out_len - used,
1656 "[Supportability] PhyDM offload ability\n");
1657 PDM_SNPF(out_len, used, output + used, out_len - used,
1658 "================================\n");
1659
1660 PDM_SNPF(out_len, used, output + used, out_len - used,
1661 "00. (( %s ))PHY PARAM OFFLOAD\n",
1662 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1663 ("V") : (".")));
1664 PDM_SNPF(out_len, used, output + used, out_len - used,
1665 "01. (( %s ))RF IQK OFFLOAD\n",
1666 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1667 ("V") : (".")));
1668 PDM_SNPF(out_len, used, output + used, out_len - used,
1669 "================================\n");
1670
1671 } else if (dm_value[0] == 101) {
1672 dm->support_ability = 0;
1673 PDM_SNPF(out_len, used, output + used, out_len - used,
1674 "Disable all support_ability components\n");
1675 } else {
1676 if (dm_value[1] == 1) { /* @enable */
1677 dm->support_ability |= (one << dm_value[0]);
1678 } else if (dm_value[1] == 2) {/* @disable */
1679 dm->support_ability &= ~(one << dm_value[0]);
1680 } else {
1681 PDM_SNPF(out_len, used, output + used, out_len - used,
1682 "[Warning!!!] 1:enable, 2:disable\n");
1683 }
1684 }
1685 PDM_SNPF(out_len, used, output + used, out_len - used,
1686 "pre-supportability = 0x%llx\n", pre_support_ability);
1687 PDM_SNPF(out_len, used, output + used, out_len - used,
1688 "Cur-supportability = 0x%llx\n", dm->support_ability);
1689 PDM_SNPF(out_len, used, output + used, out_len - used,
1690 "================================\n");
1691
1692 *_used = used;
1693 *_out_len = out_len;
1694 }
1695
phydm_watchdog_lps_32k(struct dm_struct * dm)1696 void phydm_watchdog_lps_32k(struct dm_struct *dm)
1697 {
1698 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1699
1700 phydm_common_info_self_update(dm);
1701 phydm_rssi_monitor_check(dm);
1702 phydm_dig_lps_32k(dm);
1703 phydm_common_info_self_reset(dm);
1704 }
1705
phydm_watchdog_lps(struct dm_struct * dm)1706 void phydm_watchdog_lps(struct dm_struct *dm)
1707 {
1708 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1709 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1710
1711 phydm_common_info_self_update(dm);
1712 phydm_rssi_monitor_check(dm);
1713 phydm_basic_dbg_message(dm);
1714 phydm_receiver_blocking(dm);
1715 phydm_false_alarm_counter_statistics(dm);
1716 phydm_dig_by_rssi_lps(dm);
1717 #ifdef PHYDM_SUPPORT_CCKPD
1718 phydm_cck_pd_th(dm);
1719 #endif
1720 phydm_adaptivity(dm);
1721 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1722 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1723 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
1724 odm_antenna_diversity(dm);
1725 #endif
1726 #endif
1727 phydm_common_info_self_reset(dm);
1728 #endif
1729 }
1730
phydm_watchdog_mp(struct dm_struct * dm)1731 void phydm_watchdog_mp(struct dm_struct *dm)
1732 {
1733 }
1734
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)1735 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
1736 {
1737 struct dm_struct *dm = (struct dm_struct *)dm_void;
1738
1739 if (pause_type == PHYDM_PAUSE) {
1740 dm->disable_phydm_watchdog = 1;
1741 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
1742 } else {
1743 dm->disable_phydm_watchdog = 0;
1744 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
1745 }
1746 }
1747
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)1748 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
1749 enum phydm_pause_type pause_type,
1750 enum phydm_pause_level pause_lv, u8 val_lehgth,
1751 u32 *val_buf)
1752 {
1753 struct dm_struct *dm = (struct dm_struct *)dm_void;
1754 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
1755 s8 *pause_lv_pre = &dm->s8_dummy;
1756 u32 *bkp_val = &dm->u32_dummy;
1757 u32 ori_val[5] = {0};
1758 u64 pause_func_bitmap = (u64)BIT(pause_func);
1759 u8 i = 0;
1760 u8 en_2rcca = 0;
1761 u8 en_bw40m = 0;
1762 u8 pause_result = PAUSE_FAIL;
1763
1764 PHYDM_DBG(dm, ODM_COMP_API, "\n");
1765 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
1766 ((pause_type == PHYDM_PAUSE) ? "Pause" :
1767 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
1768 pause_lv, val_lehgth);
1769
1770 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
1771 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
1772 return PAUSE_FAIL;
1773 }
1774
1775 if (pause_func == F00_DIG) {
1776 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
1777
1778 if (val_lehgth != 1) {
1779 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1780 return PAUSE_FAIL;
1781 }
1782
1783 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
1784 pause_lv_pre = &dm->pause_lv_table.lv_dig;
1785 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
1786 /*@function pointer hook*/
1787 func_t->pause_phydm_handler = phydm_set_dig_val;
1788
1789 #ifdef PHYDM_SUPPORT_CCKPD
1790 } else if (pause_func == F05_CCK_PD) {
1791 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
1792
1793 if (val_lehgth != 1) {
1794 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1795 return PAUSE_FAIL;
1796 }
1797
1798 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
1799 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
1800 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
1801 /*@function pointer hook*/
1802 func_t->pause_phydm_handler = phydm_set_cckpd_val;
1803 #endif
1804
1805 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1806 } else if (pause_func == F06_ANT_DIV) {
1807 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
1808
1809 if (val_lehgth != 1) {
1810 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1811 return PAUSE_FAIL;
1812 }
1813 /*@default antenna*/
1814 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
1815 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
1816 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
1817 /*@function pointer hook*/
1818 func_t->pause_phydm_handler = phydm_set_antdiv_val;
1819
1820 #endif
1821 #ifdef PHYDM_SUPPORT_ADAPTIVITY
1822 } else if (pause_func == F13_ADPTVTY) {
1823 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
1824
1825 if (val_lehgth != 2) {
1826 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
1827 return PAUSE_FAIL;
1828 }
1829
1830 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
1831 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
1832 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
1833 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
1834 /*@function pointer hook*/
1835 func_t->pause_phydm_handler = phydm_set_edcca_val;
1836
1837 #endif
1838 #ifdef CONFIG_ADAPTIVE_SOML
1839 } else if (pause_func == F17_ADPTV_SOML) {
1840 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
1841
1842 if (val_lehgth != 1) {
1843 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
1844 return PAUSE_FAIL;
1845 }
1846 /*SOML_ON/OFF*/
1847 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
1848
1849 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
1850 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
1851 /*@function pointer hook*/
1852 func_t->pause_phydm_handler = phydm_set_adsl_val;
1853
1854 #endif
1855 } else {
1856 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
1857 return PAUSE_FAIL;
1858 }
1859
1860 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
1861 pause_lv, *pause_lv_pre);
1862
1863 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
1864 if (pause_lv <= *pause_lv_pre) {
1865 PHYDM_DBG(dm, ODM_COMP_API,
1866 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
1867 return PAUSE_FAIL;
1868 }
1869
1870 if (!(dm->pause_ability & pause_func_bitmap)) {
1871 for (i = 0; i < val_lehgth; i++)
1872 bkp_val[i] = ori_val[i];
1873 }
1874
1875 dm->pause_ability |= pause_func_bitmap;
1876 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
1877 dm->pause_ability);
1878
1879 if (pause_type == PHYDM_PAUSE) {
1880 for (i = 0; i < val_lehgth; i++)
1881 PHYDM_DBG(dm, ODM_COMP_API,
1882 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
1883 i, val_buf[i], bkp_val[i]);
1884 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
1885 } else {
1886 for (i = 0; i < val_lehgth; i++)
1887 PHYDM_DBG(dm, ODM_COMP_API,
1888 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
1889 i, bkp_val[i]);
1890 }
1891
1892 *pause_lv_pre = pause_lv;
1893 pause_result = PAUSE_SUCCESS;
1894
1895 } else if (pause_type == PHYDM_RESUME) {
1896 if ((dm->pause_ability & pause_func_bitmap) == 0) {
1897 PHYDM_DBG(dm, ODM_COMP_API,
1898 "[RESUME] No Need to Revert\n");
1899 return PAUSE_SUCCESS;
1900 }
1901
1902 dm->pause_ability &= ~pause_func_bitmap;
1903 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
1904 dm->pause_ability);
1905
1906 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
1907
1908 for (i = 0; i < val_lehgth; i++) {
1909 PHYDM_DBG(dm, ODM_COMP_API,
1910 "[RESUME] val_idx[%d]={0x%x}\n", i,
1911 bkp_val[i]);
1912 }
1913
1914 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
1915
1916 pause_result = PAUSE_SUCCESS;
1917 } else {
1918 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
1919 pause_result = PAUSE_FAIL;
1920 }
1921 return pause_result;
1922 }
1923
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1924 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
1925 char *output, u32 *_out_len)
1926 {
1927 struct dm_struct *dm = (struct dm_struct *)dm_void;
1928 char help[] = "-h";
1929 u32 var1[10] = {0};
1930 u32 used = *_used;
1931 u32 out_len = *_out_len;
1932 u32 i;
1933 u8 length = 0;
1934 u32 buf[5] = {0};
1935 u8 set_result = 0;
1936 enum phydm_func_idx func = 0;
1937 enum phydm_pause_type type = 0;
1938 enum phydm_pause_level lv = 0;
1939
1940 if ((strcmp(input[1], help) == 0)) {
1941 PDM_SNPF(out_len, used, output + used, out_len - used,
1942 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
1943
1944 goto out;
1945 }
1946
1947 for (i = 0; i < 10; i++) {
1948 if (input[i + 1])
1949 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
1950 }
1951
1952 func = (enum phydm_func_idx)var1[0];
1953 type = (enum phydm_pause_type)var1[1];
1954 lv = (enum phydm_pause_level)var1[2];
1955
1956 for (i = 0; i < 5; i++)
1957 buf[i] = var1[3 + i];
1958
1959 if (func == F00_DIG) {
1960 PDM_SNPF(out_len, used, output + used, out_len - used,
1961 "[DIG]\n");
1962 length = 1;
1963
1964 } else if (func == F05_CCK_PD) {
1965 PDM_SNPF(out_len, used, output + used, out_len - used,
1966 "[CCK_PD]\n");
1967 length = 1;
1968 } else if (func == F06_ANT_DIV) {
1969 PDM_SNPF(out_len, used, output + used, out_len - used,
1970 "[Ant_Div]\n");
1971 length = 1;
1972 } else if (func == F13_ADPTVTY) {
1973 PDM_SNPF(out_len, used, output + used, out_len - used,
1974 "[Adaptivity]\n");
1975 length = 2;
1976 } else if (func == F17_ADPTV_SOML) {
1977 PDM_SNPF(out_len, used, output + used, out_len - used,
1978 "[ADSL]\n");
1979 length = 1;
1980 } else {
1981 PDM_SNPF(out_len, used, output + used, out_len - used,
1982 "[Set Function Error]\n");
1983 length = 0;
1984 }
1985
1986 if (length != 0) {
1987 PDM_SNPF(out_len, used, output + used, out_len - used,
1988 "{%s, lv=%d} val = %d, %d}\n",
1989 ((type == PHYDM_PAUSE) ? "Pause" :
1990 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
1991 lv, var1[3], var1[4]);
1992
1993 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
1994 }
1995
1996 PDM_SNPF(out_len, used, output + used, out_len - used,
1997 "set_result = %d\n", set_result);
1998
1999 out:
2000 *_used = used;
2001 *_out_len = out_len;
2002 }
2003
phydm_stop_dm_watchdog_check(void * dm_void)2004 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2005 {
2006 struct dm_struct *dm = (struct dm_struct *)dm_void;
2007
2008 if (dm->disable_phydm_watchdog == 1) {
2009 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2010 return true;
2011 } else {
2012 return false;
2013 }
2014 }
2015
phydm_watchdog(struct dm_struct * dm)2016 void phydm_watchdog(struct dm_struct *dm)
2017 {
2018 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2019
2020 phydm_common_info_self_update(dm);
2021 phydm_phy_info_update(dm);
2022 phydm_rssi_monitor_check(dm);
2023 phydm_basic_dbg_message(dm);
2024 phydm_dm_summary(dm, FIRST_MACID);
2025 #ifdef PHYDM_AUTO_DEGBUG
2026 phydm_auto_dbg_engine(dm);
2027 #endif
2028 phydm_receiver_blocking(dm);
2029
2030 if (phydm_stop_dm_watchdog_check(dm) == true)
2031 return;
2032
2033 phydm_hw_setting(dm);
2034
2035 #ifdef PHYDM_TDMA_DIG_SUPPORT
2036 if (dm->original_dig_restore == 0)
2037 phydm_tdma_dig_timer_check(dm);
2038 else
2039 #endif
2040 {
2041 phydm_false_alarm_counter_statistics(dm);
2042 phydm_noisy_detection(dm);
2043 phydm_dig(dm);
2044 #ifdef PHYDM_SUPPORT_CCKPD
2045 phydm_cck_pd_th(dm);
2046 #endif
2047 }
2048
2049 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2050 phydm_update_power_training_state(dm);
2051 #endif
2052 phydm_adaptivity(dm);
2053 phydm_ra_info_watchdog(dm);
2054 #ifdef CONFIG_PATH_DIVERSITY
2055 phydm_tx_path_diversity(dm);
2056 #endif
2057 phydm_cfo_tracking(dm);
2058 #ifdef CONFIG_DYNAMIC_TX_TWR
2059 phydm_dynamic_tx_power(dm);
2060 #endif
2061 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2062 odm_antenna_diversity(dm);
2063 #endif
2064 #ifdef CONFIG_ADAPTIVE_SOML
2065 phydm_adaptive_soml(dm);
2066 #endif
2067
2068 #ifdef PHYDM_BEAMFORMING_VERSION1
2069 phydm_beamforming_watchdog(dm);
2070 #endif
2071
2072 halrf_watchdog(dm);
2073 #ifdef PHYDM_PRIMARY_CCA
2074 phydm_primary_cca(dm);
2075 #endif
2076 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2077 odm_dtc(dm);
2078 #endif
2079
2080 phydm_env_mntr_watchdog(dm);
2081
2082 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2083 phydm_lna_sat_chk_watchdog(dm);
2084 #endif
2085 #ifdef CONFIG_MCC_DM
2086 phydm_mcc_switch(dm);
2087 #endif
2088
2089 #ifdef CONFIG_MU_RSOML
2090 phydm_mu_rsoml_decision(dm);
2091 #endif
2092
2093 phydm_common_info_self_reset(dm);
2094 }
2095
2096 /*@
2097 * Init /.. Fixed HW value. Only init time.
2098 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2099 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2100 u64 value)
2101 {
2102 /* This section is used for init value */
2103 switch (cmn_info) {
2104 /* @Fixed ODM value. */
2105 case ODM_CMNINFO_ABILITY:
2106 dm->support_ability = (u64)value;
2107 break;
2108
2109 case ODM_CMNINFO_RF_TYPE:
2110 dm->rf_type = (u8)value;
2111 break;
2112
2113 case ODM_CMNINFO_PLATFORM:
2114 dm->support_platform = (u8)value;
2115 break;
2116
2117 case ODM_CMNINFO_INTERFACE:
2118 dm->support_interface = (u8)value;
2119 break;
2120
2121 case ODM_CMNINFO_MP_TEST_CHIP:
2122 dm->is_mp_chip = (u8)value;
2123 break;
2124
2125 case ODM_CMNINFO_IC_TYPE:
2126 dm->support_ic_type = (u32)value;
2127 break;
2128
2129 case ODM_CMNINFO_CUT_VER:
2130 dm->cut_version = (u8)value;
2131 break;
2132
2133 case ODM_CMNINFO_FAB_VER:
2134 dm->fab_version = (u8)value;
2135 break;
2136 case ODM_CMNINFO_FW_VER:
2137 dm->fw_version = (u8)value;
2138 break;
2139 case ODM_CMNINFO_FW_SUB_VER:
2140 dm->fw_sub_version = (u8)value;
2141 break;
2142 case ODM_CMNINFO_RFE_TYPE:
2143 #if (RTL8821C_SUPPORT)
2144 if (dm->support_ic_type & ODM_RTL8821C)
2145 dm->rfe_type_expand = (u8)value;
2146 else
2147 #endif
2148 dm->rfe_type = (u8)value;
2149 phydm_init_hw_info_by_rfe(dm);
2150 break;
2151
2152 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2153 dm->ant_div_type = (u8)value;
2154 break;
2155
2156 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2157 dm->with_extenal_ant_switch = (u8)value;
2158 break;
2159
2160 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2161 case ODM_CMNINFO_BE_FIX_TX_ANT:
2162 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2163 break;
2164 #endif
2165
2166 case ODM_CMNINFO_BOARD_TYPE:
2167 if (!dm->is_init_hw_info_by_rfe)
2168 dm->board_type = (u8)value;
2169 break;
2170
2171 case ODM_CMNINFO_PACKAGE_TYPE:
2172 if (!dm->is_init_hw_info_by_rfe)
2173 dm->package_type = (u8)value;
2174 break;
2175
2176 case ODM_CMNINFO_EXT_LNA:
2177 if (!dm->is_init_hw_info_by_rfe)
2178 dm->ext_lna = (u8)value;
2179 break;
2180
2181 case ODM_CMNINFO_5G_EXT_LNA:
2182 if (!dm->is_init_hw_info_by_rfe)
2183 dm->ext_lna_5g = (u8)value;
2184 break;
2185
2186 case ODM_CMNINFO_EXT_PA:
2187 if (!dm->is_init_hw_info_by_rfe)
2188 dm->ext_pa = (u8)value;
2189 break;
2190
2191 case ODM_CMNINFO_5G_EXT_PA:
2192 if (!dm->is_init_hw_info_by_rfe)
2193 dm->ext_pa_5g = (u8)value;
2194 break;
2195
2196 case ODM_CMNINFO_GPA:
2197 if (!dm->is_init_hw_info_by_rfe)
2198 dm->type_gpa = (u16)value;
2199 break;
2200
2201 case ODM_CMNINFO_APA:
2202 if (!dm->is_init_hw_info_by_rfe)
2203 dm->type_apa = (u16)value;
2204 break;
2205
2206 case ODM_CMNINFO_GLNA:
2207 if (!dm->is_init_hw_info_by_rfe)
2208 dm->type_glna = (u16)value;
2209 break;
2210
2211 case ODM_CMNINFO_ALNA:
2212 if (!dm->is_init_hw_info_by_rfe)
2213 dm->type_alna = (u16)value;
2214 break;
2215
2216 case ODM_CMNINFO_EXT_TRSW:
2217 if (!dm->is_init_hw_info_by_rfe)
2218 dm->ext_trsw = (u8)value;
2219 break;
2220 case ODM_CMNINFO_EXT_LNA_GAIN:
2221 dm->ext_lna_gain = (u8)value;
2222 break;
2223 case ODM_CMNINFO_PATCH_ID:
2224 dm->iot_table.win_patch_id = (u8)value;
2225 break;
2226 case ODM_CMNINFO_BINHCT_TEST:
2227 dm->is_in_hct_test = (boolean)value;
2228 break;
2229 case ODM_CMNINFO_BWIFI_TEST:
2230 dm->wifi_test = (u8)value;
2231 break;
2232 case ODM_CMNINFO_SMART_CONCURRENT:
2233 dm->is_dual_mac_smart_concurrent = (boolean)value;
2234 break;
2235 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2236 case ODM_CMNINFO_CONFIG_BB_RF:
2237 dm->config_bbrf = (boolean)value;
2238 break;
2239 #endif
2240 case ODM_CMNINFO_IQKPAOFF:
2241 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2242 break;
2243 case ODM_CMNINFO_REGRFKFREEENABLE:
2244 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2245 break;
2246 case ODM_CMNINFO_RFKFREEENABLE:
2247 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2248 break;
2249 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2250 dm->normal_rx_path = (u8)value;
2251 break;
2252 case ODM_CMNINFO_VALID_PATH_SET:
2253 dm->valid_path_set = (u8)value;
2254 break;
2255 case ODM_CMNINFO_EFUSE0X3D8:
2256 dm->efuse0x3d8 = (u8)value;
2257 break;
2258 case ODM_CMNINFO_EFUSE0X3D7:
2259 dm->efuse0x3d7 = (u8)value;
2260 break;
2261 case ODM_CMNINFO_ADVANCE_OTA:
2262 dm->p_advance_ota = (u8)value;
2263 break;
2264
2265 #ifdef CONFIG_PHYDM_DFS_MASTER
2266 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2267 dm->dfs_region_domain = (u8)value;
2268 break;
2269 #endif
2270 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2271 dm->soft_ap_special_setting = (u32)value;
2272 break;
2273
2274 case ODM_CMNINFO_X_CAP_SETTING:
2275 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2276 break;
2277
2278 case ODM_CMNINFO_DPK_EN:
2279 /*@dm->dpk_en = (u1Byte)value;*/
2280 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2281 break;
2282
2283 case ODM_CMNINFO_HP_HWID:
2284 dm->hp_hw_id = (boolean)value;
2285 break;
2286 case ODM_CMNINFO_DIS_DPD:
2287 dm->en_dis_dpd = (boolean)value;
2288 break;
2289 default:
2290 break;
2291 }
2292 }
2293
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2294 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2295 void *value)
2296 {
2297 /* @Hook call by reference pointer. */
2298 switch (cmn_info) {
2299 /* @Dynamic call by reference pointer. */
2300 case ODM_CMNINFO_TX_UNI:
2301 dm->num_tx_bytes_unicast = (u64 *)value;
2302 break;
2303
2304 case ODM_CMNINFO_RX_UNI:
2305 dm->num_rx_bytes_unicast = (u64 *)value;
2306 break;
2307
2308 case ODM_CMNINFO_BAND:
2309 dm->band_type = (u8 *)value;
2310 break;
2311
2312 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2313 dm->sec_ch_offset = (u8 *)value;
2314 break;
2315
2316 case ODM_CMNINFO_SEC_MODE:
2317 dm->security = (u8 *)value;
2318 break;
2319
2320 case ODM_CMNINFO_BW:
2321 dm->band_width = (u8 *)value;
2322 break;
2323
2324 case ODM_CMNINFO_CHNL:
2325 dm->channel = (u8 *)value;
2326 break;
2327
2328 case ODM_CMNINFO_SCAN:
2329 dm->is_scan_in_process = (boolean *)value;
2330 break;
2331
2332 case ODM_CMNINFO_POWER_SAVING:
2333 dm->is_power_saving = (boolean *)value;
2334 break;
2335
2336 case ODM_CMNINFO_TDMA:
2337 dm->is_tdma = (boolean *)value;
2338 break;
2339
2340 case ODM_CMNINFO_ONE_PATH_CCA:
2341 dm->one_path_cca = (u8 *)value;
2342 break;
2343
2344 case ODM_CMNINFO_DRV_STOP:
2345 dm->is_driver_stopped = (boolean *)value;
2346 break;
2347 case ODM_CMNINFO_INIT_ON:
2348 dm->pinit_adpt_in_progress = (boolean *)value;
2349 break;
2350
2351 case ODM_CMNINFO_ANT_TEST:
2352 dm->antenna_test = (u8 *)value;
2353 break;
2354
2355 case ODM_CMNINFO_NET_CLOSED:
2356 dm->is_net_closed = (boolean *)value;
2357 break;
2358
2359 case ODM_CMNINFO_FORCED_RATE:
2360 dm->forced_data_rate = (u16 *)value;
2361 break;
2362 case ODM_CMNINFO_ANT_DIV:
2363 dm->enable_antdiv = (u8 *)value;
2364 break;
2365 case ODM_CMNINFO_PATH_DIV:
2366 dm->enable_pathdiv = (u8 *)value;
2367 break;
2368 case ODM_CMNINFO_ADAPTIVE_SOML:
2369 dm->en_adap_soml = (u8 *)value;
2370 break;
2371 case ODM_CMNINFO_ADAPTIVITY:
2372 dm->enable_adaptivity = (u8 *)value;
2373 break;
2374
2375 case ODM_CMNINFO_P2P_LINK:
2376 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2377 break;
2378
2379 case ODM_CMNINFO_IS1ANTENNA:
2380 dm->is_1_antenna = (boolean *)value;
2381 break;
2382
2383 case ODM_CMNINFO_RFDEFAULTPATH:
2384 dm->rf_default_path = (u8 *)value;
2385 break;
2386
2387 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2388 dm->is_fcs_mode_enable = (boolean *)value;
2389 break;
2390
2391 case ODM_CMNINFO_HUBUSBMODE:
2392 dm->hub_usb_mode = (u8 *)value;
2393 break;
2394 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2395 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2396 break;
2397 case ODM_CMNINFO_TX_TP:
2398 dm->current_tx_tp = (u32 *)value;
2399 break;
2400 case ODM_CMNINFO_RX_TP:
2401 dm->current_rx_tp = (u32 *)value;
2402 break;
2403 case ODM_CMNINFO_SOUNDING_SEQ:
2404 dm->sounding_seq = (u8 *)value;
2405 break;
2406 #ifdef CONFIG_PHYDM_DFS_MASTER
2407 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2408 dm->dfs_master_enabled = (u8 *)value;
2409 break;
2410 #endif
2411
2412 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2413 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2414 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2415 break;
2416 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2417 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2418 break;
2419 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2420 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2421 break;
2422 #endif
2423
2424 case ODM_CMNINFO_SOFT_AP_MODE:
2425 dm->soft_ap_mode = (u32 *)value;
2426 break;
2427 case ODM_CMNINFO_MP_MODE:
2428 dm->mp_mode = (u8 *)value;
2429 break;
2430 case ODM_CMNINFO_INTERRUPT_MASK:
2431 dm->interrupt_mask = (u32 *)value;
2432 break;
2433 case ODM_CMNINFO_BB_OPERATION_MODE:
2434 dm->bb_op_mode = (u8 *)value;
2435 break;
2436 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2437 dm->manual_supportability = (u32 *)value;
2438 break;
2439 default:
2440 /*do nothing*/
2441 break;
2442 }
2443 }
2444
2445 /*@
2446 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2447 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2448 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2449 {
2450 /* This init variable may be changed in run time. */
2451 switch (cmn_info) {
2452 case ODM_CMNINFO_LINK_IN_PROGRESS:
2453 dm->is_link_in_process = (boolean)value;
2454 break;
2455
2456 case ODM_CMNINFO_ABILITY:
2457 dm->support_ability = (u64)value;
2458 break;
2459
2460 case ODM_CMNINFO_RF_TYPE:
2461 dm->rf_type = (u8)value;
2462 break;
2463
2464 case ODM_CMNINFO_WIFI_DIRECT:
2465 dm->is_wifi_direct = (boolean)value;
2466 break;
2467
2468 case ODM_CMNINFO_WIFI_DISPLAY:
2469 dm->is_wifi_display = (boolean)value;
2470 break;
2471
2472 case ODM_CMNINFO_LINK:
2473 dm->is_linked = (boolean)value;
2474 break;
2475
2476 case ODM_CMNINFO_CMW500LINK:
2477 dm->iot_table.is_linked_cmw500 = (boolean)value;
2478 break;
2479
2480 case ODM_CMNINFO_STATION_STATE:
2481 dm->bsta_state = (boolean)value;
2482 break;
2483
2484 case ODM_CMNINFO_RSSI_MIN:
2485 dm->rssi_min = (u8)value;
2486 break;
2487
2488 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2489 dm->rssi_min_by_path = (u8)value;
2490 break;
2491
2492 case ODM_CMNINFO_DBG_COMP:
2493 dm->debug_components = (u64)value;
2494 break;
2495
2496 #ifdef ODM_CONFIG_BT_COEXIST
2497 /* The following is for BT HS mode and BT coexist mechanism. */
2498 case ODM_CMNINFO_BT_ENABLED:
2499 dm->bt_info_table.is_bt_enabled = (boolean)value;
2500 break;
2501
2502 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2503 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2504 break;
2505
2506 case ODM_CMNINFO_BT_HS_RSSI:
2507 dm->bt_info_table.bt_hs_rssi = (u8)value;
2508 break;
2509
2510 case ODM_CMNINFO_BT_OPERATION:
2511 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2512 break;
2513
2514 case ODM_CMNINFO_BT_LIMITED_DIG:
2515 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2516 break;
2517 #endif
2518
2519 case ODM_CMNINFO_AP_TOTAL_NUM:
2520 dm->ap_total_num = (u8)value;
2521 break;
2522
2523 #ifdef CONFIG_PHYDM_DFS_MASTER
2524 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2525 dm->dfs_region_domain = (u8)value;
2526 break;
2527 #endif
2528
2529 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2530 dm->is_bt_continuous_turn = (boolean)value;
2531 break;
2532 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2533 dm->is_download_fw = (boolean)value;
2534 break;
2535 case ODM_CMNINFO_PHYDM_PATCH_ID:
2536 dm->iot_table.phydm_patch_id = (u32)value;
2537 break;
2538 case ODM_CMNINFO_RRSR_VAL:
2539 dm->dm_ra_table.rrsr_val_init = (u32)value;
2540 break;
2541 default:
2542 break;
2543 }
2544 }
2545
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)2546 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
2547 {
2548 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2549 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2550 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2551
2552 switch (info_type) {
2553 /*@=== [FA Relative] ===========================================*/
2554 case PHYDM_INFO_FA_OFDM:
2555 return fa_t->cnt_ofdm_fail;
2556
2557 case PHYDM_INFO_FA_CCK:
2558 return fa_t->cnt_cck_fail;
2559
2560 case PHYDM_INFO_FA_TOTAL:
2561 return fa_t->cnt_all;
2562
2563 case PHYDM_INFO_CCA_OFDM:
2564 return fa_t->cnt_ofdm_cca;
2565
2566 case PHYDM_INFO_CCA_CCK:
2567 return fa_t->cnt_cck_cca;
2568
2569 case PHYDM_INFO_CCA_ALL:
2570 return fa_t->cnt_cca_all;
2571
2572 case PHYDM_INFO_CRC32_OK_VHT:
2573 return fa_t->cnt_vht_crc32_ok;
2574
2575 case PHYDM_INFO_CRC32_OK_HT:
2576 return fa_t->cnt_ht_crc32_ok;
2577
2578 case PHYDM_INFO_CRC32_OK_LEGACY:
2579 return fa_t->cnt_ofdm_crc32_ok;
2580
2581 case PHYDM_INFO_CRC32_OK_CCK:
2582 return fa_t->cnt_cck_crc32_ok;
2583
2584 case PHYDM_INFO_CRC32_ERROR_VHT:
2585 return fa_t->cnt_vht_crc32_error;
2586
2587 case PHYDM_INFO_CRC32_ERROR_HT:
2588 return fa_t->cnt_ht_crc32_error;
2589
2590 case PHYDM_INFO_CRC32_ERROR_LEGACY:
2591 return fa_t->cnt_ofdm_crc32_error;
2592
2593 case PHYDM_INFO_CRC32_ERROR_CCK:
2594 return fa_t->cnt_cck_crc32_error;
2595
2596 case PHYDM_INFO_EDCCA_FLAG:
2597 return fa_t->edcca_flag;
2598
2599 case PHYDM_INFO_OFDM_ENABLE:
2600 return fa_t->ofdm_block_enable;
2601
2602 case PHYDM_INFO_CCK_ENABLE:
2603 return fa_t->cck_block_enable;
2604
2605 case PHYDM_INFO_DBG_PORT_0:
2606 return fa_t->dbg_port0;
2607
2608 case PHYDM_INFO_CRC32_OK_HT_AGG:
2609 return fa_t->cnt_ht_crc32_ok_agg;
2610
2611 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
2612 return fa_t->cnt_ht_crc32_error_agg;
2613
2614 /*@=== [DIG] ================================================*/
2615
2616 case PHYDM_INFO_CURR_IGI:
2617 return dig_t->cur_ig_value;
2618
2619 /*@=== [RSSI] ===============================================*/
2620 case PHYDM_INFO_RSSI_MIN:
2621 return (u32)dm->rssi_min;
2622
2623 case PHYDM_INFO_RSSI_MAX:
2624 return (u32)dm->rssi_max;
2625
2626 case PHYDM_INFO_CLM_RATIO:
2627 return (u32)ccx_info->clm_ratio;
2628 case PHYDM_INFO_NHM_RATIO:
2629 return (u32)ccx_info->nhm_ratio;
2630 default:
2631 return 0xffffffff;
2632 }
2633 }
2634
2635 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)2636 void odm_init_all_work_items(struct dm_struct *dm)
2637 {
2638 void *adapter = dm->adapter;
2639 #if USE_WORKITEM
2640
2641 #ifdef CONFIG_ADAPTIVE_SOML
2642 odm_initialize_work_item(dm,
2643 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
2644 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
2645 (void *)adapter,
2646 "AdaptiveSOMLWorkitem");
2647 #endif
2648
2649 #ifdef ODM_EVM_ENHANCE_ANTDIV
2650 odm_initialize_work_item(dm,
2651 &dm->phydm_evm_antdiv_workitem,
2652 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
2653 (void *)adapter,
2654 "EvmAntdivWorkitem");
2655 #endif
2656
2657 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2658 odm_initialize_work_item(dm,
2659 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
2660 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
2661 (void *)adapter,
2662 "AntennaSwitchWorkitem");
2663 #endif
2664 #if (defined(CONFIG_HL_SMART_ANTENNA))
2665 odm_initialize_work_item(dm,
2666 &dm->dm_sat_table.hl_smart_antenna_workitem,
2667 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
2668 (void *)adapter,
2669 "hl_smart_ant_workitem");
2670
2671 odm_initialize_work_item(dm,
2672 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
2673 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
2674 (void *)adapter,
2675 "hl_smart_ant_decision_workitem");
2676 #endif
2677
2678 odm_initialize_work_item(
2679 dm,
2680 &dm->ra_rpt_workitem,
2681 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
2682 (void *)adapter,
2683 "ra_rpt_workitem");
2684
2685 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2686 odm_initialize_work_item(
2687 dm,
2688 &dm->fast_ant_training_workitem,
2689 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
2690 (void *)adapter,
2691 "fast_ant_training_workitem");
2692 #endif
2693
2694 #endif /*#if USE_WORKITEM*/
2695
2696 #ifdef PHYDM_BEAMFORMING_SUPPORT
2697 odm_initialize_work_item(
2698 dm,
2699 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
2700 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
2701 (void *)adapter,
2702 "txbf_enter_work_item");
2703
2704 odm_initialize_work_item(
2705 dm,
2706 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
2707 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
2708 (void *)adapter,
2709 "txbf_leave_work_item");
2710
2711 odm_initialize_work_item(
2712 dm,
2713 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
2714 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
2715 (void *)adapter,
2716 "txbf_fw_ndpa_work_item");
2717
2718 odm_initialize_work_item(
2719 dm,
2720 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
2721 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
2722 (void *)adapter,
2723 "txbf_clk_work_item");
2724
2725 odm_initialize_work_item(
2726 dm,
2727 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
2728 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
2729 (void *)adapter,
2730 "txbf_rate_work_item");
2731
2732 odm_initialize_work_item(
2733 dm,
2734 &dm->beamforming_info.txbf_info.txbf_status_work_item,
2735 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
2736 (void *)adapter,
2737 "txbf_status_work_item");
2738
2739 odm_initialize_work_item(
2740 dm,
2741 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
2742 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
2743 (void *)adapter,
2744 "txbf_reset_tx_path_work_item");
2745
2746 odm_initialize_work_item(
2747 dm,
2748 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
2749 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
2750 (void *)adapter,
2751 "txbf_get_tx_rate_work_item");
2752 #endif
2753
2754 #if (PHYDM_LA_MODE_SUPPORT == 1)
2755 odm_initialize_work_item(
2756 dm,
2757 &dm->adcsmp.adc_smp_work_item,
2758 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2759 (void *)adapter,
2760 "adc_smp_work_item");
2761
2762 odm_initialize_work_item(
2763 dm,
2764 &dm->adcsmp.adc_smp_work_item_1,
2765 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
2766 (void *)adapter,
2767 "adc_smp_work_item_1");
2768 #endif
2769 }
2770
odm_free_all_work_items(struct dm_struct * dm)2771 void odm_free_all_work_items(struct dm_struct *dm)
2772 {
2773 #if USE_WORKITEM
2774
2775 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2776 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
2777 #endif
2778
2779 #ifdef CONFIG_ADAPTIVE_SOML
2780 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
2781 #endif
2782
2783 #ifdef ODM_EVM_ENHANCE_ANTDIV
2784 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
2785 #endif
2786
2787 #if (defined(CONFIG_HL_SMART_ANTENNA))
2788 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
2789 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
2790 #endif
2791
2792 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
2793 odm_free_work_item(&dm->fast_ant_training_workitem);
2794 #endif
2795 odm_free_work_item(&dm->ra_rpt_workitem);
2796 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
2797 #endif
2798
2799 #ifdef PHYDM_BEAMFORMING_SUPPORT
2800 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
2801 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
2802 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
2803 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
2804 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
2805 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
2806 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
2807 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
2808 #endif
2809
2810 #if (PHYDM_LA_MODE_SUPPORT == 1)
2811 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
2812 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
2813 #endif
2814 }
2815 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
2816
odm_init_all_timers(struct dm_struct * dm)2817 void odm_init_all_timers(struct dm_struct *dm)
2818 {
2819 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2820 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
2821 #endif
2822 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
2823 #ifdef IS_USE_NEW_TDMA
2824 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
2825 #endif
2826 #endif
2827 #ifdef CONFIG_ADAPTIVE_SOML
2828 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
2829 #endif
2830 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2831 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
2832 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
2833 #endif
2834 #endif
2835
2836 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2837 odm_initialize_timer(dm, &dm->sbdcnt_timer,
2838 (void *)phydm_sbd_callback, NULL, "SbdTimer");
2839 #ifdef PHYDM_BEAMFORMING_SUPPORT
2840 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
2841 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
2842 "txbf_fw_ndpa_timer");
2843 #endif
2844 #endif
2845
2846 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2847 #ifdef PHYDM_BEAMFORMING_SUPPORT
2848 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
2849 (void *)beamforming_sw_timer_callback, NULL,
2850 "beamforming_timer");
2851 #endif
2852 #endif
2853 }
2854
odm_cancel_all_timers(struct dm_struct * dm)2855 void odm_cancel_all_timers(struct dm_struct *dm)
2856 {
2857 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2858 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
2859 if (dm->adapter == NULL)
2860 return;
2861 #endif
2862
2863 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2864 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
2865 #endif
2866 #ifdef PHYDM_TDMA_DIG_SUPPORT
2867 #ifdef IS_USE_NEW_TDMA
2868 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
2869 #endif
2870 #endif
2871 #ifdef CONFIG_ADAPTIVE_SOML
2872 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
2873 #endif
2874 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2875 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
2876 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
2877 #endif
2878 #endif
2879
2880 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2881 odm_cancel_timer(dm, &dm->sbdcnt_timer);
2882 #ifdef PHYDM_BEAMFORMING_SUPPORT
2883 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2884 #endif
2885 #endif
2886
2887 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2888 #ifdef PHYDM_BEAMFORMING_SUPPORT
2889 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
2890 #endif
2891 #endif
2892 }
2893
odm_release_all_timers(struct dm_struct * dm)2894 void odm_release_all_timers(struct dm_struct *dm)
2895 {
2896 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
2897 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
2898 #endif
2899 #ifdef PHYDM_TDMA_DIG_SUPPORT
2900 #ifdef IS_USE_NEW_TDMA
2901 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
2902 #endif
2903 #endif
2904 #ifdef CONFIG_ADAPTIVE_SOML
2905 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
2906 #endif
2907 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2908 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
2909 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
2910 #endif
2911 #endif
2912
2913 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2914 odm_release_timer(dm, &dm->sbdcnt_timer);
2915 #ifdef PHYDM_BEAMFORMING_SUPPORT
2916 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
2917 #endif
2918 #endif
2919
2920 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2921 #ifdef PHYDM_BEAMFORMING_SUPPORT
2922 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
2923 #endif
2924 #endif
2925 }
2926
2927 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)2928 void odm_init_all_threads(
2929 struct dm_struct *dm)
2930 {
2931 #ifdef TPT_THREAD
2932 k_tpt_task_init(dm->priv);
2933 #endif
2934 }
2935
odm_stop_all_threads(struct dm_struct * dm)2936 void odm_stop_all_threads(
2937 struct dm_struct *dm)
2938 {
2939 #ifdef TPT_THREAD
2940 k_tpt_task_stop(dm->priv);
2941 #endif
2942 }
2943 #endif
2944
2945 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2946 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
2947 * 2012/11/05
2948 */
odm_dtc(struct dm_struct * dm)2949 void odm_dtc(struct dm_struct *dm)
2950 {
2951 #ifdef CONFIG_DM_RESP_TXAGC
2952 /* RSSI higher than this value, start to decade TX power */
2953 #define DTC_BASE 35
2954
2955 /* RSSI lower than this value, start to increase TX power */
2956 #define DTC_DWN_BASE (DTC_BASE - 5)
2957
2958 /* RSSI vs TX power step mapping: decade TX power */
2959 static const u8 dtc_table_down[] = {
2960 DTC_BASE,
2961 (DTC_BASE + 5),
2962 (DTC_BASE + 10),
2963 (DTC_BASE + 15),
2964 (DTC_BASE + 20),
2965 (DTC_BASE + 25)};
2966
2967 /* RSSI vs TX power step mapping: increase TX power */
2968 static const u8 dtc_table_up[] = {
2969 DTC_DWN_BASE,
2970 (DTC_DWN_BASE - 5),
2971 (DTC_DWN_BASE - 10),
2972 (DTC_DWN_BASE - 15),
2973 (DTC_DWN_BASE - 15),
2974 (DTC_DWN_BASE - 20),
2975 (DTC_DWN_BASE - 20),
2976 (DTC_DWN_BASE - 25),
2977 (DTC_DWN_BASE - 25),
2978 (DTC_DWN_BASE - 30),
2979 (DTC_DWN_BASE - 35)};
2980
2981 u8 i;
2982 u8 dtc_steps = 0;
2983 u8 sign;
2984 u8 resp_txagc = 0;
2985
2986 #if 0
2987 /* @As DIG is disabled, DTC is also disable */
2988 if (!(dm->support_ability & ODM_XXXXXX))
2989 return;
2990 #endif
2991
2992 if (dm->rssi_min > DTC_BASE) {
2993 /* need to decade the CTS TX power */
2994 sign = 1;
2995 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
2996 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
2997 break;
2998 else
2999 dtc_steps++;
3000 }
3001 }
3002 #if 0
3003 else if (dm->rssi_min > DTC_DWN_BASE) {
3004 /* needs to increase the CTS TX power */
3005 sign = 0;
3006 dtc_steps = 1;
3007 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3008 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3009 break;
3010 else
3011 dtc_steps++;
3012 }
3013 }
3014 #endif
3015 else {
3016 sign = 0;
3017 dtc_steps = 0;
3018 }
3019
3020 resp_txagc = dtc_steps | (sign << 4);
3021 resp_txagc = resp_txagc | (resp_txagc << 5);
3022 odm_write_1byte(dm, 0x06d9, resp_txagc);
3023
3024 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3025 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3026 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3027 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3028 }
3029
3030 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3031
3032 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3033 void phydm_dc_cancellation(struct dm_struct *dm)
3034 {
3035 #ifdef PHYDM_DC_CANCELLATION
3036 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3037 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3038 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3039 u8 path = RF_PATH_A;
3040 u8 set_result;
3041
3042 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3043 return;
3044 if ((dm->support_ic_type & ODM_RTL8188F) &&
3045 dm->cut_version < ODM_CUT_D)
3046 return;
3047 if ((dm->support_ic_type & ODM_RTL8192F) &&
3048 dm->cut_version == ODM_CUT_A)
3049 return;
3050
3051 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3052
3053 /*@DC_Estimation (only for 2x2 ic now) */
3054
3055 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3056 if (path > RF_PATH_A &&
3057 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3058 ODM_RTL8710B | ODM_RTL8721D))
3059 break;
3060 else if (path > RF_PATH_B &&
3061 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3062 break;
3063 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3064 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3065 return;
3066 }
3067 odm_write_dig(dm, 0x7e);
3068 /*@Disable LNA*/
3069 if (dm->support_ic_type & ODM_RTL8821C)
3070 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3071 /*Turn off 3-wire*/
3072 phydm_stop_3_wire(dm, PHYDM_SET);
3073 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
3074 /*set debug port to 0x235*/
3075 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3076 PHYDM_DBG(dm, ODM_COMP_API,
3077 "Set Debug port Fail\n");
3078 return;
3079 }
3080 } else if (dm->support_ic_type & ODM_RTL8721D) {
3081 /*set debug port to 0x200*/
3082 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3083 PHYDM_DBG(dm, ODM_COMP_API,
3084 "Set Debug port Fail\n");
3085 return;
3086 }
3087 } else if (dm->support_ic_type & ODM_RTL8821C) {
3088 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3089 /*set debug port to 0x200*/
3090 PHYDM_DBG(dm, ODM_COMP_API,
3091 "Set Debug port Fail\n");
3092 return;
3093 }
3094 phydm_bb_dbg_port_header_sel(dm, 0x0);
3095 } else if (dm->support_ic_type & ODM_RTL8822B) {
3096 if (path == RF_PATH_A &&
3097 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3098 /*set debug port to 0x200*/
3099 PHYDM_DBG(dm, ODM_COMP_API,
3100 "Set Debug port Fail\n");
3101 return;
3102 }
3103 if (path == RF_PATH_B &&
3104 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3105 /*set debug port to 0x200*/
3106 PHYDM_DBG(dm, ODM_COMP_API,
3107 "Set Debug port Fail\n");
3108 return;
3109 }
3110 phydm_bb_dbg_port_header_sel(dm, 0x0);
3111 } else if (dm->support_ic_type & ODM_RTL8192F) {
3112 if (path == RF_PATH_A &&
3113 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3114 /*set debug port to 0x235*/
3115 PHYDM_DBG(dm, ODM_COMP_API,
3116 "Set Debug port Fail\n");
3117 return;
3118 }
3119 if (path == RF_PATH_B &&
3120 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3121 /*set debug port to 0x23d*/
3122 PHYDM_DBG(dm, ODM_COMP_API,
3123 "Set Debug port Fail\n");
3124 return;
3125 }
3126 }
3127
3128 /*@disable CCK DCNF*/
3129 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3130
3131 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3132
3133 phydm_stop_ck320(dm, true); /*stop ck320*/
3134
3135 /* the same debug port both for path-a and path-b*/
3136 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3137
3138 phydm_stop_ck320(dm, false); /*start ck320*/
3139
3140 phydm_release_bb_dbg_port(dm);
3141 /* @Turn on 3-wire*/
3142 phydm_stop_3_wire(dm, PHYDM_REVERT);
3143 /* @Enable LNA*/
3144 if (dm->support_ic_type & ODM_RTL8821C)
3145 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3146
3147 odm_write_dig(dm, 0x20);
3148
3149 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3150
3151 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3152 }
3153
3154 /*@DC_Cancellation*/
3155 /*@DC compensation to CCK data path*/
3156 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3157 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
3158 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3159 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3160
3161 /*@Before filling into registers,
3162 *offset should be multiplexed (-1)
3163 */
3164 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3165 (0x400 - offset_i_hex[0]) :
3166 (0x1ff - offset_i_hex[0]);
3167 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3168 (0x400 - offset_q_hex[0]) :
3169 (0x1ff - offset_q_hex[0]);
3170
3171 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3172 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3173 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3174 /* Path-a */
3175 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3176 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3177
3178 /*@Before filling into registers,
3179 *offset should be multiplexed (-1)
3180 */
3181 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3182 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3183
3184 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3185 (0x3c0 & offset_i_hex[0]) >> 6);
3186 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3187 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3188 (0x3c0 & offset_q_hex[0]) >> 6);
3189 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3190
3191 /* Path-b */
3192 if (dm->rf_type > RF_1T1R) {
3193 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3194 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3195
3196 /*@Before filling into registers,
3197 *offset should be multiplexed (-1)
3198 */
3199 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3200 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3201
3202 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3203 (0x3c0 & offset_i_hex[1]) >> 6);
3204 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3205 0x3f & offset_i_hex[1]);
3206 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3207 (0x3c0 & offset_q_hex[1]) >> 6);
3208 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3209 0x3f & offset_q_hex[1]);
3210 }
3211 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3212 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3213 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3214 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3215
3216 /*@Before filling into registers,
3217 *offset should be multiplexed (-1)
3218 */
3219 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3220 (0x400 - offset_i_hex[0]) :
3221 (0xff - offset_i_hex[0]);
3222 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3223 (0x400 - offset_q_hex[0]) :
3224 (0xff - offset_q_hex[0]);
3225 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3226 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3227 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3228
3229 /* Path-b */
3230 if (dm->rf_type > RF_1T1R) {
3231 /* @I:df4[27:18],Q:df4[17:8]*/
3232 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3233 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3234
3235 /*@Before filling into registers,
3236 *offset should be multiplexed (-1)
3237 */
3238 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3239 (0x400 - offset_i_hex[1]) :
3240 (0xff - offset_i_hex[1]);
3241 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3242 (0x400 - offset_q_hex[1]) :
3243 (0xff - offset_q_hex[1]);
3244 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3245 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3246 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3247 }
3248 } else if (dm->support_ic_type & (ODM_RTL8721D)) {
3249 /*judy modified 20180517*/
3250 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3251 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3252
3253 /*@Before filling into registers,
3254 *offset should be multiplexed (-1)
3255 */
3256 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3257 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3258
3259 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3260 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3261 }
3262 #endif
3263 }
3264
phydm_receiver_blocking(void * dm_void)3265 void phydm_receiver_blocking(void *dm_void)
3266 {
3267 #ifdef CONFIG_RECEIVER_BLOCKING
3268 struct dm_struct *dm = (struct dm_struct *)dm_void;
3269 u32 chnl = *dm->channel;
3270 u8 bw = *dm->band_width;
3271 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3272
3273 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3274 !(dm->support_ability & ODM_BB_ADAPTIVITY))
3275 return;
3276
3277 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3278 dm->support_ic_type & ODM_RTL8192E) {
3279 /*@8188E_T version*/
3280 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3281 goto end;
3282
3283 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3284 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3285 PHYDM_DONT_CARE);
3286 dm->is_rx_blocking_en = true;
3287 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3288 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3289 PHYDM_DONT_CARE);
3290 dm->is_rx_blocking_en = true;
3291 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3292 phydm_nbi_enable(dm, FUNC_DISABLE);
3293 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3294 dm->is_rx_blocking_en = false;
3295 }
3296 return;
3297 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3298 /*@8188E_S version*/
3299 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3300 goto end;
3301
3302 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3303 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3304 PHYDM_DONT_CARE);
3305 dm->is_rx_blocking_en = true;
3306 } else if (dm->is_rx_blocking_en && chnl != 13) {
3307 phydm_nbi_enable(dm, FUNC_DISABLE);
3308 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3309 dm->is_rx_blocking_en = false;
3310 }
3311 return;
3312 }
3313
3314 end:
3315 if (dm->is_rx_blocking_en) {
3316 phydm_nbi_enable(dm, FUNC_DISABLE);
3317 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3318 dm->is_rx_blocking_en = false;
3319 }
3320 #endif
3321 }
3322