1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2015 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef _RTL8822B_HAL_H_ 17 #define _RTL8822B_HAL_H_ 18 19 #include <osdep_service.h> /* BIT(x) */ 20 #include <drv_types.h> /* PADAPTER */ 21 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ 22 23 24 #ifdef CONFIG_SUPPORT_TRX_SHARED 25 #define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */ 26 #else /* !CONFIG_SUPPORT_TRX_SHARED */ 27 #define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ 28 #endif /* !CONFIG_SUPPORT_TRX_SHARED */ 29 30 /* 31 * MAC Register definition 32 */ 33 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8822B /* hal_com.c & phydm */ 34 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8822B /* hal_com.c & phydm */ 35 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8822B /* phydm only */ 36 #define REG_LEDCFG0 REG_LED_CFG_8822B /* rtw_mp.c */ 37 #define MSR (REG_CR_8822B + 2) /* rtw_mp.c & hal_com.c */ 38 #define MSR1 REG_CR_EXT_8822B /* rtw_mp.c & hal_com.c */ 39 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 40 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 41 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ 42 43 #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ 44 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ 45 46 /* RXERR_RPT, for rtw_mp.c */ 47 #define RXERR_TYPE_OFDM_PPDU 0 48 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 49 #define RXERR_TYPE_OFDM_MPDU_OK 0 50 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 51 #define RXERR_TYPE_CCK_PPDU 3 52 #define RXERR_TYPE_CCK_FALSE_ALARM 5 53 #define RXERR_TYPE_CCK_MPDU_OK 3 54 #define RXERR_TYPE_CCK_MPDU_FAIL 4 55 #define RXERR_TYPE_HT_PPDU 8 56 #define RXERR_TYPE_HT_FALSE_ALARM 9 57 #define RXERR_TYPE_HT_MPDU_TOTAL 6 58 #define RXERR_TYPE_HT_MPDU_OK 6 59 #define RXERR_TYPE_HT_MPDU_FAIL 7 60 #define RXERR_TYPE_RX_FULL_DROP 10 61 62 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8822B 63 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8822B 64 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \ 65 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0)) 66 67 /* 68 * BB Register definition 69 */ 70 #define rPMAC_Reset 0x100 /* hal_mp.c */ 71 72 #define rFPGA0_RFMOD 0x800 73 #define rFPGA0_TxInfo 0x804 74 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 75 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 76 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 77 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 78 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 79 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 80 #define rTxAGC_B_Rate18_06 0x830 81 #define rTxAGC_B_Rate54_24 0x834 82 #define rTxAGC_B_CCK1_55_Mcs32 0x838 83 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 84 #define rTxAGC_B_Mcs03_Mcs00 0x83C 85 #define rTxAGC_B_Mcs07_Mcs04 0x848 86 #define rTxAGC_B_Mcs11_Mcs08 0x84C 87 #define rFPGA0_XA_RFInterfaceOE 0x860 88 #define rFPGA0_XB_RFInterfaceOE 0x864 89 #define rTxAGC_B_Mcs15_Mcs12 0x868 90 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 91 #define rFPGA0_XAB_RFInterfaceSW 0x870 92 #define rFPGA0_XAB_RFParameter 0x878 93 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 94 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 95 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8822b_phy.c) */ 96 97 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 98 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 99 100 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 101 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 102 /* TX BeamForming */ 103 #define REG_BB_TX_PATH_SEL_1_8822B 0x93C /* rtl8822b_phy.c */ 104 #define REG_BB_TX_PATH_SEL_2_8822B 0x940 /* rtl8822b_phy.c */ 105 106 /* TX BeamForming */ 107 #define REG_BB_TXBF_ANT_SET_BF1_8822B 0x19AC /* rtl8822b_phy.c */ 108 #define REG_BB_TXBF_ANT_SET_BF0_8822B 0x19B4 /* rtl8822b_phy.c */ 109 110 #define rCCK0_System 0xA00 111 #define rCCK0_AFESetting 0xA04 112 113 #define rCCK0_DSPParameter2 0xA1C 114 #define rCCK0_TxFilter1 0xA20 115 #define rCCK0_TxFilter2 0xA24 116 #define rCCK0_DebugPort 0xA28 117 #define rCCK0_FalseAlarmReport 0xA2C 118 119 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 120 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 121 122 #define rOFDM0_TRxPathEnable 0xC04 123 #define rOFDM0_TRMuxPar 0xC08 124 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 125 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 126 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 127 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 128 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 129 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 130 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 131 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 132 133 #define rOFDM1_LSTF 0xD00 134 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 135 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8822b_phy.c) */ 136 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8822b_phy.c) */ 137 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8822b_phy.c) */ 138 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8822b_phy.c) */ 139 140 #define rTxAGC_A_Rate18_06 0xE00 141 #define rTxAGC_A_Rate54_24 0xE04 142 #define rTxAGC_A_CCK1_Mcs32 0xE08 143 #define rTxAGC_A_Mcs03_Mcs00 0xE10 144 #define rTxAGC_A_Mcs07_Mcs04 0xE14 145 #define rTxAGC_A_Mcs11_Mcs08 0xE18 146 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 147 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 148 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 149 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 150 /* RFE */ 151 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 152 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 153 #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 154 #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 155 #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 156 #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 157 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 158 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 159 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 160 #define bMask_RFEInv_Jaguar 0x3FF00000 161 #define bMask_AntselPathFollow_Jaguar 0x00030000 162 163 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ 164 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ 165 #define rA_RFE_Sel_Jaguar2 0x1990 166 167 /* Page1(0x100) */ 168 #define bBBResetB 0x100 169 170 /* Page8(0x800) */ 171 #define bCCKEn 0x1000000 172 #define bOFDMEn 0x2000000 173 /* Reg 0x80C rFPGA0_TxGainStage */ 174 #define bXBTxAGC 0xF00 175 #define bXCTxAGC 0xF000 176 #define bXDTxAGC 0xF0000 177 178 /* PageA(0xA00) */ 179 #define bCCKBBMode 0x3 180 181 #define bCCKScramble 0x8 182 #define bCCKTxRate 0x3000 183 184 /* General */ 185 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 186 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 187 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 188 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 189 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 190 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 191 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 192 193 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 194 #define bDisable 0x0 /* rtw_mp.c */ 195 196 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 197 198 #define Rx_Smooth_Factor 20 /* phydm only */ 199 200 /* 201 * RF Register definition 202 */ 203 #define RF_AC 0x00 204 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 205 #define RF_CHNLBW 0x18 /* rtl8822b_phy.c */ 206 #define RF_ModeTableAddr 0x30 /* rtl8822b_phy.c */ 207 #define RF_ModeTableData0 0x31 /* rtl8822b_phy.c */ 208 #define RF_ModeTableData1 0x32 /* rtl8822b_phy.c */ 209 #define RF_0x52 0x52 210 #define RF_WeLut_Jaguar 0xEF /* rtl8822b_phy.c */ 211 212 /* General Functions */ 213 void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ 214 215 #ifdef CONFIG_MP_INCLUDED 216 /* MP Functions */ 217 #include <rtw_mp.h> /* struct mp_priv */ 218 void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 219 void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 220 #endif 221 void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); 222 223 #ifdef CONFIG_USB_HCI 224 #include <rtl8822bu_hal.h> 225 #elif defined(CONFIG_SDIO_HCI) 226 #include <rtl8822bs_hal.h> 227 #elif defined(CONFIG_PCI_HCI) 228 #include <rtl8822be_hal.h> 229 #endif 230 231 #endif /* _RTL8822B_HAL_H_ */ 232