1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __RTL8821C_SPEC_H__ 17 #define __RTL8821C_SPEC_H__ 18 19 #define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C 20 21 /* 22 * MAC Register definition 23 */ 24 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ 25 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ 26 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ 27 #define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ 28 #define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ 29 #define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ 30 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 31 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 32 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ 33 34 #define REG_WOWLAN_WAKE_REASON 0x01C7 35 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C 36 37 /* RXERR_RPT, for rtw_mp.c */ 38 #define RXERR_TYPE_OFDM_PPDU 0 39 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 40 #define RXERR_TYPE_OFDM_MPDU_OK 0 41 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 42 #define RXERR_TYPE_CCK_PPDU 3 43 #define RXERR_TYPE_CCK_FALSE_ALARM 5 44 #define RXERR_TYPE_CCK_MPDU_OK 3 45 #define RXERR_TYPE_CCK_MPDU_FAIL 4 46 #define RXERR_TYPE_HT_PPDU 8 47 #define RXERR_TYPE_HT_FALSE_ALARM 9 48 #define RXERR_TYPE_HT_MPDU_TOTAL 6 49 #define RXERR_TYPE_HT_MPDU_OK 6 50 #define RXERR_TYPE_HT_MPDU_FAIL 7 51 #define RXERR_TYPE_RX_FULL_DROP 10 52 53 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C 54 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C 55 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ 56 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) 57 58 /* 59 * BB Register definition 60 */ 61 #define rPMAC_Reset 0x100 /* hal_mp.c */ 62 63 #define rFPGA0_RFMOD 0x800 64 #define rFPGA0_TxInfo 0x804 65 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 66 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 67 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 68 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 69 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 70 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 71 #define rTxAGC_B_Rate18_06 0x830 72 #define rTxAGC_B_Rate54_24 0x834 73 #define rTxAGC_B_CCK1_55_Mcs32 0x838 74 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 75 #define rTxAGC_B_Mcs03_Mcs00 0x83C 76 #define rTxAGC_B_Mcs07_Mcs04 0x848 77 #define rTxAGC_B_Mcs11_Mcs08 0x84C 78 #define rFPGA0_XA_RFInterfaceOE 0x860 79 #define rFPGA0_XB_RFInterfaceOE 0x864 80 #define rTxAGC_B_Mcs15_Mcs12 0x868 81 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 82 #define rFPGA0_XAB_RFInterfaceSW 0x870 83 #define rFPGA0_XAB_RFParameter 0x878 84 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 85 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 86 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ 87 88 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 89 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 90 91 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 92 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 93 94 #define rCCK0_System 0xA00 95 #define rCCK0_AFESetting 0xA04 96 97 #define rCCK0_DSPParameter2 0xA1C 98 #define rCCK0_TxFilter1 0xA20 99 #define rCCK0_TxFilter2 0xA24 100 #define rCCK0_DebugPort 0xA28 101 #define rCCK0_FalseAlarmReport 0xA2C 102 103 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 104 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 105 106 #define rOFDM0_TRxPathEnable 0xC04 107 #define rOFDM0_TRMuxPar 0xC08 108 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 109 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 110 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 111 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 112 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 113 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 114 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 115 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ 116 /* RFE */ 117 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 118 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 119 #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 120 #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 121 #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 122 #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 123 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 124 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 125 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 126 #define bMask_RFEInv_Jaguar 0x3FF00000 127 #define bMask_AntselPathFollow_Jaguar 0x00030000 128 129 #define rOFDM1_LSTF 0xD00 130 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 131 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ 132 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ 133 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ 134 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ 135 136 #define rTxAGC_A_Rate18_06 0xE00 137 #define rTxAGC_A_Rate54_24 0xE04 138 #define rTxAGC_A_CCK1_Mcs32 0xE08 139 #define rTxAGC_A_Mcs03_Mcs00 0xE10 140 #define rTxAGC_A_Mcs07_Mcs04 0xE14 141 #define rTxAGC_A_Mcs11_Mcs08 0xE18 142 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 143 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 144 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 145 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ 146 147 /* Page1(0x100) */ 148 #define bBBResetB 0x100 149 150 /* Page8(0x800) */ 151 #define bCCKEn 0x1000000 152 #define bOFDMEn 0x2000000 153 /* Reg 0x80C rFPGA0_TxGainStage */ 154 #define bXBTxAGC 0xF00 155 #define bXCTxAGC 0xF000 156 #define bXDTxAGC 0xF0000 157 158 /* PageA(0xA00) */ 159 #define bCCKBBMode 0x3 160 161 #define bCCKScramble 0x8 162 #define bCCKTxRate 0x3000 163 164 /* General */ 165 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 166 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 167 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 168 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 169 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 170 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 171 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 172 173 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 174 #define bDisable 0x0 /* rtw_mp.c */ 175 176 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 177 178 #define Rx_Smooth_Factor 20 /* phydm only */ 179 180 /* 181 * RF Register definition 182 */ 183 #define RF_AC 0x00 184 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 185 #define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ 186 #define RF_0x52 0x52 187 188 struct hw_port_reg { 189 u32 net_type; /*reg_offset*/ 190 u8 net_type_shift; 191 u32 macaddr; /*reg_offset*/ 192 u32 bssid; /*reg_offset*/ 193 u32 bcn_ctl; /*reg_offset*/ 194 u32 tsf_rst; /*reg_offset*/ 195 u8 tsf_rst_bit; 196 u32 bcn_space; /*reg_offset*/ 197 u8 bcn_space_shift; 198 u16 bcn_space_mask; 199 u32 ps_aid; /*reg_offset*/ 200 u32 ta; /*reg_offset*/ 201 }; 202 203 #endif /* __RTL8192E_SPEC_H__ */ 204