1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2012 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __RTL8192E_XMIT_H__ 17 #define __RTL8192E_XMIT_H__ 18 19 typedef struct txdescriptor_8192e { 20 /* Offset 0 */ 21 u32 pktlen:16; 22 u32 offset:8; 23 u32 bmc:1; 24 u32 htc:1; 25 u32 ls:1; 26 u32 fs:1; 27 u32 linip:1; 28 u32 noacm:1; 29 u32 gf:1; 30 u32 own:1; 31 32 /* Offset 4 */ 33 u32 macid:6; 34 u32 rsvd0406:2; 35 u32 qsel:5; 36 u32 rd_nav_ext:1; 37 u32 lsig_txop_en:1; 38 u32 pifs:1; 39 u32 rate_id:4; 40 u32 navusehdr:1; 41 u32 en_desc_id:1; 42 u32 sectype:2; 43 u32 rsvd0424:2; 44 u32 pkt_offset:5; /* unit: 8 bytes */ 45 u32 rsvd0431:1; 46 47 /* Offset 8 */ 48 u32 rts_rc:6; 49 u32 data_rc:6; 50 u32 agg_en:1; 51 u32 rd_en:1; 52 u32 bar_rty_th:2; 53 u32 bk:1; 54 u32 morefrag:1; 55 u32 raw:1; 56 u32 ccx:1; 57 u32 ampdu_density:3; 58 u32 bt_null:1; 59 u32 ant_sel_a:1; 60 u32 ant_sel_b:1; 61 u32 tx_ant_cck:2; 62 u32 tx_antl:2; 63 u32 tx_ant_ht:2; 64 65 /* Offset 12 */ 66 u32 nextheadpage:8; 67 u32 tailpage:8; 68 u32 seq:12; 69 u32 cpu_handle:1; 70 u32 tag1:1; 71 u32 trigger_int:1; 72 u32 hwseq_en:1; 73 74 /* Offset 16 */ 75 u32 rtsrate:5; 76 u32 ap_dcfe:1; 77 u32 hwseq_sel:2; 78 u32 userate:1; 79 u32 disrtsfb:1; 80 u32 disdatafb:1; 81 u32 cts2self:1; 82 u32 rtsen:1; 83 u32 hw_rts_en:1; 84 u32 port_id:1; 85 u32 pwr_status:3; 86 u32 wait_dcts:1; 87 u32 cts2ap_en:1; 88 u32 data_sc:2; 89 u32 data_stbc:2; 90 u32 data_short:1; 91 u32 data_bw:1; 92 u32 rts_short:1; 93 u32 rts_bw:1; 94 u32 rts_sc:2; 95 u32 vcs_stbc:2; 96 97 /* Offset 20 */ 98 u32 datarate:6; 99 u32 sgi:1; 100 u32 try_rate:1; 101 u32 data_ratefb_lmt:5; 102 u32 rts_ratefb_lmt:4; 103 u32 rty_lmt_en:1; 104 u32 data_rt_lmt:6; 105 u32 usb_txagg_num:8; 106 107 /* Offset 24 */ 108 u32 txagg_a:5; 109 u32 txagg_b:5; 110 u32 use_max_len:1; 111 u32 max_agg_num:5; 112 u32 mcsg1_max_len:4; 113 u32 mcsg2_max_len:4; 114 u32 mcsg3_max_len:4; 115 u32 mcs7_sgi_max_len:4; 116 117 /* Offset 28 */ 118 u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ 119 u32 mcsg4_max_len:4; 120 u32 mcsg5_max_len:4; 121 u32 mcsg6_max_len:4; 122 u32 mcs15_sgi_max_len:4; 123 } TXDESC_8192E, *PTXDESC_8192E; 124 125 126 127 /* For 88e early mode */ 128 #define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) 129 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) 130 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) 131 #define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) 132 #define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) 133 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) 134 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) 135 136 /* 137 * defined for TX DESC Operation 138 * */ 139 140 #define MAX_TID (15) 141 142 /* OFFSET 0 */ 143 #define OFFSET_SZ 0 144 #define OFFSET_SHT 16 145 #define BMC BIT(24) 146 #define LSG BIT(26) 147 #define FSG BIT(27) 148 #define OWN BIT(31) 149 150 151 /* OFFSET 4 */ 152 #define PKT_OFFSET_SZ 0 153 #define QSEL_SHT 8 154 #define RATE_ID_SHT 16 155 #define NAVUSEHDR BIT(20) 156 #define SEC_TYPE_SHT 22 157 #define PKT_OFFSET_SHT 26 158 159 /* OFFSET 8 */ 160 #define AGG_EN BIT(12) 161 #define AGG_BK BIT(16) 162 #define AMPDU_DENSITY_SHT 20 163 #define ANTSEL_A BIT(24) 164 #define ANTSEL_B BIT(25) 165 #define TX_ANT_CCK_SHT 26 166 #define TX_ANTL_SHT 28 167 #define TX_ANT_HT_SHT 30 168 169 /* OFFSET 12 */ 170 #define SEQ_SHT 16 171 #define EN_HWSEQ BIT(31) 172 173 /* OFFSET 16 */ 174 #define QOS BIT(6) 175 #define HW_SSN BIT(7) 176 #define USERATE BIT(8) 177 #define DISDATAFB BIT(10) 178 #define CTS_2_SELF BIT(11) 179 #define RTS_EN BIT(12) 180 #define HW_RTS_EN BIT(13) 181 #define DATA_SHORT BIT(24) 182 #define PWR_STATUS_SHT 15 183 #define DATA_SC_SHT 20 184 #define DATA_BW BIT(25) 185 186 /* OFFSET 20 */ 187 #define RTY_LMT_EN BIT(17) 188 189 190 /* OFFSET 20 */ 191 #define SGI BIT(6) 192 #define USB_TXAGG_NUM_SHT 24 193 194 195 /* *****Tx Desc Buffer content */ 196 197 /* config element for each tx buffer 198 * 199 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu) 200 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu) 201 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu) 202 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) 203 */ 204 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) 205 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) 206 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) 207 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) 208 209 210 /* Dword 0 */ 211 #define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) 212 #define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) 213 #define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) 214 /* Dword 1 */ 215 #define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) 216 #define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) 217 218 219 /* Dword 2 */ 220 #define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value) 221 /* Dword 3, RESERVED */ 222 223 224 /* *****Tx Desc content 225 * Dword 0 */ 226 #define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) 227 #define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) 228 #define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) 229 #define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) 230 #define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) 231 #define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) 232 #define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) 233 #define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) 234 #define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) 235 #define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) 236 #define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) 237 238 /* Dword 1 */ 239 #define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) 240 #define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) 241 #define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) 242 #define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) 243 #define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) 244 #define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) 245 #define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) 246 #define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) 247 #define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) 248 #define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) 249 #define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value) 250 #define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value) 251 252 253 /* Dword 2 */ 254 #define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) 255 #define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) 256 #define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) 257 #define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) 258 #define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) 259 #define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) 260 #define SET_TX_DESC_BK_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) 261 #define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) 262 #define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) 263 #define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1) 264 #define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) 265 #define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) 266 #define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) 267 #define SET_TX_DESC_GID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) 268 269 270 /* Dword 3 */ 271 #define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) 272 #define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) 273 #define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) 274 #define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) 275 #define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) 276 #define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) 277 #define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) 278 #define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) 279 #define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) 280 #define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) 281 #define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value) 282 #define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) 283 #define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) 284 #define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) 285 #define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) 286 #define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) 287 288 /* Dword 4 */ 289 #define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) 290 #define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) 291 #define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) 292 #define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) 293 #define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) 294 #define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) 295 #define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) 296 #define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) 297 #define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) 298 299 300 /* Dword 5 */ 301 #define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) 302 #define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) 303 #define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) 304 #define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) 305 #define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) 306 #define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) 307 #define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) 308 #define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) 309 #define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value) 310 #define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) 311 312 /* Dword 6 */ 313 #define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) 314 #define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) 315 #define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) 316 #define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) 317 #define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) 318 #define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) 319 320 /* Dword 7 */ 321 #ifdef CONFIG_PCI_HCI 322 #define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 323 #endif 324 325 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) 326 #define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) 327 #endif 328 #define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) 329 330 331 /* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */ 332 /* Dword 8 */ 333 334 #define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) 335 #define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) 336 #define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) 337 #define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) 338 #define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) 339 #define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) 340 341 /* Dword 9 */ 342 #define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) 343 #define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value) 344 #define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) 345 #define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) 346 347 348 #define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) 349 #define SET_EARLYMODE_LEN0_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) 350 #define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) 351 #define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) 352 #define SET_EARLYMODE_LEN2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) 353 #define SET_EARLYMODE_LEN3_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) 354 355 void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc); 356 357 #ifdef CONFIG_USB_HCI 358 s32 rtl8192eu_init_xmit_priv(PADAPTER padapter); 359 void rtl8192eu_free_xmit_priv(PADAPTER padapter); 360 s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 361 s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 362 s32 rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 363 s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter); 364 #define hal_xmit_handler rtl8192eu_xmit_buf_handler 365 void rtl8192eu_xmit_tasklet(void *priv); 366 s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 367 #endif 368 369 #ifdef CONFIG_PCI_HCI 370 s32 rtl8192ee_init_xmit_priv(PADAPTER padapter); 371 void rtl8192ee_free_xmit_priv(PADAPTER padapter); 372 struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring); 373 s32 rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 374 void rtl8192ee_xmitframe_resume(_adapter *padapter); 375 s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 376 s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 377 void rtl8192ee_xmit_tasklet(void *priv); 378 #endif 379 380 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 381 s32 rtl8192es_init_xmit_priv(PADAPTER padapter); 382 void rtl8192es_free_xmit_priv(PADAPTER padapter); 383 384 s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); 385 s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); 386 s32 rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 387 thread_return rtl8192es_xmit_thread(thread_context context); 388 s32 rtl8192es_xmit_buf_handler(PADAPTER padapter); 389 390 #ifdef CONFIG_SDIO_TX_TASKLET 391 void rtl8192es_xmit_tasklet(void *priv); 392 #endif 393 #endif 394 395 struct txrpt_ccx_92e { 396 /* offset 0 */ 397 u8 tag1:1; 398 u8 pkt_num:3; 399 u8 txdma_underflow:1; 400 u8 int_bt:1; 401 u8 int_tri:1; 402 u8 int_ccx:1; 403 404 /* offset 1 */ 405 u8 mac_id:6; 406 u8 pkt_ok:1; 407 u8 bmc:1; 408 409 /* offset 2 */ 410 u8 retry_cnt:6; 411 u8 lifetime_over:1; 412 u8 retry_over:1; 413 414 /* offset 3 */ 415 u8 ccx_qtime0; 416 u8 ccx_qtime1; 417 418 /* offset 5 */ 419 u8 final_data_rate; 420 421 /* offset 6 */ 422 u8 sw1:4; 423 u8 qsel:4; 424 425 /* offset 7 */ 426 u8 sw0; 427 }; 428 429 #ifdef CONFIG_TX_EARLY_MODE 430 void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 431 #endif 432 s32 rtl8192e_init_xmit_priv(_adapter *padapter); 433 void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); 434 435 void rtl8192e_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, 436 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 437 void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc); 438 439 u8 BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib); 440 u8 SCMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib); 441 void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); 442 void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc); 443 #if defined(CONFIG_CONCURRENT_MODE) 444 void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); 445 #endif 446 void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); 447 448 void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); 449 void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc); 450 451 #endif /* __RTL8192E_XMIT_H__ */ 452