1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 *****************************************************************************/ 16 #ifndef __INC_HAL8188FPHYREG_H__ 17 #define __INC_HAL8188FPHYREG_H__ 18 19 /*--------------------------Define Parameters-------------------------------*/ 20 21 /* ************************************************************ 22 * Regsiter offset definition 23 * ************************************************************ */ 24 25 /* 26 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 27 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 28 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 29 * 3. RF register 0x00-2E 30 * 4. Bit Mask for BB/RF register 31 * 5. Other defintion for BB/RF R/W 32 * */ 33 34 35 /* 36 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 37 * 1. Page1(0x100) 38 * */ 39 #define rPMAC_Reset 0x100 40 #define rPMAC_TxStart 0x104 41 #define rPMAC_TxLegacySIG 0x108 42 #define rPMAC_TxHTSIG1 0x10c 43 #define rPMAC_TxHTSIG2 0x110 44 #define rPMAC_PHYDebug 0x114 45 #define rPMAC_TxPacketNum 0x118 46 #define rPMAC_TxIdle 0x11c 47 #define rPMAC_TxMACHeader0 0x120 48 #define rPMAC_TxMACHeader1 0x124 49 #define rPMAC_TxMACHeader2 0x128 50 #define rPMAC_TxMACHeader3 0x12c 51 #define rPMAC_TxMACHeader4 0x130 52 #define rPMAC_TxMACHeader5 0x134 53 #define rPMAC_TxDataType 0x138 54 #define rPMAC_TxRandomSeed 0x13c 55 #define rPMAC_CCKPLCPPreamble 0x140 56 #define rPMAC_CCKPLCPHeader 0x144 57 #define rPMAC_CCKCRC16 0x148 58 #define rPMAC_OFDMRxCRC32OK 0x170 59 #define rPMAC_OFDMRxCRC32Er 0x174 60 #define rPMAC_OFDMRxParityEr 0x178 61 #define rPMAC_OFDMRxCRC8Er 0x17c 62 #define rPMAC_CCKCRxRC16Er 0x180 63 #define rPMAC_CCKCRxRC32Er 0x184 64 #define rPMAC_CCKCRxRC32OK 0x188 65 #define rPMAC_TxStatus 0x18c 66 67 /* 68 * 2. Page2(0x200) 69 * 70 * The following two definition are only used for USB interface. */ 71 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 72 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 73 74 /* 75 * 3. Page8(0x800) 76 * */ 77 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ 78 79 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 80 #define rFPGA0_PSDFunction 0x808 81 82 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 83 84 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 85 #define rFPGA0_RFTiming2 0x814 86 87 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 88 #define rFPGA0_XA_HSSIParameter2 0x824 89 #define rFPGA0_XB_HSSIParameter1 0x828 90 #define rFPGA0_XB_HSSIParameter2 0x82c 91 #define rTxAGC_B_Rate18_06 0x830 92 #define rTxAGC_B_Rate54_24 0x834 93 #define rTxAGC_B_CCK1_55_Mcs32 0x838 94 #define rTxAGC_B_Mcs03_Mcs00 0x83c 95 96 #define rTxAGC_B_Mcs07_Mcs04 0x848 97 #define rTxAGC_B_Mcs11_Mcs08 0x84c 98 99 #define rFPGA0_XA_LSSIParameter 0x840 100 #define rFPGA0_XB_LSSIParameter 0x844 101 102 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 103 #define rFPGA0_RFSleepUpParameter 0x854 104 105 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 106 #define rFPGA0_XCD_SwitchControl 0x85c 107 108 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 109 #define rFPGA0_XB_RFInterfaceOE 0x864 110 111 #define rTxAGC_B_Mcs15_Mcs12 0x868 112 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 113 114 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 115 #define rFPGA0_XCD_RFInterfaceSW 0x874 116 117 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 118 #define rFPGA0_XCD_RFParameter 0x87c 119 120 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 121 #define rFPGA0_AnalogParameter2 0x884 122 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 123 #define rFPGA0_AnalogParameter4 0x88c 124 125 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 126 #define rFPGA0_XB_LSSIReadBack 0x8a4 127 #define rFPGA0_XC_LSSIReadBack 0x8a8 128 #define rFPGA0_XD_LSSIReadBack 0x8ac 129 130 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 131 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 132 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 133 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ 134 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 135 136 /* 137 * 4. Page9(0x900) 138 * */ 139 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ 140 141 #define rFPGA1_TxBlock 0x904 /* Useless now */ 142 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 143 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ 144 #define rS0S1_PathSwitch 0x948 145 146 /* 147 * 5. PageA(0xA00) 148 * 149 * Set Control channel to upper or lower. These settings are required only for 40MHz */ 150 #define rCCK0_System 0xa00 151 152 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ 153 #define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ 154 155 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 156 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 157 158 #define rCCK0_RxHP 0xa14 159 160 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 161 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 162 163 #define rCCK0_TxFilter1 0xa20 164 #define rCCK0_TxFilter2 0xa24 165 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 166 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 167 #define rCCK0_TRSSIReport 0xa50 168 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 169 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 170 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c 171 * 172 * PageB(0xB00) 173 * */ 174 #define rPdp_AntA 0xb00 175 #define rPdp_AntA_4 0xb04 176 #define rConfig_Pmpd_AntA 0xb28 177 #define rConfig_AntA 0xb68 178 #define rConfig_AntB 0xb6c 179 #define rPdp_AntB 0xb70 180 #define rPdp_AntB_4 0xb74 181 #define rConfig_Pmpd_AntB 0xb98 182 #define rAPK 0xbd8 183 184 /* 185 * 6. PageC(0xC00) 186 * */ 187 #define rOFDM0_LSTF 0xc00 188 189 #define rOFDM0_TRxPathEnable 0xc04 190 #define rOFDM0_TRMuxPar 0xc08 191 #define rOFDM0_TRSWIsolation 0xc0c 192 193 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 194 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 195 #define rOFDM0_XBRxAFE 0xc18 196 #define rOFDM0_XBRxIQImbalance 0xc1c 197 #define rOFDM0_XCRxAFE 0xc20 198 #define rOFDM0_XCRxIQImbalance 0xc24 199 #define rOFDM0_XDRxAFE 0xc28 200 #define rOFDM0_XDRxIQImbalance 0xc2c 201 202 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ 203 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 204 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 205 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 206 207 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 208 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 209 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 210 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 211 212 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 213 #define rOFDM0_XAAGCCore2 0xc54 214 #define rOFDM0_XBAGCCore1 0xc58 215 #define rOFDM0_XBAGCCore2 0xc5c 216 #define rOFDM0_XCAGCCore1 0xc60 217 #define rOFDM0_XCAGCCore2 0xc64 218 #define rOFDM0_XDAGCCore1 0xc68 219 #define rOFDM0_XDAGCCore2 0xc6c 220 221 #define rOFDM0_AGCParameter1 0xc70 222 #define rOFDM0_AGCParameter2 0xc74 223 #define rOFDM0_AGCRSSITable 0xc78 224 #define rOFDM0_HTSTFAGC 0xc7c 225 226 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 227 #define rOFDM0_XATxAFE 0xc84 228 #define rOFDM0_XBTxIQImbalance 0xc88 229 #define rOFDM0_XBTxAFE 0xc8c 230 #define rOFDM0_XCTxIQImbalance 0xc90 231 #define rOFDM0_XCTxAFE 0xc94 232 #define rOFDM0_XDTxIQImbalance 0xc98 233 #define rOFDM0_XDTxAFE 0xc9c 234 235 #define rOFDM0_RxIQExtAnta 0xca0 236 #define rOFDM0_TxCoeff1 0xca4 237 #define rOFDM0_TxCoeff2 0xca8 238 #define rOFDM0_TxCoeff3 0xcac 239 #define rOFDM0_TxCoeff4 0xcb0 240 #define rOFDM0_TxCoeff5 0xcb4 241 #define rOFDM0_TxCoeff6 0xcb8 242 #define rOFDM0_RxHPParameter 0xce0 243 #define rOFDM0_TxPseudoNoiseWgt 0xce4 244 #define rOFDM0_FrameSync 0xcf0 245 #define rOFDM0_DFSReport 0xcf4 246 247 /* 248 * 7. PageD(0xD00) 249 * */ 250 #define rOFDM1_LSTF 0xd00 251 #define rOFDM1_TRxPathEnable 0xd04 252 253 #define rOFDM1_CFO 0xd08 /* No setting now */ 254 #define rOFDM1_CSI1 0xd10 255 #define rOFDM1_SBD 0xd14 256 #define rOFDM1_CSI2 0xd18 257 #define rOFDM1_CFOTracking 0xd2c 258 #define rOFDM1_TRxMesaure1 0xd34 259 #define rOFDM1_IntfDet 0xd3c 260 #define rOFDM1_PseudoNoiseStateAB 0xd50 261 #define rOFDM1_PseudoNoiseStateCD 0xd54 262 #define rOFDM1_RxPseudoNoiseWgt 0xd58 263 264 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 265 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 266 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 267 268 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 269 #define rOFDM_ShortCFOCD 0xdb0 270 #define rOFDM_LongCFOAB 0xdb4 271 #define rOFDM_LongCFOCD 0xdb8 272 #define rOFDM_TailCFOAB 0xdbc 273 #define rOFDM_TailCFOCD 0xdc0 274 #define rOFDM_PWMeasure1 0xdc4 275 #define rOFDM_PWMeasure2 0xdc8 276 #define rOFDM_BWReport 0xdcc 277 #define rOFDM_AGCReport 0xdd0 278 #define rOFDM_RxSNR 0xdd4 279 #define rOFDM_RxEVMCSI 0xdd8 280 #define rOFDM_SIGReport 0xddc 281 282 283 /* 284 * 8. PageE(0xE00) 285 * */ 286 #define rTxAGC_A_Rate18_06 0xe00 287 #define rTxAGC_A_Rate54_24 0xe04 288 #define rTxAGC_A_CCK1_Mcs32 0xe08 289 #define rTxAGC_A_Mcs03_Mcs00 0xe10 290 #define rTxAGC_A_Mcs07_Mcs04 0xe14 291 #define rTxAGC_A_Mcs11_Mcs08 0xe18 292 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 293 294 #define rFPGA0_IQK 0xe28 295 #define rTx_IQK_Tone_A 0xe30 296 #define rRx_IQK_Tone_A 0xe34 297 #define rTx_IQK_PI_A 0xe38 298 #define rRx_IQK_PI_A 0xe3c 299 300 #define rTx_IQK 0xe40 301 #define rRx_IQK 0xe44 302 #define rIQK_AGC_Pts 0xe48 303 #define rIQK_AGC_Rsp 0xe4c 304 #define rTx_IQK_Tone_B 0xe50 305 #define rRx_IQK_Tone_B 0xe54 306 #define rTx_IQK_PI_B 0xe58 307 #define rRx_IQK_PI_B 0xe5c 308 #define rIQK_AGC_Cont 0xe60 309 310 #define rBlue_Tooth 0xe6c 311 #define rRx_Wait_CCA 0xe70 312 #define rTx_CCK_RFON 0xe74 313 #define rTx_CCK_BBON 0xe78 314 #define rTx_OFDM_RFON 0xe7c 315 #define rTx_OFDM_BBON 0xe80 316 #define rTx_To_Rx 0xe84 317 #define rTx_To_Tx 0xe88 318 #define rRx_CCK 0xe8c 319 320 #define rTx_Power_Before_IQK_A 0xe94 321 #define rTx_Power_After_IQK_A 0xe9c 322 323 #define rRx_Power_Before_IQK_A 0xea0 324 #define rRx_Power_Before_IQK_A_2 0xea4 325 #define rRx_Power_After_IQK_A 0xea8 326 #define rRx_Power_After_IQK_A_2 0xeac 327 328 #define rTx_Power_Before_IQK_B 0xeb4 329 #define rTx_Power_After_IQK_B 0xebc 330 331 #define rRx_Power_Before_IQK_B 0xec0 332 #define rRx_Power_Before_IQK_B_2 0xec4 333 #define rRx_Power_After_IQK_B 0xec8 334 #define rRx_Power_After_IQK_B_2 0xecc 335 336 #define rRx_OFDM 0xed0 337 #define rRx_Wait_RIFS 0xed4 338 #define rRx_TO_Rx 0xed8 339 #define rStandby 0xedc 340 #define rSleep 0xee0 341 #define rPMPD_ANAEN 0xeec 342 343 /* 344 * 7. RF Register 0x00-0x2E (RF 8256) 345 * RF-0222D 0x00-3F 346 * 347 * Zebra1 */ 348 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 349 #define rZebra1_TRxEnable1 0x1 350 #define rZebra1_TRxEnable2 0x2 351 #define rZebra1_AGC 0x4 352 #define rZebra1_ChargePump 0x5 353 #define rZebra1_Channel 0x7 /* RF channel switch */ 354 355 /* #endif */ 356 #define rZebra1_TxGain 0x8 /* Useless now */ 357 #define rZebra1_TxLPF 0x9 358 #define rZebra1_RxLPF 0xb 359 #define rZebra1_RxHPFCorner 0xc 360 361 /* Zebra4 */ 362 #define rGlobalCtrl 0 /* Useless now */ 363 #define rRTL8256_TxLPF 19 364 #define rRTL8256_RxLPF 11 365 366 /* RTL8258 */ 367 #define rRTL8258_TxLPF 0x11 /* Useless now */ 368 #define rRTL8258_RxLPF 0x13 369 #define rRTL8258_RSSILPF 0xa 370 371 /* 372 * RL6052 Register definition 373 * */ 374 #define RF_AC 0x00 /* */ 375 376 #define RF_IQADJ_G1 0x01 /* */ 377 #define RF_IQADJ_G2 0x02 /* */ 378 #define RF_BS_PA_APSET_G1_G4 0x03 379 #define RF_BS_PA_APSET_G5_G8 0x04 380 #define RF_POW_TRSW 0x05 /* */ 381 382 #define RF_GAIN_RX 0x06 /* */ 383 #define RF_GAIN_TX 0x07 /* */ 384 385 #define RF_TXM_IDAC 0x08 /* */ 386 #define RF_IPA_G 0x09 /* */ 387 #define RF_TXBIAS_G 0x0A 388 #define RF_TXPA_AG 0x0B 389 #define RF_IPA_A 0x0C /* */ 390 #define RF_TXBIAS_A 0x0D 391 #define RF_BS_PA_APSET_G9_G11 0x0E 392 #define RF_BS_IQGEN 0x0F /* */ 393 394 #define RF_MODE1 0x10 /* */ 395 #define RF_MODE2 0x11 /* */ 396 397 #define RF_RX_AGC_HP 0x12 /* */ 398 #define RF_TX_AGC 0x13 /* */ 399 #define RF_BIAS 0x14 /* */ 400 #define RF_IPA 0x15 /* */ 401 #define RF_TXBIAS 0x16 402 #define RF_POW_ABILITY 0x17 /* */ 403 #define RF_MODE_AG 0x18 /* */ 404 #define rRfChannel 0x18 /* RF channel and BW switch */ 405 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 406 #define RF_TOP 0x19 /* */ 407 408 #define RF_RX_G1 0x1A /* */ 409 #define RF_RX_G2 0x1B /* */ 410 411 #define RF_RX_BB2 0x1C /* */ 412 #define RF_RX_BB1 0x1D /* */ 413 414 #define RF_RCK1 0x1E /* */ 415 #define RF_RCK2 0x1F /* */ 416 417 #define RF_TX_G1 0x20 /* */ 418 #define RF_TX_G2 0x21 /* */ 419 #define RF_TX_G3 0x22 /* */ 420 421 #define RF_TX_BB1 0x23 /* */ 422 423 #define RF_T_METER 0x24 /* */ 424 425 #define RF_SYN_G1 0x25 /* RF TX Power control */ 426 #define RF_SYN_G2 0x26 /* RF TX Power control */ 427 #define RF_SYN_G3 0x27 /* RF TX Power control */ 428 #define RF_SYN_G4 0x28 /* RF TX Power control */ 429 #define RF_SYN_G5 0x29 /* RF TX Power control */ 430 #define RF_SYN_G6 0x2A /* RF TX Power control */ 431 #define RF_SYN_G7 0x2B /* RF TX Power control */ 432 #define RF_SYN_G8 0x2C /* RF TX Power control */ 433 434 #define RF_RCK_OS 0x30 /* RF TX PA control */ 435 436 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 437 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 438 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 439 #define RF_TX_BIAS_A 0x35 440 #define RF_TX_BIAS_D 0x36 441 #define RF_LOBF_9 0x38 442 #define RF_RXRF_A3 0x3C /* */ 443 #define RF_TRSW 0x3F 444 445 #define RF_TXRF_A2 0x41 446 #define RF_TXPA_G4 0x46 447 #define RF_TXPA_A4 0x4B 448 #define RF_0x52 0x52 449 #define RF_RXG_MIX_SWBW 0x87 450 #define RF_DBG_LP_RX2 0xDF 451 #define RF_WE_LUT 0xEF 452 #define RF_S0S1 0xB0 453 454 #define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0)) 455 456 /* 457 * Bit Mask 458 * 459 * 1. Page1(0x100) */ 460 #define bBBResetB 0x100 /* Useless now? */ 461 #define bGlobalResetB 0x200 462 #define bOFDMTxStart 0x4 463 #define bCCKTxStart 0x8 464 #define bCRC32Debug 0x100 465 #define bPMACLoopback 0x10 466 #define bTxLSIG 0xffffff 467 #define bOFDMTxRate 0xf 468 #define bOFDMTxReserved 0x10 469 #define bOFDMTxLength 0x1ffe0 470 #define bOFDMTxParity 0x20000 471 #define bTxHTSIG1 0xffffff 472 #define bTxHTMCSRate 0x7f 473 #define bTxHTBW 0x80 474 #define bTxHTLength 0xffff00 475 #define bTxHTSIG2 0xffffff 476 #define bTxHTSmoothing 0x1 477 #define bTxHTSounding 0x2 478 #define bTxHTReserved 0x4 479 #define bTxHTAggreation 0x8 480 #define bTxHTSTBC 0x30 481 #define bTxHTAdvanceCoding 0x40 482 #define bTxHTShortGI 0x80 483 #define bTxHTNumberHT_LTF 0x300 484 #define bTxHTCRC8 0x3fc00 485 #define bCounterReset 0x10000 486 #define bNumOfOFDMTx 0xffff 487 #define bNumOfCCKTx 0xffff0000 488 #define bTxIdleInterval 0xffff 489 #define bOFDMService 0xffff0000 490 #define bTxMACHeader 0xffffffff 491 #define bTxDataInit 0xff 492 #define bTxHTMode 0x100 493 #define bTxDataType 0x30000 494 #define bTxRandomSeed 0xffffffff 495 #define bCCKTxPreamble 0x1 496 #define bCCKTxSFD 0xffff0000 497 #define bCCKTxSIG 0xff 498 #define bCCKTxService 0xff00 499 #define bCCKLengthExt 0x8000 500 #define bCCKTxLength 0xffff0000 501 #define bCCKTxCRC16 0xffff 502 #define bCCKTxStatus 0x1 503 #define bOFDMTxStatus 0x2 504 505 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 506 507 /* 2. Page8(0x800) */ 508 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 509 #define bJapanMode 0x2 510 #define bCCKTxSC 0x30 511 #define bCCKEn 0x1000000 512 #define bOFDMEn 0x2000000 513 514 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 515 #define bOFDMTxDACPhase 0x40000 516 #define bXATxAGC 0x3f 517 518 #define bAntennaSelect 0x0300 519 520 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 521 #define bXCTxAGC 0xf000 522 #define bXDTxAGC 0xf0000 523 524 #define bPAStart 0xf0000000 /* Useless now */ 525 #define bTRStart 0x00f00000 526 #define bRFStart 0x0000f000 527 #define bBBStart 0x000000f0 528 #define bBBCCKStart 0x0000000f 529 #define bPAEnd 0xf /* Reg0x814 */ 530 #define bTREnd 0x0f000000 531 #define bRFEnd 0x000f0000 532 #define bCCAMask 0x000000f0 /* T2R */ 533 #define bR2RCCAMask 0x00000f00 534 #define bHSSI_R2TDelay 0xf8000000 535 #define bHSSI_T2RDelay 0xf80000 536 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 537 #define bIGFromCCK 0x200 538 #define bAGCAddress 0x3f 539 #define bRxHPTx 0x7000 540 #define bRxHPT2R 0x38000 541 #define bRxHPCCKIni 0xc0000 542 #define bAGCTxCode 0xc00000 543 #define bAGCRxCode 0x300000 544 545 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 546 #define b3WireAddressLength 0x400 547 548 #define b3WireRFPowerDown 0x1 /* Useless now 549 * #define bHWSISelect 0x8 */ 550 #define b5GPAPEPolarity 0x40000000 551 #define b2GPAPEPolarity 0x80000000 552 #define bRFSW_TxDefaultAnt 0x3 553 #define bRFSW_TxOptionAnt 0x30 554 #define bRFSW_RxDefaultAnt 0x300 555 #define bRFSW_RxOptionAnt 0x3000 556 #define bRFSI_3WireData 0x1 557 #define bRFSI_3WireClock 0x2 558 #define bRFSI_3WireLoad 0x4 559 #define bRFSI_3WireRW 0x8 560 #define bRFSI_3Wire 0xf 561 562 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 563 564 #define bRFSI_TRSW 0x20 /* Useless now */ 565 #define bRFSI_TRSWB 0x40 566 #define bRFSI_ANTSW 0x100 567 #define bRFSI_ANTSWB 0x200 568 #define bRFSI_PAPE 0x400 569 #define bRFSI_PAPE5G 0x800 570 #define bBandSelect 0x1 571 #define bHTSIG2_GI 0x80 572 #define bHTSIG2_Smoothing 0x01 573 #define bHTSIG2_Sounding 0x02 574 #define bHTSIG2_Aggreaton 0x08 575 #define bHTSIG2_STBC 0x30 576 #define bHTSIG2_AdvCoding 0x40 577 #define bHTSIG2_NumOfHTLTF 0x300 578 #define bHTSIG2_CRC8 0x3fc 579 #define bHTSIG1_MCS 0x7f 580 #define bHTSIG1_BandWidth 0x80 581 #define bHTSIG1_HTLength 0xffff 582 #define bLSIG_Rate 0xf 583 #define bLSIG_Reserved 0x10 584 #define bLSIG_Length 0x1fffe 585 #define bLSIG_Parity 0x20 586 #define bCCKRxPhase 0x4 587 588 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 589 590 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 591 592 #define bLSSIReadBackData 0xfffff /* T65 RF */ 593 594 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 595 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 596 #define bRegulator0Standby 0x1 597 #define bRegulatorPLLStandby 0x2 598 #define bRegulator1Standby 0x4 599 #define bPLLPowerUp 0x8 600 #define bDPLLPowerUp 0x10 601 #define bDA10PowerUp 0x20 602 #define bAD7PowerUp 0x200 603 #define bDA6PowerUp 0x2000 604 #define bXtalPowerUp 0x4000 605 #define b40MDClkPowerUP 0x8000 606 #define bDA6DebugMode 0x20000 607 #define bDA6Swing 0x380000 608 609 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 610 611 #define b80MClkDelay 0x18000000 /* Useless */ 612 #define bAFEWatchDogEnable 0x20000000 613 614 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 615 #define bXtalCap23 0x3 616 #define bXtalCap92x 0x0f000000 617 #define bXtalCap 0x0f000000 618 619 #define bIntDifClkEnable 0x400 /* Useless */ 620 #define bExtSigClkEnable 0x800 621 #define bBandgapMbiasPowerUp 0x10000 622 #define bAD11SHGain 0xc0000 623 #define bAD11InputRange 0x700000 624 #define bAD11OPCurrent 0x3800000 625 #define bIPathLoopback 0x4000000 626 #define bQPathLoopback 0x8000000 627 #define bAFELoopback 0x10000000 628 #define bDA10Swing 0x7e0 629 #define bDA10Reverse 0x800 630 #define bDAClkSource 0x1000 631 #define bAD7InputRange 0x6000 632 #define bAD7Gain 0x38000 633 #define bAD7OutputCMMode 0x40000 634 #define bAD7InputCMMode 0x380000 635 #define bAD7Current 0xc00000 636 #define bRegulatorAdjust 0x7000000 637 #define bAD11PowerUpAtTx 0x1 638 #define bDA10PSAtTx 0x10 639 #define bAD11PowerUpAtRx 0x100 640 #define bDA10PSAtRx 0x1000 641 #define bCCKRxAGCFormat 0x200 642 #define bPSDFFTSamplepPoint 0xc000 643 #define bPSDAverageNum 0x3000 644 #define bIQPathControl 0xc00 645 #define bPSDFreq 0x3ff 646 #define bPSDAntennaPath 0x30 647 #define bPSDIQSwitch 0x40 648 #define bPSDRxTrigger 0x400000 649 #define bPSDTxTrigger 0x80000000 650 #define bPSDSineToneScale 0x7f000000 651 #define bPSDReport 0xffff 652 653 /* 3. Page9(0x900) */ 654 #define bOFDMTxSC 0x30000000 /* Useless */ 655 #define bCCKTxOn 0x1 656 #define bOFDMTxOn 0x2 657 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 658 #define bDebugItem 0xff /* reset debug page and LWord */ 659 #define bAntL 0x10 660 #define bAntNonHT 0x100 661 #define bAntHT1 0x1000 662 #define bAntHT2 0x10000 663 #define bAntHT1S1 0x100000 664 #define bAntNonHTS1 0x1000000 665 666 /* 4. PageA(0xA00) */ 667 #define bCCKBBMode 0x3 /* Useless */ 668 #define bCCKTxPowerSaving 0x80 669 #define bCCKRxPowerSaving 0x40 670 671 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 672 673 #define bCCKScramble 0x8 /* Useless */ 674 #define bCCKAntDiversity 0x8000 675 #define bCCKCarrierRecovery 0x4000 676 #define bCCKTxRate 0x3000 677 #define bCCKDCCancel 0x0800 678 #define bCCKISICancel 0x0400 679 #define bCCKMatchFilter 0x0200 680 #define bCCKEqualizer 0x0100 681 #define bCCKPreambleDetect 0x800000 682 #define bCCKFastFalseCCA 0x400000 683 #define bCCKChEstStart 0x300000 684 #define bCCKCCACount 0x080000 685 #define bCCKcs_lim 0x070000 686 #define bCCKBistMode 0x80000000 687 #define bCCKCCAMask 0x40000000 688 #define bCCKTxDACPhase 0x4 689 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 690 #define bCCKr_cp_mode0 0x0100 691 #define bCCKTxDCOffset 0xf0 692 #define bCCKRxDCOffset 0xf 693 #define bCCKCCAMode 0xc000 694 #define bCCKFalseCS_lim 0x3f00 695 #define bCCKCS_ratio 0xc00000 696 #define bCCKCorgBit_sel 0x300000 697 #define bCCKPD_lim 0x0f0000 698 #define bCCKNewCCA 0x80000000 699 #define bCCKRxHPofIG 0x8000 700 #define bCCKRxIG 0x7f00 701 #define bCCKLNAPolarity 0x800000 702 #define bCCKRx1stGain 0x7f0000 703 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 704 #define bCCKRxAGCSatLevel 0x1f000000 705 #define bCCKRxAGCSatCount 0xe0 706 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 707 #define bCCKFixedRxAGC 0x8000 708 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 709 #define bCCKAntennaPolarity 0x2000 710 #define bCCKTxFilterType 0x0c00 711 #define bCCKRxAGCReportType 0x0300 712 #define bCCKRxDAGCEn 0x80000000 713 #define bCCKRxDAGCPeriod 0x20000000 714 #define bCCKRxDAGCSatLevel 0x1f000000 715 #define bCCKTimingRecovery 0x800000 716 #define bCCKTxC0 0x3f0000 717 #define bCCKTxC1 0x3f000000 718 #define bCCKTxC2 0x3f 719 #define bCCKTxC3 0x3f00 720 #define bCCKTxC4 0x3f0000 721 #define bCCKTxC5 0x3f000000 722 #define bCCKTxC6 0x3f 723 #define bCCKTxC7 0x3f00 724 #define bCCKDebugPort 0xff0000 725 #define bCCKDACDebug 0x0f000000 726 #define bCCKFalseAlarmEnable 0x8000 727 #define bCCKFalseAlarmRead 0x4000 728 #define bCCKTRSSI 0x7f 729 #define bCCKRxAGCReport 0xfe 730 #define bCCKRxReport_AntSel 0x80000000 731 #define bCCKRxReport_MFOff 0x40000000 732 #define bCCKRxRxReport_SQLoss 0x20000000 733 #define bCCKRxReport_Pktloss 0x10000000 734 #define bCCKRxReport_Lockedbit 0x08000000 735 #define bCCKRxReport_RateError 0x04000000 736 #define bCCKRxReport_RxRate 0x03000000 737 #define bCCKRxFACounterLower 0xff 738 #define bCCKRxFACounterUpper 0xff000000 739 #define bCCKRxHPAGCStart 0xe000 740 #define bCCKRxHPAGCFinal 0x1c00 741 #define bCCKRxFalseAlarmEnable 0x8000 742 #define bCCKFACounterFreeze 0x4000 743 #define bCCKTxPathSel 0x10000000 744 #define bCCKDefaultRxPath 0xc000000 745 #define bCCKOptionRxPath 0x3000000 746 747 /* 5. PageC(0xC00) */ 748 #define bNumOfSTF 0x3 /* Useless */ 749 #define bShift_L 0xc0 750 #define bGI_TH 0xc 751 #define bRxPathA 0x1 752 #define bRxPathB 0x2 753 #define bRxPathC 0x4 754 #define bRxPathD 0x8 755 #define bTxPathA 0x1 756 #define bTxPathB 0x2 757 #define bTxPathC 0x4 758 #define bTxPathD 0x8 759 #define bTRSSIFreq 0x200 760 #define bADCBackoff 0x3000 761 #define bDFIRBackoff 0xc000 762 #define bTRSSILatchPhase 0x10000 763 #define bRxIDCOffset 0xff 764 #define bRxQDCOffset 0xff00 765 #define bRxDFIRMode 0x1800000 766 #define bRxDCNFType 0xe000000 767 #define bRXIQImb_A 0x3ff 768 #define bRXIQImb_B 0xfc00 769 #define bRXIQImb_C 0x3f0000 770 #define bRXIQImb_D 0xffc00000 771 #define bDC_dc_Notch 0x60000 772 #define bRxNBINotch 0x1f000000 773 #define bPD_TH 0xf 774 #define bPD_TH_Opt2 0xc000 775 #define bPWED_TH 0x700 776 #define bIfMF_Win_L 0x800 777 #define bPD_Option 0x1000 778 #define bMF_Win_L 0xe000 779 #define bBW_Search_L 0x30000 780 #define bwin_enh_L 0xc0000 781 #define bBW_TH 0x700000 782 #define bED_TH2 0x3800000 783 #define bBW_option 0x4000000 784 #define bRatio_TH 0x18000000 785 #define bWindow_L 0xe0000000 786 #define bSBD_Option 0x1 787 #define bFrame_TH 0x1c 788 #define bFS_Option 0x60 789 #define bDC_Slope_check 0x80 790 #define bFGuard_Counter_DC_L 0xe00 791 #define bFrame_Weight_Short 0x7000 792 #define bSub_Tune 0xe00000 793 #define bFrame_DC_Length 0xe000000 794 #define bSBD_start_offset 0x30000000 795 #define bFrame_TH_2 0x7 796 #define bFrame_GI2_TH 0x38 797 #define bGI2_Sync_en 0x40 798 #define bSarch_Short_Early 0x300 799 #define bSarch_Short_Late 0xc00 800 #define bSarch_GI2_Late 0x70000 801 #define bCFOAntSum 0x1 802 #define bCFOAcc 0x2 803 #define bCFOStartOffset 0xc 804 #define bCFOLookBack 0x70 805 #define bCFOSumWeight 0x80 806 #define bDAGCEnable 0x10000 807 #define bTXIQImb_A 0x3ff 808 #define bTXIQImb_B 0xfc00 809 #define bTXIQImb_C 0x3f0000 810 #define bTXIQImb_D 0xffc00000 811 #define bTxIDCOffset 0xff 812 #define bTxQDCOffset 0xff00 813 #define bTxDFIRMode 0x10000 814 #define bTxPesudoNoiseOn 0x4000000 815 #define bTxPesudoNoise_A 0xff 816 #define bTxPesudoNoise_B 0xff00 817 #define bTxPesudoNoise_C 0xff0000 818 #define bTxPesudoNoise_D 0xff000000 819 #define bCCADropOption 0x20000 820 #define bCCADropThres 0xfff00000 821 #define bEDCCA_H 0xf 822 #define bEDCCA_L 0xf0 823 #define bLambda_ED 0x300 824 #define bRxInitialGain 0x7f 825 #define bRxAntDivEn 0x80 826 #define bRxAGCAddressForLNA 0x7f00 827 #define bRxHighPowerFlow 0x8000 828 #define bRxAGCFreezeThres 0xc0000 829 #define bRxFreezeStep_AGC1 0x300000 830 #define bRxFreezeStep_AGC2 0xc00000 831 #define bRxFreezeStep_AGC3 0x3000000 832 #define bRxFreezeStep_AGC0 0xc000000 833 #define bRxRssi_Cmp_En 0x10000000 834 #define bRxQuickAGCEn 0x20000000 835 #define bRxAGCFreezeThresMode 0x40000000 836 #define bRxOverFlowCheckType 0x80000000 837 #define bRxAGCShift 0x7f 838 #define bTRSW_Tri_Only 0x80 839 #define bPowerThres 0x300 840 #define bRxAGCEn 0x1 841 #define bRxAGCTogetherEn 0x2 842 #define bRxAGCMin 0x4 843 #define bRxHP_Ini 0x7 844 #define bRxHP_TRLNA 0x70 845 #define bRxHP_RSSI 0x700 846 #define bRxHP_BBP1 0x7000 847 #define bRxHP_BBP2 0x70000 848 #define bRxHP_BBP3 0x700000 849 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 850 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 851 #define bRxSettle_TRSW 0x7 852 #define bRxSettle_LNA 0x38 853 #define bRxSettle_RSSI 0x1c0 854 #define bRxSettle_BBP 0xe00 855 #define bRxSettle_RxHP 0x7000 856 #define bRxSettle_AntSW_RSSI 0x38000 857 #define bRxSettle_AntSW 0xc0000 858 #define bRxProcessTime_DAGC 0x300000 859 #define bRxSettle_HSSI 0x400000 860 #define bRxProcessTime_BBPPW 0x800000 861 #define bRxAntennaPowerShift 0x3000000 862 #define bRSSITableSelect 0xc000000 863 #define bRxHP_Final 0x7000000 864 #define bRxHTSettle_BBP 0x7 865 #define bRxHTSettle_HSSI 0x8 866 #define bRxHTSettle_RxHP 0x70 867 #define bRxHTSettle_BBPPW 0x80 868 #define bRxHTSettle_Idle 0x300 869 #define bRxHTSettle_Reserved 0x1c00 870 #define bRxHTRxHPEn 0x8000 871 #define bRxHTAGCFreezeThres 0x30000 872 #define bRxHTAGCTogetherEn 0x40000 873 #define bRxHTAGCMin 0x80000 874 #define bRxHTAGCEn 0x100000 875 #define bRxHTDAGCEn 0x200000 876 #define bRxHTRxHP_BBP 0x1c00000 877 #define bRxHTRxHP_Final 0xe0000000 878 #define bRxPWRatioTH 0x3 879 #define bRxPWRatioEn 0x4 880 #define bRxMFHold 0x3800 881 #define bRxPD_Delay_TH1 0x38 882 #define bRxPD_Delay_TH2 0x1c0 883 #define bRxPD_DC_COUNT_MAX 0x600 884 /* #define bRxMF_Hold 0x3800 */ 885 #define bRxPD_Delay_TH 0x8000 886 #define bRxProcess_Delay 0xf0000 887 #define bRxSearchrange_GI2_Early 0x700000 888 #define bRxFrame_Guard_Counter_L 0x3800000 889 #define bRxSGI_Guard_L 0xc000000 890 #define bRxSGI_Search_L 0x30000000 891 #define bRxSGI_TH 0xc0000000 892 #define bDFSCnt0 0xff 893 #define bDFSCnt1 0xff00 894 #define bDFSFlag 0xf0000 895 #define bMFWeightSum 0x300000 896 #define bMinIdxTH 0x7f000000 897 #define bDAFormat 0x40000 898 #define bTxChEmuEnable 0x01000000 899 #define bTRSWIsolation_A 0x7f 900 #define bTRSWIsolation_B 0x7f00 901 #define bTRSWIsolation_C 0x7f0000 902 #define bTRSWIsolation_D 0x7f000000 903 #define bExtLNAGain 0x7c00 904 905 /* 6. PageE(0xE00) */ 906 #define bSTBCEn 0x4 /* Useless */ 907 #define bAntennaMapping 0x10 908 #define bNss 0x20 909 #define bCFOAntSumD 0x200 910 #define bPHYCounterReset 0x8000000 911 #define bCFOReportGet 0x4000000 912 #define bOFDMContinueTx 0x10000000 913 #define bOFDMSingleCarrier 0x20000000 914 #define bOFDMSingleTone 0x40000000 915 /* #define bRxPath1 0x01 */ 916 /* #define bRxPath2 0x02 */ 917 /* #define bRxPath3 0x04 */ 918 /* #define bRxPath4 0x08 */ 919 /* #define bTxPath1 0x10 */ 920 /* #define bTxPath2 0x20 */ 921 #define bHTDetect 0x100 922 #define bCFOEn 0x10000 923 #define bCFOValue 0xfff00000 924 #define bSigTone_Re 0x3f 925 #define bSigTone_Im 0x7f00 926 #define bCounter_CCA 0xffff 927 #define bCounter_ParityFail 0xffff0000 928 #define bCounter_RateIllegal 0xffff 929 #define bCounter_CRC8Fail 0xffff0000 930 #define bCounter_MCSNoSupport 0xffff 931 #define bCounter_FastSync 0xffff 932 #define bShortCFO 0xfff 933 #define bShortCFOTLength 12 /* total */ 934 #define bShortCFOFLength 11 /* fraction */ 935 #define bLongCFO 0x7ff 936 #define bLongCFOTLength 11 937 #define bLongCFOFLength 11 938 #define bTailCFO 0x1fff 939 #define bTailCFOTLength 13 940 #define bTailCFOFLength 12 941 #define bmax_en_pwdB 0xffff 942 #define bCC_power_dB 0xffff0000 943 #define bnoise_pwdB 0xffff 944 #define bPowerMeasTLength 10 945 #define bPowerMeasFLength 3 946 #define bRx_HT_BW 0x1 947 #define bRxSC 0x6 948 #define bRx_HT 0x8 949 #define bNB_intf_det_on 0x1 950 #define bIntf_win_len_cfg 0x30 951 #define bNB_Intf_TH_cfg 0x1c0 952 #define bRFGain 0x3f 953 #define bTableSel 0x40 954 #define bTRSW 0x80 955 #define bRxSNR_A 0xff 956 #define bRxSNR_B 0xff00 957 #define bRxSNR_C 0xff0000 958 #define bRxSNR_D 0xff000000 959 #define bSNREVMTLength 8 960 #define bSNREVMFLength 1 961 #define bCSI1st 0xff 962 #define bCSI2nd 0xff00 963 #define bRxEVM1st 0xff0000 964 #define bRxEVM2nd 0xff000000 965 #define bSIGEVM 0xff 966 #define bPWDB 0xff00 967 #define bSGIEN 0x10000 968 969 #define bSFactorQAM1 0xf /* Useless */ 970 #define bSFactorQAM2 0xf0 971 #define bSFactorQAM3 0xf00 972 #define bSFactorQAM4 0xf000 973 #define bSFactorQAM5 0xf0000 974 #define bSFactorQAM6 0xf0000 975 #define bSFactorQAM7 0xf00000 976 #define bSFactorQAM8 0xf000000 977 #define bSFactorQAM9 0xf0000000 978 #define bCSIScheme 0x100000 979 980 #define bNoiseLvlTopSet 0x3 /* Useless */ 981 #define bChSmooth 0x4 982 #define bChSmoothCfg1 0x38 983 #define bChSmoothCfg2 0x1c0 984 #define bChSmoothCfg3 0xe00 985 #define bChSmoothCfg4 0x7000 986 #define bMRCMode 0x800000 987 #define bTHEVMCfg 0x7000000 988 989 #define bLoopFitType 0x1 /* Useless */ 990 #define bUpdCFO 0x40 991 #define bUpdCFOOffData 0x80 992 #define bAdvUpdCFO 0x100 993 #define bAdvTimeCtrl 0x800 994 #define bUpdClko 0x1000 995 #define bFC 0x6000 996 #define bTrackingMode 0x8000 997 #define bPhCmpEnable 0x10000 998 #define bUpdClkoLTF 0x20000 999 #define bComChCFO 0x40000 1000 #define bCSIEstiMode 0x80000 1001 #define bAdvUpdEqz 0x100000 1002 #define bUChCfg 0x7000000 1003 #define bUpdEqz 0x8000000 1004 1005 /* Rx Pseduo noise */ 1006 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1007 #define bRxPesudoNoise_A 0xff 1008 #define bRxPesudoNoise_B 0xff00 1009 #define bRxPesudoNoise_C 0xff0000 1010 #define bRxPesudoNoise_D 0xff000000 1011 #define bPesudoNoiseState_A 0xffff 1012 #define bPesudoNoiseState_B 0xffff0000 1013 #define bPesudoNoiseState_C 0xffff 1014 #define bPesudoNoiseState_D 0xffff0000 1015 1016 /* 7. RF Register 1017 * Zebra1 */ 1018 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1019 #define bZebra1_TRxControl 0xc00 1020 #define bZebra1_TRxGainSetting 0x07f 1021 #define bZebra1_RxCorner 0xc00 1022 #define bZebra1_TxChargePump 0x38 1023 #define bZebra1_RxChargePump 0x7 1024 #define bZebra1_ChannelNum 0xf80 1025 #define bZebra1_TxLPFBW 0x400 1026 #define bZebra1_RxLPFBW 0x600 1027 1028 /* Zebra4 */ 1029 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1030 #define bRTL8256RegModeCtrl0 0x40 1031 #define bRTL8256_TxLPFBW 0x18 1032 #define bRTL8256_RxLPFBW 0x600 1033 1034 /* RTL8258 */ 1035 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1036 #define bRTL8258_RxLPFBW 0xc00 1037 #define bRTL8258_RSSILPFBW 0xc0 1038 1039 1040 /* 1041 * Other Definition 1042 * */ 1043 1044 /* byte endable for sb_write */ 1045 #define bByte0 0x1 /* Useless */ 1046 #define bByte1 0x2 1047 #define bByte2 0x4 1048 #define bByte3 0x8 1049 #define bWord0 0x3 1050 #define bWord1 0xc 1051 #define bDWord 0xf 1052 1053 /* for PutRegsetting & GetRegSetting BitMask */ 1054 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1055 #define bMaskByte1 0xff00 1056 #define bMaskByte2 0xff0000 1057 #define bMaskByte3 0xff000000 1058 #define bMaskHWord 0xffff0000 1059 #define bMaskLWord 0x0000ffff 1060 #define bMaskDWord 0xffffffff 1061 #define bMaskH3Bytes 0xffffff00 1062 #define bMask12Bits 0xfff 1063 #define bMaskH4Bits 0xf0000000 1064 #define bMaskOFDM_D 0xffc00000 1065 #define bMaskCCK 0x3f3f3f3f 1066 1067 1068 #define bEnable 0x1 /* Useless */ 1069 #define bDisable 0x0 1070 1071 #define LeftAntenna 0x0 /* Useless */ 1072 #define RightAntenna 0x1 1073 1074 #define tCheckTxStatus 500 /* 500ms */ /* Useless */ 1075 #define tUpdateRxCounter 100 /* 100ms */ 1076 1077 #define rateCCK 0 /* Useless */ 1078 #define rateOFDM 1 1079 #define rateHT 2 1080 1081 /* define Register-End */ 1082 #define bPMAC_End 0x1ff /* Useless */ 1083 #define bFPGAPHY0_End 0x8ff 1084 #define bFPGAPHY1_End 0x9ff 1085 #define bCCKPHY0_End 0xaff 1086 #define bOFDMPHY0_End 0xcff 1087 #define bOFDMPHY1_End 0xdff 1088 1089 /* define max debug item in each debug page 1090 * #define bMaxItem_FPGA_PHY0 0x9 1091 * #define bMaxItem_FPGA_PHY1 0x3 1092 * #define bMaxItem_PHY_11B 0x16 1093 * #define bMaxItem_OFDM_PHY0 0x29 1094 * #define bMaxItem_OFDM_PHY1 0x0 */ 1095 1096 #define bPMACControl 0x0 /* Useless */ 1097 #define bWMACControl 0x1 1098 #define bWNICControl 0x2 1099 1100 #define PathA 0x0 /* Useless */ 1101 #define PathB 0x1 1102 #define PathC 0x2 1103 #define PathD 0x3 1104 1105 /*--------------------------Define Parameters-------------------------------*/ 1106 1107 1108 /* BB Register Definition 1109 * 1110 * 4. Page9(0x900) 1111 * */ 1112 #define rDPDT_control 0x92c 1113 #define rfe_ctrl_anta_src 0x930 1114 #define rS0S1_PathSwitch 0x948 1115 #define BBrx_DFIR 0x954 1116 #define AGC_table_select 0xb2c 1117 1118 /* 1119 * PageB(0xB00) 1120 * */ 1121 #define rPdp_AntA 0xb00 1122 #define rPdp_AntA_4 0xb04 1123 #define rPdp_AntA_8 0xb08 1124 #define rPdp_AntA_C 0xb0c 1125 #define rPdp_AntA_10 0xb10 1126 #define rPdp_AntA_14 0xb14 1127 #define rPdp_AntA_18 0xb18 1128 #define rPdp_AntA_1C 0xb1c 1129 #define rPdp_AntA_20 0xb20 1130 #define rPdp_AntA_24 0xb24 1131 1132 #define rConfig_Pmpd_AntA 0xb28 1133 #define rConfig_ram64x16 0xb2c 1134 1135 #define rBndA 0xb30 1136 #define rHssiPar 0xb34 1137 1138 #define rConfig_AntA 0xb68 1139 #define rConfig_AntB 0xb6c 1140 1141 #define rPdp_AntB 0xb70 1142 #define rPdp_AntB_4 0xb74 1143 #define rPdp_AntB_8 0xb78 1144 #define rPdp_AntB_C 0xb7c 1145 #define rPdp_AntB_10 0xb80 1146 #define rPdp_AntB_14 0xb84 1147 #define rPdp_AntB_18 0xb88 1148 #define rPdp_AntB_1C 0xb8c 1149 #define rPdp_AntB_20 0xb90 1150 #define rPdp_AntB_24 0xb94 1151 1152 #define rConfig_Pmpd_AntB 0xb98 1153 1154 #define rBndB 0xba0 1155 1156 #define rAPK 0xbd8 1157 #define rPm_Rx0_AntA 0xbdc 1158 #define rPm_Rx1_AntA 0xbe0 1159 #define rPm_Rx2_AntA 0xbe4 1160 #define rPm_Rx3_AntA 0xbe8 1161 #define rPm_Rx0_AntB 0xbec 1162 #define rPm_Rx1_AntB 0xbf0 1163 #define rPm_Rx2_AntB 0xbf4 1164 #define rPm_Rx3_AntB 0xbf8 1165 1166 #endif 1167