1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16
17 #define _HAL_INTF_C_
18
19 #include <drv_types.h>
20 #include <hal_data.h>
21
22 const u32 _chip_type_to_odm_ic_type[] = {
23 0,
24 ODM_RTL8188E,
25 ODM_RTL8192E,
26 ODM_RTL8812,
27 ODM_RTL8821,
28 ODM_RTL8723B,
29 ODM_RTL8814A,
30 ODM_RTL8703B,
31 ODM_RTL8188F,
32 ODM_RTL8188F,
33 ODM_RTL8822B,
34 ODM_RTL8723D,
35 ODM_RTL8821C,
36 ODM_RTL8710B,
37 ODM_RTL8192F,
38 ODM_RTL8822C,
39 0,
40 };
41
rtw_hal_chip_configure(_adapter * padapter)42 void rtw_hal_chip_configure(_adapter *padapter)
43 {
44 padapter->hal_func.intf_chip_configure(padapter);
45 }
46
47 /*
48 * Description:
49 * Read chip internal ROM data
50 *
51 * Return:
52 * _SUCCESS success
53 * _FAIL fail
54 */
rtw_hal_read_chip_info(_adapter * padapter)55 u8 rtw_hal_read_chip_info(_adapter *padapter)
56 {
57 u8 rtn = _SUCCESS;
58 u8 hci_type = rtw_get_intf_type(padapter);
59 systime start = rtw_get_current_time();
60
61 /* before access eFuse, make sure card enable has been called */
62 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
63 && !rtw_is_hw_init_completed(padapter))
64 rtw_hal_power_on(padapter);
65
66 rtn = padapter->hal_func.read_adapter_info(padapter);
67
68 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
69 && !rtw_is_hw_init_completed(padapter))
70 rtw_hal_power_off(padapter);
71
72 RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
73
74 return rtn;
75 }
76
rtw_hal_read_chip_version(_adapter * padapter)77 void rtw_hal_read_chip_version(_adapter *padapter)
78 {
79 padapter->hal_func.read_chip_version(padapter);
80 rtw_odm_init_ic_type(padapter);
81 }
82
rtw_init_wireless_mode(_adapter * padapter)83 static void rtw_init_wireless_mode(_adapter *padapter)
84 {
85 u8 proto_wireless_mode = 0;
86 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
87 if(hal_spec->proto_cap & PROTO_CAP_11B)
88 proto_wireless_mode |= WIRELESS_11B;
89
90 if(hal_spec->proto_cap & PROTO_CAP_11G)
91 proto_wireless_mode |= WIRELESS_11G;
92 #ifdef CONFIG_80211AC_VHT
93 if(hal_spec->band_cap & BAND_CAP_5G)
94 proto_wireless_mode |= WIRELESS_11A;
95 #endif
96
97 #ifdef CONFIG_80211N_HT
98 if(hal_spec->proto_cap & PROTO_CAP_11N) {
99
100 if(hal_spec->band_cap & BAND_CAP_2G)
101 proto_wireless_mode |= WIRELESS_11_24N;
102 if(hal_spec->band_cap & BAND_CAP_5G)
103 proto_wireless_mode |= WIRELESS_11_5N;
104 }
105 #endif
106
107 #ifdef CONFIG_80211AC_VHT
108 if(hal_spec->proto_cap & PROTO_CAP_11AC)
109 proto_wireless_mode |= WIRELESS_11AC;
110 #endif
111 padapter->registrypriv.wireless_mode &= proto_wireless_mode;
112 }
113
rtw_hal_def_value_init(_adapter * padapter)114 void rtw_hal_def_value_init(_adapter *padapter)
115 {
116 if (is_primary_adapter(padapter)) {
117 /*init fw_psmode_iface_id*/
118 adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
119 /*wireless_mode*/
120 rtw_init_wireless_mode(padapter);
121 padapter->hal_func.init_default_value(padapter);
122
123 rtw_init_hal_com_default_value(padapter);
124
125 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
126 adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
127 adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
128 #endif
129 #ifdef CONFIG_HW_P0_TSF_SYNC
130 adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
131 adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
132 #endif
133
134 GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
135 }
136 }
137
rtw_hal_data_init(_adapter * padapter)138 u8 rtw_hal_data_init(_adapter *padapter)
139 {
140 if (is_primary_adapter(padapter)) {
141 padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
142 padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
143 if (padapter->HalData == NULL) {
144 RTW_INFO("cant not alloc memory for HAL DATA\n");
145 return _FAIL;
146 }
147 rtw_phydm_priv_init(padapter);
148 }
149 return _SUCCESS;
150 }
151
rtw_hal_data_deinit(_adapter * padapter)152 void rtw_hal_data_deinit(_adapter *padapter)
153 {
154 if (is_primary_adapter(padapter)) {
155 if (padapter->HalData) {
156 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
157 phy_free_filebuf(padapter);
158 #endif
159 rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
160 padapter->HalData = NULL;
161 padapter->hal_data_sz = 0;
162 }
163 }
164 }
165
rtw_hal_free_data(_adapter * padapter)166 void rtw_hal_free_data(_adapter *padapter)
167 {
168 /* free HAL Data */
169 rtw_hal_data_deinit(padapter);
170 }
rtw_hal_dm_init(_adapter * padapter)171 void rtw_hal_dm_init(_adapter *padapter)
172 {
173 if (is_primary_adapter(padapter)) {
174 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
175
176 padapter->hal_func.dm_init(padapter);
177
178 _rtw_spinlock_init(&pHalData->IQKSpinLock);
179
180 phy_load_tx_power_ext_info(padapter, 1);
181 }
182 }
rtw_hal_dm_deinit(_adapter * padapter)183 void rtw_hal_dm_deinit(_adapter *padapter)
184 {
185 if (is_primary_adapter(padapter)) {
186 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
187
188 padapter->hal_func.dm_deinit(padapter);
189
190 _rtw_spinlock_free(&pHalData->IQKSpinLock);
191 }
192 }
193
194 #ifdef CONFIG_RTW_SW_LED
rtw_hal_sw_led_init(_adapter * padapter)195 void rtw_hal_sw_led_init(_adapter *padapter)
196 {
197 struct led_priv *ledpriv = adapter_to_led(padapter);
198
199 if (ledpriv->bRegUseLed == _FALSE)
200 return;
201
202 if (!is_primary_adapter(padapter))
203 return;
204
205 if (padapter->hal_func.InitSwLeds) {
206 padapter->hal_func.InitSwLeds(padapter);
207 rtw_led_set_ctl_en_mask_primary(padapter);
208 rtw_led_set_iface_en(padapter, 1);
209 }
210 }
211
rtw_hal_sw_led_deinit(_adapter * padapter)212 void rtw_hal_sw_led_deinit(_adapter *padapter)
213 {
214 struct led_priv *ledpriv = adapter_to_led(padapter);
215
216 if (ledpriv->bRegUseLed == _FALSE)
217 return;
218
219 if (!is_primary_adapter(padapter))
220 return;
221
222 if (padapter->hal_func.DeInitSwLeds)
223 padapter->hal_func.DeInitSwLeds(padapter);
224 }
225 #endif
226
rtw_hal_power_on(_adapter * padapter)227 u32 rtw_hal_power_on(_adapter *padapter)
228 {
229 u32 ret = 0;
230 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
231
232 ret = padapter->hal_func.hal_power_on(padapter);
233
234 #ifdef CONFIG_BT_COEXIST
235 if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
236 rtw_btcoex_PowerOnSetting(padapter);
237 #endif
238
239 return ret;
240 }
rtw_hal_power_off(_adapter * padapter)241 void rtw_hal_power_off(_adapter *padapter)
242 {
243 struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
244
245 _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
246 _rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
247
248 #ifdef CONFIG_BT_COEXIST
249 rtw_btcoex_PowerOffSetting(padapter);
250 #endif
251
252 padapter->hal_func.hal_power_off(padapter);
253 }
254
255
rtw_hal_init_opmode(_adapter * padapter)256 void rtw_hal_init_opmode(_adapter *padapter)
257 {
258 NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
259 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
260 sint fw_state;
261
262 fw_state = get_fwstate(pmlmepriv);
263
264 if (fw_state & WIFI_ADHOC_STATE)
265 networkType = Ndis802_11IBSS;
266 else if (fw_state & WIFI_STATION_STATE)
267 networkType = Ndis802_11Infrastructure;
268 #ifdef CONFIG_AP_MODE
269 else if (fw_state & WIFI_AP_STATE)
270 networkType = Ndis802_11APMode;
271 #endif
272 #ifdef CONFIG_RTW_MESH
273 else if (fw_state & WIFI_MESH_STATE)
274 networkType = Ndis802_11_mesh;
275 #endif
276 else
277 return;
278
279 rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
280 }
281
282 #ifdef CONFIG_NEW_NETDEV_HDL
rtw_hal_iface_init(_adapter * adapter)283 uint rtw_hal_iface_init(_adapter *adapter)
284 {
285 uint status = _SUCCESS;
286
287 rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
288 #ifdef RTW_HALMAC
289 rtw_hal_hw_port_enable(adapter);
290 #endif
291 rtw_sec_restore_wep_key(adapter);
292 rtw_hal_init_opmode(adapter);
293 rtw_hal_start_thread(adapter);
294 return status;
295 }
rtw_hal_init(_adapter * padapter)296 uint rtw_hal_init(_adapter *padapter)
297 {
298 uint status = _SUCCESS;
299
300 status = padapter->hal_func.hal_init(padapter);
301
302 if (status == _SUCCESS) {
303 rtw_set_hw_init_completed(padapter, _TRUE);
304 if (padapter->registrypriv.notch_filter == 1)
305 rtw_hal_notch_filter(padapter, 1);
306 rtw_led_control(padapter, LED_CTL_POWER_ON);
307 init_hw_mlme_ext(padapter);
308 #ifdef CONFIG_RF_POWER_TRIM
309 rtw_bb_rf_gain_offset(padapter);
310 #endif /*CONFIG_RF_POWER_TRIM*/
311 GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
312 #ifdef CONFIG_MI_WITH_MBSSID_CAM
313 rtw_mi_set_mbid_cam(padapter);
314 #endif
315 #ifdef CONFIG_SUPPORT_MULTI_BCN
316 rtw_ap_multi_bcn_cfg(padapter);
317 #endif
318 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
319 #ifdef CONFIG_DYNAMIC_SOML
320 rtw_dyn_soml_config(padapter);
321 #endif
322 #endif
323 #ifdef CONFIG_TDMADIG
324 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
325 #endif/*CONFIG_TDMADIG*/
326 #ifdef CONFIG_RTW_TX_2PATH_EN
327 rtw_phydm_tx_2path_en(padapter);
328 #endif
329 } else {
330 rtw_set_hw_init_completed(padapter, _FALSE);
331 RTW_ERR("%s: hal_init fail\n", __func__);
332 }
333 return status;
334 }
335 #else
rtw_hal_init(_adapter * padapter)336 uint rtw_hal_init(_adapter *padapter)
337 {
338 uint status = _SUCCESS;
339 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
340 int i;
341
342 status = padapter->hal_func.hal_init(padapter);
343
344 if (status == _SUCCESS) {
345 rtw_set_hw_init_completed(padapter, _TRUE);
346 rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
347 #ifdef RTW_HALMAC
348 rtw_restore_hw_port_cfg(padapter);
349 #endif
350 if (padapter->registrypriv.notch_filter == 1)
351 rtw_hal_notch_filter(padapter, 1);
352
353 for (i = 0; i < dvobj->iface_nums; i++)
354 rtw_sec_restore_wep_key(dvobj->padapters[i]);
355
356 rtw_led_control(padapter, LED_CTL_POWER_ON);
357
358 init_hw_mlme_ext(padapter);
359
360 rtw_hal_init_opmode(padapter);
361
362 #ifdef CONFIG_RF_POWER_TRIM
363 rtw_bb_rf_gain_offset(padapter);
364 #endif /*CONFIG_RF_POWER_TRIM*/
365
366 #ifdef CONFIG_SUPPORT_MULTI_BCN
367 rtw_ap_multi_bcn_cfg(padapter);
368 #endif
369
370 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
371 #ifdef CONFIG_DYNAMIC_SOML
372 rtw_dyn_soml_config(padapter);
373 #endif
374 #endif
375 #ifdef CONFIG_TDMADIG
376 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
377 #endif/*CONFIG_TDMADIG*/
378
379 #ifdef CONFIG_RTW_TX_2PATH_EN
380 rtw_phydm_tx_2path_en(padapter);
381 #endif
382 } else {
383 rtw_set_hw_init_completed(padapter, _FALSE);
384 RTW_ERR("%s: fail\n", __func__);
385 }
386
387
388 return status;
389
390 }
391 #endif
392
rtw_hal_deinit(_adapter * padapter)393 uint rtw_hal_deinit(_adapter *padapter)
394 {
395 uint status = _SUCCESS;
396 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
397 int i;
398
399 status = padapter->hal_func.hal_deinit(padapter);
400
401 if (status == _SUCCESS) {
402 rtw_led_control(padapter, LED_CTL_POWER_OFF);
403 rtw_set_hw_init_completed(padapter, _FALSE);
404 } else
405 RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
406
407
408 return status;
409 }
410
rtw_hal_set_hwreg(_adapter * padapter,u8 variable,u8 * val)411 u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
412 {
413 return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
414 }
415
rtw_hal_get_hwreg(_adapter * padapter,u8 variable,u8 * val)416 void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
417 {
418 padapter->hal_func.GetHwRegHandler(padapter, variable, val);
419 }
420
rtw_hal_set_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)421 u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
422 {
423 return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
424 }
rtw_hal_get_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)425 u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
426 {
427 return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
428 }
429
rtw_hal_set_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)430 void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
431 {
432 padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
433 }
rtw_hal_get_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)434 void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
435 {
436 padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
437 }
438
439 /* FOR SDIO & PCIE */
rtw_hal_enable_interrupt(_adapter * padapter)440 void rtw_hal_enable_interrupt(_adapter *padapter)
441 {
442 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
443 padapter->hal_func.enable_interrupt(padapter);
444 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
445 }
446
447 /* FOR SDIO & PCIE */
rtw_hal_disable_interrupt(_adapter * padapter)448 void rtw_hal_disable_interrupt(_adapter *padapter)
449 {
450 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
451 padapter->hal_func.disable_interrupt(padapter);
452 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
453 }
454
455
rtw_hal_check_ips_status(_adapter * padapter)456 u8 rtw_hal_check_ips_status(_adapter *padapter)
457 {
458 u8 val = _FALSE;
459 if (padapter->hal_func.check_ips_status)
460 val = padapter->hal_func.check_ips_status(padapter);
461 else
462 RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
463
464 return val;
465 }
466
rtw_hal_fw_dl(_adapter * padapter,u8 wowlan)467 s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
468 {
469 return padapter->hal_func.fw_dl(padapter, wowlan);
470 }
471
472 #ifdef RTW_HALMAC
rtw_hal_fw_mem_dl(_adapter * padapter,enum fw_mem mem)473 s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
474 {
475 systime dlfw_start_time = rtw_get_current_time();
476 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
477 struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
478 s32 rst = _FALSE;
479
480 rst = padapter->hal_func.fw_mem_dl(padapter, mem);
481 RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
482
483 if (rst == _FALSE)
484 pdbgpriv->dbg_fw_mem_dl_error_cnt++;
485 if (1)
486 RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
487 return rst;
488 }
489 #endif
490
491 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
rtw_hal_clear_interrupt(_adapter * padapter)492 void rtw_hal_clear_interrupt(_adapter *padapter)
493 {
494 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
495 padapter->hal_func.clear_interrupt(padapter);
496 #endif
497 }
498 #endif
499
500 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
rtw_hal_inirp_init(_adapter * padapter)501 u32 rtw_hal_inirp_init(_adapter *padapter)
502 {
503 if (is_primary_adapter(padapter))
504 return padapter->hal_func.inirp_init(padapter);
505 return _SUCCESS;
506 }
rtw_hal_inirp_deinit(_adapter * padapter)507 u32 rtw_hal_inirp_deinit(_adapter *padapter)
508 {
509
510 if (is_primary_adapter(padapter))
511 return padapter->hal_func.inirp_deinit(padapter);
512
513 return _SUCCESS;
514 }
515 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
516
517 #if defined(CONFIG_PCI_HCI)
rtw_hal_irp_reset(_adapter * padapter)518 void rtw_hal_irp_reset(_adapter *padapter)
519 {
520 padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
521 }
522
rtw_hal_pci_dbi_write(_adapter * padapter,u16 addr,u8 data)523 void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
524 {
525 u16 cmd[2];
526
527 cmd[0] = addr;
528 cmd[1] = data;
529
530 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
531 }
532
rtw_hal_pci_dbi_read(_adapter * padapter,u16 addr)533 u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
534 {
535 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
536
537 return (u8)addr;
538 }
539
rtw_hal_pci_mdio_write(_adapter * padapter,u8 addr,u16 data)540 void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
541 {
542 u16 cmd[2];
543
544 cmd[0] = (u16)addr;
545 cmd[1] = data;
546
547 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
548 }
549
rtw_hal_pci_mdio_read(_adapter * padapter,u8 addr)550 u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
551 {
552 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
553
554 return (u8)addr;
555 }
556
rtw_hal_pci_l1off_nic_support(_adapter * padapter)557 u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
558 {
559 u8 l1off;
560
561 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
562 return l1off;
563 }
564
rtw_hal_pci_l1off_capability(_adapter * padapter)565 u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
566 {
567 u8 l1off;
568
569 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
570 return l1off;
571 }
572
573
574 #endif /* #if defined(CONFIG_PCI_HCI) */
575
576 /* for USB Auto-suspend */
rtw_hal_intf_ps_func(_adapter * padapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)577 u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
578 {
579 if (padapter->hal_func.interface_ps_func)
580 return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
581 return _FAIL;
582 }
583
rtw_hal_xmitframe_enqueue(_adapter * padapter,struct xmit_frame * pxmitframe)584 s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
585 {
586 return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
587 }
588
rtw_hal_xmit(_adapter * padapter,struct xmit_frame * pxmitframe)589 s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
590 {
591 return padapter->hal_func.hal_xmit(padapter, pxmitframe);
592 }
593
594 /*
595 * [IMPORTANT] This function would be run in interrupt context.
596 */
rtw_hal_mgnt_xmit(_adapter * padapter,struct xmit_frame * pmgntframe)597 s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
598 {
599 s32 ret = _FAIL;
600
601 update_mgntframe_attrib_addr(padapter, pmgntframe);
602
603 #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
604 if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
605 #ifdef CONFIG_RTW_MESH
606 || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
607 #endif
608 )
609 rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
610 #endif
611
612 ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
613 return ret;
614 }
615
rtw_hal_init_xmit_priv(_adapter * padapter)616 s32 rtw_hal_init_xmit_priv(_adapter *padapter)
617 {
618 return padapter->hal_func.init_xmit_priv(padapter);
619 }
rtw_hal_free_xmit_priv(_adapter * padapter)620 void rtw_hal_free_xmit_priv(_adapter *padapter)
621 {
622 padapter->hal_func.free_xmit_priv(padapter);
623 }
624
rtw_hal_init_recv_priv(_adapter * padapter)625 s32 rtw_hal_init_recv_priv(_adapter *padapter)
626 {
627 return padapter->hal_func.init_recv_priv(padapter);
628 }
rtw_hal_free_recv_priv(_adapter * padapter)629 void rtw_hal_free_recv_priv(_adapter *padapter)
630 {
631 padapter->hal_func.free_recv_priv(padapter);
632 }
633
rtw_sta_ra_registed(_adapter * padapter,struct sta_info * psta)634 void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
635 {
636 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
637 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
638
639 if (psta == NULL) {
640 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
641 rtw_warn_on(1);
642 return;
643 }
644
645 #ifdef CONFIG_AP_MODE
646 if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
647 if (psta->cmn.aid > padapter->stapriv.max_aid) {
648 RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
649 rtw_warn_on(1);
650 return;
651 }
652 rtw_ap_update_sta_ra_info(padapter, psta);
653 }
654 #endif
655
656 psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
657 /*set correct initial date rate for each mac_id */
658 hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
659
660 rtw_phydm_ra_registed(padapter, psta);
661 }
662
rtw_hal_update_ra_mask(struct sta_info * psta)663 void rtw_hal_update_ra_mask(struct sta_info *psta)
664 {
665 _adapter *padapter;
666
667 if (!psta)
668 return;
669
670 padapter = psta->padapter;
671 rtw_sta_ra_registed(padapter, psta);
672 }
673
674 /* Start specifical interface thread */
rtw_hal_start_thread(_adapter * padapter)675 void rtw_hal_start_thread(_adapter *padapter)
676 {
677 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
678 #ifndef CONFIG_SDIO_TX_TASKLET
679 padapter->hal_func.run_thread(padapter);
680 #endif
681 #endif
682 }
683 /* Start specifical interface thread */
rtw_hal_stop_thread(_adapter * padapter)684 void rtw_hal_stop_thread(_adapter *padapter)
685 {
686 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
687 #ifndef CONFIG_SDIO_TX_TASKLET
688
689 padapter->hal_func.cancel_thread(padapter);
690
691 #endif
692 #endif
693 }
694
rtw_hal_read_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask)695 u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
696 {
697 u32 data = 0;
698 if (padapter->hal_func.read_bbreg)
699 data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
700 return data;
701 }
rtw_hal_write_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)702 void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
703 {
704 if (padapter->hal_func.write_bbreg)
705 padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
706 }
707
rtw_hal_read_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)708 u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
709 {
710 u32 data = 0;
711
712 if (padapter->hal_func.read_rfreg) {
713 data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
714
715 #ifdef DBG_IO
716 if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
717 RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
718 , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
719 }
720 #endif
721 }
722
723 return data;
724 }
725
rtw_hal_write_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)726 void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
727 {
728 if (padapter->hal_func.write_rfreg) {
729
730 #ifdef DBG_IO
731 if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
732 RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
733 , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
734 }
735 #endif
736
737 padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
738
739 #ifdef CONFIG_PCI_HCI
740 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
741 rtw_udelay_os(2);
742 #endif
743 }
744 }
745
746 #ifdef CONFIG_SYSON_INDIRECT_ACCESS
rtw_hal_read_syson_reg(PADAPTER padapter,u32 RegAddr,u32 BitMask)747 u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
748 {
749 u32 data = 0;
750 if (padapter->hal_func.read_syson_reg)
751 data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
752
753 return data;
754 }
755
rtw_hal_write_syson_reg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)756 void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
757 {
758 if (padapter->hal_func.write_syson_reg)
759 padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
760 }
761 #endif
762
763 #if defined(CONFIG_PCI_HCI)
rtw_hal_interrupt_handler(_adapter * padapter)764 s32 rtw_hal_interrupt_handler(_adapter *padapter)
765 {
766 s32 ret = _FAIL;
767 ret = padapter->hal_func.interrupt_handler(padapter);
768 return ret;
769 }
770
rtw_hal_unmap_beacon_icf(_adapter * padapter)771 void rtw_hal_unmap_beacon_icf(_adapter *padapter)
772 {
773 padapter->hal_func.unmap_beacon_icf(padapter);
774 }
775 #endif
776 #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
rtw_hal_interrupt_handler(_adapter * padapter,u16 pkt_len,u8 * pbuf)777 void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
778 {
779 padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
780 }
781 #endif
782
rtw_hal_set_chnl_bw(_adapter * padapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)783 void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
784 {
785 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
786 u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
787 u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
788 u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
789 u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
790
791 if (rtw_phydm_is_iqk_in_progress(padapter))
792 RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
793
794 #ifdef CONFIG_MP_INCLUDED
795 /* MP mode channel don't use secondary channel */
796 if (rtw_mp_mode_check(padapter) == _FALSE)
797 #endif
798 {
799 #if 0
800 if (cch_160 != 0)
801 cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
802 #endif
803 if (cch_80 != 0)
804 cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
805 if (cch_40 != 0)
806 cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
807 }
808
809 pHalData->cch_80 = cch_80;
810 pHalData->cch_40 = cch_40;
811 pHalData->cch_20 = cch_20;
812
813 if (0)
814 RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
815 , channel, ch_width_str(Bandwidth), Offset40, Offset80
816 , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
817
818 padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
819 }
820
rtw_hal_dm_watchdog(_adapter * padapter)821 void rtw_hal_dm_watchdog(_adapter *padapter)
822 {
823
824 rtw_hal_turbo_edca(padapter);
825 padapter->hal_func.hal_dm_watchdog(padapter);
826
827 #ifdef CONFIG_PCI_DYNAMIC_ASPM
828 rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);
829 #endif
830 }
831
832 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_hal_dm_watchdog_in_lps(_adapter * padapter)833 void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
834 {
835 #if defined(CONFIG_CONCURRENT_MODE)
836 #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
837 if (padapter->hw_port != HW_PORT0)
838 return;
839 #endif
840 #endif
841
842 if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
843 rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
844 }
845 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
846
rtw_hal_bcn_related_reg_setting(_adapter * padapter)847 void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
848 {
849 padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
850 }
851
852 #ifdef CONFIG_HOSTAPD_MLME
rtw_hal_hostap_mgnt_xmit_entry(_adapter * padapter,_pkt * pkt)853 s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
854 {
855 if (padapter->hal_func.hostap_mgnt_xmit_entry)
856 return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
857 return _FAIL;
858 }
859 #endif /* CONFIG_HOSTAPD_MLME */
860
861 #ifdef DBG_CONFIG_ERROR_DETECT
rtw_hal_sreset_init(_adapter * padapter)862 void rtw_hal_sreset_init(_adapter *padapter)
863 {
864 padapter->hal_func.sreset_init_value(padapter);
865 }
rtw_hal_sreset_reset(_adapter * padapter)866 void rtw_hal_sreset_reset(_adapter *padapter)
867 {
868 padapter = GET_PRIMARY_ADAPTER(padapter);
869 padapter->hal_func.silentreset(padapter);
870 }
871
rtw_hal_sreset_reset_value(_adapter * padapter)872 void rtw_hal_sreset_reset_value(_adapter *padapter)
873 {
874 padapter->hal_func.sreset_reset_value(padapter);
875 }
876
rtw_hal_sreset_xmit_status_check(_adapter * padapter)877 void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
878 {
879 padapter->hal_func.sreset_xmit_status_check(padapter);
880 }
rtw_hal_sreset_linked_status_check(_adapter * padapter)881 void rtw_hal_sreset_linked_status_check(_adapter *padapter)
882 {
883 padapter->hal_func.sreset_linked_status_check(padapter);
884 }
rtw_hal_sreset_get_wifi_status(_adapter * padapter)885 u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
886 {
887 return padapter->hal_func.sreset_get_wifi_status(padapter);
888 }
889
rtw_hal_sreset_inprogress(_adapter * padapter)890 bool rtw_hal_sreset_inprogress(_adapter *padapter)
891 {
892 padapter = GET_PRIMARY_ADAPTER(padapter);
893 return padapter->hal_func.sreset_inprogress(padapter);
894 }
895 #endif /* DBG_CONFIG_ERROR_DETECT */
896
897 #ifdef CONFIG_IOL
rtw_hal_iol_cmd(ADAPTER * adapter,struct xmit_frame * xmit_frame,u32 max_waiting_ms,u32 bndy_cnt)898 int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
899 {
900 if (adapter->hal_func.IOL_exec_cmds_sync)
901 return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
902 return _FAIL;
903 }
904 #endif
905
906 #ifdef CONFIG_XMIT_THREAD_MODE
rtw_hal_xmit_thread_handler(_adapter * padapter)907 s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
908 {
909 return padapter->hal_func.xmit_thread_handler(padapter);
910 }
911 #endif
912
913 #ifdef CONFIG_RECV_THREAD_MODE
rtw_hal_recv_hdl(_adapter * adapter)914 s32 rtw_hal_recv_hdl(_adapter *adapter)
915 {
916 return adapter->hal_func.recv_hdl(adapter);
917 }
918 #endif
919
rtw_hal_notch_filter(_adapter * adapter,bool enable)920 void rtw_hal_notch_filter(_adapter *adapter, bool enable)
921 {
922 if (adapter->hal_func.hal_notch_filter)
923 adapter->hal_func.hal_notch_filter(adapter, enable);
924 }
925
926 #ifdef CONFIG_FW_C2H_REG
rtw_hal_c2h_valid(_adapter * adapter,u8 * buf)927 inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
928 {
929 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
930 HAL_VERSION *hal_ver = &HalData->version_id;
931 bool ret = _FAIL;
932
933 ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
934
935 return ret;
936 }
937
rtw_hal_c2h_evt_read(_adapter * adapter,u8 * buf)938 inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
939 {
940 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
941 HAL_VERSION *hal_ver = &HalData->version_id;
942 s32 ret = _FAIL;
943
944 ret = c2h_evt_read_88xx(adapter, buf);
945
946 return ret;
947 }
948
rtw_hal_c2h_reg_hdr_parse(_adapter * adapter,u8 * buf,u8 * id,u8 * seq,u8 * plen,u8 ** payload)949 bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
950 {
951 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
952 HAL_VERSION *hal_ver = &HalData->version_id;
953 bool ret = _FAIL;
954
955 *id = C2H_ID_88XX(buf);
956 *seq = C2H_SEQ_88XX(buf);
957 *plen = C2H_PLEN_88XX(buf);
958 *payload = C2H_PAYLOAD_88XX(buf);
959 ret = _SUCCESS;
960
961 return ret;
962 }
963 #endif /* CONFIG_FW_C2H_REG */
964
965 #ifdef CONFIG_FW_C2H_PKT
rtw_hal_c2h_pkt_hdr_parse(_adapter * adapter,u8 * buf,u16 len,u8 * id,u8 * seq,u8 * plen,u8 ** payload)966 bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
967 {
968 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
969 HAL_VERSION *hal_ver = &HalData->version_id;
970 bool ret = _FAIL;
971
972 if (!buf || len > 256 || len < 3)
973 goto exit;
974
975 *id = C2H_ID_88XX(buf);
976 *seq = C2H_SEQ_88XX(buf);
977 *plen = len - 2;
978 *payload = C2H_PAYLOAD_88XX(buf);
979 ret = _SUCCESS;
980
981 exit:
982 return ret;
983 }
984 #endif /* CONFIG_FW_C2H_PKT */
985
986 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
987 #include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
988 #endif
c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)989 s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
990 {
991 u8 sub_id = 0;
992 s32 ret = _SUCCESS;
993
994 switch (id) {
995 case C2H_FW_SCAN_COMPLETE:
996 RTW_INFO("[C2H], FW Scan Complete\n");
997 break;
998
999 #ifdef CONFIG_BT_COEXIST
1000 case C2H_BT_INFO:
1001 rtw_btcoex_BtInfoNotify(adapter, plen, payload);
1002 break;
1003 case C2H_BT_MP_INFO:
1004 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1005 MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
1006 #endif
1007 rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
1008 break;
1009 case C2H_MAILBOX_STATUS:
1010 RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
1011 break;
1012 case C2H_WLAN_INFO:
1013 rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
1014 break;
1015 #endif /* CONFIG_BT_COEXIST */
1016
1017 case C2H_IQK_FINISH:
1018 c2h_iqk_offload(adapter, payload, plen);
1019 break;
1020
1021 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1022 case C2H_FW_CHNL_SWITCH_COMPLETE:
1023 rtw_tdls_chsw_oper_done(adapter);
1024 break;
1025 case C2H_BCN_EARLY_RPT:
1026 rtw_tdls_ch_sw_back_to_base_chnl(adapter);
1027 break;
1028 #endif
1029
1030 #ifdef CONFIG_MCC_MODE
1031 case C2H_MCC:
1032 rtw_hal_mcc_c2h_handler(adapter, plen, payload);
1033 break;
1034 #endif
1035
1036 #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
1037 case C2H_MAC_HIDDEN_RPT:
1038 c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
1039 break;
1040 case C2H_MAC_HIDDEN_RPT_2:
1041 c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
1042 break;
1043 #endif
1044
1045 case C2H_DEFEATURE_DBG:
1046 c2h_defeature_dbg_hdl(adapter, payload, plen);
1047 break;
1048
1049 #ifdef CONFIG_RTW_CUSTOMER_STR
1050 case C2H_CUSTOMER_STR_RPT:
1051 c2h_customer_str_rpt_hdl(adapter, payload, plen);
1052 break;
1053 case C2H_CUSTOMER_STR_RPT_2:
1054 c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
1055 break;
1056 #endif
1057 #ifdef RTW_PER_CMD_SUPPORT_FW
1058 case C2H_PER_RATE_RPT:
1059 c2h_per_rate_rpt_hdl(adapter, payload, plen);
1060 break;
1061 #endif
1062 case C2H_EXTEND:
1063 sub_id = payload[0];
1064 /* no handle, goto default */
1065
1066 default:
1067 if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
1068 ret = _FAIL;
1069 break;
1070 }
1071
1072 if (ret != _SUCCESS) {
1073 if (id == C2H_EXTEND)
1074 RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
1075 else
1076 RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
1077 }
1078
1079 return ret;
1080 }
1081
1082 #ifndef RTW_HALMAC
rtw_hal_c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1083 s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1084 {
1085 s32 ret = _FAIL;
1086
1087 ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
1088 if (ret != _SUCCESS)
1089 ret = c2h_handler(adapter, id, seq, plen, payload);
1090
1091 return ret;
1092 }
1093
rtw_hal_c2h_id_handle_directly(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1094 s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1095 {
1096 switch (id) {
1097 case C2H_CCX_TX_RPT:
1098 case C2H_BT_MP_INFO:
1099 case C2H_FW_CHNL_SWITCH_COMPLETE:
1100 case C2H_IQK_FINISH:
1101 case C2H_MCC:
1102 case C2H_BCN_EARLY_RPT:
1103 case C2H_AP_REQ_TXRPT:
1104 case C2H_SPC_STAT:
1105 return _TRUE;
1106 default:
1107 return _FALSE;
1108 }
1109 }
1110 #endif /* !RTW_HALMAC */
1111
rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)1112 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
1113 {
1114 return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
1115 }
1116
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1117 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1118 {
1119 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1120 u16 reg_sleep;
1121 u8 bit_shift;
1122 u32 val32;
1123 s32 ret = _FAIL;
1124
1125 if (macid >= macid_ctl->num) {
1126 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1127 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1128 goto exit;
1129 }
1130
1131 if (macid < 32) {
1132 reg_sleep = macid_ctl->reg_sleep_m0;
1133 bit_shift = macid;
1134 #if (MACID_NUM_SW_LIMIT > 32)
1135 } else if (macid < 64) {
1136 reg_sleep = macid_ctl->reg_sleep_m1;
1137 bit_shift = macid - 32;
1138 #endif
1139 #if (MACID_NUM_SW_LIMIT > 64)
1140 } else if (macid < 96) {
1141 reg_sleep = macid_ctl->reg_sleep_m2;
1142 bit_shift = macid - 64;
1143 #endif
1144 #if (MACID_NUM_SW_LIMIT > 96)
1145 } else if (macid < 128) {
1146 reg_sleep = macid_ctl->reg_sleep_m3;
1147 bit_shift = macid - 96;
1148 #endif
1149 } else {
1150 rtw_warn_on(1);
1151 goto exit;
1152 }
1153
1154 if (!reg_sleep) {
1155 rtw_warn_on(1);
1156 goto exit;
1157 }
1158
1159 val32 = rtw_read32(adapter, reg_sleep);
1160 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1161 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1162 , macid, reg_sleep, val32);
1163
1164 ret = _SUCCESS;
1165
1166 if (sleep) {
1167 if (val32 & BIT(bit_shift))
1168 goto exit;
1169 val32 |= BIT(bit_shift);
1170 } else {
1171 if (!(val32 & BIT(bit_shift)))
1172 goto exit;
1173 val32 &= ~BIT(bit_shift);
1174 }
1175
1176 rtw_write32(adapter, reg_sleep, val32);
1177
1178 exit:
1179 return ret;
1180 }
1181
rtw_hal_macid_sleep(_adapter * adapter,u8 macid)1182 inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
1183 {
1184 return _rtw_hal_macid_sleep(adapter, macid, 1);
1185 }
1186
rtw_hal_macid_wakeup(_adapter * adapter,u8 macid)1187 inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
1188 {
1189 return _rtw_hal_macid_sleep(adapter, macid, 0);
1190 }
1191
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1192 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1193 {
1194 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1195 u16 reg_sleep;
1196 u32 m;
1197 u8 mid = 0;
1198 u32 val32;
1199
1200 do {
1201 if (mid == 0) {
1202 m = bmp->m0;
1203 reg_sleep = macid_ctl->reg_sleep_m0;
1204 #if (MACID_NUM_SW_LIMIT > 32)
1205 } else if (mid == 1) {
1206 m = bmp->m1;
1207 reg_sleep = macid_ctl->reg_sleep_m1;
1208 #endif
1209 #if (MACID_NUM_SW_LIMIT > 64)
1210 } else if (mid == 2) {
1211 m = bmp->m2;
1212 reg_sleep = macid_ctl->reg_sleep_m2;
1213 #endif
1214 #if (MACID_NUM_SW_LIMIT > 96)
1215 } else if (mid == 3) {
1216 m = bmp->m3;
1217 reg_sleep = macid_ctl->reg_sleep_m3;
1218 #endif
1219 } else {
1220 rtw_warn_on(1);
1221 break;
1222 }
1223
1224 if (m == 0)
1225 goto move_next;
1226
1227 if (!reg_sleep) {
1228 rtw_warn_on(1);
1229 break;
1230 }
1231
1232 val32 = rtw_read32(adapter, reg_sleep);
1233 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1234 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1235 , mid, m, reg_sleep, val32);
1236
1237 if (sleep) {
1238 if ((val32 & m) == m)
1239 goto move_next;
1240 val32 |= m;
1241 } else {
1242 if ((val32 & m) == 0)
1243 goto move_next;
1244 val32 &= ~m;
1245 }
1246
1247 rtw_write32(adapter, reg_sleep, val32);
1248
1249 move_next:
1250 mid++;
1251 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1252
1253 return _SUCCESS;
1254 }
1255
rtw_hal_macid_sleep_all_used(_adapter * adapter)1256 inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
1257 {
1258 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1259
1260 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
1261 }
1262
rtw_hal_macid_wakeup_all_used(_adapter * adapter)1263 inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
1264 {
1265 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1266
1267 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
1268 }
1269
_rtw_hal_macid_drop(_adapter * adapter,u8 macid,u8 drop)1270 static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
1271 {
1272 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1273 #ifndef CONFIG_PROTSEL_MACSLEEP
1274 u16 reg_drop = 0;
1275 #else
1276 u16 reg_drop_info = macid_ctl->reg_drop_info;
1277 u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
1278 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1279 #endif /* CONFIG_PROTSEL_MACSLEEP */
1280 u8 bit_shift;
1281 u32 val32;
1282 s32 ret = _FAIL;
1283 /* some IC doesn't have this register */
1284 #ifndef REG_PKT_BUFF_ACCESS_CTRL
1285 #define REG_PKT_BUFF_ACCESS_CTRL 0
1286 #endif
1287
1288 if (macid >= macid_ctl->num) {
1289 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1290 , ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
1291 goto exit;
1292 }
1293
1294 if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
1295 if (macid < 32) {
1296 #ifndef CONFIG_PROTSEL_MACSLEEP
1297 reg_drop = macid_ctl->reg_drop_m0;
1298 #endif /* CONFIG_PROTSEL_MACSLEEP */
1299 bit_shift = macid;
1300 #if (MACID_NUM_SW_LIMIT > 32)
1301 } else if (macid < 64) {
1302 #ifndef CONFIG_PROTSEL_MACSLEEP
1303 reg_drop = macid_ctl->reg_drop_m1;
1304 #endif /* CONFIG_PROTSEL_MACSLEEP */
1305 bit_shift = macid - 32;
1306 #endif
1307 #if (MACID_NUM_SW_LIMIT > 64)
1308 } else if (macid < 96) {
1309 #ifndef CONFIG_PROTSEL_MACSLEEP
1310 reg_drop = macid_ctl->reg_drop_m2;
1311 #endif /* CONFIG_PROTSEL_MACSLEEP */
1312 bit_shift = macid - 64;
1313 #endif
1314 #if (MACID_NUM_SW_LIMIT > 96)
1315 } else if (macid < 128) {
1316 #ifndef CONFIG_PROTSEL_MACSLEEP
1317 reg_drop = macid_ctl->reg_drop_m3;
1318 #endif /* CONFIG_PROTSEL_MACSLEEP */
1319 bit_shift = macid - 96;
1320 #endif
1321 } else {
1322 rtw_warn_on(1);
1323 goto exit;
1324 }
1325
1326 #ifndef CONFIG_PROTSEL_MACSLEEP
1327 if (!reg_drop) {
1328 rtw_warn_on(1);
1329 goto exit;
1330 }
1331 val32 = rtw_read32(adapter, reg_drop);
1332 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
1333 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1334 , macid, reg_drop, val32);*/
1335 #else
1336 if (!reg_drop_ctrl || !reg_drop_info) {
1337 rtw_warn_on(1);
1338 goto exit;
1339 }
1340
1341 val32 = rtw_read32(adapter, reg_drop_ctrl);
1342 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1343 rtw_write32(adapter, reg_drop_ctrl, val32);
1344
1345 val32 = rtw_read32(adapter, reg_drop_info);
1346 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1347 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1348 , macid, reg_drop_info, val32);*/
1349 #endif /* CONFIG_PROTSEL_MACSLEEP */
1350 ret = _SUCCESS;
1351
1352 if (drop) {
1353 if (val32 & BIT(bit_shift))
1354 goto exit;
1355 val32 |= BIT(bit_shift);
1356 } else {
1357 if (!(val32 & BIT(bit_shift)))
1358 goto exit;
1359 val32 &= ~BIT(bit_shift);
1360 }
1361
1362 #ifndef CONFIG_PROTSEL_MACSLEEP
1363 rtw_write32(adapter, reg_drop, val32);
1364 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1365 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1366 , macid, reg_drop, val32);
1367 #else
1368 rtw_write32(adapter, reg_drop_info, val32);
1369 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1370 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1371 , macid, reg_drop_info, val32);
1372 #endif /* CONFIG_PROTSEL_MACSLEEP */
1373
1374
1375 } else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
1376 u16 start_addr = macid_ctl->macid_txrpt/8;
1377 u32 txrpt_h4b = 0;
1378 u8 i;
1379
1380 /* each address means 1 byte */
1381 start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
1382 /* select tx report buffer */
1383 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
1384 /* set tx report buffer start address for reading */
1385 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1386 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
1387 /* OFFSET5 BIT2 is BIT10 of high 4 bytes */
1388 if (drop) {
1389 if (txrpt_h4b & BIT(10))
1390 goto exit;
1391 txrpt_h4b |= BIT(10);
1392 } else {
1393 if (!(txrpt_h4b & BIT(10)))
1394 goto exit;
1395 txrpt_h4b &= ~BIT(10);
1396 }
1397 /* set to macid drop field */
1398 rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
1399 /* 0x20800000 only write BIT10 of tx report buf */
1400 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
1401 #if 0 /* some ICs doesn't clear the write done bit */
1402 /* checking TX queue status */
1403 for (i = 0 ; i < 50 ; i++) {
1404 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
1405 if (txrpt_h4b & BIT(23)) {
1406 RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
1407 rtw_mdelay_os(10);
1408 } else {
1409 RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
1410 break;
1411 }
1412 }
1413 #endif
1414 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1415 RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
1416 ,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
1417 } else {
1418 RTW_INFO("There is no definition for camctl cap , please correct it\n");
1419 }
1420 exit:
1421 return ret;
1422 }
1423
rtw_hal_macid_drop(_adapter * adapter,u8 macid)1424 inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
1425 {
1426 return _rtw_hal_macid_drop(adapter, macid, 1);
1427 }
1428
rtw_hal_macid_undrop(_adapter * adapter,u8 macid)1429 inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
1430 {
1431 return _rtw_hal_macid_drop(adapter, macid, 0);
1432 }
1433
rtw_hal_fill_h2c_cmd(PADAPTER padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)1434 s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
1435 {
1436 _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
1437
1438 if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
1439 return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
1440 else if (padapter->registrypriv.mp_mode == 0)
1441 RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
1442 , FUNC_ADPT_ARG(padapter), ElementID);
1443 return _FAIL;
1444 }
1445
rtw_hal_fill_fake_txdesc(_adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)1446 void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
1447 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
1448 {
1449 padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
1450
1451 }
1452
rtw_hal_get_txbuff_rsvd_page_num(_adapter * adapter,bool wowlan)1453 u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
1454 {
1455 u8 num = 0;
1456
1457
1458 if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1459 num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
1460 } else {
1461 #ifdef RTW_HALMAC
1462 num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
1463 #endif /* RTW_HALMAC */
1464 }
1465
1466 return num;
1467 }
1468
1469 #ifdef CONFIG_GPIO_API
rtw_hal_update_hisr_hsisr_ind(_adapter * padapter,u32 flag)1470 void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
1471 {
1472 if (padapter->hal_func.update_hisr_hsisr_ind)
1473 padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
1474 }
1475
rtw_hal_gpio_func_check(_adapter * padapter,u8 gpio_num)1476 int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
1477 {
1478 int ret = _SUCCESS;
1479
1480 if (padapter->hal_func.hal_gpio_func_check)
1481 ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
1482
1483 return ret;
1484 }
1485
rtw_hal_gpio_multi_func_reset(_adapter * padapter,u8 gpio_num)1486 void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
1487 {
1488 if (padapter->hal_func.hal_gpio_multi_func_reset)
1489 padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
1490 }
1491 #endif
1492
1493 #ifdef CONFIG_FW_CORRECT_BCN
rtw_hal_fw_correct_bcn(_adapter * padapter)1494 void rtw_hal_fw_correct_bcn(_adapter *padapter)
1495 {
1496 if (padapter->hal_func.fw_correct_bcn)
1497 padapter->hal_func.fw_correct_bcn(padapter);
1498 }
1499 #endif
1500
rtw_hal_set_tx_power_level(_adapter * adapter,u8 channel)1501 void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
1502 {
1503 adapter->hal_func.set_tx_power_level_handler(adapter, channel);
1504 rtw_hal_set_txpwr_done(adapter);
1505 }
1506
rtw_hal_set_txpwr_done(_adapter * adapter)1507 void rtw_hal_set_txpwr_done(_adapter *adapter)
1508 {
1509 if (adapter->hal_func.set_txpwr_done)
1510 adapter->hal_func.set_txpwr_done(adapter);
1511 }
1512
rtw_hal_set_tx_power_index(_adapter * adapter,u32 powerindex,enum rf_path rfpath,u8 rate)1513 void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
1514 , enum rf_path rfpath, u8 rate)
1515 {
1516 adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
1517 }
1518
rtw_hal_get_tx_power_index(_adapter * adapter,enum rf_path rfpath,u8 rate,u8 bandwidth,u8 channel,struct txpwr_idx_comp * tic)1519 u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath, u8 rate
1520 , u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
1521 {
1522 return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath, rate
1523 , bandwidth, channel, tic);
1524 }
1525
1526 #ifdef RTW_HALMAC
1527 /*
1528 * Description:
1529 * Initialize MAC registers
1530 *
1531 * Return:
1532 * _TRUE success
1533 * _FALSE fail
1534 */
rtw_hal_init_mac_register(PADAPTER adapter)1535 u8 rtw_hal_init_mac_register(PADAPTER adapter)
1536 {
1537 return adapter->hal_func.init_mac_register(adapter);
1538 }
1539
1540 /*
1541 * Description:
1542 * Initialize PHY(BB/RF) related functions
1543 *
1544 * Return:
1545 * _TRUE success
1546 * _FALSE fail
1547 */
rtw_hal_init_phy(PADAPTER adapter)1548 u8 rtw_hal_init_phy(PADAPTER adapter)
1549 {
1550 return adapter->hal_func.init_phy(adapter);
1551 }
1552 #endif /* RTW_HALMAC */
1553
1554 #ifdef CONFIG_RFKILL_POLL
rtw_hal_rfkill_poll(_adapter * adapter,u8 * valid)1555 bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
1556 {
1557 bool ret;
1558
1559 if (adapter->hal_func.hal_radio_onoff_check)
1560 ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
1561 else {
1562 *valid = 0;
1563 ret = _FALSE;
1564 }
1565 return ret;
1566 }
1567 #endif
1568
1569 #define rtw_hal_error_msg(ops_fun) \
1570 RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
1571
rtw_hal_ops_check(_adapter * padapter)1572 u8 rtw_hal_ops_check(_adapter *padapter)
1573 {
1574 u8 ret = _SUCCESS;
1575 #if 1
1576 /*** initialize section ***/
1577 if (NULL == padapter->hal_func.read_chip_version) {
1578 rtw_hal_error_msg("read_chip_version");
1579 ret = _FAIL;
1580 }
1581 if (NULL == padapter->hal_func.init_default_value) {
1582 rtw_hal_error_msg("init_default_value");
1583 ret = _FAIL;
1584 }
1585 if (NULL == padapter->hal_func.intf_chip_configure) {
1586 rtw_hal_error_msg("intf_chip_configure");
1587 ret = _FAIL;
1588 }
1589 if (NULL == padapter->hal_func.read_adapter_info) {
1590 rtw_hal_error_msg("read_adapter_info");
1591 ret = _FAIL;
1592 }
1593
1594 if (NULL == padapter->hal_func.hal_power_on) {
1595 rtw_hal_error_msg("hal_power_on");
1596 ret = _FAIL;
1597 }
1598 if (NULL == padapter->hal_func.hal_power_off) {
1599 rtw_hal_error_msg("hal_power_off");
1600 ret = _FAIL;
1601 }
1602
1603 if (NULL == padapter->hal_func.hal_init) {
1604 rtw_hal_error_msg("hal_init");
1605 ret = _FAIL;
1606 }
1607 if (NULL == padapter->hal_func.hal_deinit) {
1608 rtw_hal_error_msg("hal_deinit");
1609 ret = _FAIL;
1610 }
1611
1612 /*** xmit section ***/
1613 if (NULL == padapter->hal_func.init_xmit_priv) {
1614 rtw_hal_error_msg("init_xmit_priv");
1615 ret = _FAIL;
1616 }
1617 if (NULL == padapter->hal_func.free_xmit_priv) {
1618 rtw_hal_error_msg("free_xmit_priv");
1619 ret = _FAIL;
1620 }
1621 if (NULL == padapter->hal_func.hal_xmit) {
1622 rtw_hal_error_msg("hal_xmit");
1623 ret = _FAIL;
1624 }
1625 if (NULL == padapter->hal_func.mgnt_xmit) {
1626 rtw_hal_error_msg("mgnt_xmit");
1627 ret = _FAIL;
1628 }
1629 #ifdef CONFIG_XMIT_THREAD_MODE
1630 if (NULL == padapter->hal_func.xmit_thread_handler) {
1631 rtw_hal_error_msg("xmit_thread_handler");
1632 ret = _FAIL;
1633 }
1634 #endif
1635 if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
1636 rtw_hal_error_msg("hal_xmitframe_enqueue");
1637 ret = _FAIL;
1638 }
1639 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
1640 #ifndef CONFIG_SDIO_TX_TASKLET
1641 if (NULL == padapter->hal_func.run_thread) {
1642 rtw_hal_error_msg("run_thread");
1643 ret = _FAIL;
1644 }
1645 if (NULL == padapter->hal_func.cancel_thread) {
1646 rtw_hal_error_msg("cancel_thread");
1647 ret = _FAIL;
1648 }
1649 #endif
1650 #endif
1651
1652 /*** recv section ***/
1653 if (NULL == padapter->hal_func.init_recv_priv) {
1654 rtw_hal_error_msg("init_recv_priv");
1655 ret = _FAIL;
1656 }
1657 if (NULL == padapter->hal_func.free_recv_priv) {
1658 rtw_hal_error_msg("free_recv_priv");
1659 ret = _FAIL;
1660 }
1661 #ifdef CONFIG_RECV_THREAD_MODE
1662 if (NULL == padapter->hal_func.recv_hdl) {
1663 rtw_hal_error_msg("recv_hdl");
1664 ret = _FAIL;
1665 }
1666 #endif
1667 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
1668 if (NULL == padapter->hal_func.inirp_init) {
1669 rtw_hal_error_msg("inirp_init");
1670 ret = _FAIL;
1671 }
1672 if (NULL == padapter->hal_func.inirp_deinit) {
1673 rtw_hal_error_msg("inirp_deinit");
1674 ret = _FAIL;
1675 }
1676 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
1677
1678
1679 /*** interrupt hdl section ***/
1680 #if defined(CONFIG_PCI_HCI)
1681 if (NULL == padapter->hal_func.irp_reset) {
1682 rtw_hal_error_msg("irp_reset");
1683 ret = _FAIL;
1684 }
1685 #endif/*#if defined(CONFIG_PCI_HCI)*/
1686 #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
1687 if (NULL == padapter->hal_func.interrupt_handler) {
1688 rtw_hal_error_msg("interrupt_handler");
1689 ret = _FAIL;
1690 }
1691 #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
1692
1693 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
1694 if (NULL == padapter->hal_func.enable_interrupt) {
1695 rtw_hal_error_msg("enable_interrupt");
1696 ret = _FAIL;
1697 }
1698 if (NULL == padapter->hal_func.disable_interrupt) {
1699 rtw_hal_error_msg("disable_interrupt");
1700 ret = _FAIL;
1701 }
1702 #endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
1703
1704
1705 /*** DM section ***/
1706 if (NULL == padapter->hal_func.dm_init) {
1707 rtw_hal_error_msg("dm_init");
1708 ret = _FAIL;
1709 }
1710 if (NULL == padapter->hal_func.dm_deinit) {
1711 rtw_hal_error_msg("dm_deinit");
1712 ret = _FAIL;
1713 }
1714 if (NULL == padapter->hal_func.hal_dm_watchdog) {
1715 rtw_hal_error_msg("hal_dm_watchdog");
1716 ret = _FAIL;
1717 }
1718
1719 /*** xxx section ***/
1720 if (NULL == padapter->hal_func.set_chnl_bw_handler) {
1721 rtw_hal_error_msg("set_chnl_bw_handler");
1722 ret = _FAIL;
1723 }
1724
1725 if (NULL == padapter->hal_func.set_hw_reg_handler) {
1726 rtw_hal_error_msg("set_hw_reg_handler");
1727 ret = _FAIL;
1728 }
1729 if (NULL == padapter->hal_func.GetHwRegHandler) {
1730 rtw_hal_error_msg("GetHwRegHandler");
1731 ret = _FAIL;
1732 }
1733 if (NULL == padapter->hal_func.get_hal_def_var_handler) {
1734 rtw_hal_error_msg("get_hal_def_var_handler");
1735 ret = _FAIL;
1736 }
1737 if (NULL == padapter->hal_func.SetHalDefVarHandler) {
1738 rtw_hal_error_msg("SetHalDefVarHandler");
1739 ret = _FAIL;
1740 }
1741 if (NULL == padapter->hal_func.GetHalODMVarHandler) {
1742 rtw_hal_error_msg("GetHalODMVarHandler");
1743 ret = _FAIL;
1744 }
1745 if (NULL == padapter->hal_func.SetHalODMVarHandler) {
1746 rtw_hal_error_msg("SetHalODMVarHandler");
1747 ret = _FAIL;
1748 }
1749
1750 if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
1751 rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
1752 ret = _FAIL;
1753 }
1754
1755 if (NULL == padapter->hal_func.fill_h2c_cmd) {
1756 rtw_hal_error_msg("fill_h2c_cmd");
1757 ret = _FAIL;
1758 }
1759
1760 #ifdef RTW_HALMAC
1761 if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
1762 rtw_hal_error_msg("hal_mac_c2h_handler");
1763 ret = _FAIL;
1764 }
1765 #elif !defined(CONFIG_RTL8188E)
1766 if (NULL == padapter->hal_func.c2h_handler) {
1767 rtw_hal_error_msg("c2h_handler");
1768 ret = _FAIL;
1769 }
1770 #endif
1771
1772 #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1773 if (NULL == padapter->hal_func.fill_fake_txdesc) {
1774 rtw_hal_error_msg("fill_fake_txdesc");
1775 ret = _FAIL;
1776 }
1777 #endif
1778
1779 #ifndef RTW_HALMAC
1780 if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1781 rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
1782 ret = _FAIL;
1783 }
1784 #endif /* !RTW_HALMAC */
1785
1786 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1787 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
1788 if (NULL == padapter->hal_func.clear_interrupt) {
1789 rtw_hal_error_msg("clear_interrupt");
1790 ret = _FAIL;
1791 }
1792 #endif
1793 #endif /* CONFIG_WOWLAN */
1794
1795 if (NULL == padapter->hal_func.fw_dl) {
1796 rtw_hal_error_msg("fw_dl");
1797 ret = _FAIL;
1798 }
1799
1800 #ifdef CONFIG_FW_CORRECT_BCN
1801 if (IS_HARDWARE_TYPE_8814A(padapter)
1802 && NULL == padapter->hal_func.fw_correct_bcn) {
1803 rtw_hal_error_msg("fw_correct_bcn");
1804 ret = _FAIL;
1805 }
1806 #endif
1807
1808 if (!padapter->hal_func.set_tx_power_level_handler) {
1809 rtw_hal_error_msg("set_tx_power_level_handler");
1810 ret = _FAIL;
1811 }
1812 if (!padapter->hal_func.set_tx_power_index_handler) {
1813 rtw_hal_error_msg("set_tx_power_index_handler");
1814 ret = _FAIL;
1815 }
1816 if (!padapter->hal_func.get_tx_power_index_handler) {
1817 rtw_hal_error_msg("get_tx_power_index_handler");
1818 ret = _FAIL;
1819 }
1820
1821 /*** SReset section ***/
1822 #ifdef DBG_CONFIG_ERROR_DETECT
1823 if (NULL == padapter->hal_func.sreset_init_value) {
1824 rtw_hal_error_msg("sreset_init_value");
1825 ret = _FAIL;
1826 }
1827 if (NULL == padapter->hal_func.sreset_reset_value) {
1828 rtw_hal_error_msg("sreset_reset_value");
1829 ret = _FAIL;
1830 }
1831 if (NULL == padapter->hal_func.silentreset) {
1832 rtw_hal_error_msg("silentreset");
1833 ret = _FAIL;
1834 }
1835 if (NULL == padapter->hal_func.sreset_xmit_status_check) {
1836 rtw_hal_error_msg("sreset_xmit_status_check");
1837 ret = _FAIL;
1838 }
1839 if (NULL == padapter->hal_func.sreset_linked_status_check) {
1840 rtw_hal_error_msg("sreset_linked_status_check");
1841 ret = _FAIL;
1842 }
1843 if (NULL == padapter->hal_func.sreset_get_wifi_status) {
1844 rtw_hal_error_msg("sreset_get_wifi_status");
1845 ret = _FAIL;
1846 }
1847 if (NULL == padapter->hal_func.sreset_inprogress) {
1848 rtw_hal_error_msg("sreset_inprogress");
1849 ret = _FAIL;
1850 }
1851 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
1852
1853 #ifdef RTW_HALMAC
1854 if (NULL == padapter->hal_func.init_mac_register) {
1855 rtw_hal_error_msg("init_mac_register");
1856 ret = _FAIL;
1857 }
1858 if (NULL == padapter->hal_func.init_phy) {
1859 rtw_hal_error_msg("init_phy");
1860 ret = _FAIL;
1861 }
1862 #endif /* RTW_HALMAC */
1863
1864 #ifdef CONFIG_RFKILL_POLL
1865 if (padapter->hal_func.hal_radio_onoff_check == NULL) {
1866 rtw_hal_error_msg("hal_radio_onoff_check");
1867 ret = _FAIL;
1868 }
1869 #endif
1870 #endif
1871 return ret;
1872 }
1873