1 /* 2 * SiliconBackplane Chipcommon core hardware definitions. 3 * 4 * The chipcommon core provides chip identification, SB control, 5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, 6 * GPIO interface, extbus, and support for serial and parallel flashes. 7 * 8 * Copyright (C) 2020, Broadcom. 9 * 10 * Unless you and Broadcom execute a separate written software license 11 * agreement governing use of this software, this software is licensed to you 12 * under the terms of the GNU General Public License version 2 (the "GPL"), 13 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 14 * following added to such license: 15 * 16 * As a special exception, the copyright holders of this software give you 17 * permission to link this software with independent modules, and to copy and 18 * distribute the resulting executable under terms of your choice, provided that 19 * you also meet, for each linked independent module, the terms and conditions of 20 * the license of that module. An independent module is a module which is not 21 * derived from this software. The special exception does not apply to any 22 * modifications of the software. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Dual:>> 26 */ 27 28 #ifndef _SBCHIPC_H 29 #define _SBCHIPC_H 30 31 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 32 33 /* cpp contortions to concatenate w/arg prescan */ 34 #ifndef PAD 35 #define _PADLINE(line) pad ## line 36 #define _XSTR(line) _PADLINE(line) 37 #define PAD _XSTR(__LINE__) 38 #endif /* PAD */ 39 40 #define BCM_MASK32(msb, lsb) ((~0u >> (32u - (msb) - 1u)) & (~0u << (lsb))) 41 #include <bcmutils.h> 42 #ifdef WL_INITVALS 43 #include <wl_initvals.h> 44 #endif 45 46 /** 47 * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the 48 * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to 49 * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead 50 * be assigned their respective chipc-specific address space and connected to the Always On 51 * Backplane via the APB interface. 52 */ 53 typedef volatile struct { 54 uint32 PAD[384]; 55 uint32 pmucontrol; /* 0x600 */ 56 uint32 pmucapabilities; /* 0x604 */ 57 uint32 pmustatus; /* 0x608 */ 58 uint32 res_state; /* 0x60C */ 59 uint32 res_pending; /* 0x610 */ 60 uint32 pmutimer; /* 0x614 */ 61 uint32 min_res_mask; /* 0x618 */ 62 uint32 max_res_mask; /* 0x61C */ 63 uint32 res_table_sel; /* 0x620 */ 64 uint32 res_dep_mask; 65 uint32 res_updn_timer; 66 uint32 res_timer; 67 uint32 clkstretch; 68 uint32 pmuwatchdog; 69 uint32 gpiosel; /* 0x638, rev >= 1 */ 70 uint32 gpioenable; /* 0x63c, rev >= 1 */ 71 uint32 res_req_timer_sel; /* 0x640 */ 72 uint32 res_req_timer; /* 0x644 */ 73 uint32 res_req_mask; /* 0x648 */ 74 uint32 core_cap_ext; /* 0x64C */ 75 uint32 chipcontrol_addr; /* 0x650 */ 76 uint32 chipcontrol_data; /* 0x654 */ 77 uint32 regcontrol_addr; 78 uint32 regcontrol_data; 79 uint32 pllcontrol_addr; 80 uint32 pllcontrol_data; 81 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 82 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 83 uint32 retention_ctl; /* 0x670 */ 84 uint32 ILPPeriod; /* 0x674 */ 85 uint32 PAD[2]; 86 uint32 retention_grpidx; /* 0x680 */ 87 uint32 retention_grpctl; /* 0x684 */ 88 uint32 mac_res_req_timer; /* 0x688 */ 89 uint32 mac_res_req_mask; /* 0x68c */ 90 uint32 spm_ctrl; /* 0x690 */ 91 uint32 spm_cap; /* 0x694 */ 92 uint32 spm_clk_ctrl; /* 0x698 */ 93 uint32 int_hi_status; /* 0x69c */ 94 uint32 int_lo_status; /* 0x6a0 */ 95 uint32 mon_table_addr; /* 0x6a4 */ 96 uint32 mon_ctrl_n; /* 0x6a8 */ 97 uint32 mon_status_n; /* 0x6ac */ 98 uint32 int_treshold_n; /* 0x6b0 */ 99 uint32 watermarks_n; /* 0x6b4 */ 100 uint32 spm_debug; /* 0x6b8 */ 101 uint32 PAD[1]; 102 uint32 vtrim_ctrl; /* 0x6c0 */ 103 uint32 vtrim_status; /* 0x6c4 */ 104 uint32 usec_timer; /* 0x6c8 */ 105 uint32 usec_timer_frac; /* 0x6cc */ 106 uint32 pcie_tpower_on; /* 0x6d0 */ 107 uint32 pcie_tport_cnt; /* 0x6d4 */ 108 uint32 pmucontrol_ext; /* 0x6d8 */ 109 uint32 slowclkperiod; /* 0x6dc */ 110 uint32 pmu_statstimer_addr; /* 0x6e0 */ 111 uint32 pmu_statstimer_ctrl; /* 0x6e4 */ 112 uint32 pmu_statstimer_N; /* 0x6e8 */ 113 uint32 PAD[1]; 114 uint32 mac_res_req_timer1; /* 0x6f0 */ 115 uint32 mac_res_req_mask1; /* 0x6f4 */ 116 uint32 PAD[2]; 117 uint32 pmuintmask0; /* 0x700 */ 118 uint32 pmuintmask1; /* 0x704 */ 119 uint32 PAD[2]; 120 uint32 fis_start_min_res_mask; /* 0x710 */ 121 uint32 PAD[3]; 122 uint32 rsrc_event0; /* 0x720 */ 123 uint32 PAD[3]; 124 uint32 slowtimer2; /* 0x730 */ 125 uint32 slowtimerfrac2; /* 0x734 */ 126 uint32 mac_res_req_timer2; /* 0x738 */ 127 uint32 mac_res_req_mask2; /* 0x73c */ 128 uint32 pmuintstatus; /* 0x740 */ 129 uint32 extwakeupstatus; /* 0x744 */ 130 uint32 watchdog_res_mask; /* 0x748 */ 131 uint32 PAD[1]; /* 0x74C */ 132 uint32 swscratch; /* 0x750 */ 133 uint32 PAD[3]; /* 0x754-0x75C */ 134 uint32 extwakemask0; /* 0x760 */ 135 uint32 extwakemask1; /* 0x764 */ 136 uint32 PAD[2]; /* 0x768-0x76C */ 137 uint32 extwakereqmask[2]; /* 0x770-0x774 */ 138 uint32 PAD[2]; /* 0x778-0x77C */ 139 uint32 pmuintctrl0; /* 0x780 */ 140 uint32 pmuintctrl1; /* 0x784 */ 141 uint32 PAD[2]; 142 uint32 extwakectrl[2]; /* 0x790 */ 143 uint32 PAD[7]; 144 uint32 fis_ctrl_status; /* 0x7b4 */ 145 uint32 fis_min_res_mask; /* 0x7b8 */ 146 uint32 PAD[1]; 147 uint32 precision_tmr_ctrl_status; /* 0x7c0 */ 148 uint32 precision_tmr_capture_low; /* 0x7c4 */ 149 uint32 precision_tmr_capture_high; /* 0x7c8 */ 150 uint32 precision_tmr_capture_frac; /* 0x7cc */ 151 uint32 precision_tmr_running_low; /* 0x7d0 */ 152 uint32 precision_tmr_running_high; /* 0x7d4 */ 153 uint32 precision_tmr_running_frac; /* 0x7d8 */ 154 uint32 PAD[3]; 155 uint32 core_cap_ext1; /* 0x7e8 */ 156 uint32 PAD[5]; 157 uint32 rsrc_substate_ctl_sts; /* 0x800 */ 158 uint32 rsrc_substate_trans_tmr; /* 0x804 */ 159 uint32 PAD[2]; 160 uint32 dvfs_ctrl1; /* 0x810 */ 161 uint32 dvfs_ctrl2; /* 0x814 */ 162 uint32 dvfs_voltage; /* 0x818 */ 163 uint32 dvfs_status; /* 0x81c */ 164 uint32 dvfs_core_table_address; /* 0x820 */ 165 uint32 dvfs_core_ctrl; /* 0x824 */ 166 } pmuregs_t; 167 168 typedef struct eci_prerev35 { 169 uint32 eci_output; 170 uint32 eci_control; 171 uint32 eci_inputlo; 172 uint32 eci_inputmi; 173 uint32 eci_inputhi; 174 uint32 eci_inputintpolaritylo; 175 uint32 eci_inputintpolaritymi; 176 uint32 eci_inputintpolarityhi; 177 uint32 eci_intmasklo; 178 uint32 eci_intmaskmi; 179 uint32 eci_intmaskhi; 180 uint32 eci_eventlo; 181 uint32 eci_eventmi; 182 uint32 eci_eventhi; 183 uint32 eci_eventmasklo; 184 uint32 eci_eventmaskmi; 185 uint32 eci_eventmaskhi; 186 uint32 PAD[3]; 187 } eci_prerev35_t; 188 189 typedef struct eci_rev35 { 190 uint32 eci_outputlo; 191 uint32 eci_outputhi; 192 uint32 eci_controllo; 193 uint32 eci_controlhi; 194 uint32 eci_inputlo; 195 uint32 eci_inputhi; 196 uint32 eci_inputintpolaritylo; 197 uint32 eci_inputintpolarityhi; 198 uint32 eci_intmasklo; 199 uint32 eci_intmaskhi; 200 uint32 eci_eventlo; 201 uint32 eci_eventhi; 202 uint32 eci_eventmasklo; 203 uint32 eci_eventmaskhi; 204 uint32 eci_auxtx; 205 uint32 eci_auxrx; 206 uint32 eci_datatag; 207 uint32 eci_uartescvalue; 208 uint32 eci_autobaudctr; 209 uint32 eci_uartfifolevel; 210 } eci_rev35_t; 211 212 typedef struct flash_config { 213 uint32 PAD[19]; 214 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ 215 uint32 flashstrconfig; 216 } flash_config_t; 217 218 typedef volatile struct { 219 uint32 chipid; /* 0x0 */ 220 uint32 capabilities; 221 uint32 corecontrol; /* corerev >= 1 */ 222 uint32 bist; 223 224 /* OTP */ 225 uint32 otpstatus; /* 0x10, corerev >= 10 */ 226 uint32 otpcontrol; 227 uint32 otpprog; 228 uint32 otplayout; /* corerev >= 23 */ 229 230 /* Interrupt control */ 231 uint32 intstatus; /* 0x20 */ 232 uint32 intmask; 233 234 /* Chip specific regs */ 235 uint32 chipcontrol; /* 0x28, rev >= 11 */ 236 uint32 chipstatus; /* 0x2c, rev >= 11 */ 237 238 /* Jtag Master */ 239 uint32 jtagcmd; /* 0x30, rev >= 10 */ 240 uint32 jtagir; 241 uint32 jtagdr; 242 uint32 jtagctrl; 243 244 /* serial flash interface registers */ 245 uint32 flashcontrol; /* 0x40 */ 246 uint32 flashaddress; 247 uint32 flashdata; 248 uint32 otplayoutextension; /* rev >= 35 */ 249 250 /* Silicon backplane configuration broadcast control */ 251 uint32 broadcastaddress; /* 0x50 */ 252 uint32 broadcastdata; 253 254 /* gpio - cleared only by power-on-reset */ 255 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 256 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 257 uint32 gpioin; /* 0x60 */ 258 uint32 gpioout; /* 0x64 */ 259 uint32 gpioouten; /* 0x68 */ 260 uint32 gpiocontrol; /* 0x6C */ 261 uint32 gpiointpolarity; /* 0x70 */ 262 uint32 gpiointmask; /* 0x74 */ 263 264 /* GPIO events corerev >= 11 */ 265 uint32 gpioevent; 266 uint32 gpioeventintmask; 267 268 /* Watchdog timer */ 269 uint32 watchdog; /* 0x80 */ 270 271 /* GPIO events corerev >= 11 */ 272 uint32 gpioeventintpolarity; 273 274 /* GPIO based LED powersave regs corerev >= 16 */ 275 uint32 gpiotimerval; /* 0x88 */ /* Obsolete and unused now */ 276 uint32 gpiotimeroutmask; /* Obsolete and unused now */ 277 278 /* clock control */ 279 uint32 clockcontrol_n; /* 0x90 */ 280 uint32 clockcontrol_sb; /* aka m0 */ 281 uint32 clockcontrol_pci; /* aka m1 */ 282 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 283 uint32 clockcontrol_m3; /* cpu */ 284 uint32 clkdiv; /* corerev >= 3 */ 285 uint32 gpiodebugsel; /* corerev >= 28 */ 286 uint32 capabilities_ext; /* 0xac */ 287 288 /* pll delay registers (corerev >= 4) */ 289 uint32 pll_on_delay; /* 0xb0 */ 290 uint32 fref_sel_delay; 291 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 292 uint32 PAD; 293 294 /* Instaclock registers (corerev >= 10) */ 295 uint32 system_clk_ctl; /* 0xc0 */ 296 uint32 clkstatestretch; 297 uint32 PAD[2]; 298 299 /* Indirect backplane access (corerev >= 22) */ 300 uint32 bp_addrlow; /* 0xd0 */ 301 uint32 bp_addrhigh; 302 uint32 bp_data; 303 uint32 PAD; 304 uint32 bp_indaccess; 305 /* SPI registers, corerev >= 37 */ 306 uint32 gsioctrl; 307 uint32 gsioaddress; 308 uint32 gsiodata; 309 310 /* More clock dividers (corerev >= 32) */ 311 uint32 clkdiv2; 312 /* FAB ID (corerev >= 40) */ 313 uint32 otpcontrol1; 314 uint32 fabid; /* 0xf8 */ 315 316 /* In AI chips, pointer to erom */ 317 uint32 eromptr; /* 0xfc */ 318 319 /* ExtBus control registers (corerev >= 3) */ 320 uint32 pcmcia_config; /* 0x100 */ 321 uint32 pcmcia_memwait; 322 uint32 pcmcia_attrwait; 323 uint32 pcmcia_iowait; 324 uint32 ide_config; 325 uint32 ide_memwait; 326 uint32 ide_attrwait; 327 uint32 ide_iowait; 328 uint32 prog_config; 329 uint32 prog_waitcount; 330 uint32 flash_config; 331 uint32 flash_waitcount; 332 uint32 SECI_config; /* 0x130 SECI configuration */ 333 uint32 SECI_status; 334 uint32 SECI_statusmask; 335 uint32 SECI_rxnibchanged; 336 337 #if !defined(BCMDONGLEHOST) 338 union { /* 0x140 */ 339 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ 340 struct eci_prerev35 lt35; 341 struct eci_rev35 ge35; 342 /* Other interfaces */ 343 struct flash_config flashconf; 344 uint32 PAD[20]; 345 } eci; 346 #else 347 uint32 PAD[20]; 348 #endif /* !defined(BCMDONGLEHOST) */ 349 350 /* SROM interface (corerev >= 32) */ 351 uint32 sromcontrol; /* 0x190 */ 352 uint32 sromaddress; 353 uint32 sromdata; 354 uint32 PAD[1]; /* 0x19C */ 355 /* NAND flash registers for BCM4706 (corerev = 31) */ 356 uint32 nflashctrl; /* 0x1a0 */ 357 uint32 nflashconf; 358 uint32 nflashcoladdr; 359 uint32 nflashrowaddr; 360 uint32 nflashdata; 361 uint32 nflashwaitcnt0; /* 0x1b4 */ 362 uint32 PAD[2]; 363 364 uint32 seci_uart_data; /* 0x1C0 */ 365 uint32 seci_uart_bauddiv; 366 uint32 seci_uart_fcr; 367 uint32 seci_uart_lcr; 368 uint32 seci_uart_mcr; 369 uint32 seci_uart_lsr; 370 uint32 seci_uart_msr; 371 uint32 seci_uart_baudadj; 372 /* Clock control and hardware workarounds (corerev >= 20) */ 373 uint32 clk_ctl_st; /* 0x1e0 */ 374 uint32 hw_war; 375 uint32 powerctl; /* 0x1e8 */ 376 uint32 powerctl2; /* 0x1ec */ 377 uint32 PAD[68]; 378 379 /* UARTs */ 380 uint8 uart0data; /* 0x300 */ 381 uint8 uart0imr; 382 uint8 uart0fcr; 383 uint8 uart0lcr; 384 uint8 uart0mcr; 385 uint8 uart0lsr; 386 uint8 uart0msr; 387 uint8 uart0scratch; 388 uint8 PAD[184]; /* corerev >= 65 */ 389 uint32 rng_ctrl_0; /* 0x3c0 */ 390 uint32 rng_rng_soft_reset; /* 0x3c4 */ 391 uint32 rng_rbg_soft_reset; /* 0x3c8 */ 392 uint32 rng_total_bit_cnt; /* 0x3cc */ 393 uint32 rng_total_bit_thrshld; /* 0x3d0 */ 394 uint32 rng_rev_id; /* 0x3d4 */ 395 uint32 rng_int_status_0; /* 0x3d8 */ 396 uint32 rng_int_enable_0; /* 0x3dc */ 397 uint32 rng_fifo_data; /* 0x3e0 */ 398 uint32 rng_fifo_cnt; /* 0x3e4 */ 399 uint8 PAD[24]; /* corerev >= 65 */ 400 401 uint8 uart1data; /* 0x400 */ 402 uint8 uart1imr; 403 uint8 uart1fcr; 404 uint8 uart1lcr; 405 uint8 uart1mcr; 406 uint8 uart1lsr; 407 uint8 uart1msr; 408 uint8 uart1scratch; /* 0x407 */ 409 uint32 PAD[50]; 410 uint32 sr_memrw_addr; /* 0x4d0 */ 411 uint32 sr_memrw_data; /* 0x4d4 */ 412 uint32 etbmemctrl; /* 0x4d8 */ 413 uint32 PAD[9]; 414 415 /* save/restore, corerev >= 48 */ 416 uint32 sr_capability; /* 0x500 */ 417 uint32 sr_control0; /* 0x504 */ 418 uint32 sr_control1; /* 0x508 */ 419 uint32 gpio_control; /* 0x50C */ 420 uint32 PAD[29]; 421 /* 2 SR engines case */ 422 uint32 sr1_control0; /* 0x584 */ 423 uint32 sr1_control1; /* 0x588 */ 424 uint32 PAD[29]; 425 /* PMU registers (corerev >= 20) */ 426 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP. 427 * The CPU must read them twice, compare, and retry if different. 428 */ 429 uint32 pmucontrol; /* 0x600 */ 430 uint32 pmucapabilities; 431 uint32 pmustatus; 432 uint32 res_state; 433 uint32 res_pending; 434 uint32 pmutimer; 435 uint32 min_res_mask; 436 uint32 max_res_mask; 437 uint32 res_table_sel; 438 uint32 res_dep_mask; 439 uint32 res_updn_timer; 440 uint32 res_timer; 441 uint32 clkstretch; 442 uint32 pmuwatchdog; 443 uint32 gpiosel; /* 0x638, rev >= 1 */ 444 uint32 gpioenable; /* 0x63c, rev >= 1 */ 445 uint32 res_req_timer_sel; 446 uint32 res_req_timer; 447 uint32 res_req_mask; 448 uint32 core_cap_ext; /* 0x64c */ 449 uint32 chipcontrol_addr; /* 0x650 */ 450 uint32 chipcontrol_data; /* 0x654 */ 451 uint32 regcontrol_addr; 452 uint32 regcontrol_data; 453 uint32 pllcontrol_addr; 454 uint32 pllcontrol_data; 455 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 456 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 457 uint32 retention_ctl; /* 0x670 */ 458 uint32 ILPPeriod; /* 0x674 */ 459 uint32 PAD[2]; 460 uint32 retention_grpidx; /* 0x680 */ 461 uint32 retention_grpctl; /* 0x684 */ 462 uint32 mac_res_req_timer; /* 0x688 */ 463 uint32 mac_res_req_mask; /* 0x68c */ 464 uint32 PAD[18]; 465 uint32 pmucontrol_ext; /* 0x6d8 */ 466 uint32 slowclkperiod; /* 0x6dc */ 467 uint32 pmu_statstimer_addr; /* 0x6e0 */ 468 uint32 pmu_statstimer_ctrl; /* 0x6e4 */ 469 uint32 pmu_statstimer_N; /* 0x6e8 */ 470 uint32 PAD[1]; 471 uint32 mac_res_req_timer1; /* 0x6f0 */ 472 uint32 mac_res_req_mask1; /* 0x6f4 */ 473 uint32 PAD[2]; 474 uint32 pmuintmask0; /* 0x700 */ 475 uint32 pmuintmask1; /* 0x704 */ 476 uint32 PAD[14]; 477 uint32 pmuintstatus; /* 0x740 */ 478 uint32 extwakeupstatus; /* 0x744 */ 479 uint32 PAD[6]; 480 uint32 extwakemask0; /* 0x760 */ 481 uint32 extwakemask1; /* 0x764 */ 482 uint32 PAD[2]; /* 0x768-0x76C */ 483 uint32 extwakereqmask[2]; /* 0x770-0x774 */ 484 uint32 PAD[2]; /* 0x778-0x77C */ 485 uint32 pmuintctrl0; /* 0x780 */ 486 uint32 PAD[3]; /* 0x784 - 0x78c */ 487 uint32 extwakectrl[1]; /* 0x790 */ 488 uint32 PAD[PADSZ(0x794u, 0x7b0u)]; /* 0x794 - 0x7b0 */ 489 uint32 fis_ctrl_status; /* 0x7b4 */ 490 uint32 fis_min_res_mask; /* 0x7b8 */ 491 uint32 PAD[PADSZ(0x7bcu, 0x7bcu)]; /* 0x7bc */ 492 uint32 precision_tmr_ctrl_status; /* 0x7c0 */ 493 uint32 precision_tmr_capture_low; /* 0x7c4 */ 494 uint32 precision_tmr_capture_high; /* 0x7c8 */ 495 uint32 precision_tmr_capture_frac; /* 0x7cc */ 496 uint32 precision_tmr_running_low; /* 0x7d0 */ 497 uint32 precision_tmr_running_high; /* 0x7d4 */ 498 uint32 precision_tmr_running_frac; /* 0x7d8 */ 499 uint32 PAD[PADSZ(0x7dcu, 0x7e4u)]; /* 0x7dc - 0x7e4 */ 500 uint32 core_cap_ext1; /* 0x7e8 */ 501 uint32 PAD[PADSZ(0x7ecu, 0x7fcu)]; /* 0x7ec - 0x7fc */ 502 503 uint16 sromotp[512]; /* 0x800 */ 504 #ifdef CCNFLASH_SUPPORT 505 /* Nand flash MLC controller registers (corerev >= 38) */ 506 uint32 nand_revision; /* 0xC00 */ 507 uint32 nand_cmd_start; 508 uint32 nand_cmd_addr_x; 509 uint32 nand_cmd_addr; 510 uint32 nand_cmd_end_addr; 511 uint32 nand_cs_nand_select; 512 uint32 nand_cs_nand_xor; 513 uint32 PAD; 514 uint32 nand_spare_rd0; 515 uint32 nand_spare_rd4; 516 uint32 nand_spare_rd8; 517 uint32 nand_spare_rd12; 518 uint32 nand_spare_wr0; 519 uint32 nand_spare_wr4; 520 uint32 nand_spare_wr8; 521 uint32 nand_spare_wr12; 522 uint32 nand_acc_control; 523 uint32 PAD; 524 uint32 nand_config; 525 uint32 PAD; 526 uint32 nand_timing_1; 527 uint32 nand_timing_2; 528 uint32 nand_semaphore; 529 uint32 PAD; 530 uint32 nand_devid; 531 uint32 nand_devid_x; 532 uint32 nand_block_lock_status; 533 uint32 nand_intfc_status; 534 uint32 nand_ecc_corr_addr_x; 535 uint32 nand_ecc_corr_addr; 536 uint32 nand_ecc_unc_addr_x; 537 uint32 nand_ecc_unc_addr; 538 uint32 nand_read_error_count; 539 uint32 nand_corr_stat_threshold; 540 uint32 PAD[2]; 541 uint32 nand_read_addr_x; 542 uint32 nand_read_addr; 543 uint32 nand_page_program_addr_x; 544 uint32 nand_page_program_addr; 545 uint32 nand_copy_back_addr_x; 546 uint32 nand_copy_back_addr; 547 uint32 nand_block_erase_addr_x; 548 uint32 nand_block_erase_addr; 549 uint32 nand_inv_read_addr_x; 550 uint32 nand_inv_read_addr; 551 uint32 PAD[2]; 552 uint32 nand_blk_wr_protect; 553 uint32 PAD[3]; 554 uint32 nand_acc_control_cs1; 555 uint32 nand_config_cs1; 556 uint32 nand_timing_1_cs1; 557 uint32 nand_timing_2_cs1; 558 uint32 PAD[20]; 559 uint32 nand_spare_rd16; 560 uint32 nand_spare_rd20; 561 uint32 nand_spare_rd24; 562 uint32 nand_spare_rd28; 563 uint32 nand_cache_addr; 564 uint32 nand_cache_data; 565 uint32 nand_ctrl_config; 566 uint32 nand_ctrl_status; 567 #endif /* CCNFLASH_SUPPORT */ 568 /* Note: there is a clash between GCI and NFLASH. So, 569 * we decided to have it like below. the functions accessing following 570 * have to be protected with NFLASH_SUPPORT. The functions will 571 * assert in case the clash happens. 572 */ 573 uint32 gci_corecaps0; /* GCI starting at 0xC00 */ 574 uint32 gci_corecaps1; 575 uint32 gci_corecaps2; 576 uint32 gci_corectrl; 577 uint32 gci_corestat; /* 0xC10 */ 578 uint32 gci_intstat; /* 0xC14 */ 579 uint32 gci_intmask; /* 0xC18 */ 580 uint32 gci_wakemask; /* 0xC1C */ 581 uint32 gci_levelintstat; /* 0xC20 */ 582 uint32 gci_eventintstat; /* 0xC24 */ 583 uint32 PAD[6]; 584 uint32 gci_indirect_addr; /* 0xC40 */ 585 uint32 gci_gpioctl; /* 0xC44 */ 586 uint32 gci_gpiostatus; 587 uint32 gci_gpiomask; /* 0xC4C */ 588 uint32 gci_eventsummary; /* 0xC50 */ 589 uint32 gci_miscctl; /* 0xC54 */ 590 uint32 gci_gpiointmask; 591 uint32 gci_gpiowakemask; 592 uint32 gci_input[32]; /* C60 */ 593 uint32 gci_event[32]; /* CE0 */ 594 uint32 gci_output[4]; /* D60 */ 595 uint32 gci_control_0; /* 0xD70 */ 596 uint32 gci_control_1; /* 0xD74 */ 597 uint32 gci_intpolreg; /* 0xD78 */ 598 uint32 gci_levelintmask; /* 0xD7C */ 599 uint32 gci_eventintmask; /* 0xD80 */ 600 uint32 PAD[3]; 601 uint32 gci_inbandlevelintmask; /* 0xD90 */ 602 uint32 gci_inbandeventintmask; /* 0xD94 */ 603 uint32 PAD[2]; 604 uint32 gci_seciauxtx; /* 0xDA0 */ 605 uint32 gci_seciauxrx; /* 0xDA4 */ 606 uint32 gci_secitx_datatag; /* 0xDA8 */ 607 uint32 gci_secirx_datatag; /* 0xDAC */ 608 uint32 gci_secitx_datamask; /* 0xDB0 */ 609 uint32 gci_seciusef0tx_reg; /* 0xDB4 */ 610 uint32 gci_secif0tx_offset; /* 0xDB8 */ 611 uint32 gci_secif0rx_offset; /* 0xDBC */ 612 uint32 gci_secif1tx_offset; /* 0xDC0 */ 613 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */ 614 uint32 gci_rxfifoctrl; /* 0xDC8 */ 615 uint32 gci_uartreadid; /* DCC */ 616 uint32 gci_seciuartescval; /* DD0 */ 617 uint32 PAD; 618 uint32 gci_secififolevel; /* DD8 */ 619 uint32 gci_seciuartdata; /* DDC */ 620 uint32 gci_secibauddiv; /* DE0 */ 621 uint32 gci_secifcr; /* DE4 */ 622 uint32 gci_secilcr; /* DE8 */ 623 uint32 gci_secimcr; /* DEC */ 624 uint32 gci_secilsr; /* DF0 */ 625 uint32 gci_secimsr; /* DF4 */ 626 uint32 gci_baudadj; /* DF8 */ 627 uint32 PAD; 628 uint32 gci_chipctrl; /* 0xE00 */ 629 uint32 gci_chipsts; /* 0xE04 */ 630 uint32 gci_gpioout; /* 0xE08 */ 631 uint32 gci_gpioout_read; /* 0xE0C */ 632 uint32 gci_mpwaketx; /* 0xE10 */ 633 uint32 gci_mpwakedetect; /* 0xE14 */ 634 uint32 gci_seciin_ctrl; /* 0xE18 */ 635 uint32 gci_seciout_ctrl; /* 0xE1C */ 636 uint32 gci_seciin_auxfifo_en; /* 0xE20 */ 637 uint32 gci_seciout_txen_txbr; /* 0xE24 */ 638 uint32 gci_seciin_rxbrstatus; /* 0xE28 */ 639 uint32 gci_seciin_rxerrstatus; /* 0xE2C */ 640 uint32 gci_seciin_fcstatus; /* 0xE30 */ 641 uint32 gci_seciout_txstatus; /* 0xE34 */ 642 uint32 gci_seciout_txbrstatus; /* 0xE38 */ 643 644 } chipcregs_t; 645 646 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 647 648 #if !defined(IL_BIGENDIAN) 649 #define CC_CHIPID 0 650 #define CC_CAPABILITIES 4 651 #define CC_CHIPST 0x2c 652 #define CC_EROMPTR 0xfc 653 #endif /* IL_BIGENDIAN */ 654 655 #define CC_OTPST 0x10 656 #define CC_INTSTATUS 0x20 657 #define CC_INTMASK 0x24 658 #define CC_JTAGCMD 0x30 659 #define CC_JTAGIR 0x34 660 #define CC_JTAGDR 0x38 661 #define CC_JTAGCTRL 0x3c 662 #define CC_GPIOPU 0x58 663 #define CC_GPIOPD 0x5c 664 #define CC_GPIOIN 0x60 665 #define CC_GPIOOUT 0x64 666 #define CC_GPIOOUTEN 0x68 667 #define CC_GPIOCTRL 0x6c 668 #define CC_GPIOPOL 0x70 669 #define CC_GPIOINTM 0x74 670 #define CC_GPIOEVENT 0x78 671 #define CC_GPIOEVENTMASK 0x7c 672 #define CC_WATCHDOG 0x80 673 #define CC_GPIOEVENTPOL 0x84 674 #define CC_CLKC_N 0x90 675 #define CC_CLKC_M0 0x94 676 #define CC_CLKC_M1 0x98 677 #define CC_CLKC_M2 0x9c 678 #define CC_CLKC_M3 0xa0 679 #define CC_CLKDIV 0xa4 680 #define CC_CAP_EXT 0xac 681 #define CC_SYS_CLK_CTL 0xc0 682 #define CC_BP_ADRLOW 0xd0 683 #define CC_BP_ADRHI 0xd4 684 #define CC_BP_DATA 0xd8 685 #define CC_SCR_DHD_TO_BL CC_BP_ADRHI 686 #define CC_SCR_BL_TO_DHD CC_BP_ADRLOW 687 #define CC_CLKDIV2 0xf0 688 #define CC_CLK_CTL_ST SI_CLK_CTL_ST 689 #define PMU_CTL 0x600 690 #define PMU_CAP 0x604 691 #define PMU_ST 0x608 692 #define PMU_RES_STATE 0x60c 693 #define PMU_RES_PENDING 0x610 694 #define PMU_TIMER 0x614 695 #define PMU_MIN_RES_MASK 0x618 696 #define PMU_MAX_RES_MASK 0x61c 697 #define CC_CHIPCTL_ADDR 0x650 698 #define CC_CHIPCTL_DATA 0x654 699 #define PMU_REG_CONTROL_ADDR 0x658 700 #define PMU_REG_CONTROL_DATA 0x65C 701 #define PMU_PLL_CONTROL_ADDR 0x660 702 #define PMU_PLL_CONTROL_DATA 0x664 703 #define PMU_RSRC_CONTROL_MASK 0x7B0 704 705 #define CC_SROM_CTRL 0x190 706 #define CC_SROM_ADDRESS 0x194u 707 #define CC_SROM_DATA 0x198u 708 #define CC_SROM_OTP 0x0800 709 #define CC_GCI_INDIRECT_ADDR_REG 0xC40 710 #define CC_GCI_CHIP_CTRL_REG 0xE00 711 #define CC_GCI_CC_OFFSET_2 2 712 #define CC_GCI_CC_OFFSET_5 5 713 #define CC_SWD_CTRL 0x380 714 #define CC_SWD_REQACK 0x384 715 #define CC_SWD_DATA 0x388 716 #define GPIO_SEL_0 0x00001111 717 #define GPIO_SEL_1 0x11110000 718 #define GPIO_SEL_8 0x00001111 719 #define GPIO_SEL_9 0x11110000 720 721 #define CHIPCTRLREG0 0x0 722 #define CHIPCTRLREG1 0x1 723 #define CHIPCTRLREG2 0x2 724 #define CHIPCTRLREG3 0x3 725 #define CHIPCTRLREG4 0x4 726 #define CHIPCTRLREG5 0x5 727 #define CHIPCTRLREG6 0x6 728 #define CHIPCTRLREG13 0xd 729 #define CHIPCTRLREG16 0x10 730 #define REGCTRLREG4 0x4 731 #define REGCTRLREG5 0x5 732 #define REGCTRLREG6 0x6 733 #define MINRESMASKREG 0x618 734 #define MAXRESMASKREG 0x61c 735 #define CHIPCTRLADDR 0x650 736 #define CHIPCTRLDATA 0x654 737 #define RSRCTABLEADDR 0x620 738 #define PMU_RES_DEP_MASK 0x624 739 #define RSRCUPDWNTIME 0x628 740 #define PMUREG_RESREQ_MASK 0x68c 741 #define PMUREG_RESREQ_TIMER 0x688 742 #define PMUREG_RESREQ_MASK1 0x6f4 743 #define PMUREG_RESREQ_TIMER1 0x6f0 744 #define EXT_LPO_AVAIL 0x100 745 #define LPO_SEL (1 << 0) 746 #define CC_EXT_LPO_PU 0x200000 747 #define GC_EXT_LPO_PU 0x2 748 #define CC_INT_LPO_PU 0x100000 749 #define GC_INT_LPO_PU 0x1 750 #define EXT_LPO_SEL 0x8 751 #define INT_LPO_SEL 0x4 752 #define ENABLE_FINE_CBUCK_CTRL (1 << 30) 753 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000 754 #define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17 755 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000 756 #define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16 757 #define CC_BP_IND_ACCESS_START_SHIFT 9 758 #define CC_BP_IND_ACCESS_START_MASK (1 << CC_BP_IND_ACCESS_START_SHIFT) 759 #define CC_BP_IND_ACCESS_RDWR_SHIFT 8 760 #define CC_BP_IND_ACCESS_RDWR_MASK (1 << CC_BP_IND_ACCESS_RDWR_SHIFT) 761 #define CC_BP_IND_ACCESS_ERROR_SHIFT 10 762 #define CC_BP_IND_ACCESS_ERROR_MASK (1 << CC_BP_IND_ACCESS_ERROR_SHIFT) 763 #define GC_BT_CTRL_UARTPADS_OVRD_EN (1u << 1) 764 765 #define LPO_SEL_TIMEOUT 1000 766 767 #define LPO_FINAL_SEL_SHIFT 18 768 769 #define LHL_LPO1_SEL 0 770 #define LHL_LPO2_SEL 0x1 771 #define LHL_32k_SEL 0x2 772 #define LHL_EXT_SEL 0x3 773 774 #define EXTLPO_BUF_PD 0x40 775 #define LPO1_PD_EN 0x1 776 #define LPO1_PD_SEL 0x6 777 #define LPO1_PD_SEL_VAL 0x4 778 #define LPO2_PD_EN 0x8 779 #define LPO2_PD_SEL 0x30 780 #define LPO2_PD_SEL_VAL 0x20 781 #define OSC_32k_PD 0x80 782 783 #define LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL 0x3 784 785 #define LHL_LPO_AUTO 0x0 786 #define LHL_LPO1_ENAB 0x1 787 #define LHL_LPO2_ENAB 0x2 788 #define LHL_OSC_32k_ENAB 0x3 789 #define LHL_EXT_LPO_ENAB 0x4 790 #define RADIO_LPO_ENAB 0x5 791 792 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN 0x4 793 #define LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR 0x8 794 #define LHL_CLK_DET_CNT 0xF0 795 #define LHL_CLK_DET_CNT_SHIFT 4 796 #define LPO_SEL_SHIFT 9 797 798 #define LHL_MAIN_CTL_ADR_FINAL_CLK_SEL 0x3C0000 799 #define LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL 0x600 800 801 #define CLK_DET_CNT_THRESH 8 802 803 #ifdef SR_DEBUG 804 #define SUBCORE_POWER_ON 0x0001 805 #define PHY_POWER_ON 0x0010 806 #define VDDM_POWER_ON 0x0100 807 #define MEMLPLDO_POWER_ON 0x1000 808 #define SUBCORE_POWER_ON_CHK 0x00040000 809 #define PHY_POWER_ON_CHK 0x00080000 810 #define VDDM_POWER_ON_CHK 0x00100000 811 #define MEMLPLDO_POWER_ON_CHK 0x00200000 812 #endif /* SR_DEBUG */ 813 814 #ifdef CCNFLASH_SUPPORT 815 /* NAND flash support */ 816 #define CC_NAND_REVISION 0xC00 817 #define CC_NAND_CMD_START 0xC04 818 #define CC_NAND_CMD_ADDR 0xC0C 819 #define CC_NAND_SPARE_RD_0 0xC20 820 #define CC_NAND_SPARE_RD_4 0xC24 821 #define CC_NAND_SPARE_RD_8 0xC28 822 #define CC_NAND_SPARE_RD_C 0xC2C 823 #define CC_NAND_CONFIG 0xC48 824 #define CC_NAND_DEVID 0xC60 825 #define CC_NAND_DEVID_EXT 0xC64 826 #define CC_NAND_INTFC_STATUS 0xC6C 827 #endif /* CCNFLASH_SUPPORT */ 828 829 /* chipid */ 830 #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */ 831 #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */ 832 #define CID_REV_SHIFT 16 /**< Chip Revision shift */ 833 #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */ 834 #define CID_PKG_SHIFT 20 /**< Package Option shift */ 835 #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */ 836 #define CID_CC_SHIFT 24 837 #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */ 838 #define CID_TYPE_SHIFT 28 839 840 /* capabilities */ 841 #define CC_CAP_UARTS_MASK 0x00000003u /**< Number of UARTs */ 842 #define CC_CAP_MIPSEB 0x00000004u /**< MIPS is in big-endian mode */ 843 #define CC_CAP_UCLKSEL 0x00000018u /**< UARTs clock select */ 844 #define CC_CAP_UINTCLK 0x00000008u /**< UARTs are driven by internal divided clock */ 845 #define CC_CAP_UARTGPIO 0x00000020u /**< UARTs own GPIOs 15:12 */ 846 #define CC_CAP_EXTBUS_MASK 0x000000c0u /**< External bus mask */ 847 #define CC_CAP_EXTBUS_NONE 0x00000000u /**< No ExtBus present */ 848 #define CC_CAP_EXTBUS_FULL 0x00000040u /**< ExtBus: PCMCIA, IDE & Prog */ 849 #define CC_CAP_EXTBUS_PROG 0x00000080u /**< ExtBus: ProgIf only */ 850 #define CC_CAP_FLASH_MASK 0x00000700u /**< Type of flash */ 851 #define CC_CAP_PLL_MASK 0x00038000u /**< Type of PLL */ 852 #define CC_CAP_PWR_CTL 0x00040000u /**< Power control */ 853 #define CC_CAP_OTPSIZE 0x00380000u /**< OTP Size (0 = none) */ 854 #define CC_CAP_OTPSIZE_SHIFT 19 /**< OTP Size shift */ 855 #define CC_CAP_OTPSIZE_BASE 5 /**< OTP Size base */ 856 #define CC_CAP_JTAGP 0x00400000u /**< JTAG Master Present */ 857 #define CC_CAP_ROM 0x00800000u /**< Internal boot rom active */ 858 #define CC_CAP_BKPLN64 0x08000000u /**< 64-bit backplane */ 859 #define CC_CAP_PMU 0x10000000u /**< PMU Present, rev >= 20 */ 860 #define CC_CAP_ECI 0x20000000u /**< ECI Present, rev >= 21 */ 861 #define CC_CAP_SROM 0x40000000u /**< Srom Present, rev >= 32 */ 862 #define CC_CAP_NFLASH 0x80000000u /**< Nand flash present, rev >= 35 */ 863 864 #define CC_CAP2_SECI 0x00000001u /**< SECI Present, rev >= 36 */ 865 #define CC_CAP2_GSIO 0x00000002u /**< GSIO (spi/i2c) present, rev >= 37 */ 866 867 /* capabilities extension */ 868 #define CC_CAP_EXT_SECI_PRESENT 0x00000001u /**< SECI present */ 869 #define CC_CAP_EXT_GSIO_PRESENT 0x00000002u /**< GSIO present */ 870 #define CC_CAP_EXT_GCI_PRESENT 0x00000004u /**< GCI present */ 871 #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008u /**< UART present */ 872 #define CC_CAP_EXT_AOB_PRESENT 0x00000040u /**< AOB present */ 873 #define CC_CAP_EXT_SWD_PRESENT 0x00000400u /**< SWD present */ 874 #define CC_CAP_SR_AON_PRESENT 0x0001E000u /**< SWD present */ 875 #define CC_CAP_EXT1_DVFS_PRESENT 0x00001000u /**< DVFS present */ 876 877 /* DVFS core count */ 878 #define CC_CAP_EXT1_CORE_CNT_SHIFT (7u) 879 #define CC_CAP_EXT1_CORE_CNT_MASK ((0x1Fu) << CC_CAP_EXT1_CORE_CNT_SHIFT) 880 881 /* SpmCtrl (Chipcommon Offset 0x690) 882 * Bits 27:16 AlpDiv 883 * Clock divider control for dividing ALP or TCK clock 884 * (bit 8 determines ALP vs TCK) 885 * Bits 8 UseDivTck 886 * See UseDivAlp (bit 1) for more details 887 * Bits 7:6 DebugMuxSel 888 * Controls the debug mux for SpmDebug register 889 * Bits 5 IntPending 890 * This field is set to 1 when any of the bits in IntHiStatus or IntLoStatus 891 * is set. It is automatically cleared after reading and clearing the 892 * IntHiStatus and IntLoStatus registers. This bit is Read only. 893 * Bits 4 SpmIdle 894 * Indicates whether the spm controller is running (SpmIdle=0) or in idle 895 * state (SpmIdle=1); Note that after setting Spmen=1 (or 0), it takes a 896 * few clock cycles (ILP or divided ALP) for SpmIdle to go to 0 (or 1). 897 * This bit is Read only. 898 * Bits 3 RoDisOutput 899 * Debug register - gate off all the SPM ring oscillator clock outputs 900 * Bits 2 RstSpm 901 * Reset spm controller. 902 * Put spm in reset before changing UseDivAlp and AlpDiv 903 * Bits 1 UseDivAlp 904 * This field, along with UseDivTck, selects the clock as the reference clock 905 * Bits [UseDivTck,UseDivAlp]: 906 * 00 - Use ILP clock as reference clock 907 * 01 - Use divided ALP clock 908 * 10 - Use divided jtag TCK 909 * Bits 0 Spmen 910 * 0 - SPM disabled 911 * 1 - SPM enabled 912 * Program all the SPM controls before enabling spm. For one-shot operation, 913 * SpmIdle indicates when the one-shot run has completed. After one-shot 914 * completion, spmen needs to be disabled first before enabling again. 915 */ 916 #define SPMCTRL_ALPDIV_FUNC 0x1ffu 917 #define SPMCTRL_ALPDIV_RO 0xfffu 918 #define SPMCTRL_ALPDIV_SHIFT 16u 919 #define SPMCTRL_ALPDIV_MASK (0xfffu << SPMCTRL_ALPDIV_SHIFT) 920 #define SPMCTRL_RSTSPM 0x1u 921 #define SPMCTRL_RSTSPM_SHIFT 2u 922 #define SPMCTRL_RSTSPM_MASK (0x1u << SPMCTRL_RSTSPM_SHIFT) 923 #define SPMCTRL_USEDIVALP 0x1u 924 #define SPMCTRL_USEDIVALP_SHIFT 1u 925 #define SPMCTRL_USEDIVALP_MASK (0x1u << SPMCTRL_USEDIVALP_SHIFT) 926 #define SPMCTRL_SPMEN 0x1u 927 #define SPMCTRL_SPMEN_SHIFT 0u 928 #define SPMCTRL_SPMEN_MASK (0x1u << SPMCTRL_SPMEN_SHIFT) 929 930 /* SpmClkCtrl (Chipcommon Offset 0x698) 931 * Bits 31 OneShot 932 * 0 means Take periodic measurements based on IntervalValue 933 * 1 means Take a one shot measurement 934 * when OneShot=1 IntervalValue determines the amount of time to wait before 935 * taking the measurement 936 * Bits 30:28 ROClkprediv1 937 * ROClkprediv1 and ROClkprediv2 controls the clock dividers of the RO clk 938 * before it goes to the monitor 939 * The RO clk goes through prediv1, followed by prediv2 940 * prediv1: 941 * 0 - no divide 942 * 1 - divide by 2 943 * 2 - divide by 4 944 * 3 - divide by 8 945 * 4 - divide by 16 946 * 5 - divide by 32 947 * prediv2: 948 * 0 - no divide 949 * 1 to 15 - divide by (prediv2+1) 950 */ 951 #define SPMCLKCTRL_SAMPLETIME 0x2u 952 #define SPMCLKCTRL_SAMPLETIME_SHIFT 24u 953 #define SPMCLKCTRL_SAMPLETIME_MASK (0xfu << SPMCLKCTRL_SAMPLETIME_SHIFT) 954 #define SPMCLKCTRL_ONESHOT 0x1u 955 #define SPMCLKCTRL_ONESHOT_SHIFT 31u 956 #define SPMCLKCTRL_ONESHOT_MASK (0x1u << SPMCLKCTRL_ONESHOT_SHIFT) 957 958 /* MonCtrlN (Chipcommon Offset 0x6a8) 959 * Bits 15:8 TargetRo 960 * The target ring oscillator to observe 961 * Bits 7:6 TargetRoExt 962 * Extended select option to choose the target clock to monitor; 963 * 00 - selects ring oscillator clock; 964 * 10 - selects functional clock; 965 * 11 - selects DFT clocks; 966 * Bits 15:8 (TargetRO) is used to select the specific RO or functional or 967 * DFT clock 968 * Bits 3 intHiEn 969 * Interrupt hi enable (MonEn should be 1) 970 * Bits 2 intLoEn 971 * Interrupt hi enable (MonEn should be 1) 972 * Bits 1 HwEnable 973 * TBD 974 * Bits 0 MonEn 975 * Enable monitor, interrupt and watermark functions 976 */ 977 #define MONCTRLN_TARGETRO_PMU_ALP_CLK 0u 978 #define MONCTRLN_TARGETRO_PCIE_ALP_CLK 1u 979 #define MONCTRLN_TARGETRO_CB_BP_CLK 2u 980 #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387B0 3u 981 #define MONCTRLN_TARGETRO_ARMCR4_CLK_4387C0 20u 982 #define MONCTRLN_TARGETRO_SHIFT 8u 983 #define MONCTRLN_TARGETRO_MASK (0xffu << MONCTRLN_TARGETRO_SHIFT) 984 #define MONCTRLN_TARGETROMAX 64u 985 #define MONCTRLN_TARGETROHI 32u 986 #define MONCTRLN_TARGETROEXT_RO 0x0u 987 #define MONCTRLN_TARGETROEXT_FUNC 0x2u 988 #define MONCTRLN_TARGETROEXT_DFT 0x3u 989 #define MONCTRLN_TARGETROEXT_SHIFT 6u 990 #define MONCTRLN_TARGETROEXT_MASK (0x3u << MONCTRLN_TARGETROEXT_SHIFT) 991 #define MONCTRLN_MONEN 0x1u 992 #define MONCTRLN_MONEN_SHIFT 0u 993 #define MONCTRLN_MONEN_MASK (0x1u << MONCTRLN_MONENEXT_SHIFT) 994 995 /* DvfsCoreCtrlN 996 * Bits 10 Request_override_PDn 997 * When set, the dvfs_request logic for this core is overridden with the 998 * content in Request_val_PDn. This field is ignored when 999 * DVFSCtrl1.dvfs_req_override is set. 1000 * Bits 9:8 Request_val_PDn 1001 * see Request_override_PDn description 1002 * Bits 4:0 DVFS_RsrcTrig_PDn 1003 * Specifies the pmu resource that is used to trigger the DVFS request for 1004 * this core request. Current plan is to use the appropriate PWRSW_* pmu 1005 * resource each power domain / cores 1006 */ 1007 #define CTRLN_REQUEST_OVERRIDE_SHIFT 10u 1008 #define CTRLN_REQUEST_OVERRIDE_MASK (0x1u << CTRLN_REQUEST_OVERRIDE_SHIFT) 1009 #define CTRLN_REQUEST_VAL_SHIFT 8u 1010 #define CTRLN_REQUEST_VAL_MASK (0x3u << CTRLN_REQUEST_VAL_SHIFT) 1011 #define CTRLN_RSRC_TRIG_SHIFT 0u 1012 #define CTRLN_RSRC_TRIG_MASK (0x1Fu << CTRLN_RSRC_TRIG_SHIFT) 1013 #define CTRLN_RSRC_TRIG_CHIPC 0x1Au 1014 #define CTRLN_RSRC_TRIG_PCIE 0x1Au 1015 #define CTRLN_RSRC_TRIG_ARM 0x8u 1016 #define CTRLN_RSRC_TRIG_D11_MAIN 0xEu 1017 #define CTRLN_RSRC_TRIG_D11_AUX 0xBu 1018 #define CTRLN_RSRC_TRIG_D11_SCAN 0xCu 1019 #define CTRLN_RSRC_TRIG_HWA 0x8u 1020 #define CTRLN_RSRC_TRIG_BT_MAIN 0x9u 1021 #define CTRLN_RSRC_TRIG_BT_SCAN 0xAu 1022 1023 /* DVFS core FW index */ 1024 #define DVFS_CORE_CHIPC 0u 1025 #define DVFS_CORE_PCIE 1u 1026 #define DVFS_CORE_ARM 2u 1027 #define DVFS_CORE_D11_MAIN 3u 1028 #define DVFS_CORE_D11_AUX 4u 1029 #define DVFS_CORE_D11_SCAN 5u 1030 #define DVFS_CORE_BT_MAIN 6u 1031 #define DVFS_CORE_BT_SCAN 7u 1032 #define DVFS_CORE_HWA 8u 1033 #define DVFS_CORE_SYSMEM ((PMUREV((sih)->pmurev) < 43u) ? \ 1034 9u : 8u) 1035 #define DVFS_CORE_MASK 0xFu 1036 1037 #define DVFS_CORE_INVALID_IDX 0xFFu 1038 1039 /* DVFS_Ctrl2 (PMU_BASE + 0x814) 1040 * Bits 31:28 Voltage ramp down step 1041 * Voltage increment amount during ramp down (10mv units) 1042 * Bits 27:24 Voltage ramp up step 1043 * Voltage increment amount during ramp up (10mv units) 1044 * Bits 23:16 Voltage ramp down interval 1045 * Number of clocks to wait during each voltage decrement 1046 * Bits 15:8 Voltage ramp up interval 1047 * Number of clocks to wait during each voltage increment 1048 * Bits 7:0 Clock stable time 1049 * Number of clocks to wait after dvfs_clk_sel is asserted 1050 */ 1051 #define DVFS_VOLTAGE_RAMP_DOWN_STEP 1u 1052 #define DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT 28u 1053 #define DVFS_VOLTAGE_RAMP_DOWN_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_DOWN_STEP_SHIFT) 1054 #define DVFS_VOLTAGE_RAMP_UP_STEP 1u 1055 #define DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT 24u 1056 #define DVFS_VOLTAGE_RAMP_UP_STEP_MASK (0xFu << DVFS_VOLTAGE_RAMP_UP_STEP_SHIFT) 1057 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL 1u 1058 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT 16u 1059 #define DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_DOWN_INTERVAL_SHIFT) 1060 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL 1u 1061 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT 8u 1062 #define DVFS_VOLTAGE_RAMP_UP_INTERVAL_MASK (0xFFu << DVFS_VOLTAGE_RAMP_UP_INTERVAL_SHIFT) 1063 #define DVFS_CLOCK_STABLE_TIME 3u 1064 #define DVFS_CLOCK_STABLE_TIME_SHIFT 0 1065 #define DVFS_CLOCK_STABLE_TIME_MASK (0xFFu << DVFS_CLOCK_STABLE_TIME_SHIFT) 1066 1067 /* DVFS_Voltage (PMU_BASE + 0x818) 1068 * Bits 22:16 HDV Voltage 1069 * Specifies the target HDV voltage in 10mv units 1070 * Bits 14:8 NDV Voltage 1071 * Specifies the target NDV voltage in 10mv units 1072 * Bits 6:0 LDV Voltage 1073 * Specifies the target LDV voltage in 10mv units 1074 */ 1075 #define DVFS_VOLTAGE_XDV 0u /* Reserved */ 1076 #ifdef WL_INITVALS 1077 #define DVFS_VOLTAGE_HDV (wliv_pmu_dvfs_voltage_hdv) /* 0.72V */ 1078 #define DVFS_VOLTAGE_HDV_MAX (wliv_pmu_dvfs_voltage_hdv_max) /* 0.80V */ 1079 #else 1080 #define DVFS_VOLTAGE_HDV 72u /* 0.72V */ 1081 #define DVFS_VOLTAGE_HDV_MAX 80u /* 0.80V */ 1082 #endif 1083 #define DVFS_VOLTAGE_HDV_PWR_OPT 68u /* 0.68V */ 1084 #define DVFS_VOLTAGE_HDV_SHIFT 16u 1085 #define DVFS_VOLTAGE_HDV_MASK (0x7Fu << DVFS_VOLTAGE_HDV_SHIFT) 1086 #ifdef WL_INITVALS 1087 #define DVFS_VOLTAGE_NDV (wliv_pmu_dvfs_voltage_ndv) /* 0.72V */ 1088 #define DVFS_VOLTAGE_NDV_NON_LVM (wliv_pmu_dvfs_voltage_ndv_non_lvm) /* 0.76V */ 1089 #define DVFS_VOLTAGE_NDV_MAX (wliv_pmu_dvfs_voltage_ndv_max) /* 0.80V */ 1090 #else 1091 #define DVFS_VOLTAGE_NDV 72u /* 0.72V */ 1092 #define DVFS_VOLTAGE_NDV_NON_LVM 76u /* 0.76V */ 1093 #define DVFS_VOLTAGE_NDV_MAX 80u /* 0.80V */ 1094 #endif 1095 #define DVFS_VOLTAGE_NDV_PWR_OPT 68u /* 0.68V */ 1096 #define DVFS_VOLTAGE_NDV_SHIFT 8u 1097 #define DVFS_VOLTAGE_NDV_MASK (0x7Fu << DVFS_VOLTAGE_NDV_SHIFT) 1098 #ifdef WL_INITVALS 1099 #define DVFS_VOLTAGE_LDV (wliv_pmu_dvfs_voltage_ldv) /* 0.65V */ 1100 #else 1101 #define DVFS_VOLTAGE_LDV 65u /* 0.65V */ 1102 #endif 1103 #define DVFS_VOLTAGE_LDV_PWR_OPT 65u /* 0.65V */ 1104 #define DVFS_VOLTAGE_LDV_SHIFT 0u 1105 #define DVFS_VOLTAGE_LDV_MASK (0x7Fu << DVFS_VOLTAGE_LDV_SHIFT) 1106 1107 /* DVFS_Status (PMU_BASE + 0x81C) 1108 * Bits 27:26 Raw_Core_Reqn 1109 * Bits 25:24 Active_Core_Reqn 1110 * Bits 12:11 Core_dvfs_status 1111 * Bits 9:8 Dvfs_clk_sel 1112 * 00 - LDV 1113 * 01 - NDV 1114 * Bits 6:0 Dvfs Voltage 1115 * The real time voltage that is being output from the dvfs controller 1116 */ 1117 #define DVFS_RAW_CORE_REQ_SHIFT 26u 1118 #define DVFS_RAW_CORE_REQ_MASK (0x3u << DVFS_RAW_CORE_REQ_SHIFT) 1119 #define DVFS_ACT_CORE_REQ_SHIFT 24u 1120 #define DVFS_ACT_CORE_REQ_MASK (0x3u << DVFS_ACT_CORE_REQ_SHIFT) 1121 #define DVFS_CORE_STATUS_SHIFT 11u 1122 #define DVFS_CORE_STATUS_MASK (0x3u << DVFS_CORE_STATUS_SHIFT) 1123 #define DVFS_CLK_SEL_SHIFT 8u 1124 #define DVFS_CLK_SEL_MASK (0x3u << DVFS_CLK_SEL_SHIFT) 1125 #define DVFS_VOLTAGE_SHIFT 0u 1126 #define DVFS_VOLTAGE_MASK (0x7Fu << DVFS_VOLTAGE_SHIFT) 1127 1128 /* DVFS_Ctrl1 (PMU_BASE + 0x810) 1129 * Bits 0 Enable DVFS 1130 * This bit will enable DVFS operation. When cleared, the complete DVFS 1131 * controller is bypassed and DVFS_voltage output will be the contents of 1132 * NDV voltage register 1133 */ 1134 #define DVFS_DISABLE_DVFS 0u 1135 #define DVFS_ENABLE_DVFS 1u 1136 #define DVFS_ENABLE_DVFS_SHIFT 0u 1137 #define DVFS_ENABLE_DVFS_MASK (1u << DVFS_ENABLE_DVFS_SHIFT) 1138 1139 #define DVFS_LPO_DELAY 40u /* usec (1 LPO clock + margin) */ 1140 #define DVFS_FASTLPO_DELAY 2u /* usec (1 FAST_LPO clock + margin) */ 1141 #define DVFS_NDV_LPO_DELAY 1500u 1142 #define DVFS_NDV_FASTLPO_DELAY 50u 1143 1144 #if defined(BCM_FASTLPO) && !defined(BCM_FASTLPO_DISABLED) 1145 #define DVFS_DELAY DVFS_FASTLPO_DELAY 1146 #define DVFS_NDV_DELAY DVFS_NDV_FASTLPO_DELAY 1147 #else 1148 #define DVFS_DELAY DVFS_LPO_DELAY 1149 #define DVFS_NDV_DELAY DVFS_NDV_LPO_DELAY 1150 #endif /* BCM_FASTLPO && !BCM_FASTLPO_DISABLED */ 1151 1152 #define DVFS_LDV 0u 1153 #define DVFS_NDV 1u 1154 #define DVFS_HDV 2u 1155 1156 /* PowerControl2 (Core Offset 0x1EC) 1157 * Bits 17:16 DVFSStatus 1158 * This 2-bit field is the DVFS voltage status mapped as 1159 * 00 - LDV 1160 * 01 - NDV 1161 * 10 - HDV 1162 * Bits 1:0 DVFSRequest 1163 * This 2-bit field is used to request DVFS voltage mapped as shown above 1164 */ 1165 #define DVFS_REQ_LDV DVFS_LDV 1166 #define DVFS_REQ_NDV DVFS_NDV 1167 #define DVFS_REQ_HDV DVFS_HDV 1168 #define DVFS_REQ_SHIFT 0u 1169 #define DVFS_REQ_MASK (0x3u << DVFS_REQ_SHIFT) 1170 #define DVFS_STATUS_SHIFT 16u 1171 #define DVFS_STATUS_MASK (0x3u << DVFS_STATUS_SHIFT) 1172 1173 /* GCI Chip Control 16 Register 1174 * Bits 0 CB Clock sel 1175 * 0 - 160MHz 1176 * 1 - 80Mhz - BT can force CB backplane clock to 80Mhz when wl is down 1177 */ 1178 #define GCI_CC16_CB_CLOCK_SEL_160 0u 1179 #define GCI_CC16_CB_CLOCK_SEL_80 1u 1180 #define GCI_CC16_CB_CLOCK_SEL_SHIFT 0u 1181 #define GCI_CC16_CB_CLOCK_SEL_MASK (0x1u << GCI_CC16_CB_CLOCK_SEL_SHIFT) 1182 #define GCI_CHIPCTRL_16_PRISEL_ANT_MASK_PSM_OVR (1 << 8) 1183 1184 /* WL Channel Info to BT via GCI - bits 40 - 47 */ 1185 #define GCI_WL_CHN_INFO_MASK (0xFF00) 1186 /* WL indication of MCHAN enabled/disabled to BT - bit 36 */ 1187 #define GCI_WL_MCHAN_BIT_MASK (0x0010) 1188 1189 #ifdef WLC_SW_DIVERSITY 1190 /* WL indication of SWDIV enabled/disabled to BT - bit 33 */ 1191 #define GCI_WL_SWDIV_ANT_VALID_BIT_MASK (0x0002) 1192 #define GCI_SWDIV_ANT_VALID_SHIFT 0x1 1193 #define GCI_SWDIV_ANT_VALID_DISABLE 0x0 1194 #endif 1195 1196 /* Indicate to BT that WL is scheduling ACL based ble scan grant */ 1197 #define GCI_WL2BT_ACL_BSD_BLE_SCAN_GRNT_MASK 0x8000000 1198 /* WLAN is awake Indicate to BT */ 1199 #define GCI_WL2BT_2G_AWAKE_MASK (1u << 28u) 1200 1201 /* WL inidcation of Aux Core 2G hibernate status - bit 50 */ 1202 #define GCI_WL2BT_2G_HIB_STATE_MASK (0x0040000u) 1203 1204 /* WL Traffic Indication to BT */ 1205 #define GCI_WL2BT_TRAFFIC_IND_SHIFT (12) 1206 #define GCI_WL2BT_TRAFFIC_IND_MASK (0x3 << GCI_WL2BT_TRAFFIC_IND_SHIFT) 1207 1208 /* WL Strobe to BT */ 1209 #define GCI_WL_STROBE_BIT_MASK (0x0020) 1210 /* bits [51:48] - reserved for wlan TX pwr index */ 1211 /* bits [55:52] btc mode indication */ 1212 #define GCI_WL_BTC_MODE_SHIFT (20) 1213 #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT) 1214 #define GCI_WL_ANT_BIT_MASK (0x00c0) 1215 #define GCI_WL_ANT_SHIFT_BITS (6) 1216 1217 /* bit [40] - to indicate RC2CX mode to BT */ 1218 #define GCI_WL_RC2CX_PERCTS_MASK 0x00000100u 1219 1220 /* PLL type */ 1221 #define PLL_NONE 0x00000000 1222 #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */ 1223 #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */ 1224 #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */ 1225 #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */ 1226 #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */ 1227 #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */ 1228 #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */ 1229 1230 /* ILP clock */ 1231 #define ILP_CLOCK 32000 1232 1233 /* ALP clock on pre-PMU chips */ 1234 #define ALP_CLOCK 20000000 1235 1236 #ifdef CFG_SIM 1237 #define NS_ALP_CLOCK 84922 1238 #define NS_SLOW_ALP_CLOCK 84922 1239 #define NS_CPU_CLOCK 534500 1240 #define NS_SLOW_CPU_CLOCK 534500 1241 #define NS_SI_CLOCK 271750 1242 #define NS_SLOW_SI_CLOCK 271750 1243 #define NS_FAST_MEM_CLOCK 271750 1244 #define NS_MEM_CLOCK 271750 1245 #define NS_SLOW_MEM_CLOCK 271750 1246 #else 1247 #define NS_ALP_CLOCK 125000000 1248 #define NS_SLOW_ALP_CLOCK 100000000 1249 #define NS_CPU_CLOCK 1000000000 1250 #define NS_SLOW_CPU_CLOCK 800000000 1251 #define NS_SI_CLOCK 250000000 1252 #define NS_SLOW_SI_CLOCK 200000000 1253 #define NS_FAST_MEM_CLOCK 800000000 1254 #define NS_MEM_CLOCK 533000000 1255 #define NS_SLOW_MEM_CLOCK 400000000 1256 #endif /* CFG_SIM */ 1257 1258 /* HT clock */ 1259 #define HT_CLOCK 80000000 1260 1261 /* corecontrol */ 1262 #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */ 1263 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */ 1264 #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */ 1265 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */ 1266 #define CC_RBG_RESET 0x00000040 /**< Reset RBG block (corerev > = 65 */ 1267 1268 /* retention_ctl */ 1269 #define RCTL_MEM_RET_SLEEP_LOG_SHIFT 29 1270 #define RCTL_MEM_RET_SLEEP_LOG_MASK (1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT) 1271 1272 /* 4321 chipcontrol */ 1273 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */ 1274 1275 /* Fields in the otpstatus register in rev >= 21 */ 1276 #define OTPS_OL_MASK 0x000000ff 1277 #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */ 1278 #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */ 1279 #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */ 1280 #define OTPS_OL_GU 0x00000008 /**< general use region is locked */ 1281 #define OTPS_GUP_MASK 0x00000f00 1282 #define OTPS_GUP_SHIFT 8 1283 #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */ 1284 #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */ 1285 #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */ 1286 #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */ 1287 #define OTPS_READY 0x00001000 1288 #define OTPS_RV(x) (1 << (16 + (x))) /**< redundancy entry valid */ 1289 #define OTPS_RV_MASK 0x0fff0000 1290 #define OTPS_PROGOK 0x40000000 1291 1292 /* Fields in the otpcontrol register in rev >= 21 */ 1293 #define OTPC_PROGSEL 0x00000001 1294 #define OTPC_PCOUNT_MASK 0x0000000e 1295 #define OTPC_PCOUNT_SHIFT 1 1296 #define OTPC_VSEL_MASK 0x000000f0 1297 #define OTPC_VSEL_SHIFT 4 1298 #define OTPC_TMM_MASK 0x00000700 1299 #define OTPC_TMM_SHIFT 8 1300 #define OTPC_ODM 0x00000800 1301 #define OTPC_PROGEN 0x80000000 1302 1303 /* Fields in the 40nm otpcontrol register in rev >= 40 */ 1304 #define OTPC_40NM_PROGSEL_SHIFT 0 1305 #define OTPC_40NM_PCOUNT_SHIFT 1 1306 #define OTPC_40NM_PCOUNT_WR 0xA 1307 #define OTPC_40NM_PCOUNT_V1X 0xB 1308 #define OTPC_40NM_REGCSEL_SHIFT 5 1309 #define OTPC_40NM_REGCSEL_DEF 0x4 1310 #define OTPC_40NM_PROGIN_SHIFT 8 1311 #define OTPC_40NM_R2X_SHIFT 10 1312 #define OTPC_40NM_ODM_SHIFT 11 1313 #define OTPC_40NM_DF_SHIFT 15 1314 #define OTPC_40NM_VSEL_SHIFT 16 1315 #define OTPC_40NM_VSEL_WR 0xA 1316 #define OTPC_40NM_VSEL_V1X 0xA 1317 #define OTPC_40NM_VSEL_R1X 0x5 1318 #define OTPC_40NM_COFAIL_SHIFT 30 1319 1320 #define OTPC1_CPCSEL_SHIFT 0 1321 #define OTPC1_CPCSEL_DEF 6 1322 #define OTPC1_TM_SHIFT 8 1323 #define OTPC1_TM_WR 0x84 1324 #define OTPC1_TM_V1X 0x84 1325 #define OTPC1_TM_R1X 0x4 1326 #define OTPC1_CLK_EN_MASK 0x00020000 1327 #define OTPC1_CLK_DIV_MASK 0x00FC0000 1328 1329 /* Fields in otpprog in rev >= 21 and HND OTP */ 1330 #define OTPP_COL_MASK 0x000000ff 1331 #define OTPP_COL_SHIFT 0 1332 #define OTPP_ROW_MASK 0x0000ff00 1333 #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */ 1334 #define OTPP_ROW_SHIFT 8 1335 #define OTPP_OC_MASK 0x0f000000 1336 #define OTPP_OC_SHIFT 24 1337 #define OTPP_READERR 0x10000000 1338 #define OTPP_VALUE_MASK 0x20000000 1339 #define OTPP_VALUE_SHIFT 29 1340 #define OTPP_START_BUSY 0x80000000 1341 #define OTPP_READ 0x40000000 /* HND OTP */ 1342 1343 /* Fields in otplayout register */ 1344 #define OTPL_HWRGN_OFF_MASK 0x00000FFF 1345 #define OTPL_HWRGN_OFF_SHIFT 0 1346 #define OTPL_WRAP_REVID_MASK 0x00F80000 1347 #define OTPL_WRAP_REVID_SHIFT 19 1348 #define OTPL_WRAP_TYPE_MASK 0x00070000 1349 #define OTPL_WRAP_TYPE_SHIFT 16 1350 #define OTPL_WRAP_TYPE_65NM 0 1351 #define OTPL_WRAP_TYPE_40NM 1 1352 #define OTPL_WRAP_TYPE_28NM 2 1353 #define OTPL_WRAP_TYPE_16NM 3 1354 #define OTPL_WRAP_TYPE_7NM 4 1355 #define OTPL_ROW_SIZE_MASK 0x0000F000 1356 #define OTPL_ROW_SIZE_SHIFT 12 1357 1358 /* otplayout reg corerev >= 36 */ 1359 #define OTP_CISFORMAT_NEW 0x80000000 1360 1361 /* Opcodes for OTPP_OC field */ 1362 #define OTPPOC_READ 0 1363 #define OTPPOC_BIT_PROG 1 1364 #define OTPPOC_VERIFY 3 1365 #define OTPPOC_INIT 4 1366 #define OTPPOC_SET 5 1367 #define OTPPOC_RESET 6 1368 #define OTPPOC_OCST 7 1369 #define OTPPOC_ROW_LOCK 8 1370 #define OTPPOC_PRESCN_TEST 9 1371 1372 /* Opcodes for OTPP_OC field (40NM) */ 1373 #define OTPPOC_READ_40NM 0 1374 #define OTPPOC_PROG_ENABLE_40NM 1 1375 #define OTPPOC_PROG_DISABLE_40NM 2 1376 #define OTPPOC_VERIFY_40NM 3 1377 #define OTPPOC_WORD_VERIFY_1_40NM 4 1378 #define OTPPOC_ROW_LOCK_40NM 5 1379 #define OTPPOC_STBY_40NM 6 1380 #define OTPPOC_WAKEUP_40NM 7 1381 #define OTPPOC_WORD_VERIFY_0_40NM 8 1382 #define OTPPOC_PRESCN_TEST_40NM 9 1383 #define OTPPOC_BIT_PROG_40NM 10 1384 #define OTPPOC_WORDPROG_40NM 11 1385 #define OTPPOC_BURNIN_40NM 12 1386 #define OTPPOC_AUTORELOAD_40NM 13 1387 #define OTPPOC_OVST_READ_40NM 14 1388 #define OTPPOC_OVST_PROG_40NM 15 1389 1390 /* Opcodes for OTPP_OC field (28NM) */ 1391 #define OTPPOC_READ_28NM 0 1392 #define OTPPOC_READBURST_28NM 1 1393 #define OTPPOC_PROG_ENABLE_28NM 2 1394 #define OTPPOC_PROG_DISABLE_28NM 3 1395 #define OTPPOC_PRESCREEN_28NM 4 1396 #define OTPPOC_PRESCREEN_RP_28NM 5 1397 #define OTPPOC_FLUSH_28NM 6 1398 #define OTPPOC_NOP_28NM 7 1399 #define OTPPOC_PROG_ECC_28NM 8 1400 #define OTPPOC_PROG_ECC_READ_28NM 9 1401 #define OTPPOC_PROG_28NM 10 1402 #define OTPPOC_PROGRAM_RP_28NM 11 1403 #define OTPPOC_PROGRAM_OVST_28NM 12 1404 #define OTPPOC_RELOAD_28NM 13 1405 #define OTPPOC_ERASE_28NM 14 1406 #define OTPPOC_LOAD_RF_28NM 15 1407 #define OTPPOC_CTRL_WR_28NM 16 1408 #define OTPPOC_CTRL_RD_28NM 17 1409 #define OTPPOC_READ_HP_28NM 18 1410 #define OTPPOC_READ_OVST_28NM 19 1411 #define OTPPOC_READ_VERIFY0_28NM 20 1412 #define OTPPOC_READ_VERIFY1_28NM 21 1413 #define OTPPOC_READ_FORCE0_28NM 22 1414 #define OTPPOC_READ_FORCE1_28NM 23 1415 #define OTPPOC_BURNIN_28NM 24 1416 #define OTPPOC_PROGRAM_LOCK_28NM 25 1417 #define OTPPOC_PROGRAM_TESTCOL_28NM 26 1418 #define OTPPOC_READ_TESTCOL_28NM 27 1419 #define OTPPOC_READ_FOUT_28NM 28 1420 #define OTPPOC_SFT_RESET_28NM 29 1421 1422 #define OTPP_OC_MASK_28NM 0x0f800000 1423 #define OTPP_OC_SHIFT_28NM 23 1424 1425 /* OTPControl bitmap for GCI rev >= 7 */ 1426 #define OTPC_PROGEN_28NM 0x8 1427 #define OTPC_DBLERRCLR 0x20 1428 #define OTPC_CLK_EN_MASK 0x00000040 1429 #define OTPC_CLK_DIV_MASK 0x00000F80 1430 #define OTPC_FORCE_OTP_PWR_DIS 0x00008000 1431 1432 /* Fields in otplayoutextension */ 1433 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF 1434 1435 /* Jtagm characteristics that appeared at a given corerev */ 1436 #define JTAGM_CREV_OLD 10 /**< Old command set, 16bit max IR */ 1437 #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */ 1438 #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */ 1439 1440 /* jtagcmd */ 1441 #define JCMD_START 0x80000000 1442 #define JCMD_BUSY 0x80000000 1443 #define JCMD_STATE_MASK 0x60000000 1444 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */ 1445 #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */ 1446 #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */ 1447 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */ 1448 #define JCMD0_ACC_MASK 0x0000f000 1449 #define JCMD0_ACC_IRDR 0x00000000 1450 #define JCMD0_ACC_DR 0x00001000 1451 #define JCMD0_ACC_IR 0x00002000 1452 #define JCMD0_ACC_RESET 0x00003000 1453 #define JCMD0_ACC_IRPDR 0x00004000 1454 #define JCMD0_ACC_PDR 0x00005000 1455 #define JCMD0_IRW_MASK 0x00000f00 1456 #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */ 1457 #define JCMD_ACC_IRDR 0x00000000 1458 #define JCMD_ACC_DR 0x00010000 1459 #define JCMD_ACC_IR 0x00020000 1460 #define JCMD_ACC_RESET 0x00030000 1461 #define JCMD_ACC_IRPDR 0x00040000 1462 #define JCMD_ACC_PDR 0x00050000 1463 #define JCMD_ACC_PIR 0x00060000 1464 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */ 1465 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */ 1466 #define JCMD_IRW_MASK 0x00001f00 1467 #define JCMD_IRW_SHIFT 8 1468 #define JCMD_DRW_MASK 0x0000003f 1469 1470 /* jtagctrl */ 1471 #define JCTRL_FORCE_CLK 4 /**< Force clock */ 1472 #define JCTRL_EXT_EN 2 /**< Enable external targets */ 1473 #define JCTRL_EN 1 /**< Enable Jtag master */ 1474 #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */ 1475 1476 /* swdmasterctrl */ 1477 #define SWDCTRL_INT_EN 8 /**< Enable internal targets */ 1478 #define SWDCTRL_FORCE_CLK 4 /**< Force clock */ 1479 #define SWDCTRL_OVJTAG 2 /**< Enable shared SWD/JTAG pins */ 1480 #define SWDCTRL_EN 1 /**< Enable Jtag master */ 1481 1482 /* Fields in clkdiv */ 1483 #define CLKD_SFLASH 0x1f000000 1484 #define CLKD_SFLASH_SHIFT 24 1485 #define CLKD_OTP 0x000f0000 1486 #define CLKD_OTP_SHIFT 16 1487 #define CLKD_JTAG 0x00000f00 1488 #define CLKD_JTAG_SHIFT 8 1489 #define CLKD_UART 0x000000ff 1490 1491 #define CLKD2_SROM 0x00000007 1492 #define CLKD2_SROMDIV_32 0 1493 #define CLKD2_SROMDIV_64 1 1494 #define CLKD2_SROMDIV_96 2 1495 #define CLKD2_SROMDIV_128 3 1496 #define CLKD2_SROMDIV_192 4 1497 #define CLKD2_SROMDIV_256 5 1498 #define CLKD2_SROMDIV_384 6 1499 #define CLKD2_SROMDIV_512 7 1500 #define CLKD2_SWD 0xf8000000 1501 #define CLKD2_SWD_SHIFT 27 1502 1503 /* intstatus/intmask */ 1504 #define CI_GPIO 0x00000001 /**< gpio intr */ 1505 #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */ 1506 #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */ 1507 #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */ 1508 #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */ 1509 #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */ 1510 #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */ 1511 #define CI_WECI 0x00000080 /* eci wakeup intr (corerev >= 21) */ 1512 #define CI_SPMI 0x00100000 /* SPMI (corerev >= 65) */ 1513 #define CI_RNG 0x00200000 /**< rng intr (corerev >= 65) */ 1514 #define CI_SSRESET_F0 0x10000000 /**< ss reset occurred */ 1515 #define CI_SSRESET_F1 0x20000000 /**< ss reset occurred */ 1516 #define CI_SSRESET_F2 0x40000000 /**< ss reset occurred */ 1517 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */ 1518 1519 /* slow_clk_ctl */ 1520 #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */ 1521 #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */ 1522 #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */ 1523 #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */ 1524 #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */ 1525 #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled, 1526 * 0: LPO is enabled 1527 */ 1528 #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock, 1529 * 0: power logic control 1530 */ 1531 #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors 1532 * PLL clock disable requests from core 1533 */ 1534 #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't 1535 * disable crystal when appropriate 1536 */ 1537 #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */ 1538 #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */ 1539 #define SCC_CD_SHIFT 16 1540 1541 /* system_clk_ctl */ 1542 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */ 1543 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */ 1544 #define SYCC_FP 0x00000004 /**< ForcePLLOn */ 1545 #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */ 1546 #define SYCC_HR 0x00000010 /**< Force HT */ 1547 #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 1548 #define SYCC_CD_SHIFT 16 1549 1550 /* watchdogcounter */ 1551 /* WL sub-system reset */ 1552 #define WD_SSRESET_PCIE_F0_EN 0x10000000 1553 /* BT sub-system reset */ 1554 #define WD_SSRESET_PCIE_F1_EN 0x20000000 1555 #define WD_SSRESET_PCIE_F2_EN 0x40000000 1556 /* Both WL and BT sub-system reset */ 1557 #define WD_SSRESET_PCIE_ALL_FN_EN 0x80000000 1558 #define WD_COUNTER_MASK 0x0fffffff 1559 #define WD_ENABLE_MASK \ 1560 (WD_SSRESET_PCIE_F0_EN | WD_SSRESET_PCIE_F1_EN | \ 1561 WD_SSRESET_PCIE_F2_EN | WD_SSRESET_PCIE_ALL_FN_EN) 1562 1563 /* Indirect backplane access */ 1564 #define BPIA_BYTEEN 0x0000000f 1565 #define BPIA_SZ1 0x00000001 1566 #define BPIA_SZ2 0x00000003 1567 #define BPIA_SZ4 0x00000007 1568 #define BPIA_SZ8 0x0000000f 1569 #define BPIA_WRITE 0x00000100 1570 #define BPIA_START 0x00000200 1571 #define BPIA_BUSY 0x00000200 1572 #define BPIA_ERROR 0x00000400 1573 1574 /* pcmcia/prog/flash_config */ 1575 #define CF_EN 0x00000001 /**< enable */ 1576 #define CF_EM_MASK 0x0000000e /**< mode */ 1577 #define CF_EM_SHIFT 1 1578 #define CF_EM_FLASH 0 /**< flash/asynchronous mode */ 1579 #define CF_EM_SYNC 2 /**< synchronous mode */ 1580 #define CF_EM_PCMCIA 4 /**< pcmcia mode */ 1581 #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */ 1582 #define CF_BS 0x00000020 /**< byteswap */ 1583 #define CF_CD_MASK 0x000000c0 /**< clock divider */ 1584 #define CF_CD_SHIFT 6 1585 #define CF_CD_DIV2 0x00000000 /**< backplane/2 */ 1586 #define CF_CD_DIV3 0x00000040 /**< backplane/3 */ 1587 #define CF_CD_DIV4 0x00000080 /**< backplane/4 */ 1588 #define CF_CE 0x00000100 /**< clock enable */ 1589 #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */ 1590 1591 /* pcmcia_memwait */ 1592 #define PM_W0_MASK 0x0000003f /**< waitcount0 */ 1593 #define PM_W1_MASK 0x00001f00 /**< waitcount1 */ 1594 #define PM_W1_SHIFT 8 1595 #define PM_W2_MASK 0x001f0000 /**< waitcount2 */ 1596 #define PM_W2_SHIFT 16 1597 #define PM_W3_MASK 0x1f000000 /**< waitcount3 */ 1598 #define PM_W3_SHIFT 24 1599 1600 /* pcmcia_attrwait */ 1601 #define PA_W0_MASK 0x0000003f /**< waitcount0 */ 1602 #define PA_W1_MASK 0x00001f00 /**< waitcount1 */ 1603 #define PA_W1_SHIFT 8 1604 #define PA_W2_MASK 0x001f0000 /**< waitcount2 */ 1605 #define PA_W2_SHIFT 16 1606 #define PA_W3_MASK 0x1f000000 /**< waitcount3 */ 1607 #define PA_W3_SHIFT 24 1608 1609 /* pcmcia_iowait */ 1610 #define PI_W0_MASK 0x0000003f /**< waitcount0 */ 1611 #define PI_W1_MASK 0x00001f00 /**< waitcount1 */ 1612 #define PI_W1_SHIFT 8 1613 #define PI_W2_MASK 0x001f0000 /**< waitcount2 */ 1614 #define PI_W2_SHIFT 16 1615 #define PI_W3_MASK 0x1f000000 /**< waitcount3 */ 1616 #define PI_W3_SHIFT 24 1617 1618 /* prog_waitcount */ 1619 #define PW_W0_MASK 0x0000001f /**< waitcount0 */ 1620 #define PW_W1_MASK 0x00001f00 /**< waitcount1 */ 1621 #define PW_W1_SHIFT 8 1622 #define PW_W2_MASK 0x001f0000 /**< waitcount2 */ 1623 #define PW_W2_SHIFT 16 1624 #define PW_W3_MASK 0x1f000000 /**< waitcount3 */ 1625 #define PW_W3_SHIFT 24 1626 1627 #define PW_W0 0x0000000c 1628 #define PW_W1 0x00000a00 1629 #define PW_W2 0x00020000 1630 #define PW_W3 0x01000000 1631 1632 /* flash_waitcount */ 1633 #define FW_W0_MASK 0x0000003f /**< waitcount0 */ 1634 #define FW_W1_MASK 0x00001f00 /**< waitcount1 */ 1635 #define FW_W1_SHIFT 8 1636 #define FW_W2_MASK 0x001f0000 /**< waitcount2 */ 1637 #define FW_W2_SHIFT 16 1638 #define FW_W3_MASK 0x1f000000 /**< waitcount3 */ 1639 #define FW_W3_SHIFT 24 1640 1641 /* When Srom support present, fields in sromcontrol */ 1642 #define SRC_START 0x80000000 1643 #define SRC_BUSY 0x80000000 1644 #define SRC_OPCODE 0x60000000 1645 #define SRC_OP_READ 0x00000000 1646 #define SRC_OP_WRITE 0x20000000 1647 #define SRC_OP_WRDIS 0x40000000 1648 #define SRC_OP_WREN 0x60000000 1649 #define SRC_OTPSEL 0x00000010 1650 #define SRC_OTPPRESENT 0x00000020 1651 #define SRC_LOCK 0x00000008 1652 #define SRC_SIZE_MASK 0x00000006 1653 #define SRC_SIZE_1K 0x00000000 1654 #define SRC_SIZE_4K 0x00000002 1655 #define SRC_SIZE_16K 0x00000004 1656 #define SRC_SIZE_SHIFT 1 1657 #define SRC_PRESENT 0x00000001 1658 1659 /* Fields in pmucontrol */ 1660 #define PCTL_ILP_DIV_MASK 0xffff0000 1661 #define PCTL_ILP_DIV_SHIFT 16 1662 #define PCTL_LQ_REQ_EN 0x00008000 1663 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */ 1664 #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */ 1665 #define PCTL_HT_REQ_EN 0x00000100 1666 #define PCTL_ALP_REQ_EN 0x00000080 1667 #define PCTL_XTALFREQ_MASK 0x0000007c 1668 #define PCTL_XTALFREQ_SHIFT 2 1669 #define PCTL_ILP_DIV_EN 0x00000002 1670 #define PCTL_LPO_SEL 0x00000001 1671 1672 /* Fields in pmucontrol_ext */ 1673 #define PCTL_EXT_FAST_TRANS_ENAB 0x00000001u 1674 #define PCTL_EXT_USE_LHL_TIMER 0x00000010u 1675 #define PCTL_EXT_FASTLPO_ENAB 0x00000080u 1676 #define PCTL_EXT_FASTLPO_SWENAB 0x00000200u 1677 #define PCTL_EXT_FASTSEQ_ENAB 0x00001000u 1678 #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000u /**< rev33 for FLL1M */ 1679 #define PCTL_EXT_FASTLPO_SB_SWENAB 0x00008000u /**< rev36 for FLL1M */ 1680 #define PCTL_EXT_REQ_MIRROR_ENAB 0x00010000u /**< rev36 for ReqMirrorEn */ 1681 1682 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77 1683 1684 /* Retention Control */ 1685 #define PMU_RCTL_CLK_DIV_SHIFT 0 1686 #define PMU_RCTL_CHAIN_LEN_SHIFT 12 1687 #define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 1688 #define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) 1689 #define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 1690 #define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) 1691 #define PMU_RCTL_MEMSLP_LOG_SHIFT 28 1692 #define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) 1693 #define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 1694 #define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) 1695 1696 /* Retention Group Control */ 1697 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 1698 #define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 1699 #define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) 1700 #define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 1701 #define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) 1702 #define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 1703 #define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) 1704 1705 /* Fields in clkstretch */ 1706 #define CSTRETCH_HT 0xffff0000 1707 #define CSTRETCH_ALP 0x0000ffff 1708 #define CSTRETCH_REDUCE_8 0x00080008 1709 1710 /* gpiotimerval */ 1711 #define GPIO_ONTIME_SHIFT 16 1712 1713 /* clockcontrol_n */ 1714 /* Some pll types use less than the number of bits in some of these (n or m) masks */ 1715 #define CN_N1_MASK 0x3f /**< n1 control */ 1716 #define CN_N2_MASK 0x3f00 /**< n2 control */ 1717 #define CN_N2_SHIFT 8 1718 #define CN_PLLC_MASK 0xf0000 /**< pll control */ 1719 #define CN_PLLC_SHIFT 16 1720 1721 /* clockcontrol_sb/pci/uart */ 1722 #define CC_M1_MASK 0x3f /**< m1 control */ 1723 #define CC_M2_MASK 0x3f00 /**< m2 control */ 1724 #define CC_M2_SHIFT 8 1725 #define CC_M3_MASK 0x3f0000 /**< m3 control */ 1726 #define CC_M3_SHIFT 16 1727 #define CC_MC_MASK 0x1f000000 /**< mux control */ 1728 #define CC_MC_SHIFT 24 1729 1730 /* N3M Clock control magic field values */ 1731 #define CC_F6_2 0x02 /**< A factor of 2 in */ 1732 #define CC_F6_3 0x03 /**< 6-bit fields like */ 1733 #define CC_F6_4 0x05 /**< N1, M1 or M3 */ 1734 #define CC_F6_5 0x09 1735 #define CC_F6_6 0x11 1736 #define CC_F6_7 0x21 1737 1738 #define CC_F5_BIAS 5 /**< 5-bit fields get this added */ 1739 1740 #define CC_MC_BYPASS 0x08 1741 #define CC_MC_M1 0x04 1742 #define CC_MC_M1M2 0x02 1743 #define CC_MC_M1M2M3 0x01 1744 #define CC_MC_M1M3 0x11 1745 1746 /* Type 2 Clock control magic field values */ 1747 #define CC_T2_BIAS 2 /**< n1, n2, m1 & m3 bias */ 1748 #define CC_T2M2_BIAS 3 /**< m2 bias */ 1749 1750 #define CC_T2MC_M1BYP 1 1751 #define CC_T2MC_M2BYP 2 1752 #define CC_T2MC_M3BYP 4 1753 1754 /* Type 6 Clock control magic field values */ 1755 #define CC_T6_MMASK 1 /**< bits of interest in m */ 1756 #define CC_T6_M0 120000000 /**< sb clock for m = 0 */ 1757 #define CC_T6_M1 100000000 /**< sb clock for m = 1 */ 1758 #define SB2MIPS_T6(sb) (2 * (sb)) 1759 1760 /* Common clock base */ 1761 #define CC_CLOCK_BASE1 24000000 /**< Half the clock freq */ 1762 #define CC_CLOCK_BASE2 12500000 /**< Alternate crystal on some PLLs */ 1763 1764 /* Flash types in the chipcommon capabilities register */ 1765 #define FLASH_NONE 0x000 /**< No flash */ 1766 #define SFLASH_ST 0x100 /**< ST serial flash */ 1767 #define SFLASH_AT 0x200 /**< Atmel serial flash */ 1768 #define NFLASH 0x300 /**< NAND flash */ 1769 #define PFLASH 0x700 /**< Parallel flash */ 1770 #define QSPIFLASH_ST 0x800 1771 #define QSPIFLASH_AT 0x900 1772 1773 /* Bits in the ExtBus config registers */ 1774 #define CC_CFG_EN 0x0001 /**< Enable */ 1775 #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */ 1776 #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */ 1777 #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */ 1778 #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */ 1779 #define CC_CFG_EM_IDE 0x0006 /**< IDE */ 1780 #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */ 1781 #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */ 1782 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */ 1783 #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */ 1784 #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */ 1785 1786 /* ExtBus address space */ 1787 #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */ 1788 #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */ 1789 #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */ 1790 #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */ 1791 #define CC_EB_IDE 0x1a800000 /**< IDE memory base */ 1792 #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */ 1793 #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */ 1794 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */ 1795 #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */ 1796 1797 /* Start/busy bit in flashcontrol */ 1798 #define SFLASH_OPCODE 0x000000ff 1799 #define SFLASH_ACTION 0x00000700 1800 #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */ 1801 #define SFLASH_START 0x80000000 1802 #define SFLASH_BUSY SFLASH_START 1803 1804 /* flashcontrol action codes */ 1805 #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */ 1806 #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */ 1807 #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */ 1808 #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */ 1809 #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */ 1810 #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */ 1811 #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */ 1812 1813 /* flashcontrol action+opcodes for ST flashes */ 1814 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */ 1815 #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */ 1816 #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */ 1817 #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */ 1818 #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */ 1819 #define SFLASH_ST_PP 0x0302 /**< Page Program */ 1820 #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */ 1821 #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */ 1822 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */ 1823 #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */ 1824 #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */ 1825 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */ 1826 1827 #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */ 1828 #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */ 1829 #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */ 1830 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */ 1831 1832 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */ 1833 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */ 1834 1835 #define SFLASH_WINBOND_RDID 0x0390 /* Read Manufacture ID */ 1836 #define SFLASH_WINBOND_MFID 0xef /* Winbond Manufacture ID */ 1837 1838 /* Status register bits for ST flashes */ 1839 #define SFLASH_ST_WIP 0x01 /**< Write In Progress */ 1840 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */ 1841 #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */ 1842 #define SFLASH_ST_BP_SHIFT 2 1843 #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */ 1844 1845 /* flashcontrol action+opcodes for Atmel flashes */ 1846 #define SFLASH_AT_READ 0x07e8 1847 #define SFLASH_AT_PAGE_READ 0x07d2 1848 /* PR9631: impossible to specify Atmel Buffer Read command */ 1849 #define SFLASH_AT_BUF1_READ 1850 #define SFLASH_AT_BUF2_READ 1851 #define SFLASH_AT_STATUS 0x01d7 1852 #define SFLASH_AT_BUF1_WRITE 0x0384 1853 #define SFLASH_AT_BUF2_WRITE 0x0387 1854 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 1855 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 1856 #define SFLASH_AT_BUF1_PROGRAM 0x0288 1857 #define SFLASH_AT_BUF2_PROGRAM 0x0289 1858 #define SFLASH_AT_PAGE_ERASE 0x0281 1859 #define SFLASH_AT_BLOCK_ERASE 0x0250 1860 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 1861 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 1862 #define SFLASH_AT_BUF1_LOAD 0x0253 1863 #define SFLASH_AT_BUF2_LOAD 0x0255 1864 #define SFLASH_AT_BUF1_COMPARE 0x0260 1865 #define SFLASH_AT_BUF2_COMPARE 0x0261 1866 #define SFLASH_AT_BUF1_REPROGRAM 0x0258 1867 #define SFLASH_AT_BUF2_REPROGRAM 0x0259 1868 1869 /* Status register bits for Atmel flashes */ 1870 #define SFLASH_AT_READY 0x80 1871 #define SFLASH_AT_MISMATCH 0x40 1872 #define SFLASH_AT_ID_MASK 0x38 1873 #define SFLASH_AT_ID_SHIFT 3 1874 1875 /* SPI register bits, corerev >= 37 */ 1876 #define GSIO_START 0x80000000u 1877 #define GSIO_BUSY GSIO_START 1878 1879 /* UART Function sel related */ 1880 #define MUXENAB_DEF_UART_MASK 0x0000000fu 1881 #define MUXENAB_DEF_UART_SHIFT 0 1882 1883 /* HOST_WAKE Function sel related */ 1884 #define MUXENAB_DEF_HOSTWAKE_MASK 0x000000f0u /**< configure GPIO for host_wake */ 1885 #define MUXENAB_DEF_HOSTWAKE_SHIFT 4u 1886 1887 /* GCI UART Function sel related */ 1888 #define MUXENAB_GCI_UART_MASK 0x00000f00u 1889 #define MUXENAB_GCI_UART_SHIFT 8u 1890 #define MUXENAB_GCI_UART_FNSEL_MASK 0x00003000u 1891 #define MUXENAB_GCI_UART_FNSEL_SHIFT 12u 1892 1893 /* Mask used to decide whether MUX to be performed or not */ 1894 #define MUXENAB_DEF_GETIX(val, name) \ 1895 ((((val) & MUXENAB_DEF_ ## name ## _MASK) >> MUXENAB_DEF_ ## name ## _SHIFT) - 1) 1896 1897 /* 1898 * These are the UART port assignments, expressed as offsets from the base 1899 * register. These assignments should hold for any serial port based on 1900 * a 8250, 16450, or 16550(A). 1901 */ 1902 1903 #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */ 1904 #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */ 1905 #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */ 1906 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */ 1907 #define UART_DLM 1 /**< Out: Divisor Latch High (DLAB=1) */ 1908 #define UART_IIR 2 /**< In: Interrupt Identity Register */ 1909 #define UART_FCR 2 /**< Out: FIFO Control Register */ 1910 #define UART_LCR 3 /**< Out: Line Control Register */ 1911 #define UART_MCR 4 /**< Out: Modem Control Register */ 1912 #define UART_LSR 5 /**< In: Line Status Register */ 1913 #define UART_MSR 6 /**< In: Modem Status Register */ 1914 #define UART_SCR 7 /**< I/O: Scratch Register */ 1915 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ 1916 #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */ 1917 #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */ 1918 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ 1919 #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */ 1920 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */ 1921 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ 1922 #define UART_LSR_BREAK 0x10 /**< Break interrupt */ 1923 #define UART_LSR_FRAMING 0x08 /**< Framing error */ 1924 #define UART_LSR_PARITY 0x04 /**< Parity error */ 1925 #define UART_LSR_OVERRUN 0x02 /**< Overrun error */ 1926 #define UART_LSR_RXRDY 0x01 /**< Receiver ready */ 1927 #define UART_FCR_FIFO_ENABLE 1 /**< FIFO control register bit controlling FIFO enable/disable */ 1928 1929 /* Interrupt Identity Register (IIR) bits */ 1930 #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */ 1931 #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */ 1932 #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */ 1933 #define UART_IIR_NOINT 0x1 /**< No interrupt pending */ 1934 #define UART_IIR_THRE 0x2 /**< THR empty */ 1935 #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */ 1936 #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */ 1937 #define UART_IIR_CHAR_TIME 0xc /**< Character time */ 1938 1939 /* Interrupt Enable Register (IER) bits */ 1940 #define UART_IER_PTIME 128 /**< Programmable THRE Interrupt Mode Enable */ 1941 #define UART_IER_EDSSI 8 /**< enable modem status interrupt */ 1942 #define UART_IER_ELSI 4 /**< enable receiver line status interrupt */ 1943 #define UART_IER_ETBEI 2 /**< enable transmitter holding register empty interrupt */ 1944 #define UART_IER_ERBFI 1 /**< enable data available interrupt */ 1945 1946 /* pmustatus */ 1947 #define PST_SLOW_WR_PENDING 0x0400 1948 #define PST_EXTLPOAVAIL 0x0100 1949 #define PST_WDRESET 0x0080 1950 #define PST_INTPEND 0x0040 1951 #define PST_SBCLKST 0x0030 1952 #define PST_SBCLKST_ILP 0x0010 1953 #define PST_SBCLKST_ALP 0x0020 1954 #define PST_SBCLKST_HT 0x0030 1955 #define PST_ALPAVAIL 0x0008 1956 #define PST_HTAVAIL 0x0004 1957 #define PST_RESINIT 0x0003 1958 #define PST_ILPFASTLPO 0x00010000 1959 1960 /* pmucapabilities */ 1961 #define PCAP_REV_MASK 0x000000ff 1962 #define PCAP_RC_MASK 0x00001f00 1963 #define PCAP_RC_SHIFT 8 1964 #define PCAP_TC_MASK 0x0001e000 1965 #define PCAP_TC_SHIFT 13 1966 #define PCAP_PC_MASK 0x001e0000 1967 #define PCAP_PC_SHIFT 17 1968 #define PCAP_VC_MASK 0x01e00000 1969 #define PCAP_VC_SHIFT 21 1970 #define PCAP_CC_MASK 0x1e000000 1971 #define PCAP_CC_SHIFT 25 1972 #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */ 1973 #define PCAP5_PC_SHIFT 17 1974 #define PCAP5_VC_MASK 0x07c00000 1975 #define PCAP5_VC_SHIFT 22 1976 #define PCAP5_CC_MASK 0xf8000000 1977 #define PCAP5_CC_SHIFT 27 1978 1979 /* pmucapabilities ext */ 1980 #define PCAP_EXT_ST_NUM_SHIFT (8) /* stat timer number */ 1981 #define PCAP_EXT_ST_NUM_MASK (0xf << PCAP_EXT_ST_NUM_SHIFT) 1982 #define PCAP_EXT_ST_SRC_NUM_SHIFT (12) /* stat timer source number */ 1983 #define PCAP_EXT_ST_SRC_NUM_MASK (0xf << PCAP_EXT_ST_SRC_NUM_SHIFT) 1984 #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT (20u) /* # of MAC rsrc req timers */ 1985 #define PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_MASK (7u << PCAP_EXT_MAC_RSRC_REQ_TMR_CNT_SHIFT) 1986 #define PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT (23u) /* pmu int rcvr cnt */ 1987 #define PCAP_EXT_PMU_INTR_RCVR_CNT_MASK (7u << PCAP_EXT_PMU_INTR_RCVR_CNT_SHIFT) 1988 1989 /* pmustattimer ctrl */ 1990 #define PMU_ST_SRC_SHIFT (0) /* stat timer source number */ 1991 #define PMU_ST_SRC_MASK (0xff << PMU_ST_SRC_SHIFT) 1992 #define PMU_ST_CNT_MODE_SHIFT (10) /* stat timer count mode */ 1993 #define PMU_ST_CNT_MODE_MASK (0x3 << PMU_ST_CNT_MODE_SHIFT) 1994 #define PMU_ST_EN_SHIFT (8) /* stat timer enable */ 1995 #define PMU_ST_EN_MASK (0x1 << PMU_ST_EN_SHIFT) 1996 #define PMU_ST_ENAB 1 1997 #define PMU_ST_DISAB 0 1998 #define PMU_ST_INT_EN_SHIFT (9) /* stat timer enable */ 1999 #define PMU_ST_INT_EN_MASK (0x1 << PMU_ST_INT_EN_SHIFT) 2000 #define PMU_ST_INT_ENAB 1 2001 #define PMU_ST_INT_DISAB 0 2002 2003 /* CoreCapabilitiesExtension */ 2004 #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000 2005 2006 /* PMU Resource Request Timer registers */ 2007 /* This is based on PmuRev0 */ 2008 #define PRRT_TIME_MASK 0x03ff 2009 #define PRRT_INTEN 0x0400 2010 /* ReqActive 25 2011 * The hardware sets this field to 1 when the timer expires. 2012 * Software writes this field to 1 to make immediate resource requests. 2013 */ 2014 #define PRRT_REQ_ACTIVE 0x0800 /* To check h/w status */ 2015 #define PRRT_IMMEDIATE_RES_REQ 0x0800 /* macro for sw immediate res req */ 2016 #define PRRT_ALP_REQ 0x1000 2017 #define PRRT_HT_REQ 0x2000 2018 #define PRRT_HQ_REQ 0x4000 2019 2020 /* PMU Int Control register bits */ 2021 #define PMU_INTC_ALP_REQ 0x1 2022 #define PMU_INTC_HT_REQ 0x2 2023 #define PMU_INTC_HQ_REQ 0x4 2024 2025 /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */ 2026 #define RSRC_INTR_MASK_TIMER_INT_0 1 2027 #define PMU_INTR_MASK_EXTWAKE_REQ_ACTIVE_0 (1 << 20) 2028 2029 #define PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT (8u) 2030 #define PMU_INT_STAT_RSRC_EVENT_INT0_MASK (1u << PMU_INT_STAT_RSRC_EVENT_INT0_SHIFT) 2031 2032 /* bit 16 of the PMU interrupt vector - Stats Timer Interrupt */ 2033 #define PMU_INT_STAT_TIMER_INT_SHIFT (16u) 2034 #define PMU_INT_STAT_TIMER_INT_MASK (1u << PMU_INT_STAT_TIMER_INT_SHIFT) 2035 2036 /* 2037 * bit 18 of the PMU interrupt vector - S/R self test fails 2038 */ 2039 #define PMU_INT_STAT_SR_ERR_SHIFT (18u) 2040 #define PMU_INT_STAT_SR_ERR_MASK (1u << PMU_INT_STAT_SR_ERR_SHIFT) 2041 2042 /* PMU resource bit position */ 2043 #define PMURES_BIT(bit) (1u << (bit)) 2044 2045 /* PMU resource number limit */ 2046 #define PMURES_MAX_RESNUM 30 2047 2048 /* PMU chip control0 register */ 2049 #define PMU_CHIPCTL0 0 2050 2051 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) 2052 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) 2053 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0xF << 6) 2054 #define PMU_CC0_4369B0_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) 2055 #define PMU_CC0_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) 2056 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_VAL (0 << 12) 2057 #define PMU_CC0_4369_XTAL_RES_BYPASS_START_MASK (0x7 << 12) 2058 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_VAL (0x1 << 15) 2059 #define PMU_CC0_4369_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) 2060 2061 // This is not used. so retains reset value 2062 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20u << 0u) 2063 2064 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3Fu << 0u) 2065 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1Au << 6u) 2066 #define PMU_CC0_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3Fu << 6u) 2067 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_VAL (0x00u << 12u) 2068 #define PMU_CC0_4362_XTAL_RES_BYPASS_START_MASK (0x07u << 12u) 2069 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_VAL (0x02u << 15u) 2070 #define PMU_CC0_4362_XTAL_RES_BYPASS_NORMAL_MASK (0x07u << 15u) 2071 2072 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) 2073 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) 2074 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) 2075 #define PMU_CC0_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) 2076 #define PMU_CC0_4378_XTAL_RES_BYPASS_START_VAL (0 << 12) 2077 #define PMU_CC0_4378_XTAL_RES_BYPASS_START_MASK (0x7 << 12) 2078 #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15) 2079 #define PMU_CC0_4378_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) 2080 2081 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x20 << 0) 2082 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3F << 0) 2083 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x1A << 6) 2084 #define PMU_CC0_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3F << 6) 2085 #define PMU_CC0_4387_XTAL_RES_BYPASS_START_VAL (0 << 12) 2086 #define PMU_CC0_4387_XTAL_RES_BYPASS_START_MASK (0x7 << 12) 2087 #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_VAL (0x2 << 15) 2088 #define PMU_CC0_4387_XTAL_RES_BYPASS_NORMAL_MASK (0x7 << 15) 2089 #define PMU_CC0_4387_BT_PU_WAKE_MASK (0x3u << 30u) 2090 2091 /* clock req types */ 2092 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19 2093 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) 2094 2095 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 2096 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1 2097 2098 /* Power Control */ 2099 #define PWRCTL_ENAB_MEM_CLK_GATE_SHIFT 5 2100 #define PWRCTL_FORCE_HW_PWR_REQ_OFF_SHIFT 6 2101 #define PWRCTL_AUTO_MEM_STBYRET 28 2102 2103 /* PMU chip control1 register */ 2104 #define PMU_CHIPCTL1 1 2105 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 2106 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010 2107 2108 #define PMU_CC1_IF_TYPE_MASK 0x00000030 2109 #define PMU_CC1_IF_TYPE_RMII 0x00000000 2110 #define PMU_CC1_IF_TYPE_MII 0x00000010 2111 #define PMU_CC1_IF_TYPE_RGMII 0x00000020 2112 2113 #define PMU_CC1_SW_TYPE_MASK 0x000000c0 2114 #define PMU_CC1_SW_TYPE_EPHY 0x00000000 2115 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 2116 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 2117 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 2118 2119 #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080 2120 #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000 2121 2122 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY_MASK 0x00003F00u 2123 #ifdef BCM_FASTLPO_PMU 2124 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00002000u 2125 #else 2126 #define PMU_CC1_PWRSW_CLKSTRSTP_DELAY 0x00000400u 2127 #endif /* BCM_FASTLPO_PMU */ 2128 2129 /* PMU chip control2 register */ 2130 #define PMU_CC2_CB2WL_INTR_PWRREQ_EN (1u << 13u) 2131 #define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1u << 15u) 2132 #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000u 2133 2134 #define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1u << 16u) 2135 #define PMU_CHIPCTL2 2u 2136 #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1u << 18u) 2137 #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1u << 19u) 2138 #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1u << 20u) 2139 #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1u << 21u) 2140 #define PMU_CC2_MASK_WL_DEV_WAKE (1u << 22u) 2141 #define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1u << 25u) 2142 #define PMU_CC2_GCI2_WAKE (1u << 31u) 2143 2144 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) 2145 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) 2146 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) 2147 #define PMU_CC2_4369_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) 2148 2149 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) 2150 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) 2151 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) 2152 #define PMU_CC2_4362_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) 2153 2154 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) 2155 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) 2156 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) 2157 #define PMU_CC2_4378_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) 2158 2159 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_VAL (0x3u << 26u) 2160 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_START_MASK (0x3u << 26u) 2161 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_VAL (0x0u << 28u) 2162 #define PMU_CC2_4387_XTALCORESIZE_BIAS_ADJ_NORMAL_MASK (0x3u << 28u) 2163 2164 /* PMU chip control3 register */ 2165 #define PMU_CHIPCTL3 3u 2166 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19u 2167 #define PMU_CC3_ENABLE_RF_SHIFT 22u 2168 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23u 2169 2170 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u) 2171 #define PMU_CC3_4369_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u) 2172 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u) 2173 #define PMU_CC3_4369_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u) 2174 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u) 2175 #define PMU_CC3_4369_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u) 2176 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21) 2177 #define PMU_CC3_4369_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21) 2178 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_VAL (0x2u << 12u) 2179 #define PMU_CC3_4369_XTALSEL_BIAS_RES_START_MASK (0x7u << 12u) 2180 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_VAL (0x2u << 27u) 2181 #define PMU_CC3_4369_XTALSEL_BIAS_RES_NORMAL_MASK (0x7u << 27u) 2182 2183 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_VAL (0x3Fu << 0u) 2184 #define PMU_CC3_4362_XTALCORESIZE_PMOS_START_MASK (0x3Fu << 0u) 2185 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_VAL (0x3Fu << 15u) 2186 #define PMU_CC3_4362_XTALCORESIZE_PMOS_NORMAL_MASK (0x3Fu << 15u) 2187 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_VAL (0x3Fu << 6u) 2188 #define PMU_CC3_4362_XTALCORESIZE_NMOS_START_MASK (0x3Fu << 6u) 2189 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_VAL (0x3Fu << 21u) 2190 #define PMU_CC3_4362_XTALCORESIZE_NMOS_NORMAL_MASK (0x3Fu << 21u) 2191 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_VAL (0x02u << 12u) 2192 #define PMU_CC3_4362_XTALSEL_BIAS_RES_START_MASK (0x07u << 12u) 2193 /* Changed from 6 to 4 for wlan PHN and to 2 for BT PER issues */ 2194 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_VAL (0x02u << 27u) 2195 #define PMU_CC3_4362_XTALSEL_BIAS_RES_NORMAL_MASK (0x07u << 27u) 2196 2197 #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_VAL (0x3F << 0) 2198 #define PMU_CC3_4378_XTALCORESIZE_PMOS_START_MASK (0x3F << 0) 2199 #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15) 2200 #define PMU_CC3_4378_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15) 2201 #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_VAL (0x3F << 6) 2202 #define PMU_CC3_4378_XTALCORESIZE_NMOS_START_MASK (0x3F << 6) 2203 #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21) 2204 #define PMU_CC3_4378_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21) 2205 #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_VAL (0x2 << 12) 2206 #define PMU_CC3_4378_XTALSEL_BIAS_RES_START_MASK (0x7 << 12) 2207 #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_VAL (0x2 << 27) 2208 #define PMU_CC3_4378_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27) 2209 2210 #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_VAL (0x3F << 0) 2211 #define PMU_CC3_4387_XTALCORESIZE_PMOS_START_MASK (0x3F << 0) 2212 #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_VAL (0x3F << 15) 2213 #define PMU_CC3_4387_XTALCORESIZE_PMOS_NORMAL_MASK (0x3F << 15) 2214 #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_VAL (0x3F << 6) 2215 #define PMU_CC3_4387_XTALCORESIZE_NMOS_START_MASK (0x3F << 6) 2216 #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_VAL (0x3F << 21) 2217 #define PMU_CC3_4387_XTALCORESIZE_NMOS_NORMAL_MASK (0x3F << 21) 2218 #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_VAL (0x2 << 12) 2219 #define PMU_CC3_4387_XTALSEL_BIAS_RES_START_MASK (0x7 << 12) 2220 #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_VAL (0x5 << 27) 2221 #define PMU_CC3_4387_XTALSEL_BIAS_RES_NORMAL_MASK (0x7 << 27) 2222 2223 /* PMU chip control4 register */ 2224 #define PMU_CHIPCTL4 4 2225 2226 /* 53537 series moved switch_type and gmac_if_type to CC4 [15:14] and [13:12] */ 2227 #define PMU_CC4_IF_TYPE_MASK 0x00003000 2228 #define PMU_CC4_IF_TYPE_RMII 0x00000000 2229 #define PMU_CC4_IF_TYPE_MII 0x00001000 2230 #define PMU_CC4_IF_TYPE_RGMII 0x00002000 2231 2232 #define PMU_CC4_SW_TYPE_MASK 0x0000c000 2233 #define PMU_CC4_SW_TYPE_EPHY 0x00000000 2234 #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000 2235 #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000 2236 #define PMU_CC4_SW_TYPE_RGMII 0x0000c000 2237 #define PMU_CC4_DISABLE_LQ_AVAIL (1<<27) 2238 2239 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) 2240 #define PMU_CC4_4369_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) 2241 #define PMU_CC4_4369_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) 2242 #define PMU_CC4_4369_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) 2243 2244 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDB_ON (1u << 21u) 2245 #define PMU_CC4_4369_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) 2246 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) 2247 #define PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) 2248 2249 #define PMU_CC4_4362_PD_CBUCK2VDDB_ON (1u << 15u) 2250 #define PMU_CC4_4362_PD_CBUCK2VDDRET_ON (1u << 16u) 2251 #define PMU_CC4_4362_PD_MEMLPLDO2VDDB_ON (1u << 17u) 2252 #define PMU_CC4_4362_PD_MEMLPDLO2VDDRET_ON (1u << 18u) 2253 2254 #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) 2255 #define PMU_CC4_4378_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) 2256 #define PMU_CC4_4378_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) 2257 #define PMU_CC4_4378_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) 2258 2259 #define PMU_CC4_4378_AUX_PD_CBUCK2VDDB_ON (1u << 21u) 2260 #define PMU_CC4_4378_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) 2261 #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) 2262 #define PMU_CC4_4378_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) 2263 2264 #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDB_ON (1u << 15u) 2265 #define PMU_CC4_4387_MAIN_PD_CBUCK2VDDRET_ON (1u << 16u) 2266 #define PMU_CC4_4387_MAIN_PD_MEMLPLDO2VDDB_ON (1u << 17u) 2267 #define PMU_CC4_4387_MAIN_PD_MEMLPDLO2VDDRET_ON (1u << 18u) 2268 2269 #define PMU_CC4_4387_AUX_PD_CBUCK2VDDB_ON (1u << 21u) 2270 #define PMU_CC4_4387_AUX_PD_CBUCK2VDDRET_ON (1u << 22u) 2271 #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDB_ON (1u << 23u) 2272 #define PMU_CC4_4387_AUX_PD_MEMLPLDO2VDDRET_ON (1u << 24u) 2273 2274 /* PMU chip control5 register */ 2275 #define PMU_CHIPCTL5 5 2276 2277 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDB_ON (1u << 9u) 2278 #define PMU_CC5_4369_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) 2279 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) 2280 #define PMU_CC5_4369_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) 2281 2282 #define PMU_CC5_4362_SUBCORE_CBUCK2VDDB_ON (1u << 9u) 2283 #define PMU_CC5_4362_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) 2284 #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) 2285 #define PMU_CC5_4362_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) 2286 2287 #define PMU_CC5_4378_SUBCORE_CBUCK2VDDB_ON (1u << 9u) 2288 #define PMU_CC5_4378_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) 2289 #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) 2290 #define PMU_CC5_4378_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) 2291 2292 #define PMU_CC5_4387_SUBCORE_CBUCK2VDDB_ON (1u << 9u) 2293 #define PMU_CC5_4387_SUBCORE_CBUCK2VDDRET_ON (1u << 10u) 2294 #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDB_ON (1u << 11u) 2295 #define PMU_CC5_4387_SUBCORE_MEMLPLDO2VDDRET_ON (1u << 12u) 2296 2297 #define PMU_CC5_4388_SUBCORE_SDTCCLK0_ON (1u << 3u) 2298 #define PMU_CC5_4388_SUBCORE_SDTCCLK1_ON (1u << 4u) 2299 2300 #define PMU_CC5_4389_SUBCORE_SDTCCLK0_ON (1u << 3u) 2301 #define PMU_CC5_4389_SUBCORE_SDTCCLK1_ON (1u << 4u) 2302 2303 /* PMU chip control6 register */ 2304 #define PMU_CHIPCTL6 6 2305 #define PMU_CC6_RX4_CLK_SEQ_SELECT_MASK BCM_MASK32(1u, 0u) 2306 #define PMU_CC6_ENABLE_DMN1_WAKEUP (1 << 3) 2307 #define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4) 2308 #define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6) 2309 #define PMU_CC6_ENABLE_PCIE_RETENTION (1 << 12) 2310 #define PMU_CC6_ENABLE_PMU_EXT_PERST (1 << 13) 2311 #define PMU_CC6_ENABLE_PMU_WAKEUP_PERST (1 << 14) 2312 #define PMU_CC6_ENABLE_LEGACY_WAKEUP (1 << 16) 2313 2314 /* PMU chip control7 register */ 2315 #define PMU_CHIPCTL7 7 2316 #define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN (1 << 25) 2317 #define PMU_CC7_ENABLE_MDIO_RESET_WAR (1 << 27) 2318 /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */ 2319 #define PMU_CC7_IF_TYPE_MASK 0x000000c0 2320 #define PMU_CC7_IF_TYPE_RMII 0x00000000 2321 #define PMU_CC7_IF_TYPE_MII 0x00000040 2322 #define PMU_CC7_IF_TYPE_RGMII 0x00000080 2323 2324 #define PMU_CHIPCTL8 8 2325 #define PMU_CHIPCTL9 9 2326 2327 #define PMU_CHIPCTL10 10 2328 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_SHIFT 0 2329 #define PMU_CC10_PCIE_PWRSW_RESET0_CNT_MASK 0x000000ff 2330 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_SHIFT 8 2331 #define PMU_CC10_PCIE_PWRSW_RESET1_CNT_MASK 0x0000ff00 2332 #define PMU_CC10_PCIE_PWRSW_UP_DLY_SHIFT 16 2333 #define PMU_CC10_PCIE_PWRSW_UP_DLY_MASK 0x000f0000 2334 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_SHIFT 20 2335 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_MASK 0x00f00000 2336 #define PMU_CC10_FORCE_PCIE_ON (1 << 24) 2337 #define PMU_CC10_FORCE_PCIE_SW_ON (1 << 25) 2338 #define PMU_CC10_FORCE_PCIE_RETNT_ON (1 << 26) 2339 2340 #define PMU_CC10_PCIE_PWRSW_RESET_CNT_4US 1 2341 #define PMU_CC10_PCIE_PWRSW_RESET_CNT_8US 2 2342 2343 #define PMU_CC10_PCIE_PWRSW_UP_DLY_0US 0 2344 2345 #define PMU_CC10_PCIE_PWRSW_FORCE_PWROK_DLY_4US 1 2346 #define PMU_CC10_PCIE_RESET0_CNT_SLOW_MASK (0xFu << 4u) 2347 #define PMU_CC10_PCIE_RESET1_CNT_SLOW_MASK (0xFu << 12u) 2348 2349 #define PMU_CHIPCTL11 11 2350 2351 /* PMU chip control12 register */ 2352 #define PMU_CHIPCTL12 12 2353 #define PMU_CC12_DISABLE_LQ_CLK_ON (1u << 31u) /* HW4387-254 */ 2354 2355 /* PMU chip control13 register */ 2356 #define PMU_CHIPCTL13 13 2357 2358 #define PMU_CC13_SUBCORE_CBUCK2VDDB_OFF (1u << 0u) 2359 #define PMU_CC13_SUBCORE_CBUCK2VDDRET_OFF (1u << 1u) 2360 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDB_OFF (1u << 2u) 2361 #define PMU_CC13_SUBCORE_MEMLPLDO2VDDRET_OFF (1u << 3u) 2362 2363 #define PMU_CC13_MAIN_CBUCK2VDDB_OFF (1u << 4u) 2364 #define PMU_CC13_MAIN_CBUCK2VDDRET_OFF (1u << 5u) 2365 #define PMU_CC13_MAIN_MEMLPLDO2VDDB_OFF (1u << 6u) 2366 #define PMU_CC13_MAIN_MEMLPLDO2VDDRET_OFF (1u << 7u) 2367 2368 #define PMU_CC13_AUX_CBUCK2VDDB_OFF (1u << 8u) 2369 #define PMU_CC13_AUX_MEMLPLDO2VDDB_OFF (1u << 10u) 2370 #define PMU_CC13_AUX_MEMLPLDO2VDDRET_OFF (1u << 11u) 2371 #define PMU_CC13_AUX_CBUCK2VDDRET_OFF (1u << 12u) 2372 #define PMU_CC13_CMN_MEMLPLDO2VDDRET_ON (1u << 18u) 2373 2374 /* HW4368-331 */ 2375 #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF0 (1u << 13u) 2376 #define PMU_CC13_MAIN_ALWAYS_USE_COHERENT_IF1 (1u << 14u) 2377 #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF0 (1u << 15u) 2378 #define PMU_CC13_AUX_ALWAYS_USE_COHERENT_IF1 (1u << 19u) 2379 2380 #define PMU_CC13_LHL_TIMER_SELECT (1u << 23u) 2381 2382 #define PMU_CC13_4369_LHL_TIMER_SELECT (1u << 23u) 2383 #define PMU_CC13_4378_LHL_TIMER_SELECT (1u << 23u) 2384 2385 #define PMU_CC13_4387_ENAB_RADIO_REG_CLK (1u << 9u) 2386 #define PMU_CC13_4387_LHL_TIMER_SELECT (1u << 23u) 2387 2388 #define PMU_CHIPCTL14 14 2389 #define PMU_CHIPCTL15 15 2390 #define PMU_CHIPCTL16 16 2391 #define PMU_CC16_CLK4M_DIS (1 << 4) 2392 #define PMU_CC16_FF_ZERO_ADJ (4 << 5) 2393 2394 /* PMU chip control17 register */ 2395 #define PMU_CHIPCTL17 17u 2396 2397 #define PMU_CC17_SCAN_DIG_SR_CLK_SHIFT (2u) 2398 #define PMU_CC17_SCAN_DIG_SR_CLK_MASK (3u << 2u) 2399 #define PMU_CC17_SCAN_CBUCK2VDDB_OFF (1u << 8u) 2400 #define PMU_CC17_SCAN_MEMLPLDO2VDDB_OFF (1u << 10u) 2401 #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_OFF (1u << 11u) 2402 #define PMU_CC17_SCAN_CBUCK2VDDB_ON (1u << 24u) 2403 #define PMU_CC17_SCAN_MEMLPLDO2VDDB_ON (1u << 26u) 2404 #define PMU_CC17_SCAN_MEMLPLDO2VDDRET_ON (1u << 27u) 2405 2406 #define SCAN_DIG_SR_CLK_80_MHZ (0) /* 80 MHz */ 2407 #define SCAN_DIG_SR_CLK_53P35_MHZ (1u) /* 53.35 MHz */ 2408 #define SCAN_DIG_SR_CLK_40_MHZ (2u) /* 40 MHz */ 2409 2410 /* PMU chip control18 register */ 2411 #define PMU_CHIPCTL18 18u 2412 2413 /* Expiry time for wl_SSReset if P channel sleep handshake is not through */ 2414 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_OFF (1u << 1u) 2415 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_MASK (7u << 1u) 2416 2417 #define PMU_CC18_WL_P_CHAN_TIMER_SEL_8ms 7u /* (2^(7+1))*32us = 8ms */ 2418 2419 /* Enable wl booker to force a P channel sleep handshake upon assertion of wl_SSReset */ 2420 #define PMU_CC18_WL_BOOKER_FORCEPWRDWN_EN (1u << 4u) 2421 2422 /* PMU chip control 19 register */ 2423 #define PMU_CHIPCTL19 19u 2424 2425 #define PMU_CC19_ASYNC_ATRESETMN (1u << 9u) 2426 2427 #define PMU_CHIPCTL23 23 2428 #define PMU_CC23_MACPHYCLK_MASK (1u << 31u) 2429 2430 #define PMU_CC23_AT_CLK0_ON (1u << 14u) 2431 #define PMU_CC23_AT_CLK1_ON (1u << 15u) 2432 2433 /* PMU chip control14 register */ 2434 #define PMU_CC14_MAIN_VDDB2VDDRET_UP_DLY_MASK (0xF) 2435 #define PMU_CC14_MAIN_VDDB2VDD_UP_DLY_MASK (0xF << 4) 2436 #define PMU_CC14_AUX_VDDB2VDDRET_UP_DLY_MASK (0xF << 8) 2437 #define PMU_CC14_AUX_VDDB2VDD_UP_DLY_MASK (0xF << 12) 2438 #define PMU_CC14_PCIE_VDDB2VDDRET_UP_DLY_MASK (0xF << 16) 2439 #define PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK (0xF << 20) 2440 2441 /* PMU chip control15 register */ 2442 #define PMU_CC15_PCIE_VDDB_CURRENT_LIMIT_DELAY_MASK (0xFu << 4u) 2443 #define PMU_CC15_PCIE_VDDB_FORCE_RPS_PWROK_DELAY_MASK (0xFu << 8u) 2444 2445 /* PMU corerev and chip specific PLL controls. 2446 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 2447 * to differentiate different PLLs controlled by the same PMU rev. 2448 */ 2449 /* pllcontrol registers */ 2450 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 2451 #define PMU0_PLL0_PLLCTL0 0 2452 #define PMU0_PLL0_PC0_PDIV_MASK 1 2453 #define PMU0_PLL0_PC0_PDIV_FREQ 25000 2454 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 2455 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 2456 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 2457 2458 /* PC0_DIV_ARM for PLLOUT_ARM */ 2459 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 2460 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 2461 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 2462 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 2463 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 2464 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 2465 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 2466 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 2467 2468 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 2469 #define PMU0_PLL0_PLLCTL1 1 2470 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 2471 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 2472 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 2473 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 2474 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 2475 2476 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 2477 #define PMU0_PLL0_PLLCTL2 2 2478 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 2479 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 2480 2481 /* pllcontrol registers */ 2482 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 2483 #define PMU1_PLL0_PLLCTL0 0 2484 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 2485 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 2486 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 2487 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 2488 2489 /* m<x>div */ 2490 #define PMU1_PLL0_PLLCTL1 1 2491 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 2492 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 2493 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 2494 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 2495 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 2496 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 2497 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 2498 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 2499 #define PMU1_PLL0_PC1_M4DIV_BY_9 9 2500 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 2501 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 2502 #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C 2503 #define PMU1_PLL0_PC1_M2_M4DIV_MASK 0xff00ff00 2504 #define PMU1_PLL0_PC1_HOLD_LOAD_CH 0x28 2505 2506 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 2507 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 2508 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 2509 2510 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 2511 #define PMU1_PLL0_PLLCTL2 2 2512 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 2513 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 2514 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc 2515 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 2516 #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f 2517 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 2518 #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a 2519 #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c 2520 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 2521 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 2522 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 2523 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 2524 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 2525 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 2526 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 2527 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 2528 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 2529 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 2530 2531 /* ndiv_frac */ 2532 #define PMU1_PLL0_PLLCTL3 3 2533 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 2534 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 2535 2536 /* pll_ctrl */ 2537 #define PMU1_PLL0_PLLCTL4 4 2538 2539 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 2540 #define PMU1_PLL0_PLLCTL5 5 2541 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 2542 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 2543 #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000 2544 #define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 24 2545 #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000 2546 2547 #define PMU1_PLL0_PLLCTL6 6 2548 #define PMU1_PLL0_PLLCTL7 7 2549 #define PMU1_PLL0_PLLCTL8 8 2550 2551 #define PMU1_PLLCTL8_OPENLOOP_MASK (1 << 1) 2552 2553 #define PMU1_PLL0_PLLCTL9 9 2554 2555 #define PMU1_PLL0_PLLCTL10 10 2556 2557 /* PMU rev 2 control words */ 2558 #define PMU2_PHY_PLL_PLLCTL 4 2559 #define PMU2_SI_PLL_PLLCTL 10 2560 2561 /* PMU rev 2 */ 2562 /* pllcontrol registers */ 2563 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 2564 #define PMU2_PLL_PLLCTL0 0 2565 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 2566 #define PMU2_PLL_PC0_P1DIV_SHIFT 20 2567 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 2568 #define PMU2_PLL_PC0_P2DIV_SHIFT 24 2569 2570 /* m<x>div */ 2571 #define PMU2_PLL_PLLCTL1 1 2572 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 2573 #define PMU2_PLL_PC1_M1DIV_SHIFT 0 2574 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 2575 #define PMU2_PLL_PC1_M2DIV_SHIFT 8 2576 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 2577 #define PMU2_PLL_PC1_M3DIV_SHIFT 16 2578 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 2579 #define PMU2_PLL_PC1_M4DIV_SHIFT 24 2580 2581 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 2582 #define PMU2_PLL_PLLCTL2 2 2583 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 2584 #define PMU2_PLL_PC2_M5DIV_SHIFT 0 2585 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 2586 #define PMU2_PLL_PC2_M6DIV_SHIFT 8 2587 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 2588 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 2589 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 2590 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 2591 2592 /* ndiv_frac */ 2593 #define PMU2_PLL_PLLCTL3 3 2594 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 2595 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 2596 2597 /* pll_ctrl */ 2598 #define PMU2_PLL_PLLCTL4 4 2599 2600 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 2601 #define PMU2_PLL_PLLCTL5 5 2602 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 2603 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 2604 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 2605 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 2606 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 2607 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 2608 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 2609 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 2610 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 2611 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 2612 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 2613 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 2614 2615 /* PMU rev 5 (& 6) */ 2616 #define PMU5_PLL_P1P2_OFF 0 2617 #define PMU5_PLL_P1_MASK 0x0f000000 2618 #define PMU5_PLL_P1_SHIFT 24 2619 #define PMU5_PLL_P2_MASK 0x00f00000 2620 #define PMU5_PLL_P2_SHIFT 20 2621 #define PMU5_PLL_M14_OFF 1 2622 #define PMU5_PLL_MDIV_MASK 0x000000ff 2623 #define PMU5_PLL_MDIV_WIDTH 8 2624 #define PMU5_PLL_NM5_OFF 2 2625 #define PMU5_PLL_NDIV_MASK 0xfff00000 2626 #define PMU5_PLL_NDIV_SHIFT 20 2627 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 2628 #define PMU5_PLL_NDIV_MODE_SHIFT 17 2629 #define PMU5_PLL_FMAB_OFF 3 2630 #define PMU5_PLL_MRAT_MASK 0xf0000000 2631 #define PMU5_PLL_MRAT_SHIFT 28 2632 #define PMU5_PLL_ABRAT_MASK 0x08000000 2633 #define PMU5_PLL_ABRAT_SHIFT 27 2634 #define PMU5_PLL_FDIV_MASK 0x07ffffff 2635 #define PMU5_PLL_PLLCTL_OFF 4 2636 #define PMU5_PLL_PCHI_OFF 5 2637 #define PMU5_PLL_PCHI_MASK 0x0000003f 2638 2639 /* pmu XtalFreqRatio */ 2640 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 2641 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 2642 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 2643 2644 /* Divider allocation in 5357 */ 2645 #define PMU5_MAINPLL_CPU 1 2646 #define PMU5_MAINPLL_MEM 2 2647 #define PMU5_MAINPLL_SI 3 2648 2649 #define PMU7_PLL_PLLCTL7 7 2650 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 2651 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24 2652 #define PMU7_PLL_CTL7_M4DIV_BY_6 6 2653 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc 2654 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 2655 #define PMU7_PLL_PLLCTL8 8 2656 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff 2657 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0 2658 #define PMU7_PLL_CTL8_M5DIV_BY_8 8 2659 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc 2660 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 2661 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 2662 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8 2663 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc 2664 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 2665 #define PMU7_PLL_PLLCTL11 11 2666 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00 2667 #define PMU7_PLL_PLLCTL11_VAL 0x22222200 2668 2669 /* PMU rev 15 */ 2670 #define PMU15_PLL_PLLCTL0 0 2671 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 2672 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0 2673 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC 2674 #define PMU15_PLL_PC0_FREQTGT_SHIFT 2 2675 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 2676 #define PMU15_PLL_PC0_PRESCALE_SHIFT 22 2677 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 2678 #define PMU15_PLL_PC0_KPCTRL_SHIFT 24 2679 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 2680 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 2681 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 2682 #define PMU15_PLL_PC0_FDCMODE_SHIFT 30 2683 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 2684 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 2685 2686 #define PMU15_PLL_PLLCTL1 1 2687 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060 2688 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5 2689 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040 2690 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6 2691 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80 2692 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7 2693 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000 2694 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17 2695 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000 2696 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26 2697 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000 2698 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28 2699 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000 2700 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30 2701 2702 #define PMU15_PLL_PLLCTL2 2 2703 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001 2704 #define PMU15_PLL_PC2_CTEN_SHIFT 0 2705 2706 #define PMU15_PLL_PLLCTL3 3 2707 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001 2708 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0 2709 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000 2710 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25 2711 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01 2712 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0 2713 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02 2714 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1 2715 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04 2716 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2 2717 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18 2718 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3 2719 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60 2720 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5 2721 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0 2722 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1 2723 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2 2724 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3 2725 2726 #define PMU15_PLL_PLLCTL4 4 2727 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007 2728 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0 2729 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038 2730 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3 2731 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0 2732 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6 2733 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00 2734 #define PMU15_PLL_PC4_DBGMODE_SHIFT 9 2735 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000 2736 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12 2737 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000 2738 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13 2739 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000 2740 #define PMU15_PLL_PC4_DINPOL_SHIFT 20 2741 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000 2742 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21 2743 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000 2744 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22 2745 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000 2746 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23 2747 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000 2748 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24 2749 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000 2750 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25 2751 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000 2752 #define PMU15_PLL_PC4_TEST_EN_SHIFT 26 2753 2754 #define PMU15_PLL_PLLCTL5 5 2755 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF 2756 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0 2757 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000 2758 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20 2759 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000 2760 #define PMU15_PLL_PC5_PRESCALE_SHIFT 27 2761 2762 #define PMU15_PLL_PLLCTL6 6 2763 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF 2764 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0 2765 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000 2766 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20 2767 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000 2768 #define PMU15_PLL_PC6_PRESCALE_SHIFT 27 2769 2770 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1 2771 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5 2772 #define PMU15_ARM_96MHZ 96000000 /**< 96 Mhz */ 2773 #define PMU15_ARM_98MHZ 98400000 /**< 98.4 Mhz */ 2774 #define PMU15_ARM_97MHZ 97000000 /**< 97 Mhz */ 2775 2776 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070 2777 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4 2778 2779 #define PMU17_PLLCTL2_NDIV_MODE_INT 0 2780 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1 2781 #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2 2782 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3 2783 2784 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0 2785 #define PMU17_PLLCTL0_BBPLL_DRST 3 2786 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8 2787 2788 /* PLL usage in 4716/47162 */ 2789 #define PMU4716_MAINPLL_PLL0 12 2790 2791 /* PLL Usages for 4368 */ 2792 #define PMU4368_P1DIV_LO_SHIFT 0 2793 #define PMU4368_P1DIV_HI_SHIFT 2 2794 2795 #define PMU4368_PLL1_PC4_P1DIV_MASK 0xC0000000 2796 #define PMU4368_PLL1_PC4_P1DIV_SHIFT 30 2797 #define PMU4368_PLL1_PC5_P1DIV_MASK 0x00000003 2798 #define PMU4368_PLL1_PC5_P1DIV_SHIFT 0 2799 #define PMU4368_PLL1_PC5_NDIV_INT_MASK 0x00000ffc 2800 #define PMU4368_PLL1_PC5_NDIV_INT_SHIFT 2 2801 #define PMU4368_PLL1_PC5_NDIV_FRAC_MASK 0xfffff000 2802 #define PMU4368_PLL1_PC5_NDIV_FRAC_SHIFT 12 2803 2804 /* PLL usage in 4369 */ 2805 #define PMU4369_PLL0_PC2_PDIV_MASK 0x000f0000 2806 #define PMU4369_PLL0_PC2_PDIV_SHIFT 16 2807 #define PMU4369_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 2808 #define PMU4369_PLL0_PC2_NDIV_INT_SHIFT 20 2809 #define PMU4369_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff 2810 #define PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT 0 2811 #define PMU4369_PLL1_PC5_P1DIV_MASK 0xc0000000 2812 #define PMU4369_PLL1_PC5_P1DIV_SHIFT 30 2813 #define PMU4369_PLL1_PC6_P1DIV_MASK 0x00000003 2814 #define PMU4369_PLL1_PC6_P1DIV_SHIFT 0 2815 #define PMU4369_PLL1_PC6_NDIV_INT_MASK 0x00000ffc 2816 #define PMU4369_PLL1_PC6_NDIV_INT_SHIFT 2 2817 #define PMU4369_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000 2818 #define PMU4369_PLL1_PC6_NDIV_FRAC_SHIFT 12 2819 2820 #define PMU4369_P1DIV_LO_SHIFT 0 2821 #define PMU4369_P1DIV_HI_SHIFT 2 2822 2823 #define PMU4369_PLL6VAL_P1DIV 4 2824 #define PMU4369_PLL6VAL_P1DIV_BIT3_2 1 2825 #define PMU4369_PLL6VAL_PRE_SCALE (1 << 17) 2826 #define PMU4369_PLL6VAL_POST_SCALE (1 << 3) 2827 2828 /* PLL usage in 4378 2829 * Temporay setting, update is needed. 2830 */ 2831 #define PMU4378_PLL0_PC2_P1DIV_MASK 0x000f0000 2832 #define PMU4378_PLL0_PC2_P1DIV_SHIFT 16 2833 #define PMU4378_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 2834 #define PMU4378_PLL0_PC2_NDIV_INT_SHIFT 20 2835 2836 /* PLL usage in 4387 */ 2837 #define PMU4387_PLL0_PC1_ICH2_MDIV_SHIFT 18 2838 #define PMU4387_PLL0_PC1_ICH2_MDIV_MASK 0x07FC0000 2839 #define PMU4387_PLL0_PC2_ICH3_MDIV_MASK 0x000001ff 2840 2841 /* PLL usage in 4388 */ 2842 #define PMU4388_APLL_NDIV_P 0x154u 2843 #define PMU4388_APLL_NDIV_Q 0x1ffu 2844 #define PMU4388_APLL_PDIV 0x3u 2845 #define PMU4388_ARMPLL_I_NDIV_INT_MASK 0x01ff8000u 2846 #define PMU4388_ARMPLL_I_NDIV_INT_SHIFT 15u 2847 2848 /* PLL usage in 4389 */ 2849 #define PMU4389_APLL_NDIV_P 0x154u 2850 #define PMU4389_APLL_NDIV_Q 0x1ffu 2851 #define PMU4389_APLL_PDIV 0x3u 2852 #define PMU4389_ARMPLL_I_NDIV_INT_MASK 0x01ff8000u 2853 #define PMU4389_ARMPLL_I_NDIV_INT_SHIFT 15u 2854 2855 /* 5357 Chip specific ChipControl register bits */ 2856 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 2857 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 2858 #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ 2859 /* 43217 Chip specific ChipControl register bits */ 2860 #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */ 2861 #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */ 2862 2863 #define PMU1_PLL0_CHIPCTL0 0 2864 #define PMU1_PLL0_CHIPCTL1 1 2865 #define PMU1_PLL0_CHIPCTL2 2 2866 2867 #define SOCDEVRAM_BP_ADDR 0x1E000000 2868 #define SOCDEVRAM_ARM_ADDR 0x00800000 2869 2870 #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0 2871 #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 2872 #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 2873 #define PMU_VREG0_CBUCKFSW_ADJ_SHIFT 7 2874 #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F 2875 #define PMU_VREG0_RAMP_SEL_SHIFT 13 2876 #define PMU_VREG0_RAMP_SEL_MASK 0x7 2877 #define PMU_VREG0_VFB_RSEL_SHIFT 17 2878 #define PMU_VREG0_VFB_RSEL_MASK 3 2879 2880 #define PMU_VREG4_ADDR 4 2881 2882 #define PMU_VREG4_CLDO_PWM_SHIFT 4 2883 #define PMU_VREG4_CLDO_PWM_MASK 0x7 2884 2885 #define PMU_VREG4_LPLDO1_SHIFT 15 2886 #define PMU_VREG4_LPLDO1_MASK 0x7 2887 #define PMU_VREG4_LPLDO1_1p20V 0 2888 #define PMU_VREG4_LPLDO1_1p15V 1 2889 #define PMU_VREG4_LPLDO1_1p10V 2 2890 #define PMU_VREG4_LPLDO1_1p25V 3 2891 #define PMU_VREG4_LPLDO1_1p05V 4 2892 #define PMU_VREG4_LPLDO1_1p00V 5 2893 #define PMU_VREG4_LPLDO1_0p95V 6 2894 #define PMU_VREG4_LPLDO1_0p90V 7 2895 2896 #define PMU_VREG4_LPLDO2_LVM_SHIFT 18 2897 #define PMU_VREG4_LPLDO2_LVM_MASK 0x7 2898 #define PMU_VREG4_LPLDO2_HVM_SHIFT 21 2899 #define PMU_VREG4_LPLDO2_HVM_MASK 0x7 2900 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f 2901 #define PMU_VREG4_LPLDO2_1p00V 0 2902 #define PMU_VREG4_LPLDO2_1p15V 1 2903 #define PMU_VREG4_LPLDO2_1p20V 2 2904 #define PMU_VREG4_LPLDO2_1p10V 3 2905 #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */ 2906 2907 #define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 2908 #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 2909 2910 #define PMU_VREG5_ADDR 5 2911 #define PMU_VREG5_HSICAVDD_PD_SHIFT 6 2912 #define PMU_VREG5_HSICAVDD_PD_MASK 0x1 2913 #define PMU_VREG5_HSICDVDD_PD_SHIFT 11 2914 #define PMU_VREG5_HSICDVDD_PD_MASK 0x1 2915 2916 /* 43228 chipstatus reg bits */ 2917 #define CST43228_OTP_PRESENT 0x2 2918 2919 /* 4360 Chip specific ChipControl register bits */ 2920 /* 43602 uses these ChipControl definitions as well */ 2921 #define CCTRL4360_I2C_MODE (1 << 0) 2922 #define CCTRL4360_UART_MODE (1 << 1) 2923 #define CCTRL4360_SECI_MODE (1 << 2) 2924 #define CCTRL4360_BTSWCTRL_MODE (1 << 3) 2925 #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) 2926 #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) 2927 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) 2928 #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) 2929 #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) 2930 #define CCTRL4360_BT_LGCY_MODE (1 << 9) 2931 #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) 2932 #define CCTRL4360_SECI_ON_GPIO01 (1 << 24) 2933 2934 /* 4360 Chip specific Regulator Control register bits */ 2935 #define RCTRL4360_RFLDO_PWR_DOWN (1 << 1) 2936 2937 /* 4360 PMU resources and chip status bits */ 2938 #define RES4360_REGULATOR 0 2939 #define RES4360_ILP_AVAIL 1 2940 #define RES4360_ILP_REQ 2 2941 #define RES4360_XTAL_LDO_PU 3 2942 #define RES4360_XTAL_PU 4 2943 #define RES4360_ALP_AVAIL 5 2944 #define RES4360_BBPLLPWRSW_PU 6 2945 #define RES4360_HT_AVAIL 7 2946 #define RES4360_OTP_PU 8 2947 #define RES4360_AVB_PLL_PWRSW_PU 9 2948 #define RES4360_PCIE_TL_CLK_AVAIL 10 2949 2950 #define CST4360_XTAL_40MZ 0x00000001 2951 #define CST4360_SFLASH 0x00000002 2952 #define CST4360_SPROM_PRESENT 0x00000004 2953 #define CST4360_SFLASH_TYPE 0x00000004 2954 #define CST4360_OTP_ENABLED 0x00000008 2955 #define CST4360_REMAP_ROM 0x00000010 2956 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060 2957 #define CST4360_RSRC_INIT_MODE_SHIFT 5 2958 #define CST4360_ILP_DIVEN 0x00000080 2959 #define CST4360_MODE_USB 0x00000100 2960 #define CST4360_SPROM_SIZE_MASK 0x00000600 2961 #define CST4360_SPROM_SIZE_SHIFT 9 2962 #define CST4360_BBPLL_LOCK 0x00000800 2963 #define CST4360_AVBBPLL_LOCK 0x00001000 2964 #define CST4360_USBBBPLL_LOCK 0x00002000 2965 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2966 CST4360_RSRC_INIT_MODE_SHIFT) 2967 2968 #define CCTRL_4360_UART_SEL 0x2 2969 2970 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2971 CST4360_RSRC_INIT_MODE_SHIFT) 2972 2973 #define PMU4360_CC1_GPIO7_OVRD (1<<23) /* GPIO7 override */ 2974 2975 /* 43602 PMU resources based on pmu_params.xls version v0.95 */ 2976 #define RES43602_LPLDO_PU 0 2977 #define RES43602_REGULATOR 1 2978 #define RES43602_PMU_SLEEP 2 2979 #define RES43602_RSVD_3 3 2980 #define RES43602_XTALLDO_PU 4 2981 #define RES43602_SERDES_PU 5 2982 #define RES43602_BBPLL_PWRSW_PU 6 2983 #define RES43602_SR_CLK_START 7 2984 #define RES43602_SR_PHY_PWRSW 8 2985 #define RES43602_SR_SUBCORE_PWRSW 9 2986 #define RES43602_XTAL_PU 10 2987 #define RES43602_PERST_OVR 11 2988 #define RES43602_SR_CLK_STABLE 12 2989 #define RES43602_SR_SAVE_RESTORE 13 2990 #define RES43602_SR_SLEEP 14 2991 #define RES43602_LQ_START 15 2992 #define RES43602_LQ_AVAIL 16 2993 #define RES43602_WL_CORE_RDY 17 2994 #define RES43602_ILP_REQ 18 2995 #define RES43602_ALP_AVAIL 19 2996 #define RES43602_RADIO_PU 20 2997 #define RES43602_RFLDO_PU 21 2998 #define RES43602_HT_START 22 2999 #define RES43602_HT_AVAIL 23 3000 #define RES43602_MACPHY_CLKAVAIL 24 3001 #define RES43602_PARLDO_PU 25 3002 #define RES43602_RSVD_26 26 3003 3004 /* 43602 chip status bits */ 3005 #define CST43602_SPROM_PRESENT (1<<1) 3006 #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */ 3007 #define CST43602_BBPLL_LOCK (1<<11) 3008 #define CST43602_RF_LDO_OUT_OK (1<<15) /* RF LDO output OK */ 3009 3010 #define PMU43602_CC1_GPIO12_OVRD (1<<28) /* GPIO12 override */ 3011 3012 #define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1) /* creates gated_pcie_wake, pmu_wakeup logic */ 3013 #define PMU43602_CC2_PCIE_PERST_L_WAKE_EN (1<<2) /* creates gated_pcie_wake, pmu_wakeup logic */ 3014 #define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3) 3015 #define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */ 3016 #define PMU43602_CC2_PERST_L_EXTEND_EN (1<<9) /* extend perst_l until rsc PERST_OVR comes up */ 3017 #define PMU43602_CC2_FORCE_EXT_LPO (1<<19) /* 1=ext LPO clock is the final LPO clock */ 3018 #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */ 3019 3020 #define CC_SR1_43602_SR_ASM_ADDR (0x0) 3021 3022 /* PLL CTL register values for open loop, used during S/R operation */ 3023 #define PMU43602_PLL_CTL6_VAL 0x68000528 3024 #define PMU43602_PLL_CTL7_VAL 0x6 3025 3026 #define PMU43602_CC3_ARMCR4_DBG_CLK (1 << 29) 3027 3028 #define CC_SR0_43602_SR_ENG_EN_MASK 0x1 3029 #define CC_SR0_43602_SR_ENG_EN_SHIFT 0 3030 3031 /* GCI function sel values */ 3032 #define CC_FNSEL_HWDEF (0u) 3033 #define CC_FNSEL_SAMEASPIN (1u) 3034 #define CC_FNSEL_GPIO0 (2u) 3035 #define CC_FNSEL_GPIO1 (3u) 3036 #define CC_FNSEL_GCI0 (4u) 3037 #define CC_FNSEL_GCI1 (5u) 3038 #define CC_FNSEL_UART (6u) 3039 #define CC_FNSEL_SFLASH (7u) 3040 #define CC_FNSEL_SPROM (8u) 3041 #define CC_FNSEL_MISC0 (9u) 3042 #define CC_FNSEL_MISC1 (10u) 3043 #define CC_FNSEL_MISC2 (11u) 3044 #define CC_FNSEL_IND (12u) 3045 #define CC_FNSEL_PDN (13u) 3046 #define CC_FNSEL_PUP (14u) 3047 #define CC_FNSEL_TRI (15u) 3048 3049 /* 4387 GCI function sel values */ 3050 #define CC4387_FNSEL_FUART (3u) 3051 #define CC4387_FNSEL_DBG_UART (6u) 3052 #define CC4387_FNSEL_SPI (7u) 3053 3054 /* Indices of PMU voltage regulator registers */ 3055 #define PMU_VREG_0 (0u) 3056 #define PMU_VREG_1 (1u) 3057 #define PMU_VREG_2 (2u) 3058 #define PMU_VREG_3 (3u) 3059 #define PMU_VREG_4 (4u) 3060 #define PMU_VREG_5 (5u) 3061 #define PMU_VREG_6 (6u) 3062 #define PMU_VREG_7 (7u) 3063 #define PMU_VREG_8 (8u) 3064 #define PMU_VREG_9 (9u) 3065 #define PMU_VREG_10 (10u) 3066 #define PMU_VREG_11 (11u) 3067 #define PMU_VREG_12 (12u) 3068 #define PMU_VREG_13 (13u) 3069 #define PMU_VREG_14 (14u) 3070 #define PMU_VREG_15 (15u) 3071 #define PMU_VREG_16 (16u) 3072 3073 /* 43012 Chipcommon ChipStatus bits */ 3074 #define CST43012_FLL_LOCK (1 << 13) 3075 /* 43012 resources - End */ 3076 3077 /* 43012 related Cbuck modes */ 3078 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE0 0x00001c03 3079 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE0 0x00492490 3080 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE1 0x00001c03 3081 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE1 0x00490410 3082 3083 /* 43012 related dynamic cbuck mode mask */ 3084 #define PMU_43012_VREG8_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFC07 3085 #define PMU_43012_VREG9_DYNAMIC_CBUCK_MODE_MASK 0xFFFFFFFF 3086 3087 /* 4369 related VREG masks */ 3088 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u) 3089 #define PMU_4369_VREG_5_MISCLDO_POWER_UP_SHIFT 11u 3090 #define PMU_4369_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u) 3091 #define PMU_4369_VREG_5_LPLDO_POWER_UP_SHIFT 27u 3092 #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(23u, 20u) 3093 #define PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_SHIFT 20u 3094 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28) 3095 #define PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT 28u 3096 3097 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u) 3098 #define PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT 3u 3099 3100 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u) 3101 #define PMU_4369_VREG_7_PMU_FORCE_HP_MODE_SHIFT 27u 3102 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u) 3103 #define PMU_4369_VREG_7_WL_PMU_LP_MODE_SHIFT 28u 3104 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u) 3105 #define PMU_4369_VREG_7_WL_PMU_LV_MODE_SHIFT 29u 3106 3107 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0) 3108 #define PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT 0u 3109 3110 #define PMU_4369_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9) 3111 #define PMU_4369_VREG13_RSRC_EN0_ASR_SHIFT 9u 3112 #define PMU_4369_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10) 3113 #define PMU_4369_VREG13_RSRC_EN1_ASR_SHIFT 10u 3114 #define PMU_4369_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11) 3115 #define PMU_4369_VREG13_RSRC_EN2_ASR_SHIFT 11u 3116 3117 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u) 3118 #define PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT 23u 3119 3120 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0) 3121 #define PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT 0u 3122 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15) 3123 #define PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT 15u 3124 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18) 3125 #define PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT 18u 3126 #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21) 3127 #define PMU_4369_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u 3128 3129 /* 4362 related VREG masks */ 3130 #define PMU_4362_VREG_5_MISCLDO_POWER_UP_MASK (1u << 11u) 3131 #define PMU_4362_VREG_5_MISCLDO_POWER_UP_SHIFT (11u) 3132 #define PMU_4362_VREG_5_LPLDO_POWER_UP_MASK (1u << 27u) 3133 #define PMU_4362_VREG_5_LPLDO_POWER_UP_SHIFT (27u) 3134 #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_MASK BCM_MASK32(31, 28) 3135 #define PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT (28u) 3136 #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_MASK (1u << 3u) 3137 #define PMU_4362_VREG_6_MEMLPLDO_POWER_UP_SHIFT (3u) 3138 3139 #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_MASK (1u << 27u) 3140 #define PMU_4362_VREG_7_PMU_FORCE_HP_MODE_SHIFT (27u) 3141 #define PMU_4362_VREG_7_WL_PMU_LP_MODE_MASK (1u << 28u) 3142 #define PMU_4362_VREG_7_WL_PMU_LP_MODE_SHIFT (28u) 3143 #define PMU_4362_VREG_7_WL_PMU_LV_MODE_MASK (1u << 29u) 3144 #define PMU_4362_VREG_7_WL_PMU_LV_MODE_SHIFT (29u) 3145 3146 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_MASK BCM_MASK32(4, 0) 3147 #define PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT (0u) 3148 3149 #define PMU_4362_VREG8_ASR_OVADJ_PFM_MASK BCM_MASK32(9, 5) 3150 #define PMU_4362_VREG8_ASR_OVADJ_PFM_SHIFT (5u) 3151 3152 #define PMU_4362_VREG8_ASR_OVADJ_PWM_MASK BCM_MASK32(14, 10) 3153 #define PMU_4362_VREG8_ASR_OVADJ_PWM_SHIFT (10u) 3154 3155 #define PMU_4362_VREG13_RSRC_EN0_ASR_MASK BCM_MASK32(9, 9) 3156 #define PMU_4362_VREG13_RSRC_EN0_ASR_SHIFT 9u 3157 #define PMU_4362_VREG13_RSRC_EN1_ASR_MASK BCM_MASK32(10, 10) 3158 #define PMU_4362_VREG13_RSRC_EN1_ASR_SHIFT 10u 3159 #define PMU_4362_VREG13_RSRC_EN2_ASR_MASK BCM_MASK32(11, 11) 3160 #define PMU_4362_VREG13_RSRC_EN2_ASR_SHIFT 11u 3161 3162 #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_MASK (1u << 23u) 3163 #define PMU_4362_VREG14_RSRC_EN_CSR_MASK0_SHIFT (23u) 3164 3165 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_MASK BCM_MASK32(2, 0) 3166 #define PMU_4362_VREG16_RSRC0_CBUCK_MODE_SHIFT (0u) 3167 #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_MASK BCM_MASK32(17, 15) 3168 #define PMU_4362_VREG16_RSRC0_ABUCK_MODE_SHIFT (15u) 3169 #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_MASK BCM_MASK32(20, 18) 3170 #define PMU_4362_VREG16_RSRC1_ABUCK_MODE_SHIFT (18u) 3171 #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_MASK BCM_MASK32(23, 21) 3172 #define PMU_4362_VREG16_RSRC2_ABUCK_MODE_SHIFT 21u 3173 3174 #define VREG0_4378_CSR_VOLT_ADJ_PWM_MASK 0x00001F00u 3175 #define VREG0_4378_CSR_VOLT_ADJ_PWM_SHIFT 8u 3176 #define VREG0_4378_CSR_VOLT_ADJ_PFM_MASK 0x0003E000u 3177 #define VREG0_4378_CSR_VOLT_ADJ_PFM_SHIFT 13u 3178 #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_MASK 0x007C0000u 3179 #define VREG0_4378_CSR_VOLT_ADJ_LP_PFM_SHIFT 18u 3180 #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_MASK 0x07800000u 3181 #define VREG0_4378_CSR_OUT_VOLT_TRIM_ADJ_SHIFT 23u 3182 3183 #define PMU_4387_VREG1_CSR_OVERI_DIS_MASK (1u << 22u) 3184 #define PMU_4387_VREG6_WL_PMU_LV_MODE_MASK (0x00000002u) 3185 #define PMU_4387_VREG6_MEMLDO_PU_MASK (0x00000008u) 3186 #define PMU_4387_VREG8_ASR_OVERI_DIS_MASK (1u << 7u) 3187 3188 #define PMU_4388_VREG6_WL_PMU_LV_MODE_SHIFT (1u) 3189 #define PMU_4388_VREG6_WL_PMU_LV_MODE_MASK (1u << PMU_4388_VREG6_WL_PMU_LV_MODE_SHIFT) 3190 #define PMU_4388_VREG6_MEMLDO_PU_SHIFT (3u) 3191 #define PMU_4388_VREG6_MEMLDO_PU_MASK (1u << PMU_4388_VREG6_MEMLDO_PU_SHIFT) 3192 3193 #define PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT (1u) 3194 #define PMU_4389_VREG6_WL_PMU_LV_MODE_MASK (1u << PMU_4389_VREG6_WL_PMU_LV_MODE_SHIFT) 3195 #define PMU_4389_VREG6_MEMLDO_PU_SHIFT (3u) 3196 #define PMU_4389_VREG6_MEMLDO_PU_MASK (1u << PMU_4389_VREG6_MEMLDO_PU_SHIFT) 3197 3198 #define PMU_VREG13_ASR_OVADJ_PWM_MASK (0x001F0000u) 3199 #define PMU_VREG13_ASR_OVADJ_PWM_SHIFT (16u) 3200 3201 #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_MASK (1u << 18u) 3202 #define PMU_VREG14_RSRC_EN_ASR_PWM_PFM_SHIFT (18u) 3203 3204 #define CSR_VOLT_ADJ_PWM_4378 (0x17u) 3205 #define CSR_VOLT_ADJ_PFM_4378 (0x17u) 3206 #define CSR_VOLT_ADJ_LP_PFM_4378 (0x17u) 3207 #define CSR_OUT_VOLT_TRIM_ADJ_4378 (0xEu) 3208 3209 #ifdef WL_INITVALS 3210 #define ABUCK_VOLT_SW_DEFAULT_4387 (wliv_pmu_abuck_volt) /* 1.00V */ 3211 #define CBUCK_VOLT_SW_DEFAULT_4387 (wliv_pmu_cbuck_volt) /* 0.68V */ 3212 #define CBUCK_VOLT_NON_LVM (wliv_pmu_cbuck_volt_non_lvm) /* 0.76V */ 3213 #else 3214 #define ABUCK_VOLT_SW_DEFAULT_4387 (0x1Fu) /* 1.00V */ 3215 #define CBUCK_VOLT_SW_DEFAULT_4387 (0xFu) /* 0.68V */ 3216 #define CBUCK_VOLT_NON_LVM (0x13u) /* 0.76V */ 3217 #endif 3218 3219 #define CC_GCI1_REG (0x1) 3220 3221 #define FORCE_CLK_ON 1 3222 #define FORCE_CLK_OFF 0 3223 3224 #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0) 3225 #define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ (1) 3226 #define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ 8 3227 #define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ 6 3228 3229 /* 4369 Related */ 3230 3231 /* 3232 * PMU VREG Definitions: 3233 * http://confluence.broadcom.com/display/WLAN/BCM4369+PMU+Vreg+Control+Register 3234 */ 3235 /* PMU VREG4 */ 3236 #define PMU_28NM_VREG4_WL_LDO_CNTL_EN (0x1 << 10) 3237 3238 /* PMU VREG6 */ 3239 #define PMU_28NM_VREG6_BTLDO3P3_PU (0x1 << 12) 3240 #define PMU_4387_VREG6_BTLDO3P3_PU (0x1 << 8) 3241 3242 /* PMU resources */ 3243 #define RES4347_XTAL_PU 6 3244 #define RES4347_CORE_RDY_DIG 17 3245 #define RES4347_CORE_RDY_AUX 18 3246 #define RES4347_CORE_RDY_MAIN 22 3247 3248 /* 4369 PMU Resources */ 3249 #define RES4369_DUMMY 0 3250 #define RES4369_ABUCK 1 3251 #define RES4369_PMU_SLEEP 2 3252 #define RES4369_MISCLDO 3 3253 #define RES4369_LDO3P3 4 3254 #define RES4369_FAST_LPO_AVAIL 5 3255 #define RES4369_XTAL_PU 6 3256 #define RES4369_XTAL_STABLE 7 3257 #define RES4369_PWRSW_DIG 8 3258 #define RES4369_SR_DIG 9 3259 #define RES4369_SLEEP_DIG 10 3260 #define RES4369_PWRSW_AUX 11 3261 #define RES4369_SR_AUX 12 3262 #define RES4369_SLEEP_AUX 13 3263 #define RES4369_PWRSW_MAIN 14 3264 #define RES4369_SR_MAIN 15 3265 #define RES4369_SLEEP_MAIN 16 3266 #define RES4369_DIG_CORE_RDY 17 3267 #define RES4369_CORE_RDY_AUX 18 3268 #define RES4369_ALP_AVAIL 19 3269 #define RES4369_RADIO_AUX_PU 20 3270 #define RES4369_MINIPMU_AUX_PU 21 3271 #define RES4369_CORE_RDY_MAIN 22 3272 #define RES4369_RADIO_MAIN_PU 23 3273 #define RES4369_MINIPMU_MAIN_PU 24 3274 #define RES4369_PCIE_EP_PU 25 3275 #define RES4369_COLD_START_WAIT 26 3276 #define RES4369_ARMHTAVAIL 27 3277 #define RES4369_HT_AVAIL 28 3278 #define RES4369_MACPHY_AUX_CLK_AVAIL 29 3279 #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 3280 3281 /* 3282 * 4378 PMU Resources 3283 */ 3284 #define RES4378_DUMMY 0 3285 #define RES4378_ABUCK 1 3286 #define RES4378_PMU_SLEEP 2 3287 #define RES4378_MISC_LDO 3 3288 #define RES4378_LDO3P3_PU 4 3289 #define RES4378_FAST_LPO_AVAIL 5 3290 #define RES4378_XTAL_PU 6 3291 #define RES4378_XTAL_STABLE 7 3292 #define RES4378_PWRSW_DIG 8 3293 #define RES4378_SR_DIG 9 3294 #define RES4378_SLEEP_DIG 10 3295 #define RES4378_PWRSW_AUX 11 3296 #define RES4378_SR_AUX 12 3297 #define RES4378_SLEEP_AUX 13 3298 #define RES4378_PWRSW_MAIN 14 3299 #define RES4378_SR_MAIN 15 3300 #define RES4378_SLEEP_MAIN 16 3301 #define RES4378_CORE_RDY_DIG 17 3302 #define RES4378_CORE_RDY_AUX 18 3303 #define RES4378_ALP_AVAIL 19 3304 #define RES4378_RADIO_AUX_PU 20 3305 #define RES4378_MINIPMU_AUX_PU 21 3306 #define RES4378_CORE_RDY_MAIN 22 3307 #define RES4378_RADIO_MAIN_PU 23 3308 #define RES4378_MINIPMU_MAIN_PU 24 3309 #define RES4378_CORE_RDY_CB 25 3310 #define RES4378_PWRSW_CB 26 3311 #define RES4378_ARMHTAVAIL 27 3312 #define RES4378_HT_AVAIL 28 3313 #define RES4378_MACPHY_AUX_CLK_AVAIL 29 3314 #define RES4378_MACPHY_MAIN_CLK_AVAIL 30 3315 #define RES4378_RESERVED_31 31 3316 3317 /* 3318 * 4387 PMU Resources 3319 */ 3320 #define RES4387_DUMMY 0 3321 #define RES4387_RESERVED_1 1 3322 #define RES4387_FAST_LPO_AVAIL 1 /* C0 */ 3323 #define RES4387_PMU_SLEEP 2 3324 #define RES4387_PMU_LP 2 /* C0 */ 3325 #define RES4387_MISC_LDO 3 3326 #define RES4387_RESERVED_4 4 3327 #define RES4387_SERDES_AFE_RET 4 /* C0 */ 3328 #define RES4387_XTAL_HQ 5 3329 #define RES4387_XTAL_PU 6 3330 #define RES4387_XTAL_STABLE 7 3331 #define RES4387_PWRSW_DIG 8 3332 #define RES4387_CORE_RDY_BTMAIN 9 3333 #define RES4387_CORE_RDY_BTSC 10 3334 #define RES4387_PWRSW_AUX 11 3335 #define RES4387_PWRSW_SCAN 12 3336 #define RES4387_CORE_RDY_SCAN 13 3337 #define RES4387_PWRSW_MAIN 14 3338 #define RES4387_RESERVED_15 15 3339 #define RES4387_XTAL_PM_CLK 15 /* C0 */ 3340 #define RES4387_RESERVED_16 16 3341 #define RES4387_CORE_RDY_DIG 17 3342 #define RES4387_CORE_RDY_AUX 18 3343 #define RES4387_ALP_AVAIL 19 3344 #define RES4387_RADIO_PU_AUX 20 3345 #define RES4387_RADIO_PU_SCAN 21 3346 #define RES4387_CORE_RDY_MAIN 22 3347 #define RES4387_RADIO_PU_MAIN 23 3348 #define RES4387_MACPHY_CLK_SCAN 24 3349 #define RES4387_CORE_RDY_CB 25 3350 #define RES4387_PWRSW_CB 26 3351 #define RES4387_ARMCLK_AVAIL 27 3352 #define RES4387_HT_AVAIL 28 3353 #define RES4387_MACPHY_CLK_AUX 29 3354 #define RES4387_MACPHY_CLK_MAIN 30 3355 #define RES4387_RESERVED_31 31 3356 3357 /* 4388 PMU Resources */ 3358 #define RES4388_DUMMY 0u 3359 #define RES4388_FAST_LPO_AVAIL 1u 3360 #define RES4388_PMU_LP 2u 3361 #define RES4388_MISC_LDO 3u 3362 #define RES4388_SERDES_AFE_RET 4u 3363 #define RES4388_XTAL_HQ 5u 3364 #define RES4388_XTAL_PU 6u 3365 #define RES4388_XTAL_STABLE 7u 3366 #define RES4388_PWRSW_DIG 8u 3367 #define RES4388_BTMC_TOP_RDY 9u 3368 #define RES4388_BTSC_TOP_RDY 10u 3369 #define RES4388_PWRSW_AUX 11u 3370 #define RES4388_PWRSW_SCAN 12u 3371 #define RES4388_CORE_RDY_SCAN 13u 3372 #define RES4388_PWRSW_MAIN 14u 3373 #define RES4388_RESERVED_15 15u 3374 #define RES4388_RESERVED_16 16u 3375 #define RES4388_CORE_RDY_DIG 17u 3376 #define RES4388_CORE_RDY_AUX 18u 3377 #define RES4388_ALP_AVAIL 19u 3378 #define RES4388_RADIO_PU_AUX 20u 3379 #define RES4388_RADIO_PU_SCAN 21u 3380 #define RES4388_CORE_RDY_MAIN 22u 3381 #define RES4388_RADIO_PU_MAIN 23u 3382 #define RES4388_MACPHY_CLK_SCAN 24u 3383 #define RES4388_CORE_RDY_CB 25u 3384 #define RES4388_PWRSW_CB 26u 3385 #define RES4388_ARMCLKAVAIL 27u 3386 #define RES4388_HT_AVAIL 28u 3387 #define RES4388_MACPHY_CLK_AUX 29u 3388 #define RES4388_MACPHY_CLK_MAIN 30u 3389 #define RES4388_RESERVED_31 31u 3390 3391 /* 4389 PMU Resources */ 3392 #define RES4389_DUMMY 0u 3393 #define RES4389_FAST_LPO_AVAIL 1u 3394 #define RES4389_PMU_LP 2u 3395 #define RES4389_MISC_LDO 3u 3396 #define RES4389_SERDES_AFE_RET 4u 3397 #define RES4389_XTAL_HQ 5u 3398 #define RES4389_XTAL_PU 6u 3399 #define RES4389_XTAL_STABLE 7u 3400 #define RES4389_PWRSW_DIG 8u 3401 #define RES4389_BTMC_TOP_RDY 9u 3402 #define RES4389_BTSC_TOP_RDY 10u 3403 #define RES4389_PWRSW_AUX 11u 3404 #define RES4389_PWRSW_SCAN 12u 3405 #define RES4389_CORE_RDY_SCAN 13u 3406 #define RES4389_PWRSW_MAIN 14u 3407 #define RES4389_RESERVED_15 15u 3408 #define RES4389_RESERVED_16 16u 3409 #define RES4389_CORE_RDY_DIG 17u 3410 #define RES4389_CORE_RDY_AUX 18u 3411 #define RES4389_ALP_AVAIL 19u 3412 #define RES4389_RADIO_PU_AUX 20u 3413 #define RES4389_RADIO_PU_SCAN 21u 3414 #define RES4389_CORE_RDY_MAIN 22u 3415 #define RES4389_RADIO_PU_MAIN 23u 3416 #define RES4389_MACPHY_CLK_SCAN 24u 3417 #define RES4389_CORE_RDY_CB 25u 3418 #define RES4389_PWRSW_CB 26u 3419 #define RES4389_ARMCLKAVAIL 27u 3420 #define RES4389_HT_AVAIL 28u 3421 #define RES4389_MACPHY_CLK_AUX 29u 3422 #define RES4389_MACPHY_CLK_MAIN 30u 3423 #define RES4389_RESERVED_31 31u 3424 3425 /* 4397 PMU Resources */ 3426 #define RES4397_DUMMY 0u 3427 #define RES4397_FAST_LPO_AVAIL 1u 3428 #define RES4397_PMU_LP 2u 3429 #define RES4397_MISC_LDO 3u 3430 #define RES4397_SERDES_AFE_RET 4u 3431 #define RES4397_XTAL_HQ 5u 3432 #define RES4397_XTAL_PU 6u 3433 #define RES4397_XTAL_STABLE 7u 3434 #define RES4397_PWRSW_DIG 8u 3435 #define RES4397_BTMC_TOP_RDY 9u 3436 #define RES4397_BTSC_TOP_RDY 10u 3437 #define RES4397_PWRSW_AUX 11u 3438 #define RES4397_PWRSW_SCAN 12u 3439 #define RES4397_CORE_RDY_SCAN 13u 3440 #define RES4397_PWRSW_MAIN 14u 3441 #define RES4397_XTAL_PM_CLK 15u 3442 #define RES4397_PWRSW_DRR2 16u 3443 #define RES4397_CORE_RDY_DIG 17u 3444 #define RES4397_CORE_RDY_AUX 18u 3445 #define RES4397_ALP_AVAIL 19u 3446 #define RES4397_RADIO_PU_AUX 20u 3447 #define RES4397_RADIO_PU_SCAN 21u 3448 #define RES4397_CORE_RDY_MAIN 22u 3449 #define RES4397_RADIO_PU_MAIN 23u 3450 #define RES4397_MACPHY_CLK_SCAN 24u 3451 #define RES4397_CORE_RDY_CB 25u 3452 #define RES4397_PWRSW_CB 26u 3453 #define RES4397_ARMCLKAVAIL 27u 3454 #define RES4397_HT_AVAIL 28u 3455 #define RES4397_MACPHY_CLK_AUX 29u 3456 #define RES4397_MACPHY_CLK_MAIN 30u 3457 #define RES4397_RESERVED_31 31u 3458 3459 /* 0: BToverPCIe, 1: BToverUART */ 3460 #define CST4378_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0) 3461 #define CST4378_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0) 3462 #define CST4378_SPROM_PRESENT 0x00000010 3463 3464 #define CST4387_SFLASH_PRESENT 0x00000010U 3465 3466 #define CST4387_CHIPMODE_BTOU(cs) (((cs) & (1 << 6)) != 0) 3467 #define CST4387_CHIPMODE_BTOP(cs) (((cs) & (1 << 6)) == 0) 3468 #define CST4387_SPROM_PRESENT 0x00000010 3469 3470 /* GCI chip status */ 3471 #define GCI_CS_4369_FLL1MHZ_LOCK_MASK (1 << 1) 3472 #define GCI_CS_4387_FLL1MHZ_LOCK_MASK (1 << 1) 3473 3474 #define GCI_CS_4387_FLL1MHZ_DAC_OUT_SHIFT (16u) 3475 #define GCI_CS_4387_FLL1MHZ_DAC_OUT_MASK (0x00ff0000u) 3476 #define GCI_CS_4389_FLL1MHZ_DAC_OUT_SHIFT (16u) 3477 #define GCI_CS_4389_FLL1MHZ_DAC_OUT_MASK (0x00ff0000u) 3478 3479 /* GCI chip control registers */ 3480 #define GCI_CC7_AAON_BYPASS_PWRSW_SEL 13 3481 #define GCI_CC7_AAON_BYPASS_PWRSW_SEQ_ON 14 3482 3483 /* 4368 GCI chip control registers */ 3484 #define GCI_CC7_PRISEL_MASK (1 << 8 | 1 << 9) 3485 #define GCI_CC12_PRISEL_MASK (1 << 0 | 1 << 1) 3486 #define GCI_CC12_PRISEL_SHIFT 0 3487 #define GCI_CC12_DMASK_MASK (0x3ff << 10) 3488 #define GCI_CC16_ANT_SHARE_MASK (1 << 16 | 1 << 17) 3489 3490 #define CC2_4362_SDIO_AOS_WAKEUP_MASK (1u << 24u) 3491 #define CC2_4362_SDIO_AOS_WAKEUP_SHIFT 24u 3492 3493 #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u) 3494 #define CC2_4378_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12u 3495 #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u) 3496 #define CC2_4378_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13u 3497 #define CC2_4378_MAIN_VDDRET_ON_MASK (1u << 15u) 3498 #define CC2_4378_MAIN_VDDRET_ON_SHIFT 15u 3499 #define CC2_4378_AUX_VDDRET_ON_MASK (1u << 16u) 3500 #define CC2_4378_AUX_VDDRET_ON_SHIFT 16u 3501 #define CC2_4378_GCI2WAKE_MASK (1u << 31u) 3502 #define CC2_4378_GCI2WAKE_SHIFT 31u 3503 #define CC2_4378_SDIO_AOS_WAKEUP_MASK (1u << 24u) 3504 #define CC2_4378_SDIO_AOS_WAKEUP_SHIFT 24u 3505 #define CC4_4378_LHL_TIMER_SELECT (1u << 0u) 3506 #define CC6_4378_PWROK_WDT_EN_IN_MASK (1u << 6u) 3507 #define CC6_4378_PWROK_WDT_EN_IN_SHIFT 6u 3508 #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u) 3509 #define CC6_4378_SDIO_AOS_CHIP_WAKEUP_SHIFT 24u 3510 3511 #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u) 3512 #define CC2_4378_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15u 3513 #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u) 3514 #define CC2_4378_USE_CMN_BP_CLK_ON_REQ_SHIFT 16u 3515 3516 #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u) 3517 #define CC2_4387_MAIN_MEMLPLDO_VDDB_OFF_SHIFT 12u 3518 #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u) 3519 #define CC2_4387_AUX_MEMLPLDO_VDDB_OFF_SHIFT 13u 3520 #define CC2_4387_MAIN_VDDRET_ON_MASK (1u << 15u) 3521 #define CC2_4387_MAIN_VDDRET_ON_SHIFT 15u 3522 #define CC2_4387_AUX_VDDRET_ON_MASK (1u << 16u) 3523 #define CC2_4387_AUX_VDDRET_ON_SHIFT 16u 3524 #define CC2_4387_GCI2WAKE_MASK (1u << 31u) 3525 #define CC2_4387_GCI2WAKE_SHIFT 31u 3526 #define CC2_4387_SDIO_AOS_WAKEUP_MASK (1u << 24u) 3527 #define CC2_4387_SDIO_AOS_WAKEUP_SHIFT 24u 3528 #define CC4_4387_LHL_TIMER_SELECT (1u << 0u) 3529 #define CC6_4387_PWROK_WDT_EN_IN_MASK (1u << 6u) 3530 #define CC6_4387_PWROK_WDT_EN_IN_SHIFT 6u 3531 #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u) 3532 #define CC6_4387_SDIO_AOS_CHIP_WAKEUP_SHIFT 24u 3533 3534 #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u) 3535 #define CC2_4387_USE_WLAN_BP_CLK_ON_REQ_SHIFT 15u 3536 #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u) 3537 #define CC2_4387_USE_CMN_BP_CLK_ON_REQ_SHIFT 16u 3538 3539 #define CC2_4388_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u) 3540 #define CC2_4388_MAIN_MEMLPLDO_VDDB_OFF_SHIFT (12u) 3541 #define CC2_4388_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u) 3542 #define CC2_4388_AUX_MEMLPLDO_VDDB_OFF_SHIFT (13u) 3543 #define CC2_4388_MAIN_VDDRET_ON_MASK (1u << 15u) 3544 #define CC2_4388_MAIN_VDDRET_ON_SHIFT (15u) 3545 #define CC2_4388_AUX_VDDRET_ON_MASK (1u << 16u) 3546 #define CC2_4388_AUX_VDDRET_ON_SHIFT (16u) 3547 #define CC2_4388_GCI2WAKE_MASK (1u << 31u) 3548 #define CC2_4388_GCI2WAKE_SHIFT (31u) 3549 #define CC2_4388_SDIO_AOS_WAKEUP_MASK (1u << 24u) 3550 #define CC2_4388_SDIO_AOS_WAKEUP_SHIFT (24u) 3551 #define CC4_4388_LHL_TIMER_SELECT (1u << 0u) 3552 #define CC6_4388_PWROK_WDT_EN_IN_MASK (1u << 6u) 3553 #define CC6_4388_PWROK_WDT_EN_IN_SHIFT (6u) 3554 #define CC6_4388_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u) 3555 #define CC6_4388_SDIO_AOS_CHIP_WAKEUP_SHIFT (24u) 3556 3557 #define CC2_4388_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u) 3558 #define CC2_4388_USE_WLAN_BP_CLK_ON_REQ_SHIFT (15u) 3559 #define CC2_4388_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u) 3560 #define CC2_4388_USE_CMN_BP_CLK_ON_REQ_SHIFT (16u) 3561 3562 #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_MASK (1u << 12u) 3563 #define CC2_4389_MAIN_MEMLPLDO_VDDB_OFF_SHIFT (12u) 3564 #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_MASK (1u << 13u) 3565 #define CC2_4389_AUX_MEMLPLDO_VDDB_OFF_SHIFT (13u) 3566 #define CC2_4389_MAIN_VDDRET_ON_MASK (1u << 15u) 3567 #define CC2_4389_MAIN_VDDRET_ON_SHIFT (15u) 3568 #define CC2_4389_AUX_VDDRET_ON_MASK (1u << 16u) 3569 #define CC2_4389_AUX_VDDRET_ON_SHIFT (16u) 3570 #define CC2_4389_GCI2WAKE_MASK (1u << 31u) 3571 #define CC2_4389_GCI2WAKE_SHIFT (31u) 3572 #define CC2_4389_SDIO_AOS_WAKEUP_MASK (1u << 24u) 3573 #define CC2_4389_SDIO_AOS_WAKEUP_SHIFT (24u) 3574 #define CC4_4389_LHL_TIMER_SELECT (1u << 0u) 3575 #define CC6_4389_PWROK_WDT_EN_IN_MASK (1u << 6u) 3576 #define CC6_4389_PWROK_WDT_EN_IN_SHIFT (6u) 3577 #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_MASK (1u << 24u) 3578 #define CC6_4389_SDIO_AOS_CHIP_WAKEUP_SHIFT (24u) 3579 3580 #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_MASK (1u << 15u) 3581 #define CC2_4389_USE_WLAN_BP_CLK_ON_REQ_SHIFT (15u) 3582 #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_MASK (1u << 16u) 3583 #define CC2_4389_USE_CMN_BP_CLK_ON_REQ_SHIFT (16u) 3584 3585 #define PCIE_GPIO1_GPIO_PIN CC_GCI_GPIO_0 3586 #define PCIE_PERST_GPIO_PIN CC_GCI_GPIO_1 3587 #define PCIE_CLKREQ_GPIO_PIN CC_GCI_GPIO_2 3588 3589 #define VREG5_4378_MEMLPLDO_ADJ_MASK 0xF0000000 3590 #define VREG5_4378_MEMLPLDO_ADJ_SHIFT 28 3591 #define VREG5_4378_LPLDO_ADJ_MASK 0x00F00000 3592 #define VREG5_4378_LPLDO_ADJ_SHIFT 20 3593 3594 #define VREG5_4387_MISCLDO_PU_MASK (0x00000800u) 3595 #define VREG5_4387_MISCLDO_PU_SHIFT (11u) 3596 3597 #define VREG5_4387_MEMLPLDO_ADJ_MASK 0xF0000000 3598 #define VREG5_4387_MEMLPLDO_ADJ_SHIFT 28 3599 #define VREG5_4387_LPLDO_ADJ_MASK 0x00F00000 3600 #define VREG5_4387_LPLDO_ADJ_SHIFT 20 3601 #define VREG5_4387_MISC_LDO_ADJ_MASK (0xfu) 3602 #define VREG5_4387_MISC_LDO_ADJ_SHIFT (0) 3603 3604 /* misc ldo voltage 3605 * https://drive.google.com/file/d/1JjvNhp-RIXJBtw99M4w5ww4MmDsBJbpD 3606 */ 3607 #define PMU_VREG5_MISC_LDO_VOLT_0p931 (0x7u) /* 0.93125 v */ 3608 #define PMU_VREG5_MISC_LDO_VOLT_0p912 (0x6u) /* 0.91250 v */ 3609 #define PMU_VREG5_MISC_LDO_VOLT_0p893 (0x5u) /* 0.89375 v */ 3610 #define PMU_VREG5_MISC_LDO_VOLT_0p875 (0x4u) /* 0.87500 v */ 3611 #define PMU_VREG5_MISC_LDO_VOLT_0p856 (0x3u) /* 0.85625 v */ 3612 #define PMU_VREG5_MISC_LDO_VOLT_0p837 (0x2u) /* 0.83750 v */ 3613 #define PMU_VREG5_MISC_LDO_VOLT_0p818 (0x1u) /* 0.81875 v */ 3614 #define PMU_VREG5_MISC_LDO_VOLT_0p800 (0) /* 0.80000 v */ 3615 #define PMU_VREG5_MISC_LDO_VOLT_0p781 (0xfu) /* 0.78125 v */ 3616 #define PMU_VREG5_MISC_LDO_VOLT_0p762 (0xeu) /* 0.76250 v */ 3617 #define PMU_VREG5_MISC_LDO_VOLT_0p743 (0xdu) /* 0.74375 v */ 3618 #define PMU_VREG5_MISC_LDO_VOLT_0p725 (0xcu) /* 0.72500 v */ 3619 #define PMU_VREG5_MISC_LDO_VOLT_0p706 (0xbu) /* 0.70625 v */ 3620 #define PMU_VREG5_MISC_LDO_VOLT_0p687 (0xau) /* 0.68750 v */ 3621 #define PMU_VREG5_MISC_LDO_VOLT_0p668 (0x9u) /* 0.66875 v */ 3622 #define PMU_VREG5_MISC_LDO_VOLT_0p650 (0x8u) /* 0.65000 v */ 3623 3624 /* lpldo/memlpldo voltage */ 3625 #define PMU_VREG5_LPLDO_VOLT_0_88 0xf /* 0.88v */ 3626 #define PMU_VREG5_LPLDO_VOLT_0_86 0xe /* 0.86v */ 3627 #define PMU_VREG5_LPLDO_VOLT_0_84 0xd /* 0.84v */ 3628 #define PMU_VREG5_LPLDO_VOLT_0_82 0xc /* 0.82v */ 3629 #define PMU_VREG5_LPLDO_VOLT_0_80 0xb /* 0.80v */ 3630 #define PMU_VREG5_LPLDO_VOLT_0_78 0xa /* 0.78v */ 3631 #define PMU_VREG5_LPLDO_VOLT_0_76 0x9 /* 0.76v */ 3632 #define PMU_VREG5_LPLDO_VOLT_0_74 0x8 /* 0.74v */ 3633 #define PMU_VREG5_LPLDO_VOLT_0_72 0x7 /* 0.72v */ 3634 #define PMU_VREG5_LPLDO_VOLT_1_10 0x6 /* 1.10v */ 3635 #define PMU_VREG5_LPLDO_VOLT_1_00 0x5 /* 1.00v */ 3636 #define PMU_VREG5_LPLDO_VOLT_0_98 0x4 /* 0.98v */ 3637 #define PMU_VREG5_LPLDO_VOLT_0_96 0x3 /* 0.96v */ 3638 #define PMU_VREG5_LPLDO_VOLT_0_94 0x2 /* 0.94v */ 3639 #define PMU_VREG5_LPLDO_VOLT_0_92 0x1 /* 0.92v */ 3640 #define PMU_VREG5_LPLDO_VOLT_0_90 0x0 /* 0.90v */ 3641 3642 /* Save/Restore engine */ 3643 3644 /* 512 bytes block */ 3645 #define SR_ASM_ADDR_BLK_SIZE_SHIFT (9u) 3646 3647 #define BM_ADDR_TO_SR_ADDR(bmaddr) ((bmaddr) >> SR_ASM_ADDR_BLK_SIZE_SHIFT) 3648 #define SR_ADDR_TO_BM_ADDR(sraddr) ((sraddr) << SR_ASM_ADDR_BLK_SIZE_SHIFT) 3649 3650 /* Txfifo is 512KB for main core and 128KB for aux core 3651 * We use first 12kB (0x3000) in BMC buffer for template in main core and 3652 * 6.5kB (0x1A00) in aux core, followed by ASM code 3653 */ 3654 #define SR_ASM_ADDR_MAIN_4369 BM_ADDR_TO_SR_ADDR(0xC00) 3655 #define SR_ASM_ADDR_AUX_4369 BM_ADDR_TO_SR_ADDR(0xC00) 3656 #define SR_ASM_ADDR_DIG_4369 (0x0) 3657 3658 #define SR_ASM_ADDR_MAIN_4362 BM_ADDR_TO_SR_ADDR(0xc00u) 3659 #define SR_ASM_ADDR_DIG_4362 (0x0u) 3660 3661 #define SR_ASM_ADDR_MAIN_4378 (0x18) 3662 #define SR_ASM_ADDR_AUX_4378 (0xd) 3663 /* backplane address, use last 16k of BTCM for s/r */ 3664 #define SR_ASM_ADDR_DIG_4378A0 (0x51c000) 3665 3666 /* backplane address, use last 32k of BTCM for s/r */ 3667 #define SR_ASM_ADDR_DIG_4378B0 (0x518000) 3668 3669 #define SR_ASM_ADDR_MAIN_4387 (0x18) 3670 #define SR_ASM_ADDR_AUX_4387 (0xd) 3671 #define SR_ASM_ADDR_SCAN_4387 (0) 3672 /* backplane address */ 3673 #define SR_ASM_ADDR_DIG_4387 (0x800000) 3674 3675 #define SR_ASM_ADDR_MAIN_4387C0 BM_ADDR_TO_SR_ADDR(0xC00) 3676 #define SR_ASM_ADDR_AUX_4387C0 BM_ADDR_TO_SR_ADDR(0xC00) 3677 #define SR_ASM_ADDR_DIG_4387C0 (0x931000) 3678 #define SR_ASM_ADDR_DIG_4387_C0 (0x931000) 3679 3680 #define SR_ASM_ADDR_MAIN_4388 BM_ADDR_TO_SR_ADDR(0xC00) 3681 #define SR_ASM_ADDR_AUX_4388 BM_ADDR_TO_SR_ADDR(0xC00) 3682 #define SR_ASM_ADDR_SCAN_4388 BM_ADDR_TO_SR_ADDR(0) 3683 #define SR_ASM_ADDR_DIG_4388 (0x18520000) 3684 #define SR_ASM_SIZE_DIG_4388 (65536u) 3685 #define FIS_CMN_SUBCORE_ADDR_4388 (0x1640u) 3686 3687 #define SR_ASM_ADDR_MAIN_4389C0 BM_ADDR_TO_SR_ADDR(0xC00) 3688 #define SR_ASM_ADDR_AUX_4389C0 BM_ADDR_TO_SR_ADDR(0xC00) 3689 #define SR_ASM_ADDR_SCAN_4389C0 BM_ADDR_TO_SR_ADDR(0x000) 3690 #define SR_ASM_ADDR_DIG_4389C0 (0x18520000) 3691 #define SR_ASM_SIZE_DIG_4389C0 (8192u * 8u) 3692 3693 #define SR_ASM_ADDR_MAIN_4389 BM_ADDR_TO_SR_ADDR(0xC00) 3694 #define SR_ASM_ADDR_AUX_4389 BM_ADDR_TO_SR_ADDR(0xC00) 3695 #define SR_ASM_ADDR_SCAN_4389 BM_ADDR_TO_SR_ADDR(0x000) 3696 #define SR_ASM_ADDR_DIG_4389 (0x18520000) 3697 #define SR_ASM_SIZE_DIG_4389 (8192u * 8u) 3698 #define FIS_CMN_SUBCORE_ADDR_4389 (0x1640u) 3699 3700 #define SR_ASM_ADDR_DIG_4397 (0x18520000) 3701 3702 /* SR Control0 bits */ 3703 #define SR0_SR_ENG_EN_MASK 0x1 3704 #define SR0_SR_ENG_EN_SHIFT 0 3705 #define SR0_SR_ENG_CLK_EN (1 << 1) 3706 #define SR0_RSRC_TRIGGER (0xC << 2) 3707 #define SR0_WD_MEM_MIN_DIV (0x3 << 6) 3708 #define SR0_INVERT_SR_CLK (1 << 11) 3709 #define SR0_MEM_STBY_ALLOW (1 << 16) 3710 #define SR0_ENABLE_SR_ILP (1 << 17) 3711 #define SR0_ENABLE_SR_ALP (1 << 18) 3712 #define SR0_ENABLE_SR_HT (1 << 19) 3713 #define SR0_ALLOW_PIC (3 << 20) 3714 #define SR0_ENB_PMU_MEM_DISABLE (1 << 30) 3715 3716 /* SR Control0 bits for 4369 */ 3717 #define SR0_4369_SR_ENG_EN_MASK 0x1 3718 #define SR0_4369_SR_ENG_EN_SHIFT 0 3719 #define SR0_4369_SR_ENG_CLK_EN (1 << 1) 3720 #define SR0_4369_RSRC_TRIGGER (0xC << 2) 3721 #define SR0_4369_WD_MEM_MIN_DIV (0x2 << 6) 3722 #define SR0_4369_INVERT_SR_CLK (1 << 11) 3723 #define SR0_4369_MEM_STBY_ALLOW (1 << 16) 3724 #define SR0_4369_ENABLE_SR_ILP (1 << 17) 3725 #define SR0_4369_ENABLE_SR_ALP (1 << 18) 3726 #define SR0_4369_ENABLE_SR_HT (1 << 19) 3727 #define SR0_4369_ALLOW_PIC (3 << 20) 3728 #define SR0_4369_ENB_PMU_MEM_DISABLE (1 << 30) 3729 3730 /* SR Control0 bits for 4378 */ 3731 #define SR0_4378_SR_ENG_EN_MASK 0x1 3732 #define SR0_4378_SR_ENG_EN_SHIFT 0 3733 #define SR0_4378_SR_ENG_CLK_EN (1 << 1) 3734 #define SR0_4378_RSRC_TRIGGER (0xC << 2) 3735 #define SR0_4378_WD_MEM_MIN_DIV (0x2 << 6) 3736 #define SR0_4378_INVERT_SR_CLK (1 << 11) 3737 #define SR0_4378_MEM_STBY_ALLOW (1 << 16) 3738 #define SR0_4378_ENABLE_SR_ILP (1 << 17) 3739 #define SR0_4378_ENABLE_SR_ALP (1 << 18) 3740 #define SR0_4378_ENABLE_SR_HT (1 << 19) 3741 #define SR0_4378_ALLOW_PIC (3 << 20) 3742 #define SR0_4378_ENB_PMU_MEM_DISABLE (1 << 30) 3743 3744 /* SR Control0 bits for 4387 */ 3745 #define SR0_4387_SR_ENG_EN_MASK 0x1 3746 #define SR0_4387_SR_ENG_EN_SHIFT 0 3747 #define SR0_4387_SR_ENG_CLK_EN (1 << 1) 3748 #define SR0_4387_RSRC_TRIGGER (0xC << 2) 3749 #define SR0_4387_WD_MEM_MIN_DIV (0x2 << 6) 3750 #define SR0_4387_WD_MEM_MIN_DIV_AUX (0x4 << 6) 3751 #define SR0_4387_INVERT_SR_CLK (1 << 11) 3752 #define SR0_4387_MEM_STBY_ALLOW (1 << 16) 3753 #define SR0_4387_ENABLE_SR_ILP (1 << 17) 3754 #define SR0_4387_ENABLE_SR_ALP (1 << 18) 3755 #define SR0_4387_ENABLE_SR_HT (1 << 19) 3756 #define SR0_4387_ALLOW_PIC (3 << 20) 3757 #define SR0_4387_ENB_PMU_MEM_DISABLE (1 << 30) 3758 3759 /* SR Control0 bits for 4388 */ 3760 #define SR0_4388_SR_ENG_EN_MASK 0x1u 3761 #define SR0_4388_SR_ENG_EN_SHIFT 0 3762 #define SR0_4388_SR_ENG_CLK_EN (1u << 1u) 3763 #define SR0_4388_RSRC_TRIGGER (0xCu << 2u) 3764 #define SR0_4388_WD_MEM_MIN_DIV (0x2u << 6u) 3765 #define SR0_4388_INVERT_SR_CLK (1u << 11u) 3766 #define SR0_4388_MEM_STBY_ALLOW (1u << 16u) 3767 #define SR0_4388_ENABLE_SR_ILP (1u << 17u) 3768 #define SR0_4388_ENABLE_SR_ALP (1u << 18u) 3769 #define SR0_4388_ENABLE_SR_HT (1u << 19u) 3770 #define SR0_4388_ALLOW_PIC (3u << 20u) 3771 #define SR0_4388_ENB_PMU_MEM_DISABLE (1u << 30u) 3772 3773 /* SR Control0 bits for 4389 */ 3774 #define SR0_4389_SR_ENG_EN_MASK 0x1 3775 #define SR0_4389_SR_ENG_EN_SHIFT 0 3776 #define SR0_4389_SR_ENG_CLK_EN (1 << 1) 3777 #define SR0_4389_RSRC_TRIGGER (0xC << 2) 3778 #define SR0_4389_WD_MEM_MIN_DIV (0x2 << 6) 3779 #define SR0_4389_INVERT_SR_CLK (1 << 11) 3780 #define SR0_4389_MEM_STBY_ALLOW (1 << 16) 3781 #define SR0_4389_ENABLE_SR_ILP (1 << 17) 3782 #define SR0_4389_ENABLE_SR_ALP (1 << 18) 3783 #define SR0_4389_ENABLE_SR_HT (1 << 19) 3784 #define SR0_4389_ALLOW_PIC (3 << 20) 3785 #define SR0_4389_ENB_PMU_MEM_DISABLE (1 << 30) 3786 3787 /* SR Control1 bits */ 3788 #define SR1_INIT_ADDR_MASK (0x000003FFu) 3789 #define SR1_SELFTEST_ENB_MASK (0x00004000u) 3790 #define SR1_SELFTEST_ERR_INJCT_ENB_MASK (0x00008000u) 3791 #define SR1_SELFTEST_ERR_INJCT_PRD_MASK (0xFFFF0000u) 3792 #define SR1_SELFTEST_ERR_INJCT_PRD_SHIFT (16u) 3793 3794 /* SR Control2 bits */ 3795 #define SR2_INIT_ADDR_LONG_MASK (0x00003FFFu) 3796 3797 #define SR_SELFTEST_ERR_INJCT_PRD (0x10u) 3798 3799 /* SR Status1 bits */ 3800 #define SR_STS1_SR_ERR_MASK (0x00000001u) 3801 3802 /* =========== LHL regs =========== */ 3803 /* 4369 LHL register settings */ 3804 #define LHL4369_UP_CNT 0 3805 #define LHL4369_DN_CNT 2 3806 #define LHL4369_PWRSW_EN_DWN_CNT (LHL4369_DN_CNT + 2) 3807 #define LHL4369_ISO_EN_DWN_CNT (LHL4369_PWRSW_EN_DWN_CNT + 3) 3808 #define LHL4369_SLB_EN_DWN_CNT (LHL4369_ISO_EN_DWN_CNT + 1) 3809 #define LHL4369_ASR_CLK4M_DIS_DWN_CNT (LHL4369_DN_CNT) 3810 #define LHL4369_ASR_LPPFM_MODE_DWN_CNT (LHL4369_DN_CNT) 3811 #define LHL4369_ASR_MODE_SEL_DWN_CNT (LHL4369_DN_CNT) 3812 #define LHL4369_ASR_MANUAL_MODE_DWN_CNT (LHL4369_DN_CNT) 3813 #define LHL4369_ASR_ADJ_DWN_CNT (LHL4369_DN_CNT) 3814 #define LHL4369_ASR_OVERI_DIS_DWN_CNT (LHL4369_DN_CNT) 3815 #define LHL4369_ASR_TRIM_ADJ_DWN_CNT (LHL4369_DN_CNT) 3816 #define LHL4369_VDDC_SW_DIS_DWN_CNT (LHL4369_SLB_EN_DWN_CNT + 1) 3817 #define LHL4369_VMUX_ASR_SEL_DWN_CNT (LHL4369_VDDC_SW_DIS_DWN_CNT + 1) 3818 #define LHL4369_CSR_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3819 #define LHL4369_CSR_MODE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3820 #define LHL4369_CSR_OVERI_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3821 #define LHL4369_HPBG_CHOP_DIS_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3822 #define LHL4369_SRBG_REF_SEL_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3823 #define LHL4369_PFM_PWR_SLICE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3824 #define LHL4369_CSR_TRIM_ADJ_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3825 #define LHL4369_CSR_VOLTAGE_DWN_CNT (LHL4369_VMUX_ASR_SEL_DWN_CNT + 1) 3826 #define LHL4369_HPBG_PU_EN_DWN_CNT (LHL4369_CSR_MODE_DWN_CNT + 1) 3827 3828 #define LHL4369_HPBG_PU_EN_UP_CNT (LHL4369_UP_CNT + 1) 3829 #define LHL4369_CSR_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3830 #define LHL4369_CSR_MODE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3831 #define LHL4369_CSR_OVERI_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3832 #define LHL4369_HPBG_CHOP_DIS_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3833 #define LHL4369_SRBG_REF_SEL_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3834 #define LHL4369_PFM_PWR_SLICE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3835 #define LHL4369_CSR_TRIM_ADJ_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3836 #define LHL4369_CSR_VOLTAGE_UP_CNT (LHL4369_HPBG_PU_EN_UP_CNT + 1) 3837 #define LHL4369_VMUX_ASR_SEL_UP_CNT (LHL4369_CSR_MODE_UP_CNT + 1) 3838 #define LHL4369_VDDC_SW_DIS_UP_CNT (LHL4369_VMUX_ASR_SEL_UP_CNT + 1) 3839 #define LHL4369_SLB_EN_UP_CNT (LHL4369_VDDC_SW_DIS_UP_CNT + 8) 3840 #define LHL4369_ISO_EN_UP_CNT (LHL4369_SLB_EN_UP_CNT + 1) 3841 #define LHL4369_PWRSW_EN_UP_CNT (LHL4369_ISO_EN_UP_CNT + 3) 3842 #define LHL4369_ASR_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3843 #define LHL4369_ASR_CLK4M_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3844 #define LHL4369_ASR_LPPFM_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3845 #define LHL4369_ASR_MODE_SEL_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3846 #define LHL4369_ASR_MANUAL_MODE_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3847 #define LHL4369_ASR_OVERI_DIS_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3848 #define LHL4369_ASR_TRIM_ADJ_UP_CNT (LHL4369_PWRSW_EN_UP_CNT + 1) 3849 3850 /* 4362 LHL register settings */ 3851 #define LHL4362_UP_CNT (0u) 3852 #define LHL4362_DN_CNT (2u) 3853 #define LHL4362_PWRSW_EN_DWN_CNT (LHL4362_DN_CNT + 2) 3854 #define LHL4362_ISO_EN_DWN_CNT (LHL4362_PWRSW_EN_DWN_CNT + 3) 3855 #define LHL4362_SLB_EN_DWN_CNT (LHL4362_ISO_EN_DWN_CNT + 1) 3856 #define LHL4362_ASR_CLK4M_DIS_DWN_CNT (LHL4362_DN_CNT) 3857 #define LHL4362_ASR_LPPFM_MODE_DWN_CNT (LHL4362_DN_CNT) 3858 #define LHL4362_ASR_MODE_SEL_DWN_CNT (LHL4362_DN_CNT) 3859 #define LHL4362_ASR_MANUAL_MODE_DWN_CNT (LHL4362_DN_CNT) 3860 #define LHL4362_ASR_ADJ_DWN_CNT (LHL4362_DN_CNT) 3861 #define LHL4362_ASR_OVERI_DIS_DWN_CNT (LHL4362_DN_CNT) 3862 #define LHL4362_ASR_TRIM_ADJ_DWN_CNT (LHL4362_DN_CNT) 3863 #define LHL4362_VDDC_SW_DIS_DWN_CNT (LHL4362_SLB_EN_DWN_CNT + 1) 3864 #define LHL4362_VMUX_ASR_SEL_DWN_CNT (LHL4362_VDDC_SW_DIS_DWN_CNT + 1) 3865 #define LHL4362_CSR_ADJ_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3866 #define LHL4362_CSR_MODE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3867 #define LHL4362_CSR_OVERI_DIS_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3868 #define LHL4362_HPBG_CHOP_DIS_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3869 #define LHL4362_SRBG_REF_SEL_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3870 #define LHL4362_PFM_PWR_SLICE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3871 #define LHL4362_CSR_TRIM_ADJ_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3872 #define LHL4362_CSR_VOLTAGE_DWN_CNT (LHL4362_VMUX_ASR_SEL_DWN_CNT + 1) 3873 #define LHL4362_HPBG_PU_EN_DWN_CNT (LHL4362_CSR_MODE_DWN_CNT + 1) 3874 3875 #define LHL4362_HPBG_PU_EN_UP_CNT (LHL4362_UP_CNT + 1) 3876 #define LHL4362_CSR_ADJ_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3877 #define LHL4362_CSR_MODE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3878 #define LHL4362_CSR_OVERI_DIS_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3879 #define LHL4362_HPBG_CHOP_DIS_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3880 #define LHL4362_SRBG_REF_SEL_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3881 #define LHL4362_PFM_PWR_SLICE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3882 #define LHL4362_CSR_TRIM_ADJ_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3883 #define LHL4362_CSR_VOLTAGE_UP_CNT (LHL4362_HPBG_PU_EN_UP_CNT + 1) 3884 #define LHL4362_VMUX_ASR_SEL_UP_CNT (LHL4362_CSR_MODE_UP_CNT + 1) 3885 #define LHL4362_VDDC_SW_DIS_UP_CNT (LHL4362_VMUX_ASR_SEL_UP_CNT + 1) 3886 #define LHL4362_SLB_EN_UP_CNT (LHL4362_VDDC_SW_DIS_UP_CNT + 8) 3887 #define LHL4362_ISO_EN_UP_CNT (LHL4362_SLB_EN_UP_CNT + 1) 3888 #define LHL4362_PWRSW_EN_UP_CNT (LHL4362_ISO_EN_UP_CNT + 3) 3889 #define LHL4362_ASR_ADJ_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3890 #define LHL4362_ASR_CLK4M_DIS_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3891 #define LHL4362_ASR_LPPFM_MODE_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3892 #define LHL4362_ASR_MODE_SEL_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3893 #define LHL4362_ASR_MANUAL_MODE_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3894 #define LHL4362_ASR_OVERI_DIS_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3895 #define LHL4362_ASR_TRIM_ADJ_UP_CNT (LHL4362_PWRSW_EN_UP_CNT + 1) 3896 3897 /* 4378 LHL register settings */ 3898 #define LHL4378_CSR_OVERI_DIS_DWN_CNT 5u 3899 #define LHL4378_CSR_MODE_DWN_CNT 5u 3900 #define LHL4378_CSR_ADJ_DWN_CNT 5u 3901 3902 #define LHL4378_CSR_OVERI_DIS_UP_CNT 1u 3903 #define LHL4378_CSR_MODE_UP_CNT 1u 3904 #define LHL4378_CSR_ADJ_UP_CNT 1u 3905 3906 #define LHL4378_VDDC_SW_DIS_DWN_CNT 3u 3907 #define LHL4378_ASR_ADJ_DWN_CNT 3u 3908 #define LHL4378_HPBG_CHOP_DIS_DWN_CNT 0 3909 3910 #define LHL4378_VDDC_SW_DIS_UP_CNT 3u 3911 #define LHL4378_ASR_ADJ_UP_CNT 1u 3912 #define LHL4378_HPBG_CHOP_DIS_UP_CNT 0 3913 3914 #define LHL4378_ASR_MANUAL_MODE_DWN_CNT 5u 3915 #define LHL4378_ASR_MODE_SEL_DWN_CNT 5u 3916 #define LHL4378_ASR_LPPFM_MODE_DWN_CNT 5u 3917 #define LHL4378_ASR_CLK4M_DIS_DWN_CNT 0 3918 3919 #define LHL4378_ASR_MANUAL_MODE_UP_CNT 1u 3920 #define LHL4378_ASR_MODE_SEL_UP_CNT 1u 3921 #define LHL4378_ASR_LPPFM_MODE_UP_CNT 1u 3922 #define LHL4378_ASR_CLK4M_DIS_UP_CNT 0 3923 3924 #define LHL4378_PFM_PWR_SLICE_DWN_CNT 5u 3925 #define LHL4378_ASR_OVERI_DIS_DWN_CNT 5u 3926 #define LHL4378_SRBG_REF_SEL_DWN_CNT 5u 3927 #define LHL4378_HPBG_PU_EN_DWN_CNT 6u 3928 3929 #define LHL4378_PFM_PWR_SLICE_UP_CNT 1u 3930 #define LHL4378_ASR_OVERI_DIS_UP_CNT 1u 3931 #define LHL4378_SRBG_REF_SEL_UP_CNT 1u 3932 #define LHL4378_HPBG_PU_EN_UP_CNT 0 3933 3934 #define LHL4378_CSR_TRIM_ADJ_CNT_SHIFT (16u) 3935 #define LHL4378_CSR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT) 3936 #define LHL4378_CSR_TRIM_ADJ_DWN_CNT 0 3937 #define LHL4378_CSR_TRIM_ADJ_UP_CNT 0 3938 3939 #define LHL4378_ASR_TRIM_ADJ_CNT_SHIFT (0u) 3940 #define LHL4378_ASR_TRIM_ADJ_CNT_MASK (0x3Fu << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT) 3941 #define LHL4378_ASR_TRIM_ADJ_UP_CNT 0 3942 #define LHL4378_ASR_TRIM_ADJ_DWN_CNT 0 3943 3944 #define LHL4378_PWRSW_EN_DWN_CNT 0 3945 #define LHL4378_SLB_EN_DWN_CNT 2u 3946 #define LHL4378_ISO_EN_DWN_CNT 1u 3947 3948 #define LHL4378_VMUX_ASR_SEL_DWN_CNT 4u 3949 3950 #define LHL4378_PWRSW_EN_UP_CNT 6u 3951 #define LHL4378_SLB_EN_UP_CNT 4u 3952 #define LHL4378_ISO_EN_UP_CNT 5u 3953 3954 #define LHL4378_VMUX_ASR_SEL_UP_CNT 2u 3955 3956 #define LHL4387_VMUX_ASR_SEL_DWN_CNT (8u) 3957 #define LHL4387_VMUX_ASR_SEL_UP_CNT (0x14u) 3958 3959 /* 4387 LHL register settings for top off mode */ 3960 #define LHL4387_TO_CSR_OVERI_DIS_DWN_CNT 3u 3961 #define LHL4387_TO_CSR_MODE_DWN_CNT 3u 3962 #define LHL4387_TO_CSR_ADJ_DWN_CNT 0 3963 3964 #define LHL4387_TO_CSR_OVERI_DIS_UP_CNT 1u 3965 #define LHL4387_TO_CSR_MODE_UP_CNT 1u 3966 #define LHL4387_TO_CSR_ADJ_UP_CNT 0 3967 3968 #define LHL4387_TO_VDDC_SW_DIS_DWN_CNT 4u 3969 #define LHL4387_TO_ASR_ADJ_DWN_CNT 3u 3970 #define LHL4387_TO_LP_MODE_DWN_CNT 6u 3971 #define LHL4387_TO_HPBG_CHOP_DIS_DWN_CNT 3u 3972 3973 #define LHL4387_TO_VDDC_SW_DIS_UP_CNT 0 3974 #define LHL4387_TO_ASR_ADJ_UP_CNT 1u 3975 #define LHL4387_TO_LP_MODE_UP_CNT 0 3976 #define LHL4387_TO_HPBG_CHOP_DIS_UP_CNT 1u 3977 3978 #define LHL4387_TO_ASR_MANUAL_MODE_DWN_CNT 3u 3979 #define LHL4387_TO_ASR_MODE_SEL_DWN_CNT 3u 3980 #define LHL4387_TO_ASR_LPPFM_MODE_DWN_CNT 3u 3981 #define LHL4387_TO_ASR_CLK4M_DIS_DWN_CNT 3u 3982 3983 #define LHL4387_TO_ASR_MANUAL_MODE_UP_CNT 1u 3984 #define LHL4387_TO_ASR_MODE_SEL_UP_CNT 1u 3985 #define LHL4387_TO_ASR_LPPFM_MODE_UP_CNT 1u 3986 #define LHL4387_TO_ASR_CLK4M_DIS_UP_CNT 1u 3987 3988 #define LHL4387_TO_PFM_PWR_SLICE_DWN_CNT 3u 3989 #define LHL4387_TO_ASR_OVERI_DIS_DWN_CNT 3u 3990 #define LHL4387_TO_SRBG_REF_SEL_DWN_CNT 3u 3991 #define LHL4387_TO_HPBG_PU_EN_DWN_CNT 4u 3992 3993 #define LHL4387_TO_PFM_PWR_SLICE_UP_CNT 1u 3994 #define LHL4387_TO_ASR_OVERI_DIS_UP_CNT 1u 3995 #define LHL4387_TO_SRBG_REF_SEL_UP_CNT 1u 3996 #define LHL4387_TO_HPBG_PU_EN_UP_CNT 1u 3997 3998 #define LHL4387_TO_PWRSW_EN_DWN_CNT 0 3999 #define LHL4387_TO_SLB_EN_DWN_CNT 4u 4000 #define LHL4387_TO_ISO_EN_DWN_CNT 2u 4001 #define LHL4387_TO_TOP_SLP_EN_DWN_CNT 0 4002 4003 #define LHL4387_TO_PWRSW_EN_UP_CNT 0x16u 4004 #define LHL4387_TO_SLB_EN_UP_CNT 0xeu 4005 #define LHL4387_TO_ISO_EN_UP_CNT 0x10u 4006 #define LHL4387_TO_TOP_SLP_EN_UP_CNT 2u 4007 4008 /* MacResourceReqTimer0/1 */ 4009 #define MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT 24 4010 #define MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT 26 4011 #define MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT 27 4012 #define MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT 28 4013 #define MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT 29 4014 4015 /* for pmu rev32 and higher */ 4016 #define PMU32_MAC_MAIN_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ 4017 (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ 4018 (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ 4019 (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ 4020 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) 4021 4022 #define PMU32_MAC_AUX_RSRC_REQ_TIMER ((1 << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ 4023 (1 << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ 4024 (1 << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ 4025 (1 << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ 4026 (0 << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) 4027 4028 /* for pmu rev38 and higher */ 4029 #define PMU32_MAC_SCAN_RSRC_REQ_TIMER ((1u << MAC_RSRC_REQ_TIMER_INT_ENAB_SHIFT) | \ 4030 (1u << MAC_RSRC_REQ_TIMER_FORCE_ALP_SHIFT) | \ 4031 (1u << MAC_RSRC_REQ_TIMER_FORCE_HT_SHIFT) | \ 4032 (1u << MAC_RSRC_REQ_TIMER_FORCE_HQ_SHIFT) | \ 4033 (0u << MAC_RSRC_REQ_TIMER_CLKREQ_GRP_SEL_SHIFT)) 4034 4035 /* 4369 related: 4369 parameters 4036 * http://www.sj.broadcom.com/projects/BCM4369/gallery_backend.RC6.0/design/backplane/pmu_params.xls 4037 */ 4038 #define RES4369_DUMMY 0 4039 #define RES4369_ABUCK 1 4040 #define RES4369_PMU_SLEEP 2 4041 #define RES4369_MISCLDO_PU 3 4042 #define RES4369_LDO3P3_PU 4 4043 #define RES4369_FAST_LPO_AVAIL 5 4044 #define RES4369_XTAL_PU 6 4045 #define RES4369_XTAL_STABLE 7 4046 #define RES4369_PWRSW_DIG 8 4047 #define RES4369_SR_DIG 9 4048 #define RES4369_SLEEP_DIG 10 4049 #define RES4369_PWRSW_AUX 11 4050 #define RES4369_SR_AUX 12 4051 #define RES4369_SLEEP_AUX 13 4052 #define RES4369_PWRSW_MAIN 14 4053 #define RES4369_SR_MAIN 15 4054 #define RES4369_SLEEP_MAIN 16 4055 #define RES4369_DIG_CORE_RDY 17 4056 #define RES4369_CORE_RDY_AUX 18 4057 #define RES4369_ALP_AVAIL 19 4058 #define RES4369_RADIO_AUX_PU 20 4059 #define RES4369_MINIPMU_AUX_PU 21 4060 #define RES4369_CORE_RDY_MAIN 22 4061 #define RES4369_RADIO_MAIN_PU 23 4062 #define RES4369_MINIPMU_MAIN_PU 24 4063 #define RES4369_PCIE_EP_PU 25 4064 #define RES4369_COLD_START_WAIT 26 4065 #define RES4369_ARMHTAVAIL 27 4066 #define RES4369_HT_AVAIL 28 4067 #define RES4369_MACPHY_AUX_CLK_AVAIL 29 4068 #define RES4369_MACPHY_MAIN_CLK_AVAIL 30 4069 #define RES4369_RESERVED_31 31 4070 4071 #define CST4369_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 4072 #define CST4369_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 4073 #define CST4369_SPROM_PRESENT 0x00000010 4074 4075 #define PMU_4369_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF 4076 #define PMU_4369_MACCORE_1_RES_REQ_MASK 0x7FFB3647 4077 4078 /* 4362 related */ 4079 /* 4362 resource_table 4080 * http://www.sj.broadcom.com/projects/BCM4362/gallery_backend.RC1.mar_15_2017/design/backplane/ 4081 * pmu_params.xls 4082 */ 4083 #define RES4362_DUMMY (0u) 4084 #define RES4362_ABUCK (1u) 4085 #define RES4362_PMU_SLEEP (2u) 4086 #define RES4362_MISCLDO_PU (3u) 4087 #define RES4362_LDO3P3_PU (4u) 4088 #define RES4362_FAST_LPO_AVAIL (5u) 4089 #define RES4362_XTAL_PU (6u) 4090 #define RES4362_XTAL_STABLE (7u) 4091 #define RES4362_PWRSW_DIG (8u) 4092 #define RES4362_SR_DIG (9u) 4093 #define RES4362_SLEEP_DIG (10u) 4094 #define RES4362_PWRSW_AUX (11u) 4095 #define RES4362_SR_AUX (12u) 4096 #define RES4362_SLEEP_AUX (13u) 4097 #define RES4362_PWRSW_MAIN (14u) 4098 #define RES4362_SR_MAIN (15u) 4099 #define RES4362_SLEEP_MAIN (16u) 4100 #define RES4362_DIG_CORE_RDY (17u) 4101 #define RES4362_CORE_RDY_AUX (18u) 4102 #define RES4362_ALP_AVAIL (19u) 4103 #define RES4362_RADIO_AUX_PU (20u) 4104 #define RES4362_MINIPMU_AUX_PU (21u) 4105 #define RES4362_CORE_RDY_MAIN (22u) 4106 #define RES4362_RADIO_MAIN_PU (23u) 4107 #define RES4362_MINIPMU_MAIN_PU (24u) 4108 #define RES4362_PCIE_EP_PU (25u) 4109 #define RES4362_COLD_START_WAIT (26u) 4110 #define RES4362_ARMHTAVAIL (27u) 4111 #define RES4362_HT_AVAIL (28u) 4112 #define RES4362_MACPHY_AUX_CLK_AVAIL (29u) 4113 #define RES4362_MACPHY_MAIN_CLK_AVAIL (30u) 4114 #define RES4362_RESERVED_31 (31u) 4115 4116 #define CST4362_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 4117 #define CST4362_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 4118 #define CST4362_SPROM_PRESENT (0x00000010u) 4119 4120 #define PMU_4362_MACCORE_0_RES_REQ_MASK (0x3FCBF7FFu) 4121 #define PMU_4362_MACCORE_1_RES_REQ_MASK (0x7FFB3647u) 4122 4123 #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000 4124 #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F 4125 4126 #define PMU43012_MAC_RES_REQ_TIMER 0x1D000000 4127 #define PMU43012_MAC_RES_REQ_MASK 0x3FBBF7FF 4128 4129 #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000 4130 #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F 4131 4132 /* defines to detect active host interface in use */ 4133 #define CHIP_HOSTIF_PCIEMODE 0x1 4134 #define CHIP_HOSTIF_USBMODE 0x2 4135 #define CHIP_HOSTIF_SDIOMODE 0x4 4136 #define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE) 4137 #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE) 4138 #define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE) 4139 4140 #define PATCHTBL_SIZE (0x800) 4141 #define CR4_4335_RAM_BASE (0x180000) 4142 #define CR4_4345_LT_C0_RAM_BASE (0x1b0000) 4143 #define CR4_4345_GE_C0_RAM_BASE (0x198000) 4144 #define CR4_4349_RAM_BASE (0x180000) 4145 #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000) 4146 #define CR4_4350_RAM_BASE (0x180000) 4147 #define CR4_4360_RAM_BASE (0x0) 4148 #define CR4_43602_RAM_BASE (0x180000) 4149 4150 #define CR4_4347_RAM_BASE (0x170000) 4151 #define CR4_4362_RAM_BASE (0x170000) 4152 #define CR4_4364_RAM_BASE (0x160000) 4153 #define CR4_4369_RAM_BASE (0x170000) 4154 #define CR4_4377_RAM_BASE (0x170000) 4155 #define CR4_43751_RAM_BASE (0x170000) 4156 #define CR4_43752_RAM_BASE (0x170000) 4157 #define CR4_4376_RAM_BASE (0x352000) 4158 #define CR4_4378_RAM_BASE (0x352000) 4159 #define CR4_4387_RAM_BASE (0x740000) 4160 #define CR4_4385_RAM_BASE (0x740000) 4161 #define CA7_4388_RAM_BASE (0x200000) 4162 #define CA7_4389_RAM_BASE (0x200000) 4163 #define CA7_4385_RAM_BASE (0x200000) 4164 4165 /* Physical memory in 4388a0 HWA is 64KB (8192 x 64 bits) even though 4166 * the memory space allows 192KB (0x1850_0000 - 0x1852_FFFF) 4167 */ 4168 #define HWA_MEM_BASE_4388 (0x18520000u) 4169 #define HWA_MEM_SIZE_4388 (0x10000u) 4170 4171 /* 43012 PMU resources based on pmu_params.xls - Start */ 4172 #define RES43012_MEMLPLDO_PU 0 4173 #define RES43012_PMU_SLEEP 1 4174 #define RES43012_FAST_LPO 2 4175 #define RES43012_BTLPO_3P3 3 4176 #define RES43012_SR_POK 4 4177 #define RES43012_DUMMY_PWRSW 5 4178 #define RES43012_DUMMY_LDO3P3 6 4179 #define RES43012_DUMMY_BT_LDO3P3 7 4180 #define RES43012_DUMMY_RADIO 8 4181 #define RES43012_VDDB_VDDRET 9 4182 #define RES43012_HV_LDO3P3 10 4183 #define RES43012_OTP_PU 11 4184 #define RES43012_XTAL_PU 12 4185 #define RES43012_SR_CLK_START 13 4186 #define RES43012_XTAL_STABLE 14 4187 #define RES43012_FCBS 15 4188 #define RES43012_CBUCK_MODE 16 4189 #define RES43012_CORE_READY 17 4190 #define RES43012_ILP_REQ 18 4191 #define RES43012_ALP_AVAIL 19 4192 #define RES43012_RADIOLDO_1P8 20 4193 #define RES43012_MINI_PMU 21 4194 #define RES43012_UNUSED 22 4195 #define RES43012_SR_SAVE_RESTORE 23 4196 #define RES43012_PHY_PWRSW 24 4197 #define RES43012_VDDB_CLDO 25 4198 #define RES43012_SUBCORE_PWRSW 26 4199 #define RES43012_SR_SLEEP 27 4200 #define RES43012_HT_START 28 4201 #define RES43012_HT_AVAIL 29 4202 #define RES43012_MACPHY_CLK_AVAIL 30 4203 #define CST43012_SPROM_PRESENT 0x00000010 4204 4205 /* SR Control0 bits */ 4206 #define SR0_43012_SR_ENG_EN_MASK 0x1u 4207 #define SR0_43012_SR_ENG_EN_SHIFT 0u 4208 #define SR0_43012_SR_ENG_CLK_EN (1u << 1u) 4209 #define SR0_43012_SR_RSRC_TRIGGER (0xCu << 2u) 4210 #define SR0_43012_SR_WD_MEM_MIN_DIV (0x3u << 6u) 4211 #define SR0_43012_SR_MEM_STBY_ALLOW_MSK (1u << 16u) 4212 #define SR0_43012_SR_MEM_STBY_ALLOW_SHIFT 16u 4213 #define SR0_43012_SR_ENABLE_ILP (1u << 17u) 4214 #define SR0_43012_SR_ENABLE_ALP (1u << 18u) 4215 #define SR0_43012_SR_ENABLE_HT (1u << 19u) 4216 #define SR0_43012_SR_ALLOW_PIC (3u << 20u) 4217 #define SR0_43012_SR_PMU_MEM_DISABLE (1u << 30u) 4218 #define CC_43012_VDDM_PWRSW_EN_MASK (1u << 20u) 4219 #define CC_43012_VDDM_PWRSW_EN_SHIFT (20u) 4220 #define CC_43012_SDIO_AOS_WAKEUP_MASK (1u << 24u) 4221 #define CC_43012_SDIO_AOS_WAKEUP_SHIFT (24u) 4222 4223 /* 43012 - offset at 5K */ 4224 #define SR1_43012_SR_INIT_ADDR_MASK 0x3ffu 4225 #define SR1_43012_SR_ASM_ADDR 0xAu 4226 4227 /* PLL usage in 43012 */ 4228 #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003fu 4229 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0u 4230 #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00u 4231 #define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10u 4232 #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00u 4233 #define PMU43012_PLL0_PC3_PDIV_SHIFT 10u 4234 #define PMU43012_PLL_NDIV_FRAC_BITS 20u 4235 #define PMU43012_PLL_P_DIV_SCALE_BITS 10u 4236 4237 #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003u 4238 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0u 4239 #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000cu 4240 #define CCTL_43012_ARM_ONCOUNT_SHIFT 2u 4241 4242 /* PMU Rev >= 30 */ 4243 #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000u 4244 4245 /* 43012 PMU Chip Control Registers */ 4246 #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010u 4247 #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040u 4248 #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800u 4249 #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000u 4250 #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000u 4251 #define PMUCCTL02_43012_BTLDO3P3_PU_FORCE_OFF (1u << 12u) 4252 4253 #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000u 4254 #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000u 4255 #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000u 4256 #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000u 4257 #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000u 4258 #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000u 4259 #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000u 4260 #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000u 4261 #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000u 4262 #define PMUCCTL04_43012_USE_LOCK 0x20000000u 4263 #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000u 4264 #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000u 4265 #define PMUCCTL05_43012_DISABLE_SPM_CLK (1u << 8u) 4266 #define PMUCCTL05_43012_RADIO_DIG_CLK_GATING_EN (1u << 14u) 4267 #define PMUCCTL06_43012_GCI2RDIG_USE_ASYNCAPB (1u << 31u) 4268 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0u 4269 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6u 4270 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000u 4271 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18u 4272 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000u 4273 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24u 4274 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000u 4275 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12u 4276 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038u 4277 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3u 4278 4279 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_MASK 0x00000FC0u 4280 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_SHIFT 6u 4281 /* during normal operation normal value is reduced for optimized power */ 4282 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_STARTUP_VAL 0x1Fu 4283 4284 #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400 4285 4286 #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001 4287 #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020 4288 #define PMUCCTL14_43012_DOT11MAC_PHY_CLK_EN_INITVAL 0x00000080 4289 #define PMUCCTL14_43012_DOT11MAC_PHY_CNTL_EN_INITVAL 0x00000200 4290 #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400 4291 #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000 4292 #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000 4293 #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000 4294 #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000 4295 4296 #define VREG6_43012_MEMLPLDO_ADJ_MASK 0x0000F000 4297 #define VREG6_43012_MEMLPLDO_ADJ_SHIFT 12 4298 4299 #define VREG6_43012_LPLDO_ADJ_MASK 0x000000F0 4300 #define VREG6_43012_LPLDO_ADJ_SHIFT 4 4301 4302 #define VREG7_43012_PWRSW_1P8_PU_MASK 0x00400000 4303 #define VREG7_43012_PWRSW_1P8_PU_SHIFT 22 4304 4305 /* 4378 PMU Chip Control Registers */ 4306 #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000 4307 #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15 4308 #define PMUCCTL03_4378_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F 4309 4310 #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000 4311 #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21 4312 #define PMUCCTL03_4378_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F 4313 4314 #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000 4315 #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27 4316 #define PMUCCTL03_4378_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0 4317 4318 #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0 4319 #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6 4320 #define PMUCCTL00_4378_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5 4321 4322 #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000 4323 #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_SHIFT 15 4324 #define PMUCCTL00_4378_XTAL_RES_BYPASS_NORMAL_VAL 0x7 4325 4326 /* 4387 PMU Chip Control Registers */ 4327 #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_MASK 0x001F8000 4328 #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_SHIFT 15 4329 #define PMUCCTL03_4387_XTAL_CORESIZE_PMOS_NORMAL_VAL 0x3F 4330 4331 #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_MASK 0x07E00000 4332 #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_SHIFT 21 4333 #define PMUCCTL03_4387_XTAL_CORESIZE_NMOS_NORMAL_VAL 0x3F 4334 4335 #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x38000000 4336 #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 27 4337 #define PMUCCTL03_4387_XTAL_SEL_BIAS_RES_NORMAL_VAL 0x0 4338 4339 #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x00000FC0 4340 #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 6 4341 #define PMUCCTL00_4387_XTAL_CORESIZE_BIAS_ADJ_NORMAL_VAL 0x5 4342 4343 #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_MASK 0x00038000 4344 #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_SHIFT 15 4345 #define PMUCCTL00_4387_XTAL_RES_BYPASS_NORMAL_VAL 0x7 4346 4347 /* GPIO pins */ 4348 #define CC_PIN_GPIO_00 (0u) 4349 #define CC_PIN_GPIO_01 (1u) 4350 #define CC_PIN_GPIO_02 (2u) 4351 #define CC_PIN_GPIO_03 (3u) 4352 #define CC_PIN_GPIO_04 (4u) 4353 #define CC_PIN_GPIO_05 (5u) 4354 #define CC_PIN_GPIO_06 (6u) 4355 #define CC_PIN_GPIO_07 (7u) 4356 #define CC_PIN_GPIO_08 (8u) 4357 #define CC_PIN_GPIO_09 (9u) 4358 #define CC_PIN_GPIO_10 (10u) 4359 #define CC_PIN_GPIO_11 (11u) 4360 #define CC_PIN_GPIO_12 (12u) 4361 #define CC_PIN_GPIO_13 (13u) 4362 #define CC_PIN_GPIO_14 (14u) 4363 #define CC_PIN_GPIO_15 (15u) 4364 #define CC_PIN_GPIO_16 (16u) 4365 #define CC_PIN_GPIO_17 (17u) 4366 #define CC_PIN_GPIO_18 (18u) 4367 #define CC_PIN_GPIO_19 (19u) 4368 #define CC_PIN_GPIO_20 (20u) 4369 #define CC_PIN_GPIO_21 (21u) 4370 #define CC_PIN_GPIO_22 (22u) 4371 #define CC_PIN_GPIO_23 (23u) 4372 #define CC_PIN_GPIO_24 (24u) 4373 #define CC_PIN_GPIO_25 (25u) 4374 #define CC_PIN_GPIO_26 (26u) 4375 #define CC_PIN_GPIO_27 (27u) 4376 #define CC_PIN_GPIO_28 (28u) 4377 #define CC_PIN_GPIO_29 (29u) 4378 #define CC_PIN_GPIO_30 (30u) 4379 #define CC_PIN_GPIO_31 (31u) 4380 4381 /* Last GPIO Pad */ 4382 #define CC_PIN_GPIO_LAST CC_PIN_GPIO_31 4383 4384 /* GCI chipcontrol register indices */ 4385 #define CC_GCI_CHIPCTRL_00 (0) 4386 #define CC_GCI_CHIPCTRL_01 (1) 4387 #define CC_GCI_CHIPCTRL_02 (2) 4388 #define CC_GCI_CHIPCTRL_03 (3) 4389 #define CC_GCI_CHIPCTRL_04 (4) 4390 #define CC_GCI_CHIPCTRL_05 (5) 4391 #define CC_GCI_CHIPCTRL_06 (6) 4392 #define CC_GCI_CHIPCTRL_07 (7) 4393 #define CC_GCI_CHIPCTRL_08 (8) 4394 #define CC_GCI_CHIPCTRL_09 (9) 4395 #define CC_GCI_CHIPCTRL_10 (10) 4396 #define CC_GCI_CHIPCTRL_10 (10) 4397 #define CC_GCI_CHIPCTRL_11 (11) 4398 #define CC_GCI_CHIPCTRL_12 (12) 4399 #define CC_GCI_CHIPCTRL_13 (13) 4400 #define CC_GCI_CHIPCTRL_14 (14) 4401 #define CC_GCI_CHIPCTRL_15 (15) 4402 #define CC_GCI_CHIPCTRL_16 (16) 4403 #define CC_GCI_CHIPCTRL_17 (17) 4404 #define CC_GCI_CHIPCTRL_18 (18) 4405 #define CC_GCI_CHIPCTRL_19 (19) 4406 #define CC_GCI_CHIPCTRL_20 (20) 4407 #define CC_GCI_CHIPCTRL_21 (21) 4408 #define CC_GCI_CHIPCTRL_22 (22) 4409 #define CC_GCI_CHIPCTRL_23 (23) 4410 #define CC_GCI_CHIPCTRL_24 (24) 4411 #define CC_GCI_CHIPCTRL_25 (25) 4412 #define CC_GCI_CHIPCTRL_26 (26) 4413 #define CC_GCI_CHIPCTRL_27 (27) 4414 #define CC_GCI_CHIPCTRL_28 (28) 4415 4416 /* GCI chip ctrl SDTC Soft reset */ 4417 #define GCI_CHIP_CTRL_SDTC_SOFT_RESET (1 << 31) 4418 4419 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12) 4420 4421 #define CC_GCI_04_SDIO_DRVSTR_SHIFT 15 4422 #define CC_GCI_04_SDIO_DRVSTR_MASK (0x0f << CC_GCI_04_SDIO_DRVSTR_SHIFT) /* 0x00078000 */ 4423 #define CC_GCI_04_SDIO_DRVSTR_OVERRIDE_BIT (1 << 18) 4424 #define CC_GCI_04_SDIO_DRVSTR_DEFAULT_MA 14 4425 #define CC_GCI_04_SDIO_DRVSTR_MIN_MA 2 4426 #define CC_GCI_04_SDIO_DRVSTR_MAX_MA 16 4427 4428 #define CC_GCI_04_4387C0_XTAL_PM_CLK (1u << 20u) 4429 4430 #define CC_GCI_05_4387C0_AFE_RET_ENB_MASK (1u << 7u) 4431 4432 #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_NBIT 2u 4433 #define CC_GCI_CHIPCTRL_07_BTDEFLO_ANT0_MASK 0xFu 4434 #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_NBIT 11u 4435 #define CC_GCI_CHIPCTRL_07_BTDEFHI_ANT0_MASK 1u 4436 4437 #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_NBIT 10u 4438 #define CC_GCI_CHIPCTRL_18_BTDEF_ANT0_MASK 0x1Fu 4439 #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_NBIT 15u 4440 #define CC_GCI_CHIPCTRL_18_BTDEFLO_ANT1_MASK 1u 4441 #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_NBIT 26u 4442 #define CC_GCI_CHIPCTRL_18_BTDEFHI_ANT1_MASK 0x3Fu 4443 4444 #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_NBIT 10u 4445 #define CC_GCI_CHIPCTRL_19_BTDEF_ANT1_MASK 0x7u 4446 4447 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_NBIT 16u 4448 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_NBIT 17u 4449 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_NBIT 18u 4450 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_NBIT 19u 4451 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_NBIT 20u 4452 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_NBIT 21u 4453 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_NBIT 22u 4454 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_NBIT 23u 4455 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_NBIT 24u 4456 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_NBIT 25u 4457 #define CC_GCI_CHIPCTRL_23_LVM_MODE_DISABLE_NBIT 26u 4458 4459 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_MASK (1u <<\ 4460 CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_FORCE_NBIT) 4461 #define CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_MASK (1u <<\ 4462 CC_GCI_CHIPCTRL_23_MAIN_WLSC_PRISEL_VAL_NBIT) 4463 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_MASK (1u <<\ 4464 CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_FORCE_NBIT) 4465 #define CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_MASK (1u <<\ 4466 CC_GCI_CHIPCTRL_23_AUX_WLSC_PRISEL_VAL_NBIT) 4467 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_MASK (1u <<\ 4468 CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_FORCE_NBIT) 4469 #define CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_MASK (1u <<\ 4470 CC_GCI_CHIPCTRL_23_WLSC_BTSC_PRISEL_VAL_NBIT) 4471 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_MASK (1u <<\ 4472 CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_FORCE_NBIT) 4473 #define CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_MASK (1u <<\ 4474 CC_GCI_CHIPCTRL_23_WLSC_BTMAIN_PRISEL_VAL_NBIT) 4475 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_MASK (1u <<\ 4476 CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_FORCE_NBIT) 4477 #define CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_MASK (1u <<\ 4478 CC_GCI_CHIPCTRL_23_BTMAIN_BTSC_PRISEL_VAL_NBIT) 4479 #define CC_GCI_CHIPCTRL_23_LVM_MODE_DISABLE_MASK (1u <<\ 4480 CC_GCI_CHIPCTRL_23_LVM_MODE_DISABLE_NBIT) 4481 4482 /* 2G core0/core1 Pulse width register (offset : 0x47C) 4483 * wl_rx_long_pulse_width_2g_core0 [4:0]; 4484 * wl_rx_short_pulse_width_2g_core0 [9:5]; 4485 * wl_rx_long_pulse_width_2g_core1 [20:16]; 4486 * wl_rx_short_pulse_width_2g_core1 [25:21]; 4487 */ 4488 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u) 4489 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu) 4490 #define CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ 4491 CC_GCI_CNCB_RESET_PULSE_WIDTH_2G_CORE1_NBIT) 4492 4493 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_NBIT (5u) 4494 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_NBIT (16u) 4495 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_NBIT (21u) 4496 4497 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu) 4498 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ 4499 CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_2G_CORE1_NBIT) 4500 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_MASK (0x1Fu <<\ 4501 CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE0_NBIT) 4502 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_MASK (0x1Fu <<\ 4503 CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_2G_CORE1_NBIT) 4504 4505 /* 5G core0/Core1 (offset : 0x480) 4506 * wl_rx_long_pulse_width_5g[4:0]; 4507 * wl_rx_short_pulse_width_5g[9:5] 4508 */ 4509 4510 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_NBIT (5u) 4511 4512 #define CC_GCI_CNCB_LONG_RESET_PULSE_WIDTH_5G_MASK (0x1Fu) 4513 #define CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_MASK (0x1Fu <<\ 4514 CC_GCI_CNCB_SHORT_RESET_PULSE_WIDTH_5G_NBIT) 4515 4516 #define CC_GCI_CNCB_GLITCH_FILTER_WIDTH_MASK (0xFFu) 4517 4518 #define CC_GCI_RESET_OVERRIDE_NBIT 0x1u 4519 #define CC_GCI_RESET_OVERRIDE_MASK (0x1u << \ 4520 CC_GCI_RESET_OVERRIDE_NBIT) 4521 4522 #define CC_GCI_06_JTAG_SEL_SHIFT 4u 4523 #define CC_GCI_06_JTAG_SEL_MASK (1u << 4u) 4524 4525 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00u) >> 8u) 4526 4527 #define CC_GCI_03_LPFLAGS_SFLASH_MASK (0xFFFFFFu << 8u) 4528 #define CC_GCI_03_LPFLAGS_SFLASH_VAL (0xCCCCCCu << 8u) 4529 4530 #define CC_GCI_13_INSUFF_TREFUP_FIX_SHIFT 31u 4531 /* Note: For 4368 B0 onwards, the shift offset remains the same, 4532 * but the Chip Common Ctrl GCI register is 16 4533 */ 4534 #define CC_GCI_16_INSUFF_TREFUP_FIX_SHIFT 31u 4535 4536 #define GPIO_CTRL_REG_DISABLE_INTERRUPT (3u << 9u) 4537 #define GPIO_CTRL_REG_COUNT 40 4538 4539 #ifdef WL_INITVALS 4540 #define XTAL_HQ_SETTING_4387 (wliv_pmu_xtal_HQ) 4541 #define XTAL_LQ_SETTING_4387 (wliv_pmu_xtal_LQ) 4542 #else 4543 #define XTAL_HQ_SETTING_4387 (0xFFF94D30u) 4544 #define XTAL_LQ_SETTING_4387 (0xFFF94380u) 4545 #endif 4546 4547 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_MASK (0x00000200u) 4548 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_1_SHIFT (9u) 4549 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_MASK (0xFFFFFC00u) 4550 #define CC_GCI_16_BBPLL_CH_CTRL_GRP_PD_TRIG_24_3_SHIFT (10u) 4551 4552 #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_MASK (0x0000FC00u) 4553 #define CC_GCI_17_BBPLL_CH_CTRL_GRP_PD_TRIG_30_25_SHIFT (10u) 4554 #define CC_GCI_17_BBPLL_CH_CTRL_EN_MASK (0x04000000u) 4555 4556 #define CC_GCI_20_BBPLL_CH_CTRL_GRP_MASK (0xFC000000u) 4557 #define CC_GCI_20_BBPLL_CH_CTRL_GRP_SHIFT (26u) 4558 4559 /* GCI Chip Ctrl Regs */ 4560 #define GCI_CC28_IHRP_SEL_MASK (7 << 24) 4561 #define GCI_CC28_IHRP_SEL_SHIFT (24u) 4562 4563 /* 30=MACPHY_CLK_MAIN, 29=MACPHY_CLK_AUX, 23=RADIO_PU_MAIN, 22=CORE_RDY_MAIN 4564 * 20=RADIO_PU_AUX, 18=CORE_RDY_AUX, 14=PWRSW_MAIN, 11=PWRSW_AUX 4565 */ 4566 #define GRP_PD_TRIGGER_MASK_4387 (0x60d44800u) 4567 4568 /* power down ch0=MAIN/AUX PHY_clk, ch2=MAIN/AUX MAC_clk, ch5=RFFE_clk */ 4569 #define GRP_PD_MASK_4387 (0x25u) 4570 4571 #define CC_GCI_CHIPCTRL_11_2x2_ANT_MASK 0x03 4572 #define CC_GCI_CHIPCTRL_11_SHIFT_ANT_MASK 26 4573 4574 /* GCI chipstatus register indices */ 4575 #define GCI_CHIPSTATUS_00 (0) 4576 #define GCI_CHIPSTATUS_01 (1) 4577 #define GCI_CHIPSTATUS_02 (2) 4578 #define GCI_CHIPSTATUS_03 (3) 4579 #define GCI_CHIPSTATUS_04 (4) 4580 #define GCI_CHIPSTATUS_05 (5) 4581 #define GCI_CHIPSTATUS_06 (6) 4582 #define GCI_CHIPSTATUS_07 (7) 4583 #define GCI_CHIPSTATUS_08 (8) 4584 #define GCI_CHIPSTATUS_09 (9) 4585 #define GCI_CHIPSTATUS_10 (10) 4586 #define GCI_CHIPSTATUS_11 (11) 4587 #define GCI_CHIPSTATUS_12 (12) 4588 #define GCI_CHIPSTATUS_13 (13) 4589 #define GCI_CHIPSTATUS_15 (15) 4590 4591 /* 43021 GCI chipstatus registers */ 4592 #define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK (1 << 3) 4593 4594 /* GCI Core Control Reg */ 4595 #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */ 4596 #define GCI_CORECTRL_RSL_MASK (1 << 1) /**< ResetSECILogic */ 4597 #define GCI_CORECTRL_ES_MASK (1 << 2) /**< EnableSECI */ 4598 #define GCI_CORECTRL_FSL_MASK (1 << 3) /**< Force SECI Out Low */ 4599 #define GCI_CORECTRL_SOM_MASK (7 << 4) /**< SECI Op Mode */ 4600 #define GCI_CORECTRL_US_MASK (1 << 7) /**< Update SECI */ 4601 #define GCI_CORECTRL_BOS_MASK (1 << 8) /**< Break On Sleep */ 4602 #define GCI_CORECTRL_FORCEREGCLK_MASK (1 << 18) /* ForceRegClk */ 4603 4604 /* 4378 & 4387 GCI AVS function */ 4605 #define GCI6_AVS_ENAB 1u 4606 #define GCI6_AVS_ENAB_SHIFT 31u 4607 #define GCI6_AVS_ENAB_MASK (1u << GCI6_AVS_ENAB_SHIFT) 4608 #define GCI6_AVS_CBUCK_VOLT_SHIFT 25u 4609 #define GCI6_AVS_CBUCK_VOLT_MASK (0x1Fu << GCI6_AVS_CBUCK_VOLT_SHIFT) 4610 4611 /* GCI GPIO for function sel GCI-0/GCI-1 */ 4612 #define CC_GCI_GPIO_0 (0) 4613 #define CC_GCI_GPIO_1 (1) 4614 #define CC_GCI_GPIO_2 (2) 4615 #define CC_GCI_GPIO_3 (3) 4616 #define CC_GCI_GPIO_4 (4) 4617 #define CC_GCI_GPIO_5 (5) 4618 #define CC_GCI_GPIO_6 (6) 4619 #define CC_GCI_GPIO_7 (7) 4620 #define CC_GCI_GPIO_8 (8) 4621 #define CC_GCI_GPIO_9 (9) 4622 #define CC_GCI_GPIO_10 (10) 4623 #define CC_GCI_GPIO_11 (11) 4624 #define CC_GCI_GPIO_12 (12) 4625 #define CC_GCI_GPIO_13 (13) 4626 #define CC_GCI_GPIO_14 (14) 4627 #define CC_GCI_GPIO_15 (15) 4628 4629 /* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */ 4630 #define CC_GCI_GPIO_INVALID 0xFF 4631 4632 /* 4378 LHL GPIO configuration */ 4633 #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT (3u) 4634 #define LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_MASK (1u << LHL_IOCFG_P_ADDR_LHL_GPIO_DOUT_SEL_SHIFT) 4635 4636 /* 4378 LHL SPMI bit definitions */ 4637 #define LHL_LP_CTL5_SPMI_DATA_SEL_SHIFT (8u) 4638 #define LHL_LP_CTL5_SPMI_DATA_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_DATA_SHIFT) 4639 #define LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT (6u) 4640 #define LHL_LP_CTL5_SPMI_CLK_SEL_MASK (0x3u << LHL_LP_CTL5_SPMI_CLK_SEL_SHIFT) 4641 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO0 (0u) 4642 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO1 (1u) 4643 #define LHL_LP_CTL5_SPMI_CLK_DATA_GPIO2 (2u) 4644 4645 /* Plese do not these following defines */ 4646 /* find the 4 bit mask given the bit position */ 4647 #define GCIMASK(pos) (((uint32)0xF) << pos) 4648 /* get the value which can be used to directly OR with chipcontrol reg */ 4649 #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos)) 4650 /* Extract nibble from a given position */ 4651 #define GCIGETNBL(val, pos) ((val >> pos) & 0xF) 4652 4653 /* find the 8 bit mask given the bit position */ 4654 #define GCIMASK_8B(pos) (((uint32)0xFF) << pos) 4655 /* get the value which can be used to directly OR with chipcontrol reg */ 4656 #define GCIPOSVAL_8B(val, pos) ((((uint32)val) << pos) & GCIMASK_8B(pos)) 4657 /* Extract nibble from a given position */ 4658 #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF) 4659 4660 /* find the 4 bit mask given the bit position */ 4661 #define GCIMASK_4B(pos) (((uint32)0xF) << pos) 4662 /* get the value which can be used to directly OR with chipcontrol reg */ 4663 #define GCIPOSVAL_4B(val, pos) ((((uint32)val) << pos) & GCIMASK_4B(pos)) 4664 /* Extract nibble from a given position */ 4665 #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF) 4666 4667 /* GCI Intstatus(Mask)/WakeMask Register bits. */ 4668 #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */ 4669 #define GCI_INTSTATUS_UB (1 << 1) /**< UART Break Interrupt */ 4670 #define GCI_INTSTATUS_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4671 #define GCI_INTSTATUS_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4672 #define GCI_INTSTATUS_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4673 #define GCI_INTSTATUS_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4674 #define GCI_INTSTATUS_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4675 #define GCI_INTSTATUS_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4676 #define GCI_INTSTATUS_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4677 #define GCI_INTSTATUS_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4678 #define GCI_INTSTATUS_EVENT (1 << 21) /* GCI Event Interrupt */ 4679 #define GCI_INTSTATUS_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4680 #define GCI_INTSTATUS_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4681 #define GCI_INTSTATUS_GPIOINT (1 << 25) /**< GCIGpioInt */ 4682 #define GCI_INTSTATUS_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4683 #define GCI_INTSTATUS_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4684 4685 /* GCI IntMask Register bits. */ 4686 #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4687 #define GCI_INTMASK_UB (1 << 1) /**< UART Break Interrupt */ 4688 #define GCI_INTMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4689 #define GCI_INTMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4690 #define GCI_INTMASK_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4691 #define GCI_INTMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4692 #define GCI_INTMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4693 #define GCI_INTMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4694 #define GCI_INTMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4695 #define GCI_INTMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4696 #define GCI_INTMASK_EVENT (1 << 21) /* GCI Event Interrupt */ 4697 #define GCI_INTMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4698 #define GCI_INTMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4699 #define GCI_INTMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4700 #define GCI_INTMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4701 #define GCI_INTMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4702 4703 /* GCI WakeMask Register bits. */ 4704 #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4705 #define GCI_WAKEMASK_UB (1 << 1) /**< UART Break Interrupt */ 4706 #define GCI_WAKEMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4707 #define GCI_WAKEMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4708 #define GCI_WAKE_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4709 #define GCI_WAKEMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4710 #define GCI_WAKEMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4711 #define GCI_WAKEMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4712 #define GCI_WAKEMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4713 #define GCI_WAKEMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4714 #define GCI_WAKEMASK_EVENT (1 << 21) /* GCI Event Interrupt */ 4715 #define GCI_WAKEMASK_LEVELWAKE (1 << 22) /* GCI Wake Level Interrupt */ 4716 #define GCI_WAKEMASK_EVENTWAKE (1 << 23) /* GCI Wake Event Interrupt */ 4717 #define GCI_WAKEMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4718 #define GCI_WAKEMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4719 #define GCI_WAKEMASK_LHLWLWAKE (1 << 30) /* LHL WL wake */ 4720 4721 #define GCI_WAKE_ON_GCI_GPIO1 1 4722 #define GCI_WAKE_ON_GCI_GPIO2 2 4723 #define GCI_WAKE_ON_GCI_GPIO3 3 4724 #define GCI_WAKE_ON_GCI_GPIO4 4 4725 #define GCI_WAKE_ON_GCI_GPIO5 5 4726 #define GCI_WAKE_ON_GCI_GPIO6 6 4727 #define GCI_WAKE_ON_GCI_GPIO7 7 4728 #define GCI_WAKE_ON_GCI_GPIO8 8 4729 #define GCI_WAKE_ON_GCI_SECI_IN 9 4730 4731 #define PMU_EXT_WAKE_MASK_0_SDIO (1u << 2u) 4732 #define PMU_EXT_WAKE_MASK_0_PCIE_PERST (1u << 5u) 4733 4734 #define PMU_4362_EXT_WAKE_MASK_0_SDIO (1u << 1u | 1u << 2u) 4735 4736 /* =========== LHL regs =========== */ 4737 #define LHL_PWRSEQCTL_SLEEP_EN (1 << 0) 4738 #define LHL_PWRSEQCTL_PMU_SLEEP_MODE (1 << 1) 4739 #define LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN (1 << 2) 4740 #define LHL_PWRSEQCTL_PMU_TOP_ISO_EN (1 << 3) 4741 #define LHL_PWRSEQCTL_PMU_TOP_SLB_EN (1 << 4) 4742 #define LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN (1 << 5) 4743 #define LHL_PWRSEQCTL_PMU_CLDO_PD (1 << 6) 4744 #define LHL_PWRSEQCTL_PMU_LPLDO_PD (1 << 7) 4745 #define LHL_PWRSEQCTL_PMU_RSRC6_EN (1 << 8) 4746 4747 #define PMU_SLEEP_MODE_0 (LHL_PWRSEQCTL_SLEEP_EN |\ 4748 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN) 4749 4750 #define PMU_SLEEP_MODE_1 (LHL_PWRSEQCTL_SLEEP_EN |\ 4751 LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ 4752 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ 4753 LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ 4754 LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ 4755 LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ 4756 LHL_PWRSEQCTL_PMU_CLDO_PD |\ 4757 LHL_PWRSEQCTL_PMU_RSRC6_EN) 4758 4759 #define PMU_SLEEP_MODE_2 (LHL_PWRSEQCTL_SLEEP_EN |\ 4760 LHL_PWRSEQCTL_PMU_SLEEP_MODE |\ 4761 LHL_PWRSEQCTL_PMU_FINAL_PMU_SLEEP_EN |\ 4762 LHL_PWRSEQCTL_PMU_TOP_ISO_EN |\ 4763 LHL_PWRSEQCTL_PMU_TOP_SLB_EN |\ 4764 LHL_PWRSEQCTL_PMU_TOP_PWRSW_EN |\ 4765 LHL_PWRSEQCTL_PMU_CLDO_PD |\ 4766 LHL_PWRSEQCTL_PMU_LPLDO_PD |\ 4767 LHL_PWRSEQCTL_PMU_RSRC6_EN) 4768 4769 #define LHL_PWRSEQ_CTL (0x000000ff) 4770 4771 /* LHL Top Level Power Up Control Register (lhl_top_pwrup_ctl_adr, Offset 0xE78) 4772 * Top Level Counter values for isolation, retention, Power Switch control 4773 */ 4774 #define LHL_PWRUP_ISOLATION_CNT (0x6 << 8) 4775 #define LHL_PWRUP_RETENTION_CNT (0x5 << 16) 4776 #define LHL_PWRUP_PWRSW_CNT (0x7 << 24) 4777 /* Mask is taken only for isolation 8:13 , Retention 16:21 , 4778 * Power Switch control 24:29 4779 */ 4780 #define LHL_PWRUP_CTL_MASK (0x3F3F3F00) 4781 #define LHL_PWRUP_CTL (LHL_PWRUP_ISOLATION_CNT |\ 4782 LHL_PWRUP_RETENTION_CNT |\ 4783 LHL_PWRUP_PWRSW_CNT) 4784 4785 #define LHL_PWRUP2_CLDO_DN_CNT (0x0) 4786 #define LHL_PWRUP2_LPLDO_DN_CNT (0x0 << 8) 4787 #define LHL_PWRUP2_RSRC6_DN_CN (0x4 << 16) 4788 #define LHL_PWRUP2_RSRC7_DN_CN (0x0 << 24) 4789 #define LHL_PWRUP2_CTL_MASK (0x3F3F3F3F) 4790 #define LHL_PWRUP2_CTL (LHL_PWRUP2_CLDO_DN_CNT |\ 4791 LHL_PWRUP2_LPLDO_DN_CNT |\ 4792 LHL_PWRUP2_RSRC6_DN_CN |\ 4793 LHL_PWRUP2_RSRC7_DN_CN) 4794 4795 /* LHL Top Level Power Down Control Register (lhl_top_pwrdn_ctl_adr, Offset 0xE74) */ 4796 #define LHL_PWRDN_SLEEP_CNT (0x4) 4797 #define LHL_PWRDN_CTL_MASK (0x3F) 4798 4799 /* LHL Top Level Power Down Control 2 Register (lhl_top_pwrdn2_ctl_adr, Offset 0xE80) */ 4800 #define LHL_PWRDN2_CLDO_DN_CNT (0x4) 4801 #define LHL_PWRDN2_LPLDO_DN_CNT (0x4 << 8) 4802 #define LHL_PWRDN2_RSRC6_DN_CN (0x3 << 16) 4803 #define LHL_PWRDN2_RSRC7_DN_CN (0x0 << 24) 4804 #define LHL_PWRDN2_CTL (LHL_PWRDN2_CLDO_DN_CNT |\ 4805 LHL_PWRDN2_LPLDO_DN_CNT |\ 4806 LHL_PWRDN2_RSRC6_DN_CN |\ 4807 LHL_PWRDN2_RSRC7_DN_CN) 4808 #define LHL_PWRDN2_CTL_MASK (0x3F3F3F3F) 4809 4810 #define LHL_FAST_WRITE_EN (1 << 14) 4811 4812 #define LHL_WL_MACTIMER_MASK 0xFFFFFFFF 4813 /* Write 1 to clear */ 4814 #define LHL_WL_MACTIMER_INT_ST_MASK (0x1u) 4815 4816 /* WL ARM Timer0 Interrupt Mask (lhl_wl_armtim0_intrp_adr) */ 4817 #define LHL_WL_ARMTIM0_INTRP_EN 0x00000001 4818 #define LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER 0x00000002 4819 4820 /* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */ 4821 #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001 4822 4823 /* WL MAC TimerX Interrupt Mask (lhl_wl_mactimX_intrp_adr) */ 4824 #define LHL_WL_MACTIM_INTRP_EN 0x00000001 4825 #define LHL_WL_MACTIM_INTRP_EDGE_TRIGGER 0x00000002 4826 4827 /* WL MAC TimerX Interrupt Status (lhl_wl_mactimX_st_adr) */ 4828 #define LHL_WL_MACTIM_ST_WL_MACTIM_INT_ST 0x00000001 4829 4830 /* LHL Wakeup Status (lhl_wkup_status_adr) */ 4831 #define LHL_WKUP_STATUS_WR_PENDING_ARMTIM0 0x00100000 4832 4833 #define LHL_PS_MODE_0 0 4834 #define LHL_PS_MODE_1 1 4835 4836 /* GCI EventIntMask Register SW bits */ 4837 #define GCI_MAILBOXDATA_TOWLAN (1 << 0) 4838 #define GCI_MAILBOXDATA_TOBT (1 << 1) 4839 #define GCI_MAILBOXDATA_TONFC (1 << 2) 4840 #define GCI_MAILBOXDATA_TOGPS (1 << 3) 4841 #define GCI_MAILBOXDATA_TOLTE (1 << 4) 4842 #define GCI_MAILBOXACK_TOWLAN (1 << 8) 4843 #define GCI_MAILBOXACK_TOBT (1 << 9) 4844 #define GCI_MAILBOXACK_TONFC (1 << 10) 4845 #define GCI_MAILBOXACK_TOGPS (1 << 11) 4846 #define GCI_MAILBOXACK_TOLTE (1 << 12) 4847 #define GCI_WAKE_TOWLAN (1 << 16) 4848 #define GCI_WAKE_TOBT (1 << 17) 4849 #define GCI_WAKE_TONFC (1 << 18) 4850 #define GCI_WAKE_TOGPS (1 << 19) 4851 #define GCI_WAKE_TOLTE (1 << 20) 4852 #define GCI_SWREADY (1 << 24) 4853 4854 /* GCI SECI_OUT TX Status Regiser bits */ 4855 #define GCI_SECIOUT_TXSTATUS_TXHALT (1 << 0) 4856 #define GCI_SECIOUT_TXSTATUS_TI (1 << 16) 4857 4858 /* 43012 MUX options */ 4859 #define MUXENAB43012_HOSTWAKE_MASK (0x00000001) 4860 #define MUXENAB43012_GETIX(val, name) (val - 1) 4861 4862 /* 4863 * Maximum delay for the PMU state transition in us. 4864 * This is an upper bound intended for spinwaits etc. 4865 */ 4866 #if defined(BCMQT) && defined(BCMDONGLEHOST) 4867 #define PMU_MAX_TRANSITION_DLY 1500000 4868 #else 4869 #define PMU_MAX_TRANSITION_DLY 15000 4870 #endif /* BCMDONGLEHOST */ 4871 4872 /* PMU resource up transition time in ILP cycles */ 4873 #define PMURES_UP_TRANSITION 2 4874 4875 #if !defined(BCMDONGLEHOST) 4876 /* 4877 * Information from BT to WLAN over eci_inputlo, eci_inputmi & 4878 * eci_inputhi register. Rev >=21 4879 */ 4880 /* Fields in eci_inputlo register - [0:31] */ 4881 #define ECI_INLO_TASKTYPE_MASK 0x0000000f /* [3:0] - 4 bits */ 4882 #define ECI_INLO_TASKTYPE_SHIFT 0 4883 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 4884 #define ECI_INLO_PKTDUR_SHIFT 4 4885 #define ECI_INLO_ROLE_MASK 0x00000100 /* [8] - 1 bits */ 4886 #define ECI_INLO_ROLE_SHIFT 8 4887 #define ECI_INLO_MLP_MASK 0x00000e00 /* [11:9] - 3 bits */ 4888 #define ECI_INLO_MLP_SHIFT 9 4889 #define ECI_INLO_TXPWR_MASK 0x000ff000 /* [19:12] - 8 bits */ 4890 #define ECI_INLO_TXPWR_SHIFT 12 4891 #define ECI_INLO_RSSI_MASK 0x0ff00000 /* [27:20] - 8 bits */ 4892 #define ECI_INLO_RSSI_SHIFT 20 4893 #define ECI_INLO_VAD_MASK 0x10000000 /* [28] - 1 bits */ 4894 #define ECI_INLO_VAD_SHIFT 28 4895 4896 /* 4897 * Register eci_inputlo bitfield values. 4898 * - BT packet type information bits [7:0] 4899 */ 4900 /* [3:0] - Task (link) type */ 4901 #define BT_ACL 0x00 4902 #define BT_SCO 0x01 4903 #define BT_eSCO 0x02 4904 #define BT_A2DP 0x03 4905 #define BT_SNIFF 0x04 4906 #define BT_PAGE_SCAN 0x05 4907 #define BT_INQUIRY_SCAN 0x06 4908 #define BT_PAGE 0x07 4909 #define BT_INQUIRY 0x08 4910 #define BT_MSS 0x09 4911 #define BT_PARK 0x0a 4912 #define BT_RSSISCAN 0x0b 4913 #define BT_MD_ACL 0x0c 4914 #define BT_MD_eSCO 0x0d 4915 #define BT_SCAN_WITH_SCO_LINK 0x0e 4916 #define BT_SCAN_WITHOUT_SCO_LINK 0x0f 4917 /* [7:4] = packet duration code */ 4918 /* [8] - Master / Slave */ 4919 #define BT_MASTER 0 4920 #define BT_SLAVE 1 4921 /* [11:9] - multi-level priority */ 4922 #define BT_LOWEST_PRIO 0x0 4923 #define BT_HIGHEST_PRIO 0x3 4924 /* [19:12] - BT transmit power */ 4925 /* [27:20] - BT RSSI */ 4926 /* [28] - VAD silence */ 4927 /* [31:29] - Undefined */ 4928 /* Register eci_inputmi values - [32:63] - none defined */ 4929 /* [63:32] - Undefined */ 4930 4931 /* Information from WLAN to BT over eci_output register. */ 4932 /* Fields in eci_output register - [0:31] */ 4933 #define ECI48_OUT_MASKMAGIC_HIWORD 0x55550000 4934 #define ECI_OUT_CHANNEL_MASK(ccrev) ((ccrev) < 35 ? 0xf : (ECI48_OUT_MASKMAGIC_HIWORD | 0xf000)) 4935 #define ECI_OUT_CHANNEL_SHIFT(ccrev) ((ccrev) < 35 ? 0 : 12) 4936 #define ECI_OUT_BW_MASK(ccrev) ((ccrev) < 35 ? 0x70 : (ECI48_OUT_MASKMAGIC_HIWORD | 0xe00)) 4937 #define ECI_OUT_BW_SHIFT(ccrev) ((ccrev) < 35 ? 4 : 9) 4938 #define ECI_OUT_ANTENNA_MASK(ccrev) ((ccrev) < 35 ? 0x80 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x100)) 4939 #define ECI_OUT_ANTENNA_SHIFT(ccrev) ((ccrev) < 35 ? 7 : 8) 4940 #define ECI_OUT_SIMUL_TXRX_MASK(ccrev) \ 4941 ((ccrev) < 35 ? 0x10000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x80)) 4942 #define ECI_OUT_SIMUL_TXRX_SHIFT(ccrev) ((ccrev) < 35 ? 16 : 7) 4943 #define ECI_OUT_FM_DISABLE_MASK(ccrev) \ 4944 ((ccrev) < 35 ? 0x40000 : (ECI48_OUT_MASKMAGIC_HIWORD | 0x40)) 4945 #define ECI_OUT_FM_DISABLE_SHIFT(ccrev) ((ccrev) < 35 ? 18 : 6) 4946 4947 /* Indicate control of ECI bits between s/w and dot11mac. 4948 * 0 => FW control, 1=> MAC/ucode control 4949 4950 * Current assignment (ccrev >= 35): 4951 * 0 - TxConf (ucode) 4952 * 38 - FM disable (wl) 4953 * 39 - Allow sim rx (ucode) 4954 * 40 - Num antennas (wl) 4955 * 43:41 - WLAN channel exclusion BW (wl) 4956 * 47:44 - WLAN channel (wl) 4957 * 4958 * (ccrev < 35) 4959 * 15:0 - wl 4960 * 16 - 4961 * 18 - FM disable 4962 * 30 - wl interrupt 4963 * 31 - ucode interrupt 4964 * others - unassigned (presumed to be with dot11mac/ucode) 4965 */ 4966 #define ECI_MACCTRL_BITS 0xbffb0000 4967 #define ECI_MACCTRLLO_BITS 0x1 4968 #define ECI_MACCTRLHI_BITS 0xFF 4969 4970 #endif /* !defined(BCMDONGLEHOST) */ 4971 4972 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */ 4973 #define SECI_STAT_BI (1 << 0) /* Break Interrupt */ 4974 #define SECI_STAT_SPE (1 << 1) /* Parity Error */ 4975 #define SECI_STAT_SFE (1 << 2) /* Parity Error */ 4976 #define SECI_STAT_SDU (1 << 3) /* Data Updated */ 4977 #define SECI_STAT_SADU (1 << 4) /* Auxiliary Data Updated */ 4978 #define SECI_STAT_SAS (1 << 6) /* AUX State */ 4979 #define SECI_STAT_SAS2 (1 << 7) /* AUX2 State */ 4980 #define SECI_STAT_SRITI (1 << 8) /* Idle Timer Interrupt */ 4981 #define SECI_STAT_STFF (1 << 9) /* Tx FIFO Full */ 4982 #define SECI_STAT_STFAE (1 << 10) /* Tx FIFO Almost Empty */ 4983 #define SECI_STAT_SRFE (1 << 11) /* Rx FIFO Empty */ 4984 #define SECI_STAT_SRFAF (1 << 12) /* Rx FIFO Almost Full */ 4985 #define SECI_STAT_SFCE (1 << 13) /* Flow Control Event */ 4986 4987 /* SECI configuration */ 4988 #define SECI_MODE_UART 0x0 4989 #define SECI_MODE_SECI 0x1 4990 #define SECI_MODE_LEGACY_3WIRE_BT 0x2 4991 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 4992 #define SECI_MODE_HALF_SECI 0x4 4993 4994 #define SECI_RESET (1 << 0) 4995 #define SECI_RESET_BAR_UART (1 << 1) 4996 #define SECI_ENAB_SECI_ECI (1 << 2) 4997 #define SECI_ENAB_SECIOUT_DIS (1 << 3) 4998 #define SECI_MODE_MASK 0x7 4999 #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ 5000 #define SECI_UPD_SECI (1 << 7) 5001 5002 #define SECI_AUX_TX_START (1 << 31) 5003 #define SECI_SLIP_ESC_CHAR 0xDB 5004 #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR 5005 #define SECI_SIGNOFF_1 0 5006 #define SECI_REFRESH_REQ 0xDA 5007 5008 /* seci clk_ctl_st bits */ 5009 #define CLKCTL_STS_HT_AVAIL_REQ (1 << 4) 5010 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8) 5011 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) 5012 5013 #define SECI_UART_MSR_CTS_STATE (1 << 0) 5014 #define SECI_UART_MSR_RTS_STATE (1 << 1) 5015 #define SECI_UART_SECI_IN_STATE (1 << 2) 5016 #define SECI_UART_SECI_IN2_STATE (1 << 3) 5017 5018 /* GCI RX FIFO Control Register */ 5019 #define GCI_RXF_LVL_MASK (0xFF << 0) 5020 #define GCI_RXF_TIMEOUT_MASK (0xFF << 8) 5021 5022 /* GCI UART Registers' Bit definitions */ 5023 /* Seci Fifo Level Register */ 5024 #define SECI_TXF_LVL_MASK (0x3F << 8) 5025 #define TXF_AE_LVL_DEFAULT 0x4 5026 #define SECI_RXF_LVL_FC_MASK (0x3F << 16) 5027 5028 /* SeciUARTFCR Bit definitions */ 5029 #define SECI_UART_FCR_RFR (1 << 0) 5030 #define SECI_UART_FCR_TFR (1 << 1) 5031 #define SECI_UART_FCR_SR (1 << 2) 5032 #define SECI_UART_FCR_THP (1 << 3) 5033 #define SECI_UART_FCR_AB (1 << 4) 5034 #define SECI_UART_FCR_ATOE (1 << 5) 5035 #define SECI_UART_FCR_ARTSOE (1 << 6) 5036 #define SECI_UART_FCR_ABV (1 << 7) 5037 #define SECI_UART_FCR_ALM (1 << 8) 5038 5039 /* SECI UART LCR register bits */ 5040 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ 5041 #define SECI_UART_LCR_PARITY_EN (1 << 1) 5042 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ 5043 #define SECI_UART_LCR_RX_EN (1 << 3) 5044 #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ 5045 #define SECI_UART_LCR_TXO_EN (1 << 5) 5046 #define SECI_UART_LCR_RTSO_EN (1 << 6) 5047 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7) 5048 #define SECI_UART_LCR_RXCRC_CHK (1 << 8) 5049 #define SECI_UART_LCR_TXCRC_INV (1 << 9) 5050 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10) 5051 #define SECI_UART_LCR_TXCRC_EN (1 << 11) 5052 #define SECI_UART_LCR_RXSYNC_EN (1 << 12) 5053 5054 #define SECI_UART_MCR_TX_EN (1 << 0) 5055 #define SECI_UART_MCR_PRTS (1 << 1) 5056 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) 5057 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3) 5058 #define SECI_UART_MCR_LOOPBK_EN (1 << 4) 5059 #define SECI_UART_MCR_AUTO_RTS (1 << 5) 5060 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) 5061 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) 5062 #define SECI_UART_MCR_XONOFF_RPT (1 << 9) 5063 5064 /* SeciUARTLSR Bit Mask */ 5065 #define SECI_UART_LSR_RXOVR_MASK (1 << 0) 5066 #define SECI_UART_LSR_RFF_MASK (1 << 1) 5067 #define SECI_UART_LSR_TFNE_MASK (1 << 2) 5068 #define SECI_UART_LSR_TI_MASK (1 << 3) 5069 #define SECI_UART_LSR_TPR_MASK (1 << 4) 5070 #define SECI_UART_LSR_TXHALT_MASK (1 << 5) 5071 5072 /* SeciUARTMSR Bit Mask */ 5073 #define SECI_UART_MSR_CTSS_MASK (1 << 0) 5074 #define SECI_UART_MSR_RTSS_MASK (1 << 1) 5075 #define SECI_UART_MSR_SIS_MASK (1 << 2) 5076 #define SECI_UART_MSR_SIS2_MASK (1 << 3) 5077 5078 /* SeciUARTData Bits */ 5079 #define SECI_UART_DATA_RF_NOT_EMPTY_BIT (1 << 12) 5080 #define SECI_UART_DATA_RF_FULL_BIT (1 << 13) 5081 #define SECI_UART_DATA_RF_OVRFLOW_BIT (1 << 14) 5082 #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF 5083 #define SECI_UART_DATA_RF_RD_PTR_SHIFT 16 5084 #define SECI_UART_DATA_RF_WR_PTR_SHIFT 24 5085 5086 /* LTECX: ltecxmux */ 5087 #define LTECX_EXTRACT_MUX(val, idx) (getbit4(&(val), (idx))) 5088 5089 /* LTECX: ltecxmux MODE */ 5090 #define LTECX_MUX_MODE_IDX 0 5091 #define LTECX_MUX_MODE_WCI2 0x0 5092 #define LTECX_MUX_MODE_GPIO 0x1 5093 5094 /* LTECX GPIO Information Index */ 5095 #define LTECX_NVRAM_FSYNC_IDX 0 5096 #define LTECX_NVRAM_LTERX_IDX 1 5097 #define LTECX_NVRAM_LTETX_IDX 2 5098 #define LTECX_NVRAM_WLPRIO_IDX 3 5099 5100 /* LTECX WCI2 Information Index */ 5101 #define LTECX_NVRAM_WCI2IN_IDX 0 5102 #define LTECX_NVRAM_WCI2OUT_IDX 1 5103 5104 /* LTECX: Macros to get GPIO/FNSEL/GCIGPIO */ 5105 #define LTECX_EXTRACT_PADNUM(val, idx) (getbit8(&(val), (idx))) 5106 #define LTECX_EXTRACT_FNSEL(val, idx) (getbit4(&(val), (idx))) 5107 #define LTECX_EXTRACT_GCIGPIO(val, idx) (getbit4(&(val), (idx))) 5108 5109 /* WLAN channel numbers - used from wifi.h */ 5110 5111 /* WLAN BW */ 5112 #define ECI_BW_20 0x0 5113 #define ECI_BW_25 0x1 5114 #define ECI_BW_30 0x2 5115 #define ECI_BW_35 0x3 5116 #define ECI_BW_40 0x4 5117 #define ECI_BW_45 0x5 5118 #define ECI_BW_50 0x6 5119 #define ECI_BW_ALL 0x7 5120 5121 /* WLAN - number of antenna */ 5122 #define WLAN_NUM_ANT1 TXANT_0 5123 #define WLAN_NUM_ANT2 TXANT_1 5124 5125 /* otpctrl1 0xF4 */ 5126 #define OTPC_FORCE_PWR_OFF 0x02000000 5127 /* chipcommon s/r registers introduced with cc rev >= 48 */ 5128 #define CC_SR_CTL0_ENABLE_MASK 0x1 5129 #define CC_SR_CTL0_ENABLE_SHIFT 0 5130 #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ 5131 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */ 5132 #define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk in sr_engine */ 5133 #define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 /* Allow Subcore mem StandBy? */ 5134 #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 5135 #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 5136 #define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power domains */ 5137 #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 5138 #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 5139 5140 #define CC_SR_CTL1_SR_INIT_MASK 0x3FF 5141 #define CC_SR_CTL1_SR_INIT_SHIFT 0 5142 5143 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 5144 #define ECI_INLO_PKTDUR_SHIFT 4 5145 5146 /* gci chip control bits */ 5147 #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0 5148 #define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT 1 5149 #define GCI_GPIO_CHIPCTRL_INVERT_BIT 2 5150 #define GCI_GPIO_CHIPCTRL_PULLUP_BIT 3 5151 #define GCI_GPIO_CHIPCTRL_PULLDN_BIT 4 5152 #define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT 5 5153 #define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT 6 5154 #define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT 7 5155 5156 /* gci GPIO input status bits */ 5157 #define GCI_GPIO_STS_VALUE_BIT 0 5158 #define GCI_GPIO_STS_POS_EDGE_BIT 1 5159 #define GCI_GPIO_STS_NEG_EDGE_BIT 2 5160 #define GCI_GPIO_STS_FAST_EDGE_BIT 3 5161 #define GCI_GPIO_STS_CLEAR 0xF 5162 5163 #define GCI_GPIO_STS_EDGE_TRIG_BIT 0 5164 #define GCI_GPIO_STS_NEG_EDGE_TRIG_BIT 1 5165 #define GCI_GPIO_STS_DUAL_EDGE_TRIG_BIT 2 5166 #define GCI_GPIO_STS_WL_DIN_SELECT 6 5167 5168 #define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT) 5169 5170 /* SR Power Control */ 5171 #define SRPWR_DMN0_PCIE (0) /* PCIE */ 5172 #define SRPWR_DMN0_PCIE_SHIFT (SRPWR_DMN0_PCIE) /* PCIE */ 5173 #define SRPWR_DMN0_PCIE_MASK (1 << SRPWR_DMN0_PCIE_SHIFT) /* PCIE */ 5174 #define SRPWR_DMN1_ARMBPSD (1) /* ARM/BP/SDIO */ 5175 #define SRPWR_DMN1_ARMBPSD_SHIFT (SRPWR_DMN1_ARMBPSD) /* ARM/BP/SDIO */ 5176 #define SRPWR_DMN1_ARMBPSD_MASK (1 << SRPWR_DMN1_ARMBPSD_SHIFT) /* ARM/BP/SDIO */ 5177 #define SRPWR_DMN2_MACAUX (2) /* MAC/Phy Aux */ 5178 #define SRPWR_DMN2_MACAUX_SHIFT (SRPWR_DMN2_MACAUX) /* MAC/Phy Aux */ 5179 #define SRPWR_DMN2_MACAUX_MASK (1 << SRPWR_DMN2_MACAUX_SHIFT) /* MAC/Phy Aux */ 5180 #define SRPWR_DMN3_MACMAIN (3) /* MAC/Phy Main */ 5181 #define SRPWR_DMN3_MACMAIN_SHIFT (SRPWR_DMN3_MACMAIN) /* MAC/Phy Main */ 5182 #define SRPWR_DMN3_MACMAIN_MASK (1 << SRPWR_DMN3_MACMAIN_SHIFT) /* MAC/Phy Main */ 5183 5184 #define SRPWR_DMN4_MACSCAN (4) /* MAC/Phy Scan */ 5185 #define SRPWR_DMN4_MACSCAN_SHIFT (SRPWR_DMN4_MACSCAN) /* MAC/Phy Scan */ 5186 #define SRPWR_DMN4_MACSCAN_MASK (1 << SRPWR_DMN4_MACSCAN_SHIFT) /* MAC/Phy Scan */ 5187 5188 #define SRPWR_DMN_MAX (5) 5189 /* all power domain mask */ 5190 #define SRPWR_DMN_ALL_MASK(sih) si_srpwr_domain_all_mask(sih) 5191 5192 #define SRPWR_REQON_SHIFT (8) /* PowerOnRequest[11:8] */ 5193 #define SRPWR_REQON_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_REQON_SHIFT) 5194 5195 #define SRPWR_STATUS_SHIFT (16) /* ExtPwrStatus[19:16], RO */ 5196 #define SRPWR_STATUS_MASK(sih) (SRPWR_DMN_ALL_MASK(sih) << SRPWR_STATUS_SHIFT) 5197 5198 #define SRPWR_BT_STATUS_SHIFT (20) /* PowerDomain[20:21], RO */ 5199 #define SRPWR_BT_STATUS_MASK (0x3) 5200 5201 #define SRPWR_DMN_ID_SHIFT (28) /* PowerDomain[31:28], RO */ 5202 #define SRPWR_DMN_ID_MASK (0xF) 5203 5204 #define SRPWR_UP_DOWN_DELAY 100 /* more than 3 ILP clocks */ 5205 5206 /* PMU Precision Usec Timer */ 5207 #define PMU_PREC_USEC_TIMER_ENABLE 0x1 5208 5209 /* Random Number/Bit Generator defines */ 5210 #define MASK_1BIT(offset) (0x1u << offset) 5211 5212 #define CC_RNG_CTRL_0_RBG_EN_SHIFT (0u) 5213 #define CC_RNG_CTRL_0_RBG_EN_MASK (0x1FFFu << CC_RNG_CTRL_0_RBG_EN_SHIFT) 5214 #define CC_RNG_CTRL_0_RBG_EN (0x1FFFu) 5215 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT (12u) 5216 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_MASK (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) 5217 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_1MHz (0x3u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) 5218 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_2MHz (0x2u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) 5219 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_4MHz (0x1u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) 5220 #define CC_RNG_CTRL_0_RBG_DEV_CTRL_8MHz (0x0u << CC_RNG_CTRL_0_RBG_DEV_CTRL_SHIFT) 5221 5222 /* RNG_FIFO_COUNT */ 5223 /* RFC - RNG FIFO COUNT */ 5224 #define CC_RNG_FIFO_COUNT_RFC_SHIFT (0u) 5225 #define CC_RNG_FIFO_COUNT_RFC_MASK (0xFFu << CC_RNG_FIFO_COUNT_RFC_SHIFT) 5226 5227 /* RNG interrupt */ 5228 #define CC_RNG_TOT_BITS_CNT_IRQ_SHIFT (0u) 5229 #define CC_RNG_TOT_BITS_CNT_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_CNT_IRQ_SHIFT) 5230 #define CC_RNG_TOT_BITS_MAX_IRQ_SHIFT (1u) 5231 #define CC_RNG_TOT_BITS_MAX_IRQ_MASK (0x1u << CC_RNG_TOT_BITS_MAX_IRQ_SHIFT) 5232 #define CC_RNG_FIFO_FULL_IRQ_SHIFT (2u) 5233 #define CC_RNG_FIFO_FULL_IRQ_MASK (0x1u << CC_RNG_FIFO_FULL_IRQ_SHIFT) 5234 #define CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT (3u) 5235 #define CC_RNG_FIFO_OVER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_OVER_RUN_IRQ_SHIFT) 5236 #define CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT (4u) 5237 #define CC_RNG_FIFO_UNDER_RUN_IRQ_MASK (0x1u << CC_RNG_FIFO_UNDER_RUN_IRQ_SHIFT) 5238 #define CC_RNG_NIST_FAIL_IRQ_SHIFT (5u) 5239 #define CC_RNG_NIST_FAIL_IRQ_MASK (0x1u << CC_RNG_NIST_FAIL_IRQ_SHIFT) 5240 #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_SHIFT (17u) 5241 #define CC_RNG_STARTUP_TRANSITION_MET_IRQ_MASK (0x1u << \ 5242 CC_RNG_STARTUP_TRANSITION_MET_IRQ_SHIFT) 5243 #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_SHIFT (31u) 5244 #define CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_MASK (0x1u << \ 5245 CC_RNG_MASTER_FAIL_LOCKOUT_IRQ_SHIFT) 5246 5247 /* FISCtrlStatus */ 5248 #define PMU_CLEAR_FIS_DONE_SHIFT 1u 5249 #define PMU_CLEAR_FIS_DONE_MASK (1u << PMU_CLEAR_FIS_DONE_SHIFT) 5250 5251 #define PMU_FIS_FORCEON_ALL_SHIFT 4u 5252 #define PMU_FIS_FORCEON_ALL_MASK (1u << PMU_FIS_FORCEON_ALL_SHIFT) 5253 5254 #define PMU_FIS_DN_TIMER_VAL_SHIFT 16u 5255 #define PMU_FIS_DN_TIMER_VAL_MASK 0x7FFF0000u 5256 5257 #define PMU_FIS_DN_TIMER_VAL_4378 0x2f80u /* micro second */ 5258 #define PMU_FIS_DN_TIMER_VAL_4388 0x3f80u /* micro second */ 5259 #define PMU_FIS_DN_TIMER_VAL_4389 0x3f80u /* micro second */ 5260 5261 #define PMU_FIS_PCIE_SAVE_EN_SHIFT 5u 5262 #define PMU_FIS_PCIE_SAVE_EN_VALUE (1u << PMU_FIS_PCIE_SAVE_EN_SHIFT) 5263 5264 #define PMU_REG6_RFLDO_CTRL 0x000000E0 5265 #define PMU_REG6_RFLDO_CTRL_SHFT 5 5266 5267 #define PMU_REG6_BTLDO_CTRL 0x0000E000 5268 #define PMU_REG6_BTLDO_CTRL_SHFT 13 5269 5270 /* ETBMemCtrl */ 5271 #define CC_ETBMEMCTRL_FORCETMCINTFTOETB_SHIFT 1u 5272 #define CC_ETBMEMCTRL_FORCETMCINTFTOETB_MASK (1u << CC_ETBMEMCTRL_FORCETMCINTFTOETB_SHIFT) 5273 5274 /* SSSR dumps locations on the backplane space */ 5275 #define BCM4387_SSSR_DUMP_AXI_MAIN 0xE8C00000u 5276 #define BCM4387_SSSR_DUMP_MAIN_SIZE 160000u 5277 #define BCM4387_SSSR_DUMP_AXI_AUX 0xE8400000u 5278 #define BCM4387_SSSR_DUMP_AUX_SIZE 160000u 5279 #define BCM4387_SSSR_DUMP_AXI_SCAN 0xE9400000u 5280 #define BCM4387_SSSR_DUMP_SCAN_SIZE 32768u 5281 5282 #endif /* _SBCHIPC_H */ 5283