1 /* 2 * Basic types and constants relating to 802.11ax/HE STA 3 * This is a portion of 802.11ax definition. The rest are in 802.11.h. 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _802_11ax_h_ 26 #define _802_11ax_h_ 27 28 #include <typedefs.h> 29 #include <802.11.h> 30 #include <bcmtlv.h> 31 32 /* This marks the start of a packed structure section. */ 33 #include <packed_section_start.h> 34 35 /* HT Control Field: (Table 9-9a) */ 36 #define HTC_HE_VARIANT 0x03u 37 #define HTC_HEVAR_SHIFT 0 /* HE VARIANT shift */ 38 #define HTC_HEVAR(htc) (((htc) & HTC_HE_VARIANT) >> HTC_HEVAR_SHIFT) 39 40 /* HT Control IDs: (Table 9-18a & Table 9-9a) */ 41 #define HTC_HE_CTLID_SHIFT 0x02u /* HTC HE CTLID shift */ 42 #define HTC_HE_CTLID_MASK 0x0Fu /* HTC HE CTLID mask */ 43 #define HTC_HE_CTLID(htc) (((htc) >> HTC_HE_CTLID_SHIFT) & HTC_HE_CTLID_MASK) 44 45 #define HTC_HE_CTLID_TRS 0x0u /* Triggered response scheduling */ 46 #define HTC_HE_CTLID_OMI 0x1u /* Operating mode */ 47 #define HTC_HE_CTLID_HLA 0x2u /* HE link adaptation */ 48 #define HTC_HE_CTLID_BSR 0x3u /* Buffer status report */ 49 #define HTC_HE_CTLID_UPH 0x4u /* UL power headroom */ 50 #define HTC_HE_CTLID_BQR 0x5u /* Bandwidth query report */ 51 #define HTC_HE_CTLID_CAS 0x6u /* Command and status */ 52 53 /* HTC-Control field definitions: (Table 9.9a HTC Control field) */ 54 #define HTC_HE_CTL_SIZE 30u /* HTC Control field size */ 55 #define HTC_HE_CTL_DEFAULT 0xFFFFFFFC 56 57 /* A-Control offset definitions: (Figure 9.18a Control ID subfield values) */ 58 #define HE_ACTRL_TRS_FSZ 26u 59 #define HE_ACTRL_OMI_FSZ 12u 60 #define HE_ACTRL_HLA_FSZ 26u 61 #define HE_ACTRL_BSR_FSZ 26u 62 #define HE_ACTRL_UPH_FSZ 8u 63 #define HE_ACTRL_BQR_FSZ 10u 64 #define HE_ACTRL_CAS_FSZ 8u 65 66 /* OM-Control Field definitions: (Figure 9.15d Control Information subfield for OM Control) */ 67 #define HE_OMI_RXNSS_FSZ 3 68 #define HE_OMI_RXNSS_IDX 0 69 #define HE_OMI_RXNSS_MASK 0x07u 70 #define HE_OMI_CHW_FSZ 2 71 #define HE_OMI_CHW_IDX 3 72 #define HE_OMI_CHW_MASK 0x18u 73 #define HE_OMI_ULMU_DIS_FSZ 1 74 #define HE_OMI_ULMU_DIS_IDX 5 75 #define HE_OMI_ULMU_DIS_MASK 0x20u 76 #define HE_OMI_TXNSTS_FSZ 3 77 #define HE_OMI_TXNSTS_IDX 6 78 #define HE_OMI_TXNSTS_MASK 0x1c0u 79 #define HE_OMI_ERSU_DIS_FSZ 1 80 #define HE_OMI_ERSU_DIS_IDX 9 81 #define HE_OMI_ERSU_DIS_MASK 0x200u 82 #define HE_OMI_DLMU_RSD_RCM_FSZ 1 83 #define HE_OMI_DLMU_RSD_RCM_IDX 10 84 #define HE_OMI_DLMU_RSD_RCM_MASK 0x400u 85 #define HE_OMI_ULMU_DATA_DIS_FSZ 1 86 #define HE_OMI_ULMU_DATA_DIS_IDX 11 87 #define HE_OMI_ULMU_DATA_DIS_MASK 0x800u 88 89 /* OM-Control Channel Width Subfield definition, as per 9.2.4.6a.2 OM Control */ 90 #define OMI_CHW_20MHZ 0 91 #define OMI_CHW_40MHZ 1 92 #define OMI_CHW_80MHZ 2 93 #define OMI_CHW_160MHZ_80P80MHZ 3 94 95 /* Table 9-18d ACI Bitmap subfield encoding */ 96 #define HE_BSR_ACI_MAP_BE 0u 97 #define HE_BSR_ACI_MAP_BK 1u 98 #define HE_BSR_ACI_MAP_VI 2u 99 #define HE_BSR_ACI_MAP_VO 3u 100 101 /* GI And LTF Type subfield encoding (Table 9-31d) */ 102 #define HE_LTF_1_GI_1_6us (0u) 103 #define HE_LTF_2_GI_1_6us (1u) 104 #define HE_LTF_4_GI_3_2us (2u) 105 106 /* special STA-IDs (Section 27.11.1) */ 107 #define HE_STAID_BSS_BCAST 0 108 #define HE_STAID_UNASSOCIATED_STA 2045u 109 #define HE_STAID_NO_USER 2046u 110 #define HE_STAID_MBSS_BCAST 2047u 111 #define HE_STAID_MASK 0x07FFu 112 #define HE_AID12_MASK 0x0FFFu 113 114 /** 115 * HE Capabilites element (sec 9.4.2.218) 116 */ 117 118 /* HE MAC Capabilities Information field (figure 9-589ck) */ 119 #define HE_MAC_CAP_INFO_SIZE 6u 120 typedef uint8 he_mac_cap_t[HE_MAC_CAP_INFO_SIZE]; 121 122 /* bit position and field width */ 123 #define HE_MAC_HTC_HE_SUPPORT_IDX 0 /* HTC HE Support */ 124 #define HE_MAC_HTC_HE_SUPPORT_FSZ 1 125 #define HE_MAC_TWT_REQ_SUPPORT_IDX 1 /* TWT Requestor Support */ 126 #define HE_MAC_TWT_REQ_SUPPORT_FSZ 1 127 #define HE_MAC_TWT_RESP_SUPPORT_IDX 2 /* TWT Responder Support */ 128 #define HE_MAC_TWT_RESP_SUPPORT_FSZ 1 129 #define HE_MAC_FRAG_SUPPORT_IDX 3 /* Fragmentation Support */ 130 #define HE_MAC_FRAG_SUPPORT_FSZ 2 131 #define HE_MAC_MAX_MSDU_FRAGS_IDX 5 /* Max. Fragmented MSDUs */ 132 #define HE_MAC_MAX_MSDU_FRAGS_FSZ 3 133 #define HE_MAC_MIN_FRAG_SIZE_IDX 8 /* Min. Fragment Size */ 134 #define HE_MAC_MIN_FRAG_SIZE_FSZ 2 135 #define HE_MAC_TRIG_MAC_PAD_DUR_IDX 10 /* Trigger Frame MAC Pad Dur */ 136 #define HE_MAC_TRIG_MAC_PAD_DUR_FSZ 2 137 #define HE_MAC_MULTI_TID_AGG_RX_IDX 12 /* Multi TID Agg. Rx support */ 138 #define HE_MAC_MULTI_TID_AGG_RX_FSZ 3 139 #define HE_MAC_LINK_ADAPT_IDX 15 /* HE Link Adaptation Support */ 140 #define HE_MAC_LINK_ADAPT_FSZ 2 141 #define HE_MAC_ALL_ACK_SUPPORT_IDX 17 /* All Ack Support */ 142 #define HE_MAC_ALL_ACK_SUPPORT_FSZ 1 143 #define HE_MAC_TRS_SUPPORT_IDX 18 /* TRS Support */ 144 #define HE_MAC_TRS_SUPPORT_FSZ 1 145 #define HE_MAC_BSR_SUPPORT_IDX 19 /* BSR Support */ 146 #define HE_MAC_BSR_SUPPORT_FSZ 1 147 #define HE_MAC_BCAST_TWT_SUPPORT_IDX 20 /* Broadcast TWT Support */ 148 #define HE_MAC_BCAST_TWT_SUPPORT_FSZ 1 149 #define HE_MAC_32BA_BITMAP_SUPPORT_IDX 21 /* 32-bit BA Bitmap Support */ 150 #define HE_MAC_32BA_BITMAP_SUPPORT_FSZ 1 151 #define HE_MAC_MU_CASCADE_SUPPORT_IDX 22 /* MU Cascade Support */ 152 #define HE_MAC_MU_CASCADE_SUPPORT_FSZ 1 153 #define HE_MAC_ACK_ENAB_AGG_SUPPORT_IDX 23 /* Ack Enabled Agg. Support */ 154 #define HE_MAC_ACK_ENAB_AGG_SUPPORT_FSZ 1 155 /* bit 24 - Reserved */ 156 #define HE_MAC_OMI_CONTROL_SUPPORT_IDX 25 /* OMI Control Support */ 157 #define HE_MAC_OMI_CONTROL_SUPPORT_FSZ 1 158 #define HE_MAC_OFDMA_RA_SUPPORT_IDX 26 /* OFDMA RA Support */ 159 #define HE_MAC_OFDMA_RA_SUPPORT_FSZ 1 160 #define HE_MAC_MAX_AMPDU_LEN_EXP_IDX 27 /* Max AMPDU Length Exponent */ 161 #define HE_MAC_MAX_AMPDU_LEN_EXP_FSZ 2 162 #define HE_MAC_AMSDU_FRAG_SUPPORT_IDX 29 /* AMSDU Fragementation Support */ 163 #define HE_MAC_AMSDU_FRAG_SUPPORT_FSZ 1 164 #define HE_MAC_FLEX_TWT_SCHEDULE_IDX 30 /* Flexible TWT Schedule Support */ 165 #define HE_MAC_FLEX_TWT_SCHEDULE_FSZ 1 166 #define HE_MAC_RX_MBSS_CTL_FRAME_IDX 31 /* Rx control frames to Multi BSS */ 167 #define HE_MAC_RX_MBSS_CTL_FRAME_FSZ 1 168 #define HE_MAC_RX_AGG_BSRP_BQRP_IDX 32 /* Aggregated BSRP BQRP Rx */ 169 #define HE_MAC_RX_AGG_BSRP_BQRP_FSZ 1 170 #define HE_MAC_QTP_SUPPORT_IDX 33 /* Support Quiet time period */ 171 #define HE_MAC_QTP_SUPPORT_FSZ 1 172 #define HE_MAC_BQR_SUPPORT_IDX 34 /* Support BQR */ 173 #define HE_MAC_BQR_SUPPORT_FSZ 1 174 #define HE_MAC_SRP_RESPONDER_IDX 35 /* SRP responder Support */ 175 #define HE_MAC_SRP_RESPONDER_FSZ 1 176 #define HE_MAC_NDP_FDBK_SUPPORT_IDX 36 /* NDP feedback report Support */ 177 #define HE_MAC_NDP_FDBK_SUPPORT_FSZ 1 178 #define HE_MAC_OPS_SUPPORT_IDX 37 /* OPS support */ 179 #define HE_MAC_OPS_SUPPORT_FSZ 1 180 #define HE_MAC_AMSDU_IN_AMPDU_IDX 38 /* AMSDU in AMPDU support */ 181 #define HE_MAC_AMSDU_IN_AMPDU_FSZ 1 182 #define HE_MAC_MULTI_TID_AGG_TX_IDX 39 /* Multi TID Agg. Tx support */ 183 #define HE_MAC_MULTI_TID_AGG_TX_FSZ 3 184 #define HE_MAC_SST_SUPPORT_IDX 42 /* Sub-channel Selective channel */ 185 #define HE_MAC_SST_SUPPORT_FSZ 1 186 #define HE_MAC_UL_2X_996_TONE_RU_SUPP_IDX 43 /* UL 2X 996 tone RU Support */ 187 #define HE_MAC_UL_2X_996_TONE_RU_SUPP_FSZ 1 188 #define HE_MAC_UL_MU_DATA_DISABLE_RX_IDX 44 /* OM - UL MU Data Disable RX */ 189 #define HE_MAC_UL_MU_DATA_DISABLE_RX_FSZ 1 190 #define HE_MAC_DYNAMIC_SM_PWR_SAVE_IDX 45 /* HE Dynamic SM Power Save */ 191 #define HE_MAC_DYNAMIC_SM_PWR_SAVE_FSZ 1 192 #define HE_MAC_PUNCT_SOUNDING_SUPP_IDX 46 /* Punctured Sounding Support */ 193 #define HE_MAC_PUNCT_SOUNDING_SUPP_FSZ 1 194 #define HE_MAC_HT_VHT_TRIG_FRAME_RX_IDX 47 /* HT And VHT Trigger Frame RX Support */ 195 #define HE_MAC_HT_VHT_TRIG_FRAME_RX_FSZ 1 196 197 /* HE PHY Capabilities Information field (figure 9-589cl) */ 198 #define HE_PHY_CAP_INFO_SIZE 11u 199 typedef uint8 he_phy_cap_t[HE_PHY_CAP_INFO_SIZE]; 200 201 /* bit position and field width */ 202 /* bit 0 - Reserved */ 203 #define HE_PHY_CH_WIDTH_SET_IDX 1 /* Channel Width Set */ 204 #define HE_PHY_CH_WIDTH_SET_FSZ 7 205 #define HE_PHY_PUNCT_PREAMBLE_RX_IDX 8 /* Punctured Preamble Rx */ 206 #define HE_PHY_PUNCT_PREAMBLE_RX_FSZ 4 207 #define HE_PHY_DEVICE_CLASS_IDX 12 /* Device Class */ 208 #define HE_PHY_DEVICE_CLASS_FSZ 1 209 #define HE_PHY_LDPC_PYLD_IDX 13 /* LDPC Coding In Payload */ 210 #define HE_PHY_LDPC_PYLD_FSZ 1 211 #define HE_PHY_SU_PPDU_1x_LTF_0_8_GI_IDX 14 /* SU PPDU 1x LTF GI 0.8 us */ 212 #define HE_PHY_SU_PPDU_1x_LTF_0_8_GI_FSZ 1 213 #define HE_PHY_MIDAMBLE_MAX_NSTS_IDX 15 /* Midamble Tx/Rx Max NSTS */ 214 #define HE_PHY_MIDAMBLE_MAX_NSTS_FSZ 2 215 #define HE_PHY_NDP_4x_LTF_3_2_GI_IDX 17 /* NDP with 4xLTF 3.2us GI */ 216 #define HE_PHY_NDP_4x_LTF_3_2_GI_FSZ 1 217 #define HE_PHY_STBC_TX_IDX 18 /* STBC Tx for <= 80 MHz */ 218 #define HE_PHY_STBC_TX_FSZ 1 219 #define HE_PHY_STBC_RX_IDX 19 /* STBC Rx for <= 80 MHz */ 220 #define HE_PHY_STBC_RX_FSZ 1 221 #define HE_PHY_DOPPLER_TX_IDX 20 /* Doppler Tx */ 222 #define HE_PHY_DOPPLER_TX_FSZ 1 223 #define HE_PHY_DOPPLER_RX_IDX 21 /* Doppler Rx */ 224 #define HE_PHY_DOPPLER_RX_FSZ 1 225 #define HE_PHY_FULL_BW_UL_MU_MIMO_IDX 22 /* Full bandwidth UL MU MIMO */ 226 #define HE_PHY_FULL_BW_UL_MU_MIMO_FSZ 1 227 #define HE_PHY_PART_BW_UL_MU_MIMO_IDX 23 /* Partial bandwidth UL MU MIMO */ 228 #define HE_PHY_PART_BW_UL_MU_MIMO_FSZ 1 229 #define HE_PHY_DCM_MAX_CONST_TX_IDX 24 /* DCM Max Constellation Tx */ 230 #define HE_PHY_DCM_MAX_CONST_TX_FSZ 2 231 #define HE_PHY_DCM_MAX_NSS_TX_IDX 26 /* DCM Max NSS Tx */ 232 #define HE_PHY_DCM_MAX_NSS_TX_FSZ 1 233 #define HE_PHY_DCM_MAX_CONST_RX_IDX 27 /* DCM Max Constellation Rx */ 234 #define HE_PHY_DCM_MAX_CONST_RX_FSZ 2 235 #define HE_PHY_DCM_MAX_NSS_RX_IDX 29 /* DCM Max NSS Rx */ 236 #define HE_PHY_DCM_MAX_NSS_RX_FSZ 1 237 #define HE_PHY_RX_MU_PPDU_IDX 30 /* Rx HE MU PPDU From nonAP STA */ 238 #define HE_PHY_RX_MU_PPDU_FSZ 1 239 #define HE_PHY_SU_BEAMFORMER_IDX 31 /* SU Beamformer */ 240 #define HE_PHY_SU_BEAMFORMER_FSZ 1 241 #define HE_PHY_SU_BEAMFORMEE_IDX 32 /* SU Beamformee */ 242 #define HE_PHY_SU_BEAMFORMEE_FSZ 1 243 #define HE_PHY_MU_BEAMFORMER_IDX 33 /* MU Beamformer */ 244 #define HE_PHY_MU_BEAMFORMER_FSZ 1 245 #define HE_PHY_BEAMFORMEE_STS_BELOW80MHZ_IDX 34 /* Beamformee STS For <= 80MHz */ 246 #define HE_PHY_BEAMFORMEE_STS_BELOW80MHZ_FSZ 3 247 #define HE_PHY_BEAMFORMEE_STS_ABOVE80MHZ_IDX 37 /* Beamformee STS For >80 MHz */ 248 #define HE_PHY_BEAMFORMEE_STS_ABOVE80MHZ_FSZ 3 249 #define HE_PHY_SOUND_DIM_BELOW80MHZ_IDX 40 /* Num. Sounding Dim.<= 80 MHz */ 250 #define HE_PHY_SOUND_DIM_BELOW80MHZ_FSZ 3 251 #define HE_PHY_SOUND_DIM_ABOVE80MHZ_IDX 43 /* Num. Sounding Dim.> 80 MHz */ 252 #define HE_PHY_SOUND_DIM_ABOVE80MHZ_FSZ 3 253 #define HE_PHY_SU_FEEDBACK_NG16_SUPPORT_IDX 46 /* Ng=16 For SU Feedback */ 254 #define HE_PHY_SU_FEEDBACK_NG16_SUPPORT_FSZ 1 255 #define HE_PHY_MU_FEEDBACK_NG16_SUPPORT_IDX 47 /* Ng=16 For MU Feedback */ 256 #define HE_PHY_MU_FEEDBACK_NG16_SUPPORT_FSZ 1 257 #define HE_PHY_SU_CODEBOOK_SUPPORT_IDX 48 /* Codebook Sz {4, 2} For SU */ 258 #define HE_PHY_SU_CODEBOOK_SUPPORT_FSZ 1 259 #define HE_PHY_MU_CODEBOOK_SUPPORT_IDX 49 /* Codebook Size {7, 5} For MU */ 260 #define HE_PHY_MU_CODEBOOK_SUPPORT_FSZ 1 261 #define HE_PHY_TRG_SU_BFM_FEEDBACK_IDX 50 /* Triggered SU TXBF Feedback */ 262 #define HE_PHY_TRG_SU_BFM_FEEDBACK_FSZ 1 263 #define HE_PHY_TRG_MU_BFM_FEEDBACK_IDX 51 /* Triggered MU TXBF partial BW Feedback */ 264 #define HE_PHY_TRG_MU_BFM_FEEDBACK_FSZ 1 265 #define HE_PHY_TRG_CQI_FEEDBACK_IDX 52 /* Triggered CQI Feedback */ 266 #define HE_PHY_TRG_CQI_FEEDBACK_FSZ 1 267 #define HE_PHY_PART_BW_EXT_RANGE_IDX 53 /* Partial BW Extended Range */ 268 #define HE_PHY_PART_BW_EXT_RANGE_FSZ 1 269 #define HE_PHY_DL_MU_MIMO_PART_BW_IDX 54 /* Partial Bandwidth DL MU MIMO */ 270 #define HE_PHY_DL_MU_MIMO_PART_BW_FSZ 1 271 #define HE_PHY_PPE_THRESH_PRESENT_IDX 55 /* PPE Threshold Present */ 272 #define HE_PHY_PPE_THRESH_PRESENT_FSZ 1 273 #define HE_PHY_SRP_SR_SUPPORT_IDX 56 /* SRP based SR Support */ 274 #define HE_PHY_SRP_SR_SUPPORT_FSZ 1 275 #define HE_PHY_POWER_BOOST_FACTOR_IDX 57 /* Power Boost Factor Support */ 276 #define HE_PHY_POWER_BOOST_FACTOR_FSZ 1 277 #define HE_PHY_4X_LTF_0_8_GI_SUPPORT_IDX 58 /* HE SU PPDU And HE MU PPDU with 278 * 4x HE-LTF And 0.8 us GI 279 */ 280 #define HE_PHY_4X_LTF_0_8_GI_SUPPORT_FSZ 1 281 #define HE_PHY_MAX_NC_IDX 59 /* Maximum NC */ 282 #define HE_PHY_MAX_NC_FSZ 3 283 #define HE_PHY_STBC_TX_ABOVE_80_IDX 62 /* STBC Tx above 80 MHz */ 284 #define HE_PHY_STBC_TX_ABOVE_80_FSZ 1 285 #define HE_PHY_STBC_RX_ABOVE_80_IDX 63 /* STBC Rx above 80 MHz */ 286 #define HE_PHY_STBC_RX_ABOVE_80_FSZ 1 287 #define HE_PHY_ER_SU_4X_LTF_0_8_GI_IDX 64 /* ER SU PPDU 4x HE-LTF 0.8 GI */ 288 #define HE_PHY_ER_SU_4X_LTF_0_8_GI_FSZ 1 289 #define HE_PHY_20_IN_40_2G_IDX 65 /* 20 in 40 MHz HE PPDU in 2G */ 290 #define HE_PHY_20_IN_40_2G_FSZ 1 291 #define HE_PHY_20_IN_160_80P80_IDX 66 /* 20 in 160/80+80 MHz HE PPDU */ 292 #define HE_PHY_20_IN_160_80P80_FSZ 1 293 #define HE_PHY_80_IN_160_80P80_IDX 67 /* 80 in 160/80+80 MHz HE PPDU */ 294 #define HE_PHY_80_IN_160_80P80_FSZ 1 295 #define HE_PHY_ER_SU_1X_LTF_0_8_GI_IDX 68 /* HE ER SU 1x HE-LTF 0.8 GI */ 296 #define HE_PHY_ER_SU_1X_LTF_0_8_GI_FSZ 1 297 #define HE_PHY_MIDAMBLE_2X_1X_LTF_IDX 69 /* Midamble TX/RX 2x & 1x HE LTF */ 298 #define HE_PHY_MIDAMBLE_2X_1X_LTF_FSZ 1 299 #define HE_PHY_DCM_MAX_BW_IDX 70 /* DCM Max BW */ 300 #define HE_PHY_DCM_MAX_BW_FSZ 2 301 #define HE_PHY_ABOVE16_OFDM_SYM_IDX 72 /* Longer than 16 HE-SIGB OFDM 302 * Symbol support 303 */ 304 #define HE_PHY_ABOVE16_OFDM_SYM_FSZ 1 305 #define HE_PHY_NON_TRIG_CQI_FDBK_IDX 73 /* Non-triggered CQI feedback Support */ 306 #define HE_PHY_NON_TRIG_CQI_FDBK_FSZ 1 307 #define HE_PHY_1024_QAM_TX_BELOW_242_RU_IDX 74 /* Tx 1024 QAM in < 242 RU Tone Support */ 308 #define HE_PHY_1024_QAM_TX_BELOW_242_RU_FSZ 1 309 #define HE_PHY_1024_QAM_RX_BELOW_242_RU_IDX 75 /* Rx 1024 QAM in < 242 RU Tone Support */ 310 #define HE_PHY_1024_QAM_RX_BELOW_242_RU_FSZ 1 311 #define HE_PHY_RX_FULL_BW_MU_COMP_SIGB_IDX 76 /* Rx Full BW MU PPDU with Comp. SIGB */ 312 #define HE_PHY_RX_FULL_BW_MU_COMP_SIGB_FSZ 1 313 #define HE_PHY_RX_FULL_BW_MU_NON_COMP_SIGB_IDX 77 /* Rx Full BW MU PPDU Non-Comp SIGB */ 314 #define HE_PHY_RX_FULL_BW_MU_NON_COMP_SIGB_FSZ 1 315 316 /* HE Mac Capabilities values */ 317 /* b3-b4: Fragmentation Support field (table 9-262z) */ 318 #define HE_MAC_FRAG_NOSUPPORT 0 /* dynamic fragmentation not supported */ 319 #define HE_MAC_FRAG_PER_MPDU 1 /* dynamic fragmentation of MPDU/SMPDU */ 320 #define HE_MAC_FRAG_ONE_PER_AMPDU 2 /* upto 1 fragment per AMPDU/MMPDU */ 321 #define HE_MAC_FRAG_MULTI_PER_AMPDU 3 /* multiple fragment per AMPDU */ 322 323 /* b5-b7 : Maximum Number Of Fragmented MSDUs/AMSDUs Exponent */ 324 #define HE_MAC_MAXFRAG_NUM_NO_RESTRICT 7 325 326 /* b8-b9: Minimum payload size of first fragment */ 327 #define HE_MAC_MINFRAG_NO_RESTRICT 0 /* no restriction on min. payload size */ 328 #define HE_MAC_MINFRAG_SIZE_128 1 /* minimum payload size of 128 Bytes */ 329 #define HE_MAC_MINFRAG_SIZE_256 2 /* minimum payload size of 256 Bytes */ 330 #define HE_MAC_MINFRAG_SIZE_512 3 /* minimum payload size of 512 Bytes */ 331 332 /* b10-b11: Trigger Frame MAC Padding Duration */ 333 #define HE_MAC_TRIG_MAC_PAD_0 0 334 #define HE_MAC_TRIG_MAC_PAD_8us 1 335 #define HE_MAC_TRIG_MAC_PAD_16us 2 336 337 /* b15-b16: HE Link Adaptation */ 338 #define HE_MAC_SEND_NO_MFB 0 /* if STA does not provide HE MFB */ 339 #define HE_MAC_SEND_UNSOLICATED_MFB 2 /* if STA provides unsolicited HE MFB */ 340 #define HE_MAC_SEND_MFB_IN_RESPONSE 3 /* if STA can provide HE MFB in response to 341 * HE MRQ and if the STA provides unsolicited HE MFB. 342 */ 343 344 /* b27-b28: Max. AMPDU Length HE Exponent */ 345 /* Use Max AMPDU length exponent from VHT or HT */ 346 #define HE_MAC_MAX_AMPDU_EXP_ADOPT_VHT (0) 347 /* Max. AMPDU length = 348 * 2^(20 + MAX_AMPDU_LEN_HE_EXPO_1) -1 (if this value in VHT CAP is 7) or 349 * 2^(16 + MAX_AMPDU_LEN_HE_EXPO_1) -1 (if this value in HT CAP is 3). 350 */ 351 #define HE_MAC_MAX_AMPDU_EXP_HE_1 (1) 352 /* Max. AMPDU length = 353 * 2^(20 + MAX_AMPDU_LEN_HE_EXPO_2) -1 (if this value in VHT CAP is 7) or 354 * 2^(16 + MAX_AMPDU_LEN_HE_EXPO_2) -1 (if this value in HT CAP is 3). 355 */ 356 #define HE_MAC_MAX_AMPDU_EXP_HE_2 (2) 357 /* Max. AMPDU length = 358 * 2^(20 + MAX_AMPDU_LEN_HE_EXPO_3) -1 (if this value in VHT CAP is 7) or 359 * 2^(16 + MAX_AMPDU_LEN_HE_EXPO_3) -1 (if this value in HT CAP is 3). 360 */ 361 #define HE_MAC_MAX_AMPDU_EXP_HE_3 (3) 362 363 /* HE PHY Capabilities values */ 364 /* b1-b7: Channel Width Support field */ 365 #define HE_PHY_CH_WIDTH_2G_40 0x01 366 #define HE_PHY_CH_WIDTH_5G_80 0x02 367 #define HE_PHY_CH_WIDTH_5G_160 0x04 368 #define HE_PHY_CH_WIDTH_5G_80P80 0x08 369 #define HE_PHY_CH_WIDTH_2G_242RU 0x10 370 #define HE_PHY_CH_WIDTH_5G_242RU 0x20 371 372 /* b8-b11: Preamble puncturing Rx */ 373 /* Rx of 80 MHz preamble where secondary 20 MHz subchannel is punctured */ 374 #define HE_PHY_PREAMBLE_PUNC_RX_0 0x1 375 /* Rx of 80 MHz preamble where one of two 20 MHz subchannels in secondary 40 MHz is punctured */ 376 #define HE_PHY_PREAMBLE_PUNC_RX_1 0x2 377 /* Rx of 160 MHz or 80+80 MHz preamble where primary 80 MHz of 378 * preamble only the secondary 20 MHz is punctured 379 */ 380 #define HE_PHY_PREAMBLE_PUNC_RX_2 0x4 381 /* Rx of 160 MHz or 80+80 MHz preamble where primary 80 MHz of 382 * the preamble, the primary 40 MHz is present 383 */ 384 #define HE_PHY_PREAMBLE_PUNC_RX_3 0x8 385 386 /* b24-b26: DCM Encoding Tx */ 387 #define HE_PHY_TX_DCM_ENC_NOSUPPORT 0x00 388 #define HE_PHY_TX_DCM_ENC_BPSK 0x01 389 #define HE_PHY_TX_DCM_ENC_QPSK 0x02 390 #define HE_PHY_TX_DCM_ENC_QAM 0x03 391 392 #define HE_PHY_TX_DCM_1_SS 0x00 393 #define HE_PHY_TX_DCM_2_SS 0x01 394 395 /* b27-b29: DCM Encoding Rx */ 396 #define HE_PHY_RX_DCM_ENC_NOSUPPORT 0x00 397 #define HE_PHY_RX_DCM_ENC_BPSK 0x01 398 #define HE_PHY_RX_DCM_ENC_QPSK 0x02 399 #define HE_PHY_RX_DCM_ENC_QAM 0x03 400 401 #define HE_PHY_RX_DCM_1_SS 0x00 402 #define HE_PHY_RX_DCM_2_SS 0x01 403 404 /* b70-b71: DCM Max BW */ 405 #define HE_PHY_DCM_MAX_BW_20 0 406 #define HE_PHY_DCM_MAX_BW_40 1 407 #define HE_PHY_DCM_MAX_BW_80 2 408 #define HE_PHY_DCM_MAX_BW_160 3 409 410 /* HE Duration based RTS Threshold Figure 9-589cr */ 411 #define HE_RTS_THRES_DISABLED 1023 412 #define HE_RTS_THRES_ALL_FRAMES 0 413 #define HE_RTS_THRES_MASK 0x03ff 414 415 /* Tx Rx HE MCS Support field format : Table 9-589cm */ 416 #define HE_TX_RX_MCS_NSS_SUP_FIELD_MIN_SIZE 4u 417 418 /** 419 * Bandwidth configuration indices used in the HE TX-RX MCS support field 420 * Section 9.4.2.218.4 421 */ 422 #define HE_BW20_CFG_IDX 0 423 #define HE_BW40_CFG_IDX 1 424 #define HE_BW80_CFG_IDX 2 425 #define HE_BW80P80_CFG_IDX 3 426 #define HE_BW160_CFG_IDX 4 427 #define HE_MAX_BW_CFG 5 428 429 #define HE_MCS_CODE_0_7 0u 430 #define HE_MCS_CODE_0_9 1u 431 #define HE_MCS_CODE_0_11 2u 432 #define HE_MCS_CODE_NONE 3u 433 #define HE_MCS_CODE_SIZE 2u /* num bits */ 434 #define HE_MCS_CODE_MASK 0x3u /* mask for 1-stream */ 435 436 /* Defines for The Max HE MCS For n SS subfield (where n = 1, ..., 8) */ 437 #define HE_MCS_MAP_NSS_MAX 8u /* Max number of streams possible */ 438 #define HE_MCS_NSS_SET_MASK 0xffffu /* Field is to be 16 bits long */ 439 #define HE_MCS_NSS_GET_SS_IDX(nss) (((nss)-1u) * HE_MCS_CODE_SIZE) 440 #define HE_MCS_NSS_GET_MCS(nss, mcs_nss_map) \ 441 (((mcs_nss_map) >> HE_MCS_NSS_GET_SS_IDX(nss)) & HE_MCS_CODE_MASK) 442 #define HE_MCS_NSS_SET_MCS(nss, mcs_code, mcs_nss_map) \ 443 do { \ 444 (mcs_nss_map) &= (~(HE_MCS_CODE_MASK << HE_MCS_NSS_GET_SS_IDX(nss))); \ 445 (mcs_nss_map) |= (((mcs_code) & HE_MCS_CODE_MASK) << HE_MCS_NSS_GET_SS_IDX(nss)); \ 446 (mcs_nss_map) &= (HE_MCS_NSS_SET_MASK); \ 447 } while (0) 448 449 #define HE_BW80_ORDR_IDX 0u 450 #define HE_BW160_ORDR_IDX 1u 451 #define HE_BW80P80_ORDR_IDX 2u 452 453 #define HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN 2u /* 2 bytes */ 454 #define HE_MCS_NSS_SUP_FLD_UNIT_MAP_SZ (HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN * 8u) /* 16 bits */ 455 456 /* Two unit-maps (TX+RX) */ 457 #define HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN (HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN * 2u) 458 #define HE_MCS_NSS_SUP_FLD_TXRX_MAP_SZ (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN * 8u) /* 32 bits */ 459 460 /* One TX-RX unit-map (80 MHz) */ 461 #define HE_MCS_NSS_SUP_FLD_MIN_LEN (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN) 462 /* Three TX-RX unit-maps (80 MHz, 160MHz, 80+80MHz) */ 463 #define HE_MCS_NSS_SUP_FLD_MAX_LEN (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN * 3u) 464 465 /* HE Capabilities element */ 466 BWL_PRE_PACKED_STRUCT struct he_cap_ie { 467 uint8 id; 468 uint8 len; 469 uint8 id_ext; 470 he_mac_cap_t mac_cap; /* MAC Capabilities Information */ 471 he_phy_cap_t phy_cap; /* PHY Capabilities Information */ 472 /* he_tx_rx_mcs_nss_sup_t txx_rx_mcs_nss_sup; */ /* Tx Rx HE MCS NSS Support (variable) */ 473 /* he_ppe_ths_t ppe_ths; */ /* PPE Thresholds (optional) */ 474 } BWL_POST_PACKED_STRUCT; 475 476 typedef struct he_cap_ie he_cap_ie_t; 477 478 /* Multiple BSSID element */ 479 BWL_PRE_PACKED_STRUCT struct nontrans_BSSID_cap { 480 uint8 id; /* 83 */ 481 uint8 len; 482 uint16 capability; 483 } BWL_POST_PACKED_STRUCT; 484 485 typedef struct nontrans_BSSID_cap nontrans_BSSID_cap_t; 486 487 BWL_PRE_PACKED_STRUCT struct multi_BSSID_index { 488 uint8 id; /* 85 */ 489 uint8 len; /* 3 in beacon, 1 in probe response */ 490 uint8 bssid_index; /* between 1 and 2^n - 1 */ 491 uint8 dtim_period; /* only valid in beacon */ 492 uint8 dtim_count; /* only valid in beacon */ 493 } BWL_POST_PACKED_STRUCT; 494 495 typedef struct multi_BSSID_index multi_BSSID_index_t; 496 497 BWL_PRE_PACKED_STRUCT struct fms_descriptor { 498 uint8 id; /* 86 */ 499 uint8 len; 500 uint8 num_FMS_counters; 501 uint8 *FMS_counters; 502 uint8 *FMSID; 503 } BWL_POST_PACKED_STRUCT; 504 505 typedef struct fms_descriptor fms_descriptor_t; 506 507 BWL_PRE_PACKED_STRUCT struct nontrans_BSSID_profile_subie { 508 uint8 subie_id; /* 0 */ 509 uint8 subie_len; 510 uint8 moreie[1]; 511 } BWL_POST_PACKED_STRUCT; 512 513 typedef struct nontrans_BSSID_profile_subie nontrans_BSSID_profile_subie_t; 514 515 BWL_PRE_PACKED_STRUCT struct multi_BSSID_ie { 516 uint8 id; 517 uint8 len; 518 uint8 maxBSSID_indicator; 519 nontrans_BSSID_profile_subie_t profile[1]; 520 } BWL_POST_PACKED_STRUCT; 521 522 typedef struct multi_BSSID_ie multi_BSSID_ie_t; 523 #define DOT11_MULTIPLE_BSSID_PROFILE_SUBID 0 524 525 /* Table 9-262ab, Highest MCS Supported subfield encoding */ 526 #define HE_CAP_MCS_CODE_0_7 0 527 #define HE_CAP_MCS_CODE_0_8 1 528 #define HE_CAP_MCS_CODE_0_9 2 529 #define HE_CAP_MCS_CODE_0_10 3 530 #define HE_CAP_MCS_CODE_0_11 4 531 #define HE_CAP_MCS_CODE_SIZE 3 /* num bits for 1-stream */ 532 #define HE_CAP_MCS_CODE_MASK 0x7 /* mask for 1-stream */ 533 534 #define HE_CAP_MCS_MAP_NSS_MAX 8u /* Max number of streams possible */ 535 536 #define HE_MAX_RU_COUNT 4u /* Max number of RU allocation possible */ 537 538 #define HE_NSSM1_IDX 0 /* Offset of NSSM1 field */ 539 #define HE_NSSM1_LEN 3 /* length of NSSM1 field in bits */ 540 541 #define HE_RU_INDEX_MASK_IDX 3 /* Offset of RU index mask field */ 542 #define HE_RU_INDEX_MASK_LEN 4u /* length of RU Index mask field in bits */ 543 544 /* PPE Threshold field (figure 9-589co) */ 545 #define HE_PPE_THRESH_NSS_RU_FSZ 3u 546 547 /* PPE Threshold Info field (figure 9-589cp) */ 548 /* ruc: RU Count; NSSnM1: NSSn - 1; RUmM1: RUm - 1 */ 549 /* bit offset in PPE Threshold field */ 550 #define HE_PPET16_BIT_OFFSET(ruc, NSSnM1, RUmM1) \ 551 (HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((NSSnM1) * (ruc) + (RUmM1)) * 6) 552 553 #define HE_PPET8_BIT_OFFSET(ruc, NSSnM1, RUmM1) \ 554 (HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((NSSnM1) * (ruc) + (RUmM1)) * 6 + 3) 555 556 /* Total PPE Threshold field byte length (Figure 9-589cq) */ 557 #define HE_PPE_THRESH_LEN(nss, ruc) \ 558 (CEIL((HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((nss) * (ruc) * 6)), 8)) 559 560 /* RU Allocation Index encoding (table 9-262ae) */ 561 #define HE_RU_ALLOC_IDX_242 0 /* RU alloc: 282 tones */ 562 #define HE_RU_ALLOC_IDX_484 1 /* RU alloc: 484 tones - 40Mhz */ 563 #define HE_RU_ALLOC_IDX_996 2 /* RU alloc: 996 tones - 80Mhz */ 564 #define HE_RU_ALLOC_IDX_2x996 3 /* RU alloc: 2x996 tones - 80p80/160Mhz */ 565 566 /* Constellation Index encoding (table 9-262ac) */ 567 #define HE_CONST_IDX_BPSK 0 568 #define HE_CONST_IDX_QPSK 1 569 #define HE_CONST_IDX_16QAM 2 570 #define HE_CONST_IDX_64QAM 3 571 #define HE_CONST_IDX_256QAM 4 572 #define HE_CONST_IDX_1024QAM 5 573 #define HE_CONST_IDX_RSVD 6 574 #define HE_CONST_IDX_NONE 7 575 576 /* Min HE cap ie length when only 80Mhz is supported */ 577 #define HE_CAP_IE_MIN_LEN (sizeof(he_cap_ie_t) - TLV_HDR_LEN + HE_MCS_NSS_SUP_FLD_MIN_LEN) 578 579 /* Max HE cap ie length considering MAX NSS and RU */ 580 #define HE_CAP_IE_MAX_LEN (sizeof(he_cap_ie_t) - TLV_HDR_LEN + HE_MCS_NSS_SUP_FLD_MAX_LEN + \ 581 HE_PPE_THRESH_LEN(HE_CAP_MCS_MAP_NSS_MAX, HE_MAX_RU_COUNT)) 582 /** 583 * HE Operation IE (Section 9.4.2.238) 584 */ 585 /* HE Operation Parameters field (figure 9-589cr) */ 586 #define HE_OP_PARAMS_SIZE 3u 587 typedef uint8 he_op_parms_t[HE_OP_PARAMS_SIZE]; 588 589 /* bit position and field width */ 590 #define HE_OP_DEF_PE_DUR_IDX 0u /* Default PE Duration */ 591 #define HE_OP_DEF_PE_DUR_FSZ 3u 592 #define HE_OP_TWT_REQD_IDX 3u /* TWT Required */ 593 #define HE_OP_TWT_REQD_FSZ 1u 594 #define HE_OP_TXOP_DUR_RTS_THRESH_IDX 4u /* TXOP Duration Based RTS Threshold */ 595 #define HE_OP_TXOP_DUR_RTS_THRESH_FSZ 10u 596 #define HE_OP_VHT_OP_PRESENT_IDX 14u /* VHT Oper Info Present */ 597 #define HE_OP_VHT_OP_PRESENT_FSZ 1u 598 #define HE_OP_COL_LOC_BSS_IDX 15u 599 #define HE_OP_COL_LOC_BSS_FSZ 1u 600 #define HE_OP_ER_SU_DISABLE_IDX 16u 601 #define HE_OP_ER_SU_DISABLE_FSZ 1u 602 #define HE_OP_6G_OP_INFO_PRESENT_IDX 17u 603 #define HE_OP_6G_OP_INFO_PRESENT_FSZ 1u 604 605 /* BSS Color Information field (figure 9-589cs) */ 606 #define HE_OP_BSS_COLOR_IDX 0 /* BSS Color */ 607 #define HE_OP_BSS_COLOR_FSZ 6 608 #define HE_OP_PART_BSS_COLOR_IDX 6 /* Partial BSS Color */ 609 #define HE_OP_PART_BSS_COLOR_FSZ 1 610 #define HE_OP_DISABLE_BSSCOLOR_IDX 7 /* BSS Color Disable */ 611 #define HE_OP_DISABLE_BSSCOLOR_FSZ 1 612 613 /* b4-b13: TXOP Duration RTS threshold */ 614 #define HE_OP_TXOP_RTS_THRESH_DISABLED 1023u 615 616 #define HE_BASIC_MCS_NSS_SIZE 2u 617 typedef uint8 he_basic_mcs_nss_set_t[HE_BASIC_MCS_NSS_SIZE]; 618 619 #define HE_OP_MAX_BSSID_IND_LEN 1u 620 #define HE_OP_6G_OPER_INFO_LEN 5u 621 /* HE Operation element */ 622 BWL_PRE_PACKED_STRUCT struct he_op_ie { 623 uint8 id; 624 uint8 len; 625 uint8 id_ext; 626 he_op_parms_t parms; 627 uint8 bsscolor_info; 628 he_basic_mcs_nss_set_t mcs_nss_op; /* Basic HE MCS & NSS Set */ 629 } BWL_POST_PACKED_STRUCT; 630 631 typedef struct he_op_ie he_op_ie_t; 632 633 #define HE_OP_IE_MIN_LEN (sizeof(he_op_ie_t) - TLV_HDR_LEN) 634 #define HE_OP_IE_MAX_LEN (sizeof(he_op_ie_t) - TLV_HDR_LEN + VHT_OP_INFO_LEN +\ 635 HE_OP_MAX_BSSID_IND_LEN + HE_OP_6G_OPER_INFO_LEN) 636 637 #define HE_6G_OP_BW_20 0u 638 #define HE_6G_OP_BW_40 1u 639 #define HE_6G_OP_BW_80 2u 640 #define HE_6G_OP_BW_160_80P80 3u 641 642 /* Regulatory Info subfield in the United States */ 643 #define HE_6G_OP_REG_INFO_INDOOR_AP_US 0u 644 #define HE_6G_OP_REG_INFO_SP_AP_US 1u 645 646 /* Figure 9-788l Control field format in Draft P802.11ax_D6.0 */ 647 #define HE_6G_CTL_CHBW_MASK 0x03u 648 #define HE_6G_OP_CTL_CHBW(ctl) (ctl & HE_6G_CTL_CHBW_MASK) 649 #define HE_6G_CTL_DUP_BCN_MASK 0x04u 650 #define HE_6G_CTL_REG_INFO_MASK 0x38u 651 #define HE_6G_CTL_REG_INFO_SHIFT 3u 652 #define HE_6G_OP_CTL_REG_INFO(ctl) \ 653 ((ctl & HE_6G_CTL_REG_INFO_MASK) >> HE_6G_CTL_REG_INFO_SHIFT) 654 655 /* HE 6G Operation info */ 656 BWL_PRE_PACKED_STRUCT struct he_6g_op_info { 657 uint8 pri_chan; 658 uint8 control; 659 uint8 seg0; 660 uint8 seg1; 661 uint8 min_rate; 662 } BWL_POST_PACKED_STRUCT; 663 664 typedef struct he_6g_op_info he_6g_op_info_t; 665 666 /* HE Extended Capabilities element */ 667 BWL_PRE_PACKED_STRUCT struct he_6g_cap_ie { 668 uint8 id; 669 uint8 len; 670 uint8 id_ext; 671 uint16 cap_info; /* Capabilities Information */ 672 } BWL_POST_PACKED_STRUCT; 673 674 typedef struct he_6g_cap_ie he_6g_cap_ie_t; 675 #define HE_6G_CAP_IE_LEN sizeof(he_6g_cap_ie_t) 676 677 /* HE Capabilities Information bit position and fieldwidth. 678 * Figure 9-787ai Capabilities Information field format in 679 * Draft P802.11ax_D5.0. 680 */ 681 #define HE_6G_CAP_MIN_MPDU_START_MASK 0x0007u 682 #define HE_6G_CAP_MAX_AMPDU_LEN_EXP_MASK 0x0038u 683 #define HE_6G_CAP_MAX_AMPDU_LEN_EXP_SHIFT 3u 684 #define HE_6G_CAP_MAX_MPDU_LEN_MASK 0x00C0u 685 #define HE_6G_CAP_MAX_MPDU_LEN_SHIFT 6u 686 #define HE_6G_CAP_SM_PW_SAVE_MASK 0x0600u 687 #define HE_6G_CAP_SM_PW_SAVE_SHIFT 9u 688 #define HE_6G_CAP_RD_RESPONDER_MASK 0x0800u 689 #define HE_6G_CAP_RD_RESPONDER_SHIFT 11u 690 #define HE_6G_CAP_RX_ANT_PATN_CONST_MASK 0x1000u 691 #define HE_6G_CAP_RX_ANT_PATN_CONST_SHIFT 12u 692 #define HE_6G_CAP_TX_ANT_PATN_CONST_MASK 0x2000u 693 #define HE_6G_CAP_TX_ANT_PATN_CONST_SHIFT 13u 694 695 #define HE_6G_CAP_MIN_MPDU_START(cap) ((cap) & HE_6G_CAP_MIN_MPDU_START_MASK) 696 #define HE_6G_CAP_MAX_AMPDU_LEN_EXP(cap) (((cap) & HE_6G_CAP_MAX_AMPDU_LEN_EXP_MASK) >> \ 697 HE_6G_CAP_MAX_AMPDU_LEN_EXP_SHIFT) 698 #define HE_6G_CAP_MAX_MPDU_LEN(cap) (((cap) & HE_6G_CAP_MAX_MPDU_LEN_MASK) >> \ 699 HE_6G_CAP_MAX_MPDU_LEN_SHIFT) 700 #define HE_6G_CAP_SM_PW_SAVE(cap) (((cap) & HE_6G_CAP_SM_PW_SAVE_MASK) >> \ 701 HE_6G_CAP_SM_PW_SAVE_SHIFT) 702 #define HE_6G_CAP_RD_RESPONDER(cap) (((cap) & HE_6G_CAP_RD_RESPONDER_MASK) != 0) 703 #define HE_6G_CAP_RX_ANT_PATN_CONST(cap) (((cap) & HE_6G_CAP_RX_ANT_PATN_CONST_MASK) != 0) 704 #define HE_6G_CAP_TX_ANT_PATN_CONST(cap) (((cap) & HE_6G_CAP_TX_ANT_PATN_CONST_MASK) != 0) 705 706 /** 707 * UORA parameter set element (sec 9.4.2.244) 708 */ 709 BWL_PRE_PACKED_STRUCT struct he_uora_ie { 710 uint8 id; 711 uint8 len; 712 uint8 id_ext; 713 uint8 ocw_range; 714 } BWL_POST_PACKED_STRUCT; 715 716 typedef struct he_uora_ie he_uora_ie_t; 717 718 /* Bit field Masks */ 719 #define HE_UORA_EOCW_MIN_IDX 0u 720 #define HE_UORA_EOCW_MIN_FSZ 3u 721 #define HE_UORA_EOCW_MAX_IDX 3u 722 #define HE_UORA_EOCW_MAX_FSZ 3u 723 /* Reserved -bit6 -7 */ 724 725 /** 726 * MU EDCA parameter set element (sec 9.4.2.245) 727 */ 728 BWL_PRE_PACKED_STRUCT struct he_mu_ac_param_record { 729 uint8 aci_aifsn; 730 uint8 ecw_min_max; 731 uint8 muedca_timer; 732 } BWL_POST_PACKED_STRUCT; 733 734 typedef struct he_mu_ac_param_record he_mu_ac_param_record_t; 735 736 BWL_PRE_PACKED_STRUCT struct he_muedca_ie { 737 uint8 id; 738 uint8 len; 739 uint8 id_ext; 740 uint8 mu_qos_info; 741 he_mu_ac_param_record_t param_ac[AC_COUNT]; 742 } BWL_POST_PACKED_STRUCT; 743 744 typedef struct he_muedca_ie he_muedca_ie_t; 745 746 #define HE_MU_EDCA_PARAM_UPD_CNT_IDX 0u /* EDCA Parameter Set Update Count */ 747 #define HE_MU_EDCA_PARAM_UPD_CNT_LEN 4u 748 749 #define HE_MU_SIGA_SIGB_MCS_DPCU 0 750 #define HE_MU_SIGA_SIGB_SYMS_DPCU 3u 751 #define HE_MU_SIGA_GI_LTF_DPCU 3u 752 753 /** 754 * Spatial Reuse Parameter Set element (sec 9.4.2.241) 755 */ 756 /* bit position and field width */ 757 #define HE_SRP_CTRL_SRP_DISALLOW_IDX 0 /* SRP Disallowed */ 758 #define HE_SRP_CTRL_SRP_DISALLOW_FSZ 1 759 #define HE_SRP_CTRL_NON_SRG_OBSS_PD_SR_DISALLOW_IDX 1 /* NonSRG OBSS PD SR Disallowed */ 760 #define HE_SRP_CTRL_NON_SRG_OBSS_PD_SR_DISALLOW_FSZ 1 761 #define HE_SRP_CTRL_NON_SRG_OFFSET_PRESENT_IDX 2 /* NonSRG Offset Present */ 762 #define HE_SRP_CTRL_NON_SRG_OFFSET_PRESENT_FSZ 1 763 #define HE_SRP_CTRL_SRG_INFO_PRESENT_IDX 3 /* SRG Information Present */ 764 #define HE_SRP_CTRL_SRG_INFO_PRESENT_FSZ 1 765 #define HE_SRP_CTRL_HESIGA_SR_VALUE15_ALLOWED_IDX 4 /* HESIGA_SRP_value15_allowed */ 766 #define HE_SRP_CTRL_HESIGA_SR_VALUE15_ALLOWED_FSZ 1 767 /* Reserved b5-b7 */ 768 769 /* Spatial reuse element element */ 770 BWL_PRE_PACKED_STRUCT struct he_srp_ie { 771 uint8 id; 772 uint8 len; 773 uint8 id_ext; 774 uint8 sr_control; 775 } BWL_POST_PACKED_STRUCT; 776 777 typedef struct he_srp_ie he_srp_ie_t; 778 779 #define HE_SRP_NON_SRG_OBSS_PD_MAX_OFFSET_LEN 1u 780 #define HE_SRP_SRG_OBSS_PD_MIN_OFFSET_LEN 1u 781 #define HE_SRP_SRG_OBSS_PD_MAX_OFFSET_LEN 1u 782 #define HE_SRP_SRG_BSSCOLOR_BITMAP_LEN 8u 783 #define HE_SRP_SRG_PARTIAL_BSSID_BITMAP_LEN 8u 784 785 #define HE_SRP_IE_MIN_LEN (sizeof(he_srp_ie_t) - TLV_HDR_LEN) 786 #define HE_SRP_IE_MAX_LEN (sizeof(he_srp_ie_t) - TLV_HDR_LEN +\ 787 HE_SRP_NON_SRG_OBSS_PD_MAX_OFFSET_LEN + HE_SRP_SRG_OBSS_PD_MIN_OFFSET_LEN\ 788 HE_SRP_SRG_OBSS_PD_MAX_OFFSET_LEN + HE_SRP_SRG_BSSCOLOR_BITMAP_LEN\ 789 HE_SRP_SRG_PARTIAL_BSSID_BITMAP_LEN) 790 791 /* Bit field Masks */ 792 #define HE_SRP_CTRL_SRP_DISALLOW (1 << HE_SRP_CTRL_SRP_DISALLOW_IDX) 793 #define HE_SRP_CTRL_NON_SRG_OBSS_PD_SR_DISALLOW (1 << HE_SRP_CTRL_NON_SRG_OBSS_PD_SR_DISALLOW_IDX) 794 #define HE_SRP_CTRL_NON_SRG_OFFSET_PRESENT (1 << HE_SRP_CTRL_NON_SRG_OFFSET_PRESENT_IDX) 795 #define HE_SRP_CTRL_SRG_INFO_PRESENT (1 << HE_SRP_CTRL_SRG_INFO_PRESENT_IDX) 796 #define HE_SRP_CTRL_HESIGA_SR_VALUE15_ALLOWED (1 << HE_SRP_CTRL_HESIGA_SR_VALUE15_ALLOWED_IDX) 797 798 /** 799 * ref: (Table 28-21 Page 473 D3.0) 800 * 801 * -Spatial Reuse field encoding for an HE SU PPDU, HE ER SU PPDU, and HE MU PPDU 802 */ 803 #define HE_SRP_DISALLOW 0u /* SRP_DISALLOW */ 804 /* Values 1 to 12 are reserved */ 805 #define HE_SR_RESTRICTED 13u /* SR Restricted */ 806 #define HE_SR_DELAY 14u /* SR Delay */ 807 #define HE_SRP_AND_NON_SRG_OBSS_PD_PROHIBITED 15u /* SRP_AND_NON_SRG_OBSS_PD_PROHIBITED */ 808 #define HE_SRP_MASK 0x0Fu 809 810 /** 811 * BSS Color Change Announcement element (sec 9.4.2.243) 812 */ 813 /* bit position and field width */ 814 #define HE_BSSCOLOR_CHANGE_NEWCOLOR_IDX 0 /* New BSSColor info */ 815 #define HE_BSSCOLOR_CHANGE_NEWCOLOR_FSZ 6u 816 817 /* HE Bsscolor change element */ 818 BWL_PRE_PACKED_STRUCT struct he_bsscolor_change_ie { 819 uint8 id; 820 uint8 len; 821 uint8 id_ext; 822 uint8 color_switch_cntdwn; 823 uint8 new_bsscolor_info; 824 } BWL_POST_PACKED_STRUCT; 825 826 typedef struct he_bsscolor_change_ie he_bsscolor_change_ie_t; 827 828 /* HE SU bit position and field width */ 829 #define HE_SU_PPDU_FORMAT_IDX 0u 830 #define HE_SU_PPDU_FORMAT_FSZ 1u 831 #define HE_SU_PPDU_BEAM_CHANGE_IDX 1u 832 #define HE_SU_PPDU_BEAM_CHANGE_FSZ 1u 833 #define HE_SU_PPDU_DL_UL_IDX 2u 834 #define HE_SU_PPDU_DL_UL_FSZ 1u 835 #define HE_SU_PPDU_MCS_IDX 3u 836 #define HE_SU_PPDU_MCS_FSZ 4u 837 #define HE_SU_PPDU_DCM_IDX 7u 838 #define HE_SU_PPDU_DCM_FSZ 1u 839 #define HE_SU_PPDU_BSS_COLOR_IDX 8u 840 #define HE_SU_PPDU_BSS_COLOR_FSZ 6u 841 #define HE_SU_PPDU_SR_IDX 15 842 #define HE_SU_PPDU_SR_FSZ 4u 843 #define HE_SU_PPDU_BW_IDX 19u 844 #define HE_SU_PPDU_BW_FSZ 2u 845 #define HE_SU_PPDU_GI_IDX 21u 846 #define HE_SU_PPDU_GI_FSZ 2u 847 #define HE_SU_PPDU_LTF_SIZE_IDX 21u 848 #define HE_SU_PPDU_LTF_SIZE_FSZ 2u 849 #define HE_SU_PPDU_NUM_LTF_IDX 21u 850 #define HE_SU_PPDU_NUM_LTF_FSZ 2u 851 #define HE_SU_PPDU_NSTS_IDX 23u 852 #define HE_SU_PPDU_NSTS_FSZ 3u 853 #define HE_SU_PPDU_DOPPLER_NOTSET_NSTS_IDX 23u 854 #define HE_SU_PPDU_DOPPLER_NOTSET_NSTS_FSZ 3u 855 #define HE_SU_PPDU_DOPPLER_SET_NSTS_IDX 23u 856 #define HE_SU_PPDU_DOPPLER_SET_NSTS_FSZ 2u 857 #define HE_SU_PPDU_MIDAMBLE_IDX 25u 858 #define HE_SU_PPDU_MIDAMBLE_FSZ 1u 859 #define HE_SU_PPDU_TXOP_IDX 26u 860 #define HE_SU_PPDU_TXOP_FSZ 7u 861 #define HE_SU_PPDU_CODING_IDX 33u 862 #define HE_SU_PPDU_CODING_FSZ 1u 863 #define HE_SU_PPDU_LDPC_IDX 34u 864 #define HE_SU_PPDU_LDPC_FSZ 1u 865 #define HE_SU_PPDU_STBC_IDX 35u 866 #define HE_SU_PPDU_STBC_FSZ 1u 867 #define HE_SU_PPDU_TXBF_IDX 36u 868 #define HE_SU_PPDU_TXBF_FSZ 1u 869 #define HE_SU_PPDU_PADDING_IDX 37u 870 #define HE_SU_PPDU_PADDING_FSZ 2u 871 #define HE_SU_PPDU_PE_IDX 39u 872 #define HE_SU_PPDU_PE_FSZ 1u 873 #define HE_SU_PPDU_DOPPLER_IDX 41u 874 #define HE_SU_PPDU_DOPPLER_FSZ 1u 875 876 /* For HE SU/RE SIG A : PLCP0 bit fields [32bit] */ 877 #define HE_SU_RE_SIGA_FORMAT_MASK 0x00000001u 878 #define HE_SU_RE_SIGA_RE_VAL 0x00000000u 879 #define HE_SU_RE_SIGA_SU_VAL 0x00000001u 880 #define HE_SU_RE_SIGA_FORMAT_SHIFT 0u 881 #define HE_SU_RE_SIGA_BEAM_CHANGE_SHIFT 1u 882 #define HE_SU_RE_SIGA_UL_DL_SHIFT 2u 883 #define HE_SU_RE_SIGA_MCS_MASK 0x00000078u 884 #define HE_SU_RE_SIGA_MCS_SHIFT 3u 885 #define HE_SU_RE_SIGA_DCM_MASK 0x00000080u 886 #define HE_SU_RE_SIGA_DCM_SHIFT 7u 887 #define HE_SU_RE_SIGA_BSS_COLOR_SHIFT 8u /* Bits 13:8 */ 888 #define HE_SU_RE_SIGA_BSS_COLOR_MASK 0x00003F00u 889 #define HE_SU_RE_SIGA_RSVD_PLCP0_VAL 0x00004000u 890 #define HE_SU_RE_SIGA_SRP_VAL_SHIFT 15u /* Bits 18:15 */ 891 #define HE_SU_RE_SIGA_SRP_VAL_MASK 0x00078000u 892 #define HE_SU_SIGA_BW_MASK 0x00180000u 893 #define HE_SU_SIGA_BW_SHIFT 19u 894 #define HE_RE_SIGA_TONE_MASK 0x00180000u 895 #define HE_RE_SIGA_TONE_SHIFT 19u 896 #define HE_SU_RE_SIGA_20MHZ_VAL 0x00000000u 897 #define HE_SU_RE_SIGA_40MHZ_VAL 0x00080000u 898 #define HE_SU_RE_SIGA_80MHZ_VAL 0x00100000u 899 #define HE_SU_RE_SIGA_160MHZ_VAL 0x00180000u 900 #define HE_SU_RE_SIGA_GI_LTF_MASK 0x00600000u 901 #define HE_SU_RE_SIGA_1xLTF_GI8us_VAL 0x00000000u 902 #define HE_SU_RE_SIGA_2xLTF_GI8us_VAL 0x00200000u 903 #define HE_SU_RE_SIGA_2xLTF_GI16us_VAL 0x00400000u 904 #define HE_SU_RE_SIGA_4xLTF_GI32us_VAL 0x00600000u 905 #define HE_SU_RE_SIGA_GI_LTF_SHIFT 21u 906 #define HE_SU_RE_SIGA_NSTS_MASK 0x03800000u 907 #define HE_SU_RE_SIGA_NSTS_SHIFT 23u 908 #define HE_SU_RE_SIGA_TXOP_PLCP0_MASK 0xFC000000u 909 #define HE_SU_RE_SIGA_TXOP_PLCP0_SHIFT 26u 910 911 /* For HE SU SIG EXT : PLCP0 bit fields [32bit] */ 912 #define HE_SU_SIG_EXT_GI_LTF_MASK 0x00000003u 913 #define HE_SU_SIG_EXT_1xLTF_GI8us_VAL 0x00000000u 914 #define HE_SU_SIG_EXT_2xLTF_GI8us_VAL 0x00000001u 915 #define HE_SU_SIG_EXT_2xLTF_GI16us_VAL 0x00000002u 916 #define HE_SU_SIG_EXT_4xLTF_GI32us_VAL 0x00000003u 917 #define HE_SU_SIG_EXT_STBC_MASK 0x00000040u 918 #define HE_SU_SIG_EXT_STBC_SHIFT 6u 919 #define HE_SU_SIG_EXT_LDPC_MASK 0x00000080u 920 #define HE_SU_SIG_EXT_LDPC_SHIFT 7u 921 #define HE_SU_SIG_EXT_MCS_MASK 0x0000f000u 922 #define HE_SU_SIG_EXT_MCS_SHIFT 12u 923 #define HE_SU_SIG_EXT_DCM_MASK 0x00010000u 924 #define HE_SU_SIG_EXT_DCM_SHIFT 16u 925 #define HE_SU_SIG_EXT_NSTS_MASK 0x000e0000u 926 #define HE_SU_SIG_EXT_NSTS_SHIFT 17u 927 #define HE_SU_SIG_EXT_CODING_MASK 0x00800000u 928 #define HE_SU_SIG_EXT_CODING_SHIFT 23u 929 930 /* HE mu ppdu - bit position and field width */ 931 #define HE_MU_PPDU_DL_UL_IDX 0u 932 #define HE_MU_PPDU_DL_UL_FSZ 1u 933 #define HE_MU_PPDU_SIGB_MCS_IDX 1u 934 #define HE_MU_PPDU_SIGB_MCS_FSZ 3u 935 #define HE_MU_PPDU_SIGB_DCM_IDX 4u 936 #define HE_MU_PPDU_SIGB_DCM_FSZ 1u 937 #define HE_MU_PPDU_BSS_COLOR_IDX 5u 938 #define HE_MU_PPDU_BSS_COLOR_FSZ 6u 939 #define HE_MU_PPDU_SR_IDX 11u 940 #define HE_MU_PPDU_SR_FSZ 4u 941 942 #define HE_MU_PPDU_SIGB_SYM_MU_MIMO_USER_IDX 18u 943 #define HE_MU_PPDU_SIGB_SYM_MU_MIMO_USER_FSZ 3u 944 945 #define HE_MU_PPDU_PRE_PUNCR_SIGA_IDX 15u 946 #define HE_MU_PPDU_PRE_PUNCR_SIGA_FSZ 2u 947 948 #define HE_MU_PPDU_BW_SIGA_IDX 15u 949 #define HE_MU_PPDU_BW_SIGA_FSZ 2u 950 #define HE_MU_PPDU_BW_SIGA_KNOWN_IDX 17u 951 #define HE_MU_PPDU_BW_SIGA_KNOWN_FSZ 1u 952 953 #define HE_MU_PPDU_SIGB_SYMB_IDX 18u 954 #define HE_MU_PPDU_SIGB_SYMB_FSZ 4u 955 956 #define HE_MU_PPDU_SIGB_COMP_IDX 22u 957 #define HE_MU_PPDU_SIGB_COMP_FSZ 1u 958 #define HE_MU_PPDU_GI_IDX 23u 959 #define HE_MU_PPDU_GI_FSZ 2u 960 #define HE_MU_PPDU_LTF_SIZE_IDX 23u 961 #define HE_MU_PPDU_LTF_SIZE_FSZ 2u 962 #define HE_MU_PPDU_NUM_LTF_IDX 23u 963 #define HE_MU_PPDU_NUM_LTF_FSZ 2u 964 #define HE_MU_PPDU_DOPPLER_IDX 25u 965 #define HE_MU_PPDU_DOPPLER_FSZ 1u 966 #define HE_MU_PPDU_TXOP_IDX 26u 967 #define HE_MU_PPDU_TXOP_FSZ 7u 968 #define HE_MU_PPDU_MIDAMBLE_IDX 34u 969 #define HE_MU_PPDU_MIDAMBLE_FSZ 3u 970 #define HE_MU_PPDU_LDPC_IDX 37u 971 #define HE_MU_PPDU_LDPC_FSZ 1u 972 #define HE_MU_PPDU_STBC_IDX 38u 973 #define HE_MU_PPDU_STBC_FSZ 1u 974 #define HE_MU_PPDU_PADDING_IDX 39u 975 #define HE_MU_PPDU_PADDING_FSZ 2u 976 #define HE_MU_PPDU_PE_IDX 41u 977 #define HE_MU_PPDU_PE_FSZ 1u 978 979 /* he trigger ppdu - bit position and field width */ 980 #define HE_TRIG_PPDU_BSS_COLOR_IDX 1u 981 #define HE_TRIG_PPDU_BSS_COLOR_FSZ 6u 982 983 /* full spatial reuse field */ 984 #define HE_TRIG_PPDU_SR_IDX 7u 985 #define HE_TRIG_PPDU_SR_FSZ 16u 986 987 #define HE_TRIG_PPDU_SR1_IDX 7u 988 #define HE_TRIG_PPDU_SR1_FSZ 4u 989 #define HE_TRIG_PPDU_SR2_IDX 11u 990 #define HE_TRIG_PPDU_SR2_FSZ 4u 991 #define HE_TRIG_PPDU_SR3_IDX 15u 992 #define HE_TRIG_PPDU_SR3_FSZ 4u 993 #define HE_TRIG_PPDU_SR4_IDX 19u 994 #define HE_TRIG_PPDU_SR4_FSZ 4u 995 #define HE_TRIG_PPDU_TXOP_IDX 26u 996 #define HE_TRIG_PPDU_TXOP_FSZ 7u 997 998 /* For HE MU SIG A : PLCP0 bit fields [32bit] */ 999 #define HE_MU_SIGA_UL_DL_SHIFT 0 1000 #define HE_MU_SIGA_UL_TB_PPDU 0 1001 #define HE_MU_SIGA_SIGB_MCS_MASK 0x000000E 1002 #define HE_MU_SIGA_SIGB_MCS_SHIFT 1 1003 #define HE_MU_SIGA_SIGB_DCM_SHIFT 4 1004 #define HE_MU_SIGA_SIGB_DCM_DISABLED 0 1005 #define HE_MU_SIGA_BW_SHIFT 15 1006 #define HE_MU_SIGA_BW_80_UNPUNCTURED 2 1007 #define HE_MU_SIGA_BW_SEC_20_PUNCTURED 4 1008 #define HE_MU_SIGA_BW_SEC_40_PUNCTURED 5 1009 #define HE_MU_SIGA_SIGB_SYMS_SHIFT 18 1010 #define HE_MU_SIGA_GI_LTF_MASK 0x01800000 1011 #define HE_MU_SIGA_GI_LTF_SHIFT 23 1012 1013 /* For HE MU SIG A : PLCP1 bit fields [32bit] */ 1014 #define HE_MU_SIGA_STBC_MASK 0x00000040 1015 #define HE_MU_SIGA_STBC_SHIFT 6 1016 1017 /* For HE SU/RE SIG A : PLCP1 bit fields [16bit] */ 1018 #define HE_SU_RE_SIGA_TXOP_PLCP1_MASK 0x0001 1019 #define HE_SU_RE_SIGA_TXOP_PLCP1_SHIFT 0 1020 #define HE_SU_RE_SIGA_CODING_MASK 0x0002 1021 #define HE_SU_RE_SIGA_CODING_SHIFT 1 1022 #define HE_SU_RE_SIGA_LDPC_EXTRA_MASK 0x0004 1023 #define HE_SU_RE_SIGA_LDPC_EXTRA_SHIFT 2 1024 #define HE_SU_RE_SIGA_STBC_MASK 0x0008 1025 #define HE_SU_RE_SIGA_STBC_SHIFT 3 1026 #define HE_SU_RE_SIGA_BEAMFORM_MASK 0x0010 1027 #define HE_SU_RE_SIGA_BEAMFORM_SHIFT 4 1028 #define HE_SU_RE_SIGA_RSVD_PLCP1_VAL 0x0100 1029 1030 /* For HE MU SIG A : PLCP1 bit fields [16bit] */ 1031 #define HE_MU_SIGA_RSVD_SHIFT 1 1032 #define HE_MU_SIGA_LTF_SYMS_SHIFT 2 1033 1034 /* For HE SU SIG A : RX PLCP4 bit fields [8bit] */ 1035 #define HE_SU_SIGA2_STBC_RX_MASK 0x08u 1036 1037 /* For HE ER SIG A : RX PLCP4 bit fields [8bit] */ 1038 #define HE_ER_SIGA2_STBC_RX_MASK 0x08u 1039 1040 /* For HE MU SIG A : RX PLCP4 bit fields [8bit] */ 1041 #define HE_MU_SIGA2_STBC_RX_MASK 0x40u 1042 1043 /* This marks the end of a packed structure section. */ 1044 #include <packed_section_end.h> 1045 1046 /* HE Action Frame */ 1047 /* FIXME: use temporary Offsets until the spec assigns them */ 1048 #define HE_AF_CAT_OFF 0 1049 #define HE_AF_ACT_OFF 1 1050 1051 /* TWT Setup */ 1052 #define HE_AF_TWT_SETUP_TOKEN_OFF 2 1053 #define HE_AF_TWT_SETUP_TWT_IE_OFF 3 1054 1055 /* TWT Teardown */ 1056 #define HE_AF_TWT_TEARDOWN_FLOW_OFF 2 1057 1058 /* TWT Information */ 1059 #define HE_AF_TWT_INFO_OFF 2 1060 1061 /* HE Action ID */ 1062 /* FIXME: use temporary IDs until ANA assigns them */ 1063 #define HE_ACTION_TWT_SETUP 1 1064 #define HE_ACTION_TWT_TEARDOWN 2 1065 #define HE_ACTION_TWT_INFO 3 1066 1067 /* HE Basic trigger frame common info fields */ 1068 #define HE_TRIG_CMNINFO_SZ 8 1069 typedef uint8 he_trig_cmninfo_set_t[HE_TRIG_CMNINFO_SZ]; 1070 1071 /* bit position and field width */ 1072 #define HE_TRIG_CMNINFO_FRMTYPE_INDX 0 /* Trigger frame type */ 1073 #define HE_TRIG_CMNINFO_FRMTYPE_FSZ 4 1074 #define HE_TRIG_CMNINFO_LSIGLEN_INDX 4 /* L-sig length */ 1075 #define HE_TRIG_CMNINFO_LSIGLEN_FSZ 12 1076 #define HE_TRIG_CMNINFO_CASCADEIND_INDX 16 /* Cascade indication */ 1077 #define HE_TRIG_CMNINFO_CASCADEIND_FSZ 1 1078 #define HE_TRIG_CMNINFO_CSREQ_INDX 17 /* Carrier sense indication */ 1079 #define HE_TRIG_CMNINFO_CSREQ_FSZ 1 1080 #define HE_TRIG_CMNINFO_BWINFO_INDX 18 /* Bw info */ 1081 #define HE_TRIG_CMNINFO_BWINFO_FSZ 2 1082 #define HE_TRIG_CMNINFO_GI_LTF_INDX 20 /* Cp-LTF size */ 1083 #define HE_TRIG_CMNINFO_GI_LTF_FSZ 2 1084 #define HE_TRIG_CMNINFO_MUMIMO_LTF_INDX 22 /* HE-LTF mask enable */ 1085 #define HE_TRIG_CMNINFO_MUMIMO_LTF_FSZ 1 1086 #define HE_TRIG_CMNINFO_HELTF_SYM_INDX 23 /* He-LTF sumbols */ 1087 #define HE_TRIG_CMNINFO_HELTF_SYM_FSZ 3 1088 #define HE_TRIG_CMNINFO_STBC_INDX 26 /* STBC support */ 1089 #define HE_TRIG_CMNINFO_STBC_FSZ 1 1090 #define HE_TRIG_CMNINFO_LDPC_EXTSYM_INDX 27 /* LDPC extra symbol */ 1091 #define HE_TRIG_CMNINFO_LDPC_EXTSYM_FSZ 1 1092 #define HE_TRIG_CMNINFO_AP_TXPWR_INDX 28 /* AP TX power */ 1093 #define HE_TRIG_CMNINFO_AP_TXPWR_FSZ 6 1094 #define HE_TRIG_CMNINFO_AFACT_INDX 34 /* a-factor */ 1095 #define HE_TRIG_CMNINFO_AFACT_FSZ 2 1096 #define HE_TRIG_CMNINFO_PEDISAMBIG_INDX 36 /* PE disambiguity */ 1097 #define HE_TRIG_CMNINFO_PEDISAMBIG_FSZ 1 1098 #define HE_TRIG_CMNINFO_SPTIAL_REUSE_INDX 37 /* spatial re-use */ 1099 #define HE_TRIG_CMNINFO_SPTIAL_REUSE_FSZ 16 1100 #define HE_TRIG_CMNINFO_DOPPLER_INDX 53 /* doppler supoort */ 1101 #define HE_TRIG_CMNINFO_DOPPLER_FSZ 1 1102 #define HE_TRIG_CMNINFO_HESIGA_RSVD_INDX 54 /* rsvd bits from HE-SIGA */ 1103 #define HE_TRIG_CMNINFO_HESIGA_RSVD_FSZ 9 1104 #define HE_TRIG_CMNINFO_RSVD_INDX 63 /* reseved bit from HE-SIGA */ 1105 #define HE_TRIG_CMNINFO_RSVD_FSZ 1 1106 1107 /* HE Basic trigger frame user info fields */ 1108 #define HE_TRIG_USRINFO_SZ 5 1109 typedef uint8 he_trig_usrinfo_set_t[HE_TRIG_USRINFO_SZ]; 1110 1111 /* bit position and field width */ 1112 #define HE_TRIG_USRINFO_AID_INDX 0 /* AID */ 1113 #define HE_TRIG_USRINFO_AID_FSZ 12 1114 #define HE_TRIG_USRINFO_RU_ALLOC_INDX 12 /* RU allocation index */ 1115 #define HE_TRIG_USRINFO_RU_ALLOC_FSZ 8 1116 #define HE_TRIG_USRINFO_CODING_INDX 20 /* coding type (BCC/LDPC) */ 1117 #define HE_TRIG_USRINFO_CODING_FSZ 1 1118 #define HE_TRIG_USRINFO_MCS_INDX 21 /* MCS index value */ 1119 #define HE_TRIG_USRINFO_MCS_FSZ 4 1120 #define HE_TRIG_USRINFO_DCM_INDX 25 /* Dual carrier modulation */ 1121 #define HE_TRIG_USRINFO_DCM_FSZ 1 1122 #define HE_TRIG_USRINFO_SSALLOC_STRMOFFSET_INDX 26 /* stream offset */ 1123 #define HE_TRIG_USRINFO_SSALLOC_STRMOFFSET_FSZ 3 1124 #define HE_TRIG_USRINFO_SSALLOC_NSS_INDX 29 /* number of spatial streams */ 1125 #define HE_TRIG_USRINFO_SSALLOC_NSS_FSZ 3 1126 #define HE_TRIG_USRINFO_TARGET_RSSI_INDX 32 /* Target RSSI */ 1127 #define HE_TRIG_USRINFO_TARGET_RSSI_FSZ 7 1128 #define HE_TRIG_USRINFO_RSVD_INDX 39 /* Reserved bit */ 1129 #define HE_TRIG_USRINFO_RSVD_FSZ 1 1130 1131 /* Different types of trigger frame */ 1132 #define HE_TRIG_TYPE_BASIC_FRM 0 /* basic trigger frame */ 1133 #define HE_TRIG_TYPE_BEAM_RPT_POLL_FRM 1 /* beamforming report poll frame */ 1134 #define HE_TRIG_TYPE_MU_BAR_FRM 2 /* MU-BAR frame */ 1135 #define HE_TRIG_TYPE_MU_RTS__FRM 3 /* MU-RTS frame */ 1136 #define HE_TRIG_TYPE_BSR_FRM 4 /* Buffer status report poll */ 1137 1138 /* HE Timing related parameters (Table 28-9) */ 1139 #define HE_T_LEG_STF 8 1140 #define HE_T_LEG_LTF 8 1141 #define HE_T_LEG_LSIG 4 1142 #define HE_T_RL_SIG 4 1143 #define HE_T_SIGA 8 1144 #define HE_T_STF 4 /* STF for SU / MU HE PPDUs */ 1145 #define HE_T_TB_PPDU_STF 8 /* STF for HE trigger based PPDUs */ 1146 #define HE_T_LEG_PREAMBLE (HE_T_LEG_STF + HE_T_LEG_LTF + HE_T_LEG_LSIG) 1147 #define HE_T_LEG_SYMB 4 1148 #define HE_RU_26_TONE 26 1149 #define HE_RU_52_TONE 52 1150 #define HE_RU_106_TONE 106 1151 #define HE_RU_242_TONE 242 1152 #define HE_RU_484_TONE 484 1153 #define HE_RU_996_TONE 996 1154 #define HE_RU_2x996_TONE 1992 1155 #define HE_MAX_26_TONE_RU_INDX 36 1156 #define HE_MAX_52_TONE_RU_INDX 52 1157 #define HE_MAX_106_TONE_RU_INDX 60 1158 #define HE_MAX_242_TONE_RU_INDX 64 1159 #define HE_MAX_484_TONE_RU_INDX 66 1160 #define HE_MAX_996_TONE_RU_INDX 67 1161 #define HE_MAX_2x996_TONE_RU_INDX 68 1162 1163 /** 1164 * ref: (Table 28-9 Page 285) 1165 * 1166 * - for calculation purpose - in multiples of 10 (*10) 1167 */ 1168 #define HE_T_LTF_1X 32 1169 #define HE_T_LTF_2X 64 1170 #define HE_T_LTF_4X 128 1171 #define HE_T_SYM1 136 /* OFDM symbol duration with base GI */ 1172 #define HE_T_SYM2 144 /* OFDM symbol duration with double GI */ 1173 #define HE_T_SYM4 160 /* OFDM symbol duration with quad GI */ 1174 1175 #define HE_N_LEG_SYM 3 /* bytes per legacy symbol */ 1176 #define HE_N_TAIL 6 /* tail field bits for BCC */ 1177 #define HE_N_SERVICE 16 /* bits in service field */ 1178 #define HE_T_MAX_PE 16 /* max Packet extension duration */ 1179 1180 #endif /* _802_11ax_h_ */ 1181