1 /* 2 * 'Standard' SDIO HOST CONTROLLER driver 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Open:>> 22 * 23 * $Id: bcmsdstd.h 833030 2019-08-02 17:22:42Z jl904071 $ 24 */ 25 #ifndef _BCM_SD_STD_H 26 #define _BCM_SD_STD_H 27 28 /* global msglevel for debug messages - bitvals come from sdiovar.h */ 29 #ifdef BCMDBG 30 #define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0) 31 #define sd_trace(x) do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0) 32 #define sd_info(x) do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0) 33 #define sd_debug(x) do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0) 34 #define sd_data(x) do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0) 35 #define sd_ctrl(x) do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0) 36 #define sd_dma(x) do { if (sd_msglevel & SDH_DMA_VAL) printf x; } while (0) 37 #else 38 #define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0) 39 #define sd_trace(x) 40 #define sd_info(x) 41 #define sd_debug(x) 42 #define sd_data(x) 43 #define sd_ctrl(x) 44 #define sd_dma(x) 45 #endif /* BCMDBG */ 46 47 #define sd_sync_dma(sd, read, nbytes) 48 #define sd_init_dma(sd) 49 #define sd_ack_intr(sd) 50 #define sd_wakeup(sd); 51 /* Allocate/init/free per-OS private data */ 52 extern int sdstd_osinit(sdioh_info_t *sd); 53 extern void sdstd_osfree(sdioh_info_t *sd); 54 55 #ifdef BCMPERFSTATS 56 #define sd_log(x) do { if (sd_msglevel & SDH_LOG_VAL) bcmlog x; } while (0) 57 #else 58 #define sd_log(x) 59 #endif 60 61 #define SDIOH_ASSERT(exp) \ 62 do { if (!(exp)) \ 63 printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \ 64 } while (0) 65 66 #define BLOCK_SIZE_4318 64 67 #define BLOCK_SIZE_4328 512 68 69 /* internal return code */ 70 #define SUCCESS 0 71 #define ERROR 1 72 73 /* private bus modes */ 74 #define SDIOH_MODE_SPI 0 75 #define SDIOH_MODE_SD1 1 76 #define SDIOH_MODE_SD4 2 77 78 #define MAX_SLOTS 6 /* For PCI: Only 6 BAR entries => 6 slots */ 79 #define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */ 80 81 #define SDIOH_TYPE_ARASAN_HDK 1 82 #define SDIOH_TYPE_BCM27XX 2 83 #ifdef BCMINTERNAL 84 #define SDIOH_TYPE_JINVANI_GOLD 3 85 #endif 86 #define SDIOH_TYPE_TI_PCIXX21 4 /* TI PCIxx21 Standard Host Controller */ 87 #define SDIOH_TYPE_RICOH_R5C822 5 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */ 88 #define SDIOH_TYPE_JMICRON 6 /* JMicron Standard SDIO Host Controller */ 89 90 /* For linux, allow yielding for dongle */ 91 #if defined(linux) && defined(BCMDONGLEHOST) 92 #define BCMSDYIELD 93 #endif 94 95 /* Expected card status value for CMD7 */ 96 #define SDIOH_CMD7_EXP_STATUS 0x00001E00 97 98 #define RETRIES_LARGE 100000 99 #ifdef BCMQT 100 extern void sdstd_os_yield(sdioh_info_t *sd); 101 #define RETRIES_SMALL 10000 102 #else 103 #define sdstd_os_yield(sd) do {} while (0) 104 #define RETRIES_SMALL 100 105 #endif 106 107 #define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */ 108 #define USE_MULTIBLOCK 0x4 109 110 #define USE_FIFO 0x8 /* Fifo vs non-fifo */ 111 112 #define CLIENT_INTR 0x100 /* Get rid of this! */ 113 114 #define HC_INTR_RETUNING 0x1000 115 116 #ifdef BCMSDIOH_TXGLOM 117 /* Total glom pkt can not exceed 64K 118 * need one more slot for glom padding packet 119 */ 120 #define SDIOH_MAXGLOM_SIZE (40+1) 121 122 typedef struct glom_buf { 123 uint32 count; /* Total number of pkts queued */ 124 void *dma_buf_arr[SDIOH_MAXGLOM_SIZE]; /* Frame address */ 125 dmaaddr_t dma_phys_arr[SDIOH_MAXGLOM_SIZE]; /* DMA_MAPed address of frames */ 126 uint16 nbytes[SDIOH_MAXGLOM_SIZE]; /* Size of each frame */ 127 } glom_buf_t; 128 #endif 129 130 struct sdioh_info { 131 uint cfg_bar; /* pci cfg address for bar */ 132 uint32 caps; /* cached value of capabilities reg */ 133 uint32 curr_caps; /* max current capabilities reg */ 134 135 osl_t *osh; /* osh handler */ 136 volatile char *mem_space; /* pci device memory va */ 137 uint lockcount; /* nest count of sdstd_lock() calls */ 138 bool client_intr_enabled; /* interrupt connnected flag */ 139 bool intr_handler_valid; /* client driver interrupt handler valid */ 140 sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ 141 void *intr_handler_arg; /* argument to call interrupt handler */ 142 bool initialized; /* card initialized */ 143 uint target_dev; /* Target device ID */ 144 uint16 intmask; /* Current active interrupts */ 145 void *sdos_info; /* Pointer to per-OS private data */ 146 void *bcmsdh; /* handler to upper layer stack (bcmsdh) */ 147 148 uint32 controller_type; /* Host controller type */ 149 uint8 version; /* Host Controller Spec Compliance Version */ 150 uint irq; /* Client irq */ 151 int intrcount; /* Client interrupts */ 152 int local_intrcount; /* Controller interrupts */ 153 bool host_init_done; /* Controller initted */ 154 bool card_init_done; /* Client SDIO interface initted */ 155 bool polled_mode; /* polling for command completion */ 156 157 bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */ 158 /* Must be on for sd_multiblock to be effective */ 159 bool use_client_ints; /* If this is false, make sure to restore */ 160 /* polling hack in wl_linux.c:wl_timer() */ 161 int adapter_slot; /* Maybe dealing with multiple slots/controllers */ 162 int sd_mode; /* SD1/SD4/SPI */ 163 int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ 164 uint32 data_xfer_count; /* Current transfer */ 165 uint16 card_rca; /* Current Address */ 166 int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */ 167 uint8 num_funcs; /* Supported funcs on client */ 168 uint32 com_cis_ptr; 169 uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; 170 void *dma_buf; /* DMA Buffer virtual address */ 171 dmaaddr_t dma_phys; /* DMA Buffer physical address */ 172 void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */ 173 dmaaddr_t adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */ 174 175 /* adjustments needed to make the dma align properly */ 176 void *dma_start_buf; 177 dmaaddr_t dma_start_phys; 178 uint alloced_dma_size; 179 void *adma2_dscr_start_buf; 180 dmaaddr_t adma2_dscr_start_phys; 181 uint alloced_adma2_dscr_size; 182 183 int r_cnt; /* rx count */ 184 int t_cnt; /* tx_count */ 185 bool got_hcint; /* local interrupt flag */ 186 uint16 last_intrstatus; /* to cache intrstatus */ 187 int host_UHSISupported; /* whether UHSI is supported for HC. */ 188 int card_UHSI_voltage_Supported; /* whether UHSI is supported for 189 * Card in terms of Voltage [1.8 or 3.3]. 190 */ 191 int global_UHSI_Supp; /* type of UHSI support in both host and card. 192 * HOST_SDR_UNSUPP: capabilities not supported/matched 193 * HOST_SDR_12_25: SDR12 and SDR25 supported 194 * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd 195 */ 196 volatile int sd3_dat_state; /* data transfer state used for retuning check */ 197 volatile int sd3_tun_state; /* tuning state used for retuning check */ 198 bool sd3_tuning_reqd; /* tuning requirement parameter */ 199 bool sd3_tuning_disable; /* tuning disable due to bus sleeping */ 200 uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */ 201 #ifdef BCMSDIOH_TXGLOM 202 glom_buf_t glom_info; /* pkt information used for glomming */ 203 uint txglom_mode; /* Txglom mode: 0 - copy, 1 - multi-descriptor */ 204 #endif 205 }; 206 207 #define DMA_MODE_NONE 0 208 #define DMA_MODE_SDMA 1 209 #define DMA_MODE_ADMA1 2 210 #define DMA_MODE_ADMA2 3 211 #define DMA_MODE_ADMA2_64 4 212 #define DMA_MODE_AUTO -1 213 214 #define USE_DMA(sd) ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE)) 215 216 /* States for Tuning and corr data */ 217 #define TUNING_IDLE 0 218 #define TUNING_START 1 219 #define TUNING_START_AFTER_DAT 2 220 #define TUNING_ONGOING 3 221 222 #define DATA_TRANSFER_IDLE 0 223 #define DATA_TRANSFER_ONGOING 1 224 225 #define CHECK_TUNING_PRE_DATA 1 226 #define CHECK_TUNING_POST_DATA 2 227 228 #ifdef DHD_DEBUG 229 #define SD_DHD_DISABLE_PERIODIC_TUNING 0x01 230 #define SD_DHD_ENABLE_PERIODIC_TUNING 0x00 231 #endif 232 233 /************************************************************ 234 * Internal interfaces: per-port references into bcmsdstd.c 235 */ 236 237 /* Global message bits */ 238 extern uint sd_msglevel; 239 240 /* OS-independent interrupt handler */ 241 extern bool check_client_intr(sdioh_info_t *sd); 242 243 /* Core interrupt enable/disable of device interrupts */ 244 extern void sdstd_devintr_on(sdioh_info_t *sd); 245 extern void sdstd_devintr_off(sdioh_info_t *sd); 246 247 /* Enable/disable interrupts for local controller events */ 248 extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err); 249 extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err); 250 251 /* Wait for specified interrupt and error bits to be set */ 252 extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err); 253 254 /************************************************************** 255 * Internal interfaces: bcmsdstd.c references to per-port code 256 */ 257 258 /* Register mapping routines */ 259 extern uint32 *sdstd_reg_map(osl_t *osh, dmaaddr_t addr, int size); 260 extern void sdstd_reg_unmap(osl_t *osh, dmaaddr_t addr, int size); 261 262 /* Interrupt (de)registration routines */ 263 extern int sdstd_register_irq(sdioh_info_t *sd, uint irq); 264 extern void sdstd_free_irq(uint irq, sdioh_info_t *sd); 265 266 /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */ 267 extern void sdstd_lock(sdioh_info_t *sd); 268 extern void sdstd_unlock(sdioh_info_t *sd); 269 extern void sdstd_waitlockfree(sdioh_info_t *sd); 270 271 /* OS-specific wrappers for safe concurrent register access */ 272 extern void sdstd_os_lock_irqsave(sdioh_info_t *sd, ulong* flags); 273 extern void sdstd_os_unlock_irqrestore(sdioh_info_t *sd, ulong* flags); 274 275 /* OS-specific wait-for-interrupt-or-status */ 276 extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits); 277 278 /* used by bcmsdstd_linux [implemented in sdstd] */ 279 extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd); 280 extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd); 281 extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd); 282 extern void sdstd_3_check_and_do_tuning(sdioh_info_t *sd, int tuning_param); 283 extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd); 284 extern int sdstd_3_get_tune_state(sdioh_info_t *sd); 285 extern int sdstd_3_get_data_state(sdioh_info_t *sd); 286 extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state); 287 extern void sdstd_3_set_data_state(sdioh_info_t *sd, int state); 288 extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd); 289 extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd); 290 extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode); 291 292 /* used by sdstd [implemented in bcmsdstd_linux/ndis] */ 293 extern void sdstd_3_start_tuning(sdioh_info_t *sd); 294 extern void sdstd_3_osinit_tuning(sdioh_info_t *sd); 295 extern void sdstd_3_osclean_tuning(sdioh_info_t *sd); 296 297 extern void sdstd_enable_disable_periodic_timer(sdioh_info_t * sd, uint val); 298 299 extern sdioh_info_t *sdioh_attach(osl_t *osh, void *bar0, uint irq); 300 extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *sd); 301 #endif /* _BCM_SD_STD_H */ 302