1 /** @file mlan_decl.h 2 * 3 * @brief This file declares the generic data structures and APIs. 4 * 5 * Copyright (C) 2008-2017, Marvell International Ltd. 6 * 7 * This software file (the "File") is distributed by Marvell International 8 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 9 * (the "License"). You may use, redistribute and/or modify this File in 10 * accordance with the terms and conditions of the License, a copy of which 11 * is available by writing to the Free Software Foundation, Inc., 12 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 13 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 14 * 15 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 17 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 18 * this warranty disclaimer. 19 */ 20 21 /****************************************************** 22 Change log: 23 11/07/2008: initial version 24 ******************************************************/ 25 26 #ifndef _MLAN_DECL_H_ 27 #define _MLAN_DECL_H_ 28 29 /** MLAN release version */ 30 #define MLAN_RELEASE_VERSION "C506" 31 32 /** Re-define generic data types for MLAN/MOAL */ 33 /** Signed char (1-byte) */ 34 typedef signed char t_s8; 35 /** Unsigned char (1-byte) */ 36 typedef unsigned char t_u8; 37 /** Signed short (2-bytes) */ 38 typedef short t_s16; 39 /** Unsigned short (2-bytes) */ 40 typedef unsigned short t_u16; 41 /** Signed long (4-bytes) */ 42 typedef int t_s32; 43 /** Unsigned long (4-bytes) */ 44 typedef unsigned int t_u32; 45 /** Signed long long 8-bytes) */ 46 typedef long long t_s64; 47 /** Unsigned long long 8-bytes) */ 48 typedef unsigned long long t_u64; 49 /** Void pointer (4-bytes) */ 50 typedef void t_void; 51 /** Size type */ 52 typedef t_u32 t_size; 53 /** Boolean type */ 54 typedef t_u8 t_bool; 55 56 #ifdef MLAN_64BIT 57 /** Pointer type (64-bit) */ 58 typedef t_u64 t_ptr; 59 /** Signed value (64-bit) */ 60 typedef t_s64 t_sval; 61 #else 62 /** Pointer type (32-bit) */ 63 typedef t_u32 t_ptr; 64 /** Signed value (32-bit) */ 65 typedef t_s32 t_sval; 66 #endif 67 68 /** Constants below */ 69 70 #ifdef __GNUC__ 71 /** Structure packing begins */ 72 #define MLAN_PACK_START 73 /** Structure packeing end */ 74 #define MLAN_PACK_END __attribute__((packed)) 75 #else /* !__GNUC__ */ 76 #ifdef PRAGMA_PACK 77 /** Structure packing begins */ 78 #define MLAN_PACK_START 79 /** Structure packeing end */ 80 #define MLAN_PACK_END 81 #else /* !PRAGMA_PACK */ 82 /** Structure packing begins */ 83 #define MLAN_PACK_START __packed 84 /** Structure packing end */ 85 #define MLAN_PACK_END 86 #endif /* PRAGMA_PACK */ 87 #endif /* __GNUC__ */ 88 89 #ifndef INLINE 90 #ifdef __GNUC__ 91 /** inline directive */ 92 #define INLINE inline 93 #else 94 /** inline directive */ 95 #define INLINE __inline 96 #endif 97 #endif 98 99 /** MLAN TRUE */ 100 #define MTRUE (1) 101 /** MLAN FALSE */ 102 #define MFALSE (0) 103 104 #define CHANNEL_SPEC_SNIFFER_MODE 1 105 106 #ifndef MACSTR 107 /** MAC address security format */ 108 #define MACSTR "%02x:XX:XX:XX:%02x:%02x" 109 #endif 110 111 #ifndef MAC2STR 112 /** MAC address security print arguments */ 113 #define MAC2STR(a) (a)[0], (a)[4], (a)[5] 114 #endif 115 116 #ifndef FULL_MACSTR 117 #define FULL_MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" 118 #endif 119 #ifndef FULL_MAC2STR 120 #define FULL_MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] 121 #endif 122 123 /** Macros for Data Alignment : size */ 124 #define ALIGN_SZ(p, a) \ 125 (((p) + ((a) - 1)) & ~((a) - 1)) 126 127 /** Macros for Data Alignment : address */ 128 #define ALIGN_ADDR(p, a) \ 129 ((((t_ptr)(p)) + (((t_ptr)(a)) - 1)) & ~(((t_ptr)(a)) - 1)) 130 131 /** Return the byte offset of a field in the given structure */ 132 #define MLAN_FIELD_OFFSET(type, field) ((t_u32)(t_ptr)&(((type *)0)->field)) 133 /** Return aligned offset */ 134 #define OFFSET_ALIGN_ADDR(p, a) (t_u32)(ALIGN_ADDR(p, a) - (t_ptr)p) 135 136 /** Maximum BSS numbers */ 137 #define MLAN_MAX_BSS_NUM (16) 138 139 /** NET IP alignment */ 140 #define MLAN_NET_IP_ALIGN 2 141 142 /** DMA alignment */ 143 /* SDIO3.0 Inrevium Adapter require 32 bit DMA alignment */ 144 #define DMA_ALIGNMENT 32 145 146 /** max size of TxPD */ 147 #define MAX_TXPD_SIZE 32 148 149 /** Minimum data header length */ 150 #define MLAN_MIN_DATA_HEADER_LEN (DMA_ALIGNMENT+MAX_TXPD_SIZE) 151 152 /** rx data header length */ 153 #define MLAN_RX_HEADER_LEN MLAN_MIN_DATA_HEADER_LEN 154 155 /** This is current limit on Maximum Tx AMPDU allowed */ 156 #define MLAN_MAX_TX_BASTREAM_SUPPORTED 16 157 #define MLAN_MAX_TX_BASTREAM_DEFAULT 2 158 /** This is current limit on Maximum Rx AMPDU allowed */ 159 #define MLAN_MAX_RX_BASTREAM_SUPPORTED 16 160 161 #ifdef STA_SUPPORT 162 /** Default Win size attached during ADDBA request */ 163 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 64 164 /** Default Win size attached during ADDBA response */ 165 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 64 166 /** RX winsize for COEX */ 167 #define MLAN_STA_COEX_AMPDU_DEF_RXWINSIZE 16 168 #endif /* STA_SUPPORT */ 169 #ifdef UAP_SUPPORT 170 /** Default Win size attached during ADDBA request */ 171 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 48 172 /** Default Win size attached during ADDBA response */ 173 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 32 174 /** RX winsize for COEX */ 175 #define MLAN_UAP_COEX_AMPDU_DEF_RXWINSIZE 16 176 #endif /* UAP_SUPPORT */ 177 178 #ifdef WIFI_DIRECT_SUPPORT 179 /** WFD use the same window size for tx/rx */ 180 #define MLAN_WFD_AMPDU_DEF_TXRXWINSIZE 64 181 /** RX winsize for COEX */ 182 #define MLAN_WFD_COEX_AMPDU_DEF_RXWINSIZE 16 183 #endif 184 185 /** NAN use the same window size for tx/rx */ 186 #define MLAN_NAN_AMPDU_DEF_TXRXWINSIZE 16 187 /** RX winsize for COEX */ 188 #define MLAN_NAN_COEX_AMPDU_DEF_RXWINSIZE 16 189 190 /** Block ack timeout value */ 191 #define MLAN_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff 192 /** Maximum Tx Win size configured for ADDBA request [10 bits] */ 193 #define MLAN_AMPDU_MAX_TXWINSIZE 0x3ff 194 /** Maximum Rx Win size configured for ADDBA request [10 bits] */ 195 #define MLAN_AMPDU_MAX_RXWINSIZE 0x3ff 196 197 /** Rate index for HR/DSSS 0 */ 198 #define MLAN_RATE_INDEX_HRDSSS0 0 199 /** Rate index for HR/DSSS 3 */ 200 #define MLAN_RATE_INDEX_HRDSSS3 3 201 /** Rate index for OFDM 0 */ 202 #define MLAN_RATE_INDEX_OFDM0 4 203 /** Rate index for OFDM 7 */ 204 #define MLAN_RATE_INDEX_OFDM7 11 205 /** Rate index for MCS 0 */ 206 #define MLAN_RATE_INDEX_MCS0 0 207 /** Rate index for MCS 7 */ 208 #define MLAN_RATE_INDEX_MCS7 7 209 /** Rate index for MCS 9 */ 210 #define MLAN_RATE_INDEX_MCS9 9 211 /** Rate index for MCS 32 */ 212 #define MLAN_RATE_INDEX_MCS32 32 213 /** Rate index for MCS 127 */ 214 #define MLAN_RATE_INDEX_MCS127 127 215 216 /** Rate bitmap for OFDM 0 */ 217 #define MLAN_RATE_BITMAP_OFDM0 16 218 /** Rate bitmap for OFDM 7 */ 219 #define MLAN_RATE_BITMAP_OFDM7 23 220 /** Rate bitmap for MCS 0 */ 221 #define MLAN_RATE_BITMAP_MCS0 32 222 /** Rate bitmap for MCS 127 */ 223 #define MLAN_RATE_BITMAP_MCS127 159 224 225 /** Size of rx data buffer */ 226 #define MLAN_RX_DATA_BUF_SIZE (4 * 1024) 227 /** Size of rx command buffer */ 228 #define MLAN_RX_CMD_BUF_SIZE (2 * 1024) 229 230 #define MLAN_USB_RX_DATA_BUF_SIZE MLAN_RX_DATA_BUF_SIZE 231 232 /** MLAN MAC Address Length */ 233 #define MLAN_MAC_ADDR_LENGTH (6) 234 /** MLAN 802.11 MAC Address */ 235 typedef t_u8 mlan_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH]; 236 237 /** MLAN Maximum SSID Length */ 238 #define MLAN_MAX_SSID_LENGTH (32) 239 240 /** RTS/FRAG related defines */ 241 /** Minimum RTS value */ 242 #define MLAN_RTS_MIN_VALUE (0) 243 /** Maximum RTS value */ 244 #define MLAN_RTS_MAX_VALUE (2347) 245 /** Minimum FRAG value */ 246 #define MLAN_FRAG_MIN_VALUE (256) 247 /** Maximum FRAG value */ 248 #define MLAN_FRAG_MAX_VALUE (2346) 249 250 /** Minimum tx retry count */ 251 #define MLAN_TX_RETRY_MIN (0) 252 /** Maximum tx retry count */ 253 #define MLAN_TX_RETRY_MAX (14) 254 255 /** max Wmm AC queues */ 256 #define MAX_AC_QUEUES 4 257 258 /** define SDIO block size for data Tx/Rx */ 259 /* We support up to 480-byte block size due to FW buffer limitation. */ 260 #define MLAN_SDIO_BLOCK_SIZE 256 261 262 /** define SDIO block size for firmware download */ 263 #define MLAN_SDIO_BLOCK_SIZE_FW_DNLD MLAN_SDIO_BLOCK_SIZE 264 265 /** define allocated buffer size */ 266 #define ALLOC_BUF_SIZE (4 * 1024) 267 /** SDIO MP aggr pkt limit */ 268 #define SDIO_MP_AGGR_DEF_PKT_LIMIT (16) 269 270 /** SDIO IO Port mask */ 271 #define MLAN_SDIO_IO_PORT_MASK 0xfffff 272 /** SDIO Block/Byte mode mask */ 273 #define MLAN_SDIO_BYTE_MODE_MASK 0x80000000 274 275 /** Max retry number of IO write */ 276 #define MAX_WRITE_IOMEM_RETRY 2 277 278 /** IN parameter */ 279 #define IN 280 /** OUT parameter */ 281 #define OUT 282 283 /** BIT value */ 284 #define MBIT(x) (((t_u32)1) << (x)) 285 286 /** Buffer flag for requeued packet */ 287 #define MLAN_BUF_FLAG_REQUEUED_PKT MBIT(0) 288 /** Buffer flag for transmit buf from moal */ 289 #define MLAN_BUF_FLAG_MOAL_TX_BUF MBIT(1) 290 /** Buffer flag for malloc mlan_buffer */ 291 #define MLAN_BUF_FLAG_MALLOC_BUF MBIT(2) 292 293 /** Buffer flag for bridge packet */ 294 #define MLAN_BUF_FLAG_BRIDGE_BUF MBIT(3) 295 296 /** Buffer flag for TDLS */ 297 #define MLAN_BUF_FLAG_TDLS MBIT(8) 298 299 /** Buffer flag for TCP_ACK */ 300 #define MLAN_BUF_FLAG_TCP_ACK MBIT(9) 301 302 /** Buffer flag for TX_STATUS */ 303 #define MLAN_BUF_FLAG_TX_STATUS MBIT(10) 304 305 /** Buffer flag for NET_MONITOR */ 306 #define MLAN_BUF_FLAG_NET_MONITOR MBIT(11) 307 308 /** Buffer flag for NULL data packet */ 309 #define MLAN_BUF_FLAG_NULL_PKT MBIT(12) 310 311 #define MLAN_BUF_FLAG_TX_CTRL MBIT(14) 312 313 #ifdef DEBUG_LEVEL1 314 /** Debug level bit definition */ 315 #define MMSG MBIT(0) 316 #define MFATAL MBIT(1) 317 #define MERROR MBIT(2) 318 #define MDATA MBIT(3) 319 #define MCMND MBIT(4) 320 #define MEVENT MBIT(5) 321 #define MINTR MBIT(6) 322 #define MIOCTL MBIT(7) 323 324 #define MMPA_D MBIT(15) 325 #define MDAT_D MBIT(16) 326 #define MCMD_D MBIT(17) 327 #define MEVT_D MBIT(18) 328 #define MFW_D MBIT(19) 329 #define MIF_D MBIT(20) 330 331 #define MENTRY MBIT(28) 332 #define MWARN MBIT(29) 333 #define MINFO MBIT(30) 334 #define MHEX_DUMP MBIT(31) 335 #endif /* DEBUG_LEVEL1 */ 336 337 /** Memory allocation type: DMA */ 338 #define MLAN_MEM_DMA MBIT(0) 339 340 /** Default memory allocation flag */ 341 #define MLAN_MEM_DEF 0 342 343 /** mlan_status */ 344 typedef enum _mlan_status { 345 MLAN_STATUS_FAILURE = 0xffffffff, 346 MLAN_STATUS_SUCCESS = 0, 347 MLAN_STATUS_PENDING, 348 MLAN_STATUS_RESOURCE, 349 MLAN_STATUS_COMPLETE, 350 } mlan_status; 351 352 /** mlan_error_code */ 353 typedef enum _mlan_error_code { 354 /** No error */ 355 MLAN_ERROR_NO_ERROR = 0, 356 /** Firmware/device errors below (MSB=0) */ 357 MLAN_ERROR_FW_NOT_READY = 0x00000001, 358 MLAN_ERROR_FW_BUSY = 0x00000002, 359 MLAN_ERROR_FW_CMDRESP = 0x00000003, 360 MLAN_ERROR_DATA_TX_FAIL = 0x00000004, 361 MLAN_ERROR_DATA_RX_FAIL = 0x00000005, 362 /** Driver errors below (MSB=1) */ 363 MLAN_ERROR_PKT_SIZE_INVALID = 0x80000001, 364 MLAN_ERROR_PKT_TIMEOUT = 0x80000002, 365 MLAN_ERROR_PKT_INVALID = 0x80000003, 366 MLAN_ERROR_CMD_INVALID = 0x80000004, 367 MLAN_ERROR_CMD_TIMEOUT = 0x80000005, 368 MLAN_ERROR_CMD_DNLD_FAIL = 0x80000006, 369 MLAN_ERROR_CMD_CANCEL = 0x80000007, 370 MLAN_ERROR_CMD_RESP_FAIL = 0x80000008, 371 MLAN_ERROR_CMD_ASSOC_FAIL = 0x80000009, 372 MLAN_ERROR_CMD_SCAN_FAIL = 0x8000000A, 373 MLAN_ERROR_IOCTL_INVALID = 0x8000000B, 374 MLAN_ERROR_IOCTL_FAIL = 0x8000000C, 375 MLAN_ERROR_EVENT_UNKNOWN = 0x8000000D, 376 MLAN_ERROR_INVALID_PARAMETER = 0x8000000E, 377 MLAN_ERROR_NO_MEM = 0x8000000F, 378 /** More to add */ 379 } mlan_error_code; 380 381 /** mlan_buf_type */ 382 typedef enum _mlan_buf_type { 383 MLAN_BUF_TYPE_CMD = 1, 384 MLAN_BUF_TYPE_DATA, 385 MLAN_BUF_TYPE_EVENT, 386 MLAN_BUF_TYPE_RAW_DATA, 387 MLAN_BUF_TYPE_SPA_DATA, 388 } mlan_buf_type; 389 390 /** MLAN BSS type */ 391 typedef enum _mlan_bss_type { 392 MLAN_BSS_TYPE_STA = 0, 393 MLAN_BSS_TYPE_UAP = 1, 394 #ifdef WIFI_DIRECT_SUPPORT 395 MLAN_BSS_TYPE_WIFIDIRECT = 2, 396 #endif 397 MLAN_BSS_TYPE_NAN = 4, 398 MLAN_BSS_TYPE_ANY = 0xff, 399 } mlan_bss_type; 400 401 /** MLAN BSS role */ 402 typedef enum _mlan_bss_role { 403 MLAN_BSS_ROLE_STA = 0, 404 MLAN_BSS_ROLE_UAP = 1, 405 MLAN_BSS_ROLE_ANY = 0xff, 406 } mlan_bss_role; 407 408 /** BSS role bit mask */ 409 #define BSS_ROLE_BIT_MASK MBIT(0) 410 411 /** Get BSS role */ 412 #define GET_BSS_ROLE(priv) ((priv)->bss_role & BSS_ROLE_BIT_MASK) 413 414 /** mlan_data_frame_type */ 415 typedef enum _mlan_data_frame_type { 416 MLAN_DATA_FRAME_TYPE_ETH_II = 0, 417 MLAN_DATA_FRAME_TYPE_802_11, 418 } mlan_data_frame_type; 419 420 /** mlan_event_id */ 421 typedef enum _mlan_event_id { 422 /* Event generated by firmware (MSB=0) */ 423 MLAN_EVENT_ID_FW_UNKNOWN = 0x00000001, 424 MLAN_EVENT_ID_FW_ADHOC_LINK_SENSED = 0x00000002, 425 MLAN_EVENT_ID_FW_ADHOC_LINK_LOST = 0x00000003, 426 MLAN_EVENT_ID_FW_DISCONNECTED = 0x00000004, 427 MLAN_EVENT_ID_FW_MIC_ERR_UNI = 0x00000005, 428 MLAN_EVENT_ID_FW_MIC_ERR_MUL = 0x00000006, 429 MLAN_EVENT_ID_FW_BCN_RSSI_LOW = 0x00000007, 430 MLAN_EVENT_ID_FW_BCN_RSSI_HIGH = 0x00000008, 431 MLAN_EVENT_ID_FW_BCN_SNR_LOW = 0x00000009, 432 MLAN_EVENT_ID_FW_BCN_SNR_HIGH = 0x0000000A, 433 MLAN_EVENT_ID_FW_MAX_FAIL = 0x0000000B, 434 MLAN_EVENT_ID_FW_DATA_RSSI_LOW = 0x0000000C, 435 MLAN_EVENT_ID_FW_DATA_RSSI_HIGH = 0x0000000D, 436 MLAN_EVENT_ID_FW_DATA_SNR_LOW = 0x0000000E, 437 MLAN_EVENT_ID_FW_DATA_SNR_HIGH = 0x0000000F, 438 MLAN_EVENT_ID_FW_LINK_QUALITY = 0x00000010, 439 MLAN_EVENT_ID_FW_PORT_RELEASE = 0x00000011, 440 MLAN_EVENT_ID_FW_PRE_BCN_LOST = 0x00000012, 441 MLAN_EVENT_ID_FW_DEBUG_INFO = 0x00000013, 442 MLAN_EVENT_ID_FW_WMM_CONFIG_CHANGE = 0x0000001A, 443 MLAN_EVENT_ID_FW_HS_WAKEUP = 0x0000001B, 444 MLAN_EVENT_ID_FW_BG_SCAN = 0x0000001D, 445 MLAN_EVENT_ID_FW_BG_SCAN_STOPPED = 0x0000001E, 446 MLAN_EVENT_ID_FW_WEP_ICV_ERR = 0x00000020, 447 MLAN_EVENT_ID_FW_STOP_TX = 0x00000021, 448 MLAN_EVENT_ID_FW_START_TX = 0x00000022, 449 MLAN_EVENT_ID_FW_CHANNEL_SWITCH_ANN = 0x00000023, 450 MLAN_EVENT_ID_FW_RADAR_DETECTED = 0x00000024, 451 MLAN_EVENT_ID_FW_CHANNEL_REPORT_RDY = 0x00000025, 452 MLAN_EVENT_ID_FW_BW_CHANGED = 0x00000026, 453 MLAN_EVENT_ID_FW_REMAIN_ON_CHAN_EXPIRED = 0x0000002B, 454 #ifdef UAP_SUPPORT 455 MLAN_EVENT_ID_UAP_FW_BSS_START = 0x0000002C, 456 MLAN_EVENT_ID_UAP_FW_BSS_ACTIVE = 0x0000002D, 457 MLAN_EVENT_ID_UAP_FW_BSS_IDLE = 0x0000002E, 458 MLAN_EVENT_ID_UAP_FW_STA_CONNECT = 0x00000030, 459 MLAN_EVENT_ID_UAP_FW_STA_DISCONNECT = 0x00000031, 460 #endif 461 462 MLAN_EVENT_ID_FW_DUMP_INFO = 0x00000033, 463 464 MLAN_EVENT_ID_FW_TX_STATUS = 0x00000034, 465 MLAN_EVENT_ID_FW_CHAN_SWITCH_COMPLETE = 0x00000036, 466 /* Event generated by MLAN driver (MSB=1) */ 467 MLAN_EVENT_ID_DRV_CONNECTED = 0x80000001, 468 MLAN_EVENT_ID_DRV_DEFER_HANDLING = 0x80000002, 469 MLAN_EVENT_ID_DRV_HS_ACTIVATED = 0x80000003, 470 MLAN_EVENT_ID_DRV_HS_DEACTIVATED = 0x80000004, 471 MLAN_EVENT_ID_DRV_MGMT_FRAME = 0x80000005, 472 MLAN_EVENT_ID_DRV_OBSS_SCAN_PARAM = 0x80000006, 473 MLAN_EVENT_ID_DRV_PASSTHRU = 0x80000007, 474 MLAN_EVENT_ID_DRV_SCAN_REPORT = 0x80000009, 475 MLAN_EVENT_ID_DRV_MEAS_REPORT = 0x8000000A, 476 MLAN_EVENT_ID_DRV_ASSOC_FAILURE_REPORT = 0x8000000B, 477 MLAN_EVENT_ID_DRV_REPORT_STRING = 0x8000000F, 478 MLAN_EVENT_ID_DRV_DBG_DUMP = 0x80000012, 479 MLAN_EVENT_ID_DRV_BGSCAN_RESULT = 0x80000013, 480 MLAN_EVENT_ID_DRV_FLUSH_RX_WORK = 0x80000015, 481 MLAN_EVENT_ID_DRV_DEFER_RX_WORK = 0x80000016, 482 MLAN_EVENT_ID_DRV_TDLS_TEARDOWN_REQ = 0x80000017, 483 MLAN_EVENT_ID_DRV_FT_RESPONSE = 0x80000018, 484 MLAN_EVENT_ID_DRV_FLUSH_MAIN_WORK = 0x80000019, 485 #ifdef UAP_SUPPORT 486 MLAN_EVENT_ID_DRV_UAP_CHAN_INFO = 0x80000020, 487 #endif 488 MLAN_EVENT_ID_FW_ROAM_OFFLOAD_RESULT = 0x80000023, 489 MLAN_EVENT_ID_NAN_STARTED = 0x80000024, 490 } mlan_event_id; 491 492 /** Data Structures */ 493 /** mlan_image data structure */ 494 typedef struct _mlan_fw_image { 495 /** Helper image buffer pointer */ 496 t_u8 *phelper_buf; 497 /** Helper image length */ 498 t_u32 helper_len; 499 /** Firmware image buffer pointer */ 500 t_u8 *pfw_buf; 501 /** Firmware image length */ 502 t_u32 fw_len; 503 /** Firmware reload flag */ 504 t_u8 fw_reload; 505 } mlan_fw_image, *pmlan_fw_image; 506 507 #define OID_TYPE_CAL 0x2 508 #define OID_TYPE_DPD 0xa 509 510 /** Custom data structure */ 511 typedef struct _mlan_init_param { 512 /** DPD data buffer pointer */ 513 t_u8 *pdpd_data_buf; 514 /** DPD data length */ 515 t_u32 dpd_data_len; 516 /** region txpowerlimit cfg data buffer pointer */ 517 t_u8 *ptxpwr_data_buf; 518 /** region txpowerlimit cfg data length */ 519 t_u32 txpwr_data_len; 520 /** Cal data buffer pointer */ 521 t_u8 *pcal_data_buf; 522 /** Cal data length */ 523 t_u32 cal_data_len; 524 /** Other custom data */ 525 } mlan_init_param, *pmlan_init_param; 526 527 /** channel band */ 528 enum { 529 BAND_2GHZ = 0, 530 BAND_5GHZ = 1, 531 BAND_4GHZ = 2, 532 }; 533 534 /** channel offset */ 535 enum { 536 SEC_CHAN_NONE = 0, 537 SEC_CHAN_ABOVE = 1, 538 SEC_CHAN_5MHZ = 2, 539 SEC_CHAN_BELOW = 3 540 }; 541 542 /** channel bandwidth */ 543 enum { 544 CHAN_BW_20MHZ = 0, 545 CHAN_BW_10MHZ, 546 CHAN_BW_40MHZ, 547 }; 548 549 /** scan mode */ 550 enum { 551 SCAN_MODE_MANUAL = 0, 552 SCAN_MODE_ACS, 553 SCAN_MODE_USER, 554 }; 555 556 /** Band_Config_t */ 557 typedef MLAN_PACK_START struct _Band_Config_t { 558 #ifdef BIG_ENDIAN_SUPPORT 559 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=user*/ 560 t_u8 scanMode:2; 561 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 562 t_u8 chan2Offset:2; 563 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 564 t_u8 chanWidth:2; 565 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 566 t_u8 chanBand:2; 567 #else 568 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 569 t_u8 chanBand:2; 570 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 571 t_u8 chanWidth:2; 572 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 573 t_u8 chan2Offset:2; 574 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=Adoption mode*/ 575 t_u8 scanMode:2; 576 #endif 577 } MLAN_PACK_END Band_Config_t; 578 579 /** channel_band_t */ 580 typedef MLAN_PACK_START struct _chan_band_info { 581 /** Band Configuration */ 582 Band_Config_t bandcfg; 583 /** channel */ 584 t_u8 channel; 585 /** 11n flag */ 586 t_u8 is_11n_enabled; 587 /** center channel */ 588 t_u8 center_chan; 589 } MLAN_PACK_END chan_band_info; 590 591 /** mlan_event data structure */ 592 typedef struct _mlan_event { 593 /** BSS index number for multiple BSS support */ 594 t_u32 bss_index; 595 /** Event ID */ 596 mlan_event_id event_id; 597 /** Event length */ 598 t_u32 event_len; 599 /** Event buffer */ 600 t_u8 event_buf[0]; 601 } mlan_event, *pmlan_event; 602 603 /** mlan_ioctl_req data structure */ 604 typedef struct _mlan_ioctl_req { 605 /** Pointer to previous mlan_ioctl_req */ 606 struct _mlan_ioctl_req *pprev; 607 /** Pointer to next mlan_ioctl_req */ 608 struct _mlan_ioctl_req *pnext; 609 /** Status code from firmware/driver */ 610 t_u32 status_code; 611 /** BSS index number for multiple BSS support */ 612 t_u32 bss_index; 613 /** Request id */ 614 t_u32 req_id; 615 /** Action: set or get */ 616 t_u32 action; 617 /** Pointer to buffer */ 618 t_u8 *pbuf; 619 /** Length of buffer */ 620 t_u32 buf_len; 621 /** Length of the data read/written in buffer */ 622 t_u32 data_read_written; 623 /** Length of buffer needed */ 624 t_u32 buf_len_needed; 625 /** Reserved for MOAL module */ 626 t_ptr reserved_1; 627 } mlan_ioctl_req, *pmlan_ioctl_req; 628 629 /** mix rate information structure */ 630 typedef MLAN_PACK_START struct _mix_rate_info { 631 /** bit0: LGI: gi=0, SGI: gi= 1 */ 632 /** bit1-2: 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */ 633 /** bit3-4: LG: format=0, HT: format=1, VHT: format=2 */ 634 /** bit5: LDPC: 0-not support, 1-support */ 635 /** bit6-7:reserved */ 636 t_u8 rate_info; 637 /** MCS index */ 638 t_u8 mcs_index; 639 /** bitrate, in 500Kbps */ 640 t_u16 bitrate; 641 } MLAN_PACK_END mix_rate_info, *pmix_rate_info; 642 643 /** rxpd extra information structure */ 644 typedef MLAN_PACK_START struct _rxpd_extra_info { 645 /** flags */ 646 t_u8 flags; 647 /** channel.flags */ 648 t_u16 channel_flags; 649 /** mcs.known */ 650 t_u8 mcs_known; 651 /** mcs.flags */ 652 t_u8 mcs_flags; 653 } MLAN_PACK_END rxpd_extra_info, *prxpd_extra_info; 654 655 /** rdaio tap information structure */ 656 typedef MLAN_PACK_START struct _radiotap_info { 657 /** Rate Info */ 658 mix_rate_info rate_info; 659 /** SNR */ 660 t_s8 snr; 661 /** Noise Floor */ 662 t_s8 nf; 663 /** band config */ 664 t_u8 band_config; 665 /** chan number */ 666 t_u8 chan_num; 667 /** antenna */ 668 t_u8 antenna; 669 /** extra rxpd info from FW */ 670 rxpd_extra_info extra_info; 671 } MLAN_PACK_END radiotap_info, *pradiotap_info; 672 673 /** txpower structure */ 674 typedef MLAN_PACK_START struct { 675 #ifdef BIG_ENDIAN_SUPPORT 676 /** Host tx power ctrl: 677 0x0: use fw setting for TX power 678 0x1: value specified in bit[6] and bit[5:0] are valid */ 679 t_u8 hostctl:1; 680 /** Sign of the power specified in bit[5:0] */ 681 t_u8 sign:1; 682 /** Power to be used for transmission(in dBm) */ 683 t_u8 abs_val:6; 684 #else 685 /** Power to be used for transmission(in dBm) */ 686 t_u8 abs_val:6; 687 /** Sign of the power specified in bit[5:0] */ 688 t_u8 sign:1; 689 /** Host tx power ctrl: 690 0x0: use fw setting for TX power 691 0x1: value specified in bit[6] and bit[5:0] are valid */ 692 t_u8 hostctl:1; 693 #endif 694 } MLAN_PACK_END tx_power_t; 695 /* pkt_txctrl */ 696 typedef MLAN_PACK_START struct _pkt_txctrl { 697 /**Data rate in unit of 0.5Mbps */ 698 t_u16 data_rate; 699 /*Channel number to transmit the frame */ 700 t_u8 channel; 701 /** Bandwidth to transmit the frame*/ 702 t_u8 bw; 703 /** Power to be used for transmission*/ 704 union { 705 tx_power_t tp; 706 t_u8 val; 707 } tx_power; 708 /** Retry time of tx transmission*/ 709 t_u8 retry_limit; 710 } MLAN_PACK_END pkt_txctrl, *ppkt_txctrl; 711 712 /** pkt_rxinfo */ 713 typedef MLAN_PACK_START struct _pkt_rxinfo { 714 /** Data rate of received paccket*/ 715 t_u16 data_rate; 716 /** Channel on which packet was received*/ 717 t_u8 channel; 718 /** Rx antenna*/ 719 t_u8 antenna; 720 /** Rx Rssi*/ 721 t_u8 rssi; 722 } MLAN_PACK_END pkt_rxinfo, *ppkt_rxinfo; 723 724 /** mlan_buffer data structure */ 725 typedef struct _mlan_buffer { 726 /** Pointer to previous mlan_buffer */ 727 struct _mlan_buffer *pprev; 728 /** Pointer to next mlan_buffer */ 729 struct _mlan_buffer *pnext; 730 /** Status code from firmware/driver */ 731 t_u32 status_code; 732 /** Flags for this buffer */ 733 t_u32 flags; 734 /** BSS index number for multiple BSS support */ 735 t_u32 bss_index; 736 /** Buffer descriptor, e.g. skb in Linux */ 737 t_void *pdesc; 738 /** Pointer to buffer */ 739 t_u8 *pbuf; 740 /** Offset to data */ 741 t_u32 data_offset; 742 /** Data length */ 743 t_u32 data_len; 744 /** Buffer type: data, cmd, event etc. */ 745 mlan_buf_type buf_type; 746 747 /** Fields below are valid for data packet only */ 748 /** QoS priority */ 749 t_u32 priority; 750 /** Time stamp when packet is received (seconds) */ 751 t_u32 in_ts_sec; 752 /** Time stamp when packet is received (micro seconds) */ 753 t_u32 in_ts_usec; 754 /** Time stamp when packet is processed (seconds) */ 755 t_u32 out_ts_sec; 756 /** Time stamp when packet is processed (micro seconds) */ 757 t_u32 out_ts_usec; 758 /** tx_seq_num */ 759 t_u32 tx_seq_num; 760 761 /** Fields below are valid for MLAN module only */ 762 /** Pointer to parent mlan_buffer */ 763 struct _mlan_buffer *pparent; 764 /** Use count for this buffer */ 765 t_u32 use_count; 766 union { 767 pkt_txctrl tx_info; 768 pkt_rxinfo rx_info; 769 } u; 770 } mlan_buffer, *pmlan_buffer; 771 772 /** mlan_fw_info data structure */ 773 typedef struct _mlan_hw_info { 774 /** Firmware capabilities */ 775 t_u32 fw_cap; 776 } mlan_hw_info, *pmlan_hw_info; 777 778 /** mlan_bss_attr data structure */ 779 typedef struct _mlan_bss_attr { 780 /** BSS type */ 781 t_u32 bss_type; 782 /** Data frame type: Ethernet II, 802.11, etc. */ 783 t_u32 frame_type; 784 /** The BSS is active (non-0) or not (0). */ 785 t_u32 active; 786 /** BSS Priority */ 787 t_u32 bss_priority; 788 /** BSS number */ 789 t_u32 bss_num; 790 /** The BSS is virtual */ 791 t_u32 bss_virtual; 792 } mlan_bss_attr, *pmlan_bss_attr; 793 794 /** bss tbl data structure */ 795 typedef struct _mlan_bss_tbl { 796 /** BSS Attributes */ 797 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 798 } mlan_bss_tbl, *pmlan_bss_tbl; 799 800 #ifdef PRAGMA_PACK 801 #pragma pack(push, 1) 802 #endif 803 804 /** Type enumeration for the command result */ 805 typedef MLAN_PACK_START enum _mlan_cmd_result_e { 806 MLAN_CMD_RESULT_SUCCESS = 0, 807 MLAN_CMD_RESULT_FAILURE = 1, 808 MLAN_CMD_RESULT_TIMEOUT = 2, 809 MLAN_CMD_RESULT_INVALID_DATA = 3 810 } MLAN_PACK_END mlan_cmd_result_e; 811 812 /** Type enumeration of WMM AC_QUEUES */ 813 typedef MLAN_PACK_START enum _mlan_wmm_ac_e { 814 WMM_AC_BK, 815 WMM_AC_BE, 816 WMM_AC_VI, 817 WMM_AC_VO 818 } MLAN_PACK_END mlan_wmm_ac_e; 819 820 /** Type enumeration for the action field in the Queue Config command */ 821 typedef MLAN_PACK_START enum _mlan_wmm_queue_config_action_e { 822 MLAN_WMM_QUEUE_CONFIG_ACTION_GET = 0, 823 MLAN_WMM_QUEUE_CONFIG_ACTION_SET = 1, 824 MLAN_WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2, 825 MLAN_WMM_QUEUE_CONFIG_ACTION_MAX 826 } MLAN_PACK_END mlan_wmm_queue_config_action_e; 827 828 /** Type enumeration for the action field in the queue stats command */ 829 typedef MLAN_PACK_START enum _mlan_wmm_queue_stats_action_e { 830 MLAN_WMM_STATS_ACTION_START = 0, 831 MLAN_WMM_STATS_ACTION_STOP = 1, 832 MLAN_WMM_STATS_ACTION_GET_CLR = 2, 833 MLAN_WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */ 834 MLAN_WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */ 835 MLAN_WMM_STATS_ACTION_MAX 836 } MLAN_PACK_END mlan_wmm_queue_stats_action_e; 837 838 /** 839 * @brief IOCTL structure for a Traffic stream status. 840 * 841 */ 842 typedef MLAN_PACK_START struct { 843 /** TSID: Range: 0->7 */ 844 t_u8 tid; 845 /** TSID specified is valid */ 846 t_u8 valid; 847 /** AC TSID is active on */ 848 t_u8 access_category; 849 /** UP specified for the TSID */ 850 t_u8 user_priority; 851 /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */ 852 t_u8 psb; 853 /** Upstream(0), Downlink(1), Bidirectional(3) */ 854 t_u8 flow_dir; 855 /** Medium time granted for the TSID */ 856 t_u16 medium_time; 857 } MLAN_PACK_END wlan_ioctl_wmm_ts_status_t, 858 /** Type definition of mlan_ds_wmm_ts_status for MLAN_OID_WMM_CFG_TS_STATUS */ 859 mlan_ds_wmm_ts_status, *pmlan_ds_wmm_ts_status; 860 861 /** Max Ie length */ 862 #define MAX_IE_SIZE 256 863 864 /** custom IE */ 865 typedef MLAN_PACK_START struct _custom_ie { 866 /** IE Index */ 867 t_u16 ie_index; 868 /** Mgmt Subtype Mask */ 869 t_u16 mgmt_subtype_mask; 870 /** IE Length */ 871 t_u16 ie_length; 872 /** IE buffer */ 873 t_u8 ie_buffer[MAX_IE_SIZE]; 874 } MLAN_PACK_END custom_ie; 875 876 /** Max IE index to FW */ 877 #define MAX_MGMT_IE_INDEX_TO_FW 4 878 /** Max IE index per BSS */ 879 #define MAX_MGMT_IE_INDEX 16 880 881 /** custom IE info */ 882 typedef MLAN_PACK_START struct _custom_ie_info { 883 /** size of buffer */ 884 t_u16 buf_size; 885 /** no of buffers of buf_size */ 886 t_u16 buf_count; 887 } MLAN_PACK_END custom_ie_info; 888 889 /** TLV buffer : Max Mgmt IE */ 890 typedef MLAN_PACK_START struct _tlvbuf_max_mgmt_ie { 891 /** Type */ 892 t_u16 type; 893 /** Length */ 894 t_u16 len; 895 /** No of tuples */ 896 t_u16 count; 897 /** custom IE info tuples */ 898 custom_ie_info info[MAX_MGMT_IE_INDEX]; 899 } MLAN_PACK_END tlvbuf_max_mgmt_ie; 900 901 /** TLV buffer : custom IE */ 902 typedef MLAN_PACK_START struct _tlvbuf_custom_ie { 903 /** Type */ 904 t_u16 type; 905 /** Length */ 906 t_u16 len; 907 /** IE data */ 908 custom_ie ie_data_list[MAX_MGMT_IE_INDEX_TO_FW]; 909 /** Max mgmt IE TLV */ 910 tlvbuf_max_mgmt_ie max_mgmt_ie; 911 } MLAN_PACK_END mlan_ds_misc_custom_ie; 912 913 /** Max TDLS config data length */ 914 #define MAX_TDLS_DATA_LEN 1024 915 916 /** Action commands for TDLS enable/disable */ 917 #define WLAN_TDLS_CONFIG 0x00 918 /** Action commands for TDLS configuration :Set */ 919 #define WLAN_TDLS_SET_INFO 0x01 920 /** Action commands for TDLS configuration :Discovery Request */ 921 #define WLAN_TDLS_DISCOVERY_REQ 0x02 922 /** Action commands for TDLS configuration :Setup Request */ 923 #define WLAN_TDLS_SETUP_REQ 0x03 924 /** Action commands for TDLS configuration :Tear down Request */ 925 #define WLAN_TDLS_TEAR_DOWN_REQ 0x04 926 /** Action ID for TDLS power mode */ 927 #define WLAN_TDLS_POWER_MODE 0x05 928 /**Action ID for init TDLS Channel Switch*/ 929 #define WLAN_TDLS_INIT_CHAN_SWITCH 0x06 930 /** Action ID for stop TDLS Channel Switch */ 931 #define WLAN_TDLS_STOP_CHAN_SWITCH 0x07 932 /** Action ID for configure CS related parameters */ 933 #define WLAN_TDLS_CS_PARAMS 0x08 934 /** Action ID for Disable CS */ 935 #define WLAN_TDLS_CS_DISABLE 0x09 936 /** Action ID for TDLS link status */ 937 #define WLAN_TDLS_LINK_STATUS 0x0A 938 /** Action ID for Host TDLS config uapsd and CS */ 939 #define WLAN_HOST_TDLS_CONFIG 0x0D 940 /** Action ID for TDLS CS immediate return */ 941 #define WLAN_TDLS_DEBUG_CS_RET_IM 0xFFF7 942 /** Action ID for TDLS Stop RX */ 943 #define WLAN_TDLS_DEBUG_STOP_RX 0xFFF8 944 /** Action ID for TDLS Allow weak security for links establish */ 945 #define WLAN_TDLS_DEBUG_ALLOW_WEAK_SECURITY 0xFFF9 946 /** Action ID for TDLS Ignore key lifetime expiry */ 947 #define WLAN_TDLS_DEBUG_IGNORE_KEY_EXPIRY 0xFFFA 948 /** Action ID for TDLS Higher/Lower mac Test */ 949 #define WLAN_TDLS_DEBUG_HIGHER_LOWER_MAC 0xFFFB 950 /** Action ID for TDLS Prohibited Test */ 951 #define WLAN_TDLS_DEBUG_SETUP_PROHIBITED 0xFFFC 952 /** Action ID for TDLS Existing link Test */ 953 #define WLAN_TDLS_DEBUG_SETUP_SAME_LINK 0xFFFD 954 /** Action ID for TDLS Fail Setup Confirm */ 955 #define WLAN_TDLS_DEBUG_FAIL_SETUP_CONFIRM 0xFFFE 956 /** Action commands for TDLS debug: Wrong BSS Request */ 957 #define WLAN_TDLS_DEBUG_WRONG_BSS 0xFFFF 958 959 /** tdls each link rate information */ 960 typedef MLAN_PACK_START struct _tdls_link_rate_info { 961 /** Tx Data Rate */ 962 t_u8 tx_data_rate; 963 /** Tx Rate HT info*/ 964 t_u8 tx_rate_htinfo; 965 } MLAN_PACK_END tdls_link_rate_info; 966 967 /** tdls each link status */ 968 typedef MLAN_PACK_START struct _tdls_each_link_status { 969 /** peer mac Address */ 970 t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH]; 971 /** Link Flags */ 972 t_u8 link_flags; 973 /** Traffic Status */ 974 t_u8 traffic_status; 975 /** Tx Failure Count */ 976 t_u8 tx_fail_count; 977 /** Channel Number */ 978 t_u32 active_channel; 979 /** Last Data RSSI in dBm */ 980 t_s16 data_rssi_last; 981 /** Last Data NF in dBm */ 982 t_s16 data_nf_last; 983 /** AVG DATA RSSI in dBm */ 984 t_s16 data_rssi_avg; 985 /** AVG DATA NF in dBm */ 986 t_s16 data_nf_avg; 987 union { 988 /** tdls rate info */ 989 tdls_link_rate_info rate_info; 990 /** tdls link final rate*/ 991 t_u16 final_data_rate; 992 } u; 993 /** Security Method */ 994 t_u8 security_method; 995 /** Key Lifetime in milliseconds */ 996 t_u32 key_lifetime; 997 /** Key Length */ 998 t_u8 key_length; 999 /** actual key */ 1000 t_u8 key[0]; 1001 } MLAN_PACK_END tdls_each_link_status; 1002 1003 /** TDLS configuration data */ 1004 typedef MLAN_PACK_START struct _tdls_all_config { 1005 union { 1006 /** TDLS state enable disable */ 1007 MLAN_PACK_START struct _tdls_config { 1008 /** enable or disable */ 1009 t_u16 enable; 1010 } MLAN_PACK_END tdls_config; 1011 /** Host tdls config */ 1012 MLAN_PACK_START struct _host_tdls_cfg { 1013 /** support uapsd */ 1014 t_u8 uapsd_support; 1015 /** channel_switch */ 1016 t_u8 cs_support; 1017 /** TLV length */ 1018 t_u16 tlv_len; 1019 /** tdls info */ 1020 t_u8 tlv_buffer[0]; 1021 } MLAN_PACK_END host_tdls_cfg; 1022 /** TDLS set info */ 1023 MLAN_PACK_START struct _tdls_set_data { 1024 /** (tlv + capInfo) length */ 1025 t_u16 tlv_length; 1026 /** Cap Info */ 1027 t_u16 cap_info; 1028 /** TLV buffer */ 1029 t_u8 tlv_buffer[0]; 1030 } MLAN_PACK_END tdls_set; 1031 1032 /** TDLS discovery and others having mac argument */ 1033 MLAN_PACK_START struct _tdls_discovery_data { 1034 /** peer mac Address */ 1035 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1036 } MLAN_PACK_END tdls_discovery, tdls_stop_chan_switch, 1037 tdls_link_status_req; 1038 1039 /** TDLS discovery Response */ 1040 MLAN_PACK_START struct _tdls_discovery_resp { 1041 /** payload length */ 1042 t_u16 payload_len; 1043 /** peer mac Address */ 1044 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1045 /** RSSI */ 1046 t_s8 rssi; 1047 /** Cap Info */ 1048 t_u16 cap_info; 1049 /** TLV buffer */ 1050 t_u8 tlv_buffer[0]; 1051 } MLAN_PACK_END tdls_discovery_resp; 1052 1053 /** TDLS setup request */ 1054 MLAN_PACK_START struct _tdls_setup_data { 1055 /** peer mac Address */ 1056 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1057 /** timeout value in milliseconds */ 1058 t_u32 setup_timeout; 1059 /** key lifetime in milliseconds */ 1060 t_u32 key_lifetime; 1061 } MLAN_PACK_END tdls_setup; 1062 1063 /** TDLS tear down info */ 1064 MLAN_PACK_START struct _tdls_tear_down_data { 1065 /** peer mac Address */ 1066 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1067 /** reason code */ 1068 t_u16 reason_code; 1069 } MLAN_PACK_END tdls_tear_down, tdls_cmd_resp; 1070 1071 /** TDLS power mode info */ 1072 MLAN_PACK_START struct _tdls_power_mode_data { 1073 /** peer mac Address */ 1074 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1075 /** Power Mode */ 1076 t_u16 power_mode; 1077 } MLAN_PACK_END tdls_power_mode; 1078 1079 /** TDLS channel switch info */ 1080 MLAN_PACK_START struct _tdls_chan_switch { 1081 /** peer mac Address */ 1082 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1083 /** Channel Switch primary channel no */ 1084 t_u8 primary_channel; 1085 /** Channel Switch secondary channel offset */ 1086 t_u8 secondary_channel_offset; 1087 /** Channel Switch Band */ 1088 t_u8 band; 1089 /** Channel Switch time in milliseconds */ 1090 t_u16 switch_time; 1091 /** Channel Switch timeout in milliseconds */ 1092 t_u16 switch_timeout; 1093 /** Channel Regulatory class*/ 1094 t_u8 regulatory_class; 1095 /** peridicity flag*/ 1096 t_u8 periodicity; 1097 } MLAN_PACK_END tdls_chan_switch; 1098 1099 /** TDLS channel switch paramters */ 1100 MLAN_PACK_START struct _tdls_cs_params { 1101 /** unit time, multiples of 10ms */ 1102 t_u8 unit_time; 1103 /** threshold for other link */ 1104 t_u8 threshold_otherlink; 1105 /** threshold for direct link */ 1106 t_u8 threshold_directlink; 1107 } MLAN_PACK_END tdls_cs_params; 1108 1109 /** tdls disable channel switch */ 1110 MLAN_PACK_START struct _tdls_disable_cs { 1111 /** Data*/ 1112 t_u16 data; 1113 } MLAN_PACK_END tdls_disable_cs; 1114 /** TDLS debug data */ 1115 MLAN_PACK_START struct _tdls_debug_data { 1116 /** debug data */ 1117 t_u16 debug_data; 1118 } MLAN_PACK_END tdls_debug_data; 1119 1120 /** TDLS link status Response */ 1121 MLAN_PACK_START struct _tdls_link_status_resp { 1122 /** payload length */ 1123 t_u16 payload_len; 1124 /** number of links */ 1125 t_u8 active_links; 1126 /** structure for link status */ 1127 tdls_each_link_status link_stats[1]; 1128 } MLAN_PACK_END tdls_link_status_resp; 1129 1130 } u; 1131 } MLAN_PACK_END tdls_all_config; 1132 1133 /** TDLS configuration buffer */ 1134 typedef MLAN_PACK_START struct _buf_tdls_config { 1135 /** TDLS Action */ 1136 t_u16 tdls_action; 1137 /** TDLS data */ 1138 t_u8 tdls_data[MAX_TDLS_DATA_LEN]; 1139 } MLAN_PACK_END mlan_ds_misc_tdls_config; 1140 1141 /** Event structure for tear down */ 1142 typedef struct _tdls_tear_down_event { 1143 /** Peer mac address */ 1144 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1145 /** Reason code */ 1146 t_u16 reason_code; 1147 } tdls_tear_down_event; 1148 1149 #ifdef PRAGMA_PACK 1150 #pragma pack(pop) 1151 #endif 1152 1153 /** mlan_callbacks data structure */ 1154 typedef struct _mlan_callbacks { 1155 /** moal_get_fw_data */ 1156 mlan_status (*moal_get_fw_data) (IN t_void *pmoal_handle, 1157 IN t_u32 offset, 1158 IN t_u32 len, OUT t_u8 *pbuf); 1159 /** moal_get_hw_spec_complete */ 1160 mlan_status (*moal_get_hw_spec_complete) (IN t_void *pmoal_handle, 1161 IN mlan_status status, 1162 IN mlan_hw_info * phw, 1163 IN pmlan_bss_tbl ptbl); 1164 /** moal_init_fw_complete */ 1165 mlan_status (*moal_init_fw_complete) (IN t_void *pmoal_handle, 1166 IN mlan_status status); 1167 /** moal_shutdown_fw_complete */ 1168 mlan_status (*moal_shutdown_fw_complete) (IN t_void *pmoal_handle, 1169 IN mlan_status status); 1170 /** moal_send_packet_complete */ 1171 mlan_status (*moal_send_packet_complete) (IN t_void *pmoal_handle, 1172 IN pmlan_buffer pmbuf, 1173 IN mlan_status status); 1174 /** moal_recv_complete */ 1175 mlan_status (*moal_recv_complete) (IN t_void *pmoal_handle, 1176 IN pmlan_buffer pmbuf, 1177 IN t_u32 port, 1178 IN mlan_status status); 1179 /** moal_recv_packet */ 1180 mlan_status (*moal_recv_packet) (IN t_void *pmoal_handle, 1181 IN pmlan_buffer pmbuf); 1182 /** moal_recv_event */ 1183 mlan_status (*moal_recv_event) (IN t_void *pmoal_handle, 1184 IN pmlan_event pmevent); 1185 /** moal_ioctl_complete */ 1186 mlan_status (*moal_ioctl_complete) (IN t_void *pmoal_handle, 1187 IN pmlan_ioctl_req pioctl_req, 1188 IN mlan_status status); 1189 1190 /** moal_alloc_mlan_buffer */ 1191 mlan_status (*moal_alloc_mlan_buffer) (IN t_void *pmoal_handle, 1192 IN t_u32 size, 1193 OUT pmlan_buffer *pmbuf); 1194 /** moal_free_mlan_buffer */ 1195 mlan_status (*moal_free_mlan_buffer) (IN t_void *pmoal_handle, 1196 IN pmlan_buffer pmbuf); 1197 1198 /** moal_write_reg */ 1199 mlan_status (*moal_write_reg) (IN t_void *pmoal_handle, 1200 IN t_u32 reg, IN t_u32 data); 1201 /** moal_read_reg */ 1202 mlan_status (*moal_read_reg) (IN t_void *pmoal_handle, 1203 IN t_u32 reg, OUT t_u32 *data); 1204 /** moal_write_data_sync */ 1205 mlan_status (*moal_write_data_sync) (IN t_void *pmoal_handle, 1206 IN pmlan_buffer pmbuf, 1207 IN t_u32 port, IN t_u32 timeout); 1208 /** moal_read_data_sync */ 1209 mlan_status (*moal_read_data_sync) (IN t_void *pmoal_handle, 1210 IN OUT pmlan_buffer pmbuf, 1211 IN t_u32 port, IN t_u32 timeout); 1212 /** moal_malloc */ 1213 mlan_status (*moal_malloc) (IN t_void *pmoal_handle, 1214 IN t_u32 size, 1215 IN t_u32 flag, OUT t_u8 **ppbuf); 1216 /** moal_mfree */ 1217 mlan_status (*moal_mfree) (IN t_void *pmoal_handle, IN t_u8 *pbuf); 1218 /** moal_vmalloc */ 1219 mlan_status (*moal_vmalloc) (IN t_void *pmoal_handle, 1220 IN t_u32 size, OUT t_u8 **ppbuf); 1221 /** moal_vfree */ 1222 mlan_status (*moal_vfree) (IN t_void *pmoal_handle, IN t_u8 *pbuf); 1223 /** moal_memset */ 1224 t_void *(*moal_memset) (IN t_void *pmoal_handle, 1225 IN t_void *pmem, IN t_u8 byte, IN t_u32 num); 1226 /** moal_memcpy */ 1227 t_void *(*moal_memcpy) (IN t_void *pmoal_handle, 1228 IN t_void *pdest, 1229 IN const t_void *psrc, IN t_u32 num); 1230 /** moal_memmove */ 1231 t_void *(*moal_memmove) (IN t_void *pmoal_handle, 1232 IN t_void *pdest, 1233 IN const t_void *psrc, IN t_u32 num); 1234 /** moal_memcmp */ 1235 t_s32 (*moal_memcmp) (IN t_void *pmoal_handle, 1236 IN const t_void *pmem1, 1237 IN const t_void *pmem2, IN t_u32 num); 1238 /** moal_udelay */ 1239 t_void (*moal_udelay) (IN t_void *pmoal_handle, IN t_u32 udelay); 1240 /** moal_get_system_time */ 1241 mlan_status (*moal_get_system_time) (IN t_void *pmoal_handle, 1242 OUT t_u32 *psec, OUT t_u32 *pusec); 1243 /** moal_init_timer*/ 1244 mlan_status (*moal_init_timer) (IN t_void *pmoal_handle, 1245 OUT t_void **pptimer, 1246 IN t_void (*callback) (t_void 1247 *pcontext), 1248 IN t_void *pcontext); 1249 /** moal_free_timer */ 1250 mlan_status (*moal_free_timer) (IN t_void *pmoal_handle, 1251 IN t_void *ptimer); 1252 /** moal_start_timer*/ 1253 mlan_status (*moal_start_timer) (IN t_void *pmoal_handle, 1254 IN t_void *ptimer, 1255 IN t_u8 periodic, IN t_u32 msec); 1256 /** moal_stop_timer*/ 1257 mlan_status (*moal_stop_timer) (IN t_void *pmoal_handle, 1258 IN t_void *ptimer); 1259 /** moal_init_lock */ 1260 mlan_status (*moal_init_lock) (IN t_void *pmoal_handle, 1261 OUT t_void **pplock); 1262 /** moal_free_lock */ 1263 mlan_status (*moal_free_lock) (IN t_void *pmoal_handle, 1264 IN t_void *plock); 1265 /** moal_spin_lock */ 1266 mlan_status (*moal_spin_lock) (IN t_void *pmoal_handle, 1267 IN t_void *plock); 1268 /** moal_spin_unlock */ 1269 mlan_status (*moal_spin_unlock) (IN t_void *pmoal_handle, 1270 IN t_void *plock); 1271 /** moal_print */ 1272 t_void (*moal_print) (IN t_void *pmoal_handle, 1273 IN t_u32 level, IN char *pformat, IN ... 1274 ); 1275 /** moal_print_netintf */ 1276 t_void (*moal_print_netintf) (IN t_void *pmoal_handle, 1277 IN t_u32 bss_index, IN t_u32 level); 1278 /** moal_assert */ 1279 t_void (*moal_assert) (IN t_void *pmoal_handle, IN t_u32 cond); 1280 /** moal_hist_data_add */ 1281 t_void (*moal_hist_data_add) (IN t_void *pmoal_handle, 1282 IN t_u32 bss_index, 1283 IN t_u8 rx_rate, 1284 IN t_s8 snr, 1285 IN t_s8 nflr, IN t_u8 antenna); 1286 t_void (*moal_updata_peer_signal) (IN t_void *pmoal_handle, 1287 IN t_u32 bss_index, 1288 IN t_u8 *peer_addr, 1289 IN t_s8 snr, IN t_s8 nflr); 1290 mlan_status (*moal_get_host_time_ns) (OUT t_u64 *time); 1291 t_u32 (*moal_do_div) (IN t_u64 num, IN t_u32 base); 1292 } mlan_callbacks, *pmlan_callbacks; 1293 1294 /** Parameter unchanged, use MLAN default setting */ 1295 #define ROBUSTCOEX_GPIO_UNCHANGED 0 1296 /** Parameter enabled, override MLAN default setting */ 1297 #define ROBUSTCOEX_GPIO_CFG 1 1298 1299 /** Interrupt Mode SDIO */ 1300 #define INT_MODE_SDIO 0 1301 /** Interrupt Mode GPIO */ 1302 #define INT_MODE_GPIO 1 1303 /** New mode: GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1 */ 1304 #define GPIO_INT_NEW_MODE 255 1305 1306 /** Parameter unchanged, use MLAN default setting */ 1307 #define MLAN_INIT_PARA_UNCHANGED 0 1308 /** Parameter enabled, override MLAN default setting */ 1309 #define MLAN_INIT_PARA_ENABLED 1 1310 /** Parameter disabled, override MLAN default setting */ 1311 #define MLAN_INIT_PARA_DISABLED 2 1312 1313 /** mlan_device data structure */ 1314 typedef struct _mlan_device { 1315 /** MOAL Handle */ 1316 t_void *pmoal_handle; 1317 /** BSS Attributes */ 1318 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 1319 /** Callbacks */ 1320 mlan_callbacks callbacks; 1321 #ifdef MFG_CMD_SUPPORT 1322 /** MFG mode */ 1323 t_u32 mfg_mode; 1324 #endif 1325 /** SDIO interrupt mode (0: INT_MODE_SDIO, 1: INT_MODE_GPIO) */ 1326 t_u32 int_mode; 1327 /** GPIO interrupt pin number */ 1328 t_u32 gpio_pin; 1329 #ifdef DEBUG_LEVEL1 1330 /** Driver debug bit masks */ 1331 t_u32 drvdbg; 1332 #endif 1333 /** allocate fixed buffer size for scan beacon buffer*/ 1334 t_u32 fixed_beacon_buffer; 1335 #ifdef SDIO_MULTI_PORT_TX_AGGR 1336 /** SDIO MPA Tx */ 1337 t_u32 mpa_tx_cfg; 1338 #endif 1339 #ifdef SDIO_MULTI_PORT_RX_AGGR 1340 /** SDIO MPA Rx */ 1341 t_u32 mpa_rx_cfg; 1342 #endif 1343 /** SDIO Single port rx aggr */ 1344 t_u8 sdio_rx_aggr_enable; 1345 #if defined(SDIO_MULTI_PORT_TX_AGGR) || defined(SDIO_MULTI_PORT_RX_AGGR) 1346 /* see blk_queue_max_segment_size */ 1347 t_u32 max_seg_size; 1348 /* see blk_queue_max_segments */ 1349 t_u16 max_segs; 1350 #endif 1351 /** Auto deep sleep */ 1352 t_u32 auto_ds; 1353 /** IEEE PS mode */ 1354 t_u32 ps_mode; 1355 /** Max Tx buffer size */ 1356 t_u32 max_tx_buf; 1357 #if defined(STA_SUPPORT) 1358 /** 802.11d configuration */ 1359 t_u32 cfg_11d; 1360 #endif 1361 /** enable/disable rx work */ 1362 t_u8 rx_work; 1363 /** dev cap mask */ 1364 t_u32 dev_cap_mask; 1365 /** oob independent reset */ 1366 t_u32 indrstcfg; 1367 /** dtim interval */ 1368 t_u32 multi_dtim; 1369 /** IEEE ps inactivity timeout value */ 1370 t_u32 inact_tmo; 1371 /** Host sleep wakeup interval */ 1372 t_u32 hs_wake_interval; 1373 /** GPIO to indicate wakeup source */ 1374 t_u8 indication_gpio; 1375 /** channel time and mode for DRCS*/ 1376 t_u32 drcs_chantime_mode; 1377 t_bool fw_region; 1378 } mlan_device, *pmlan_device; 1379 1380 /** MLAN API function prototype */ 1381 #define MLAN_API 1382 1383 /** Registration */ 1384 MLAN_API mlan_status mlan_register(IN pmlan_device pmdevice, 1385 OUT t_void **ppmlan_adapter); 1386 1387 /** Un-registration */ 1388 MLAN_API mlan_status mlan_unregister(IN t_void *pmlan_adapter 1389 ); 1390 1391 /** Firmware Downloading */ 1392 MLAN_API mlan_status mlan_dnld_fw(IN t_void *pmlan_adapter, 1393 IN pmlan_fw_image pmfw); 1394 1395 /** Custom data pass API */ 1396 MLAN_API mlan_status mlan_set_init_param(IN t_void *pmlan_adapter, 1397 IN pmlan_init_param pparam); 1398 1399 /** Firmware Initialization */ 1400 MLAN_API mlan_status mlan_init_fw(IN t_void *pmlan_adapter 1401 ); 1402 1403 /** Firmware Shutdown */ 1404 MLAN_API mlan_status mlan_shutdown_fw(IN t_void *pmlan_adapter 1405 ); 1406 1407 /** Main Process */ 1408 MLAN_API mlan_status mlan_main_process(IN t_void *pmlan_adapter 1409 ); 1410 1411 /** Rx process */ 1412 mlan_status mlan_rx_process(IN t_void *pmlan_adapter, IN t_u8 *rx_pkts); 1413 1414 /** Packet Transmission */ 1415 MLAN_API mlan_status mlan_send_packet(IN t_void *pmlan_adapter, 1416 IN pmlan_buffer pmbuf); 1417 1418 /** Packet Reception complete callback */ 1419 MLAN_API mlan_status mlan_recv_packet_complete(IN t_void *pmlan_adapter, 1420 IN pmlan_buffer pmbuf, 1421 IN mlan_status status); 1422 1423 /** interrupt handler */ 1424 MLAN_API mlan_status mlan_interrupt(IN t_void *pmlan_adapter); 1425 1426 #if defined(SYSKT) 1427 /** GPIO IRQ callback function */ 1428 MLAN_API t_void mlan_hs_callback(IN t_void *pctx); 1429 #endif /* SYSKT_MULTI || SYSKT */ 1430 1431 MLAN_API t_void mlan_pm_wakeup_card(IN t_void *pmlan_adapter); 1432 1433 MLAN_API t_u8 mlan_is_main_process_running(IN t_void *adapter); 1434 1435 /** mlan ioctl */ 1436 MLAN_API mlan_status mlan_ioctl(IN t_void *pmlan_adapter, 1437 IN pmlan_ioctl_req pioctl_req); 1438 /** mlan select wmm queue */ 1439 MLAN_API t_u8 mlan_select_wmm_queue(IN t_void *pmlan_adapter, 1440 IN t_u8 bss_num, IN t_u8 tid); 1441 #endif /* !_MLAN_DECL_H_ */ 1442