1 /* 2 * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific 3 * device core support 4 * 5 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: sbsdpcmdev.h 616398 2016-02-01 09:37:52Z $ 31 */ 32 33 #ifndef _sbsdpcmdev_h_ 34 #define _sbsdpcmdev_h_ 35 36 /* cpp contortions to concatenate w/arg prescan */ 37 #ifndef PAD 38 #define _PADLINE(line) pad ## line 39 #define _XSTR(line) _PADLINE(line) 40 #define PAD _XSTR(__LINE__) 41 #endif /* PAD */ 42 43 typedef volatile struct { 44 dma64regs_t xmt; /* dma tx */ 45 uint32 PAD[2]; 46 dma64regs_t rcv; /* dma rx */ 47 uint32 PAD[2]; 48 } dma64p_t; 49 50 /* dma64 sdiod corerev >= 1 */ 51 typedef volatile struct { 52 dma64p_t dma64regs[2]; 53 dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */ 54 uint32 PAD[28]; 55 } sdiodma64_t; 56 57 /* dma32 sdiod corerev == 0 */ 58 typedef volatile struct { 59 dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */ 60 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */ 61 uint32 PAD[44]; 62 } sdiodma32_t; 63 64 /* dma32 regs for pcmcia core */ 65 typedef volatile struct { 66 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ 67 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ 68 uint32 PAD[52]; 69 } pcmdma32_t; 70 71 /* core registers */ 72 typedef volatile struct { 73 uint32 corecontrol; /* CoreControl, 0x000, rev8 */ 74 uint32 corestatus; /* CoreStatus, 0x004, rev8 */ 75 uint32 PAD[1]; 76 uint32 biststatus; /* BistStatus, 0x00c, rev8 */ 77 78 /* PCMCIA access */ 79 uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ 80 uint16 PAD[1]; 81 uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */ 82 uint16 PAD[1]; 83 uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */ 84 uint16 PAD[1]; 85 uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */ 86 uint16 PAD[1]; 87 88 /* interrupt */ 89 uint32 intstatus; /* IntStatus, 0x020, rev8 */ 90 uint32 hostintmask; /* IntHostMask, 0x024, rev8 */ 91 uint32 intmask; /* IntSbMask, 0x028, rev8 */ 92 uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ 93 uint32 sbintmask; /* SBIntMask, 0x030, rev8 */ 94 uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */ 95 uint32 PAD[2]; 96 uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ 97 uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ 98 uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ 99 uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ 100 101 /* synchronized access to registers in SDIO clock domain */ 102 uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */ 103 uint32 PAD[1]; 104 uint32 MiscHostAccessIntEn; 105 uint32 PAD[1]; 106 107 /* PCMCIA frame control */ 108 uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ 109 uint8 PAD[3]; 110 uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */ 111 uint8 PAD[155]; 112 113 /* interrupt batching control */ 114 uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ 115 uint32 PAD[3]; 116 117 /* counters */ 118 uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ 119 uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ 120 uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ 121 uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ 122 uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ 123 uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ 124 uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ 125 uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ 126 uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ 127 uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ 128 uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ 129 uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ 130 uint32 PAD[40]; 131 uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ 132 uint32 PAD[1]; 133 uint32 powerctl; /* 0x1e8 */ 134 uint32 PAD[5]; 135 136 /* DMA engines */ 137 volatile union { 138 pcmdma32_t pcm32; 139 sdiodma32_t sdiod32; 140 sdiodma64_t sdiod64; 141 } dma; 142 143 uint32 PAD[12]; /* 0x300-0x32c */ 144 uint32 chipid; /* SDIO ChipID Register, 0x330, rev31 */ 145 uint32 eromptr; /* SDIO EromPtrOffset Register, 0x334, rev31 */ 146 uint32 PAD[50]; 147 148 /* SDIO/PCMCIA CIS region */ 149 char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */ 150 151 /* PCMCIA function control registers */ 152 char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */ 153 uint16 PAD[55]; 154 155 /* PCMCIA backplane access */ 156 uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */ 157 uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */ 158 uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */ 159 uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */ 160 uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */ 161 uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */ 162 uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */ 163 uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */ 164 uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */ 165 uint16 PAD[31]; 166 167 /* sprom "size" & "blank" info */ 168 uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ 169 uint32 PAD[464]; 170 171 /* Sonics SiliconBackplane registers */ 172 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ 173 } sdpcmd_regs_t; 174 175 /* corecontrol */ 176 #define CC_CISRDY (1 << 0) /* CIS Ready */ 177 #define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */ 178 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 179 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */ 180 #define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */ 181 #define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */ 182 183 /* corestatus */ 184 #define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */ 185 #define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */ 186 #define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */ 187 188 #define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */ 189 #define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */ 190 #define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */ 191 #define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */ 192 193 /* intstatus */ 194 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 195 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 196 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 197 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 198 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 199 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 200 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 201 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 202 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 203 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 204 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 205 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 206 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 207 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 208 #define I_PC (1 << 10) /* descriptor error */ 209 #define I_PD (1 << 11) /* data error */ 210 #define I_DE (1 << 12) /* Descriptor protocol Error */ 211 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 212 #define I_RO (1 << 14) /* Receive fifo Overflow */ 213 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 214 #define I_RI (1 << 16) /* Receive Interrupt */ 215 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 216 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 217 #define I_XI (1 << 24) /* Transmit Interrupt */ 218 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 219 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 220 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 221 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 222 #define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */ 223 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 224 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 225 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */ 226 #define I_DMA (I_RI | I_XI | I_ERRORS) 227 228 /* sbintstatus */ 229 #define I_SB_SERR (1 << 8) /* Backplane SError (write) */ 230 #define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */ 231 #define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */ 232 233 /* sdioaccess */ 234 #define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */ 235 #define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */ 236 #define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */ 237 #define SDA_WRITE 0x01000000 /* Write bit */ 238 #define SDA_READ 0x00000000 /* Write bit cleared for Read */ 239 #define SDA_BUSY 0x80000000 /* Busy bit */ 240 241 /* sdioaccess-accessible register address spaces */ 242 #define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */ 243 #define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */ 244 #define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */ 245 #define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */ 246 #define SDA_F3_FBR_SPACE 0x400 /* sdioAccess F3 FBR register space */ 247 248 /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */ 249 #define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */ 250 #define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */ 251 #define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */ 252 #define SDA_DEVICECONTROL 0x009 /* DeviceControl */ 253 #define SDA_SBADDRLOW 0x00a /* SbAddrLow */ 254 #define SDA_SBADDRMID 0x00b /* SbAddrMid */ 255 #define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */ 256 #define SDA_FRAMECTRL 0x00d /* FrameCtrl */ 257 #define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */ 258 #define SDA_SDIOPULLUP 0x00f /* SdioPullUp */ 259 #define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */ 260 #define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */ 261 #define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */ 262 #define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */ 263 #define SDA_MESBUSYCNTRL 0x01d /* mesBusyCntrl */ 264 #define SDA_WAKEUPCTRL 0x01e /* WakeupCtrl */ 265 #define SDA_SLEEPCSR 0x01f /* sleepCSR */ 266 267 /* SDA_F1_REG_SPACE register bits */ 268 /* sleepCSR register */ 269 #define SDA_SLEEPCSR_KEEP_SDIO_ON 0x1 270 271 /* SDA_F2WATERMARK */ 272 #define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */ 273 274 /* SDA_SBADDRLOW */ 275 #define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */ 276 277 /* SDA_SBADDRMID */ 278 #define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */ 279 280 /* SDA_SBADDRHIGH */ 281 #define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */ 282 283 /* SDA_FRAMECTRL */ 284 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 285 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 286 #define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */ 287 #define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */ 288 289 /* pcmciaframectrl */ 290 #define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 291 #define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 292 293 /* intrcvlazy */ 294 #define IRL_TO_MASK 0x00ffffff /* timeout */ 295 #define IRL_FC_MASK 0xff000000 /* frame count */ 296 #define IRL_FC_SHIFT 24 /* frame count */ 297 298 /* rx header */ 299 typedef volatile struct { 300 uint16 len; 301 uint16 flags; 302 } sdpcmd_rxh_t; 303 304 /* rx header flags */ 305 #define RXF_CRC 0x0001 /* CRC error detected */ 306 #define RXF_WOOS 0x0002 /* write frame out of sync */ 307 #define RXF_WF_TERM 0x0004 /* write frame terminated */ 308 #define RXF_ABORT 0x0008 /* write frame aborted */ 309 #define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */ 310 311 /* HW frame tag */ 312 #define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */ 313 314 #define SDPCM_HWEXT_LEN 8 315 316 #endif /* _sbsdpcmdev_h_ */ 317