1 /* 2 * Extended Trap data component interface file. 3 * 4 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id$ 30 */ 31 32 #ifndef _ETD_H_ 33 #define _ETD_H_ 34 35 #if defined(ETD) && !defined(WLETD) 36 #include <hnd_trap.h> 37 #endif // endif 38 #include <bcmutils.h> 39 /* Tags for structures being used by etd info iovar. 40 * Related structures are defined in wlioctl.h. 41 */ 42 #define ETD_TAG_JOIN_CLASSIFICATION_INFO 10 /* general information about join request */ 43 #define ETD_TAG_JOIN_TARGET_CLASSIFICATION_INFO 11 /* per target (AP) join information */ 44 #define ETD_TAG_ASSOC_STATE 12 /* current state of the Device association state machine */ 45 #define ETD_TAG_CHANNEL 13 /* current channel on which the association was performed */ 46 #define ETD_TAG_TOTAL_NUM_OF_JOIN_ATTEMPTS 14 /* number of join attempts (bss_retries) */ 47 48 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1 3 49 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2 6 50 51 #ifndef _LANGUAGE_ASSEMBLY 52 53 #define HND_EXTENDED_TRAP_VERSION 1 54 #define HND_EXTENDED_TRAP_BUFLEN 512 55 56 typedef struct hnd_ext_trap_hdr { 57 uint8 version; /* Extended trap version info */ 58 uint8 reserved; /* currently unused */ 59 uint16 len; /* Length of data excluding this header */ 60 uint8 data[]; /* TLV data */ 61 } hnd_ext_trap_hdr_t; 62 63 typedef enum { 64 TAG_TRAP_NONE = 0, /* None trap type */ 65 TAG_TRAP_SIGNATURE = 1, /* Processor register dumps */ 66 TAG_TRAP_STACK = 2, /* Processor stack dump (possible code locations) */ 67 TAG_TRAP_MEMORY = 3, /* Memory subsystem dump */ 68 TAG_TRAP_DEEPSLEEP = 4, /* Deep sleep health check failures */ 69 TAG_TRAP_PSM_WD = 5, /* PSM watchdog information */ 70 TAG_TRAP_PHY = 6, /* Phy related issues */ 71 TAG_TRAP_BUS = 7, /* Bus level issues */ 72 TAG_TRAP_MAC_SUSP = 8, /* Mac level suspend issues */ 73 TAG_TRAP_BACKPLANE = 9, /* Backplane related errors */ 74 /* Values 10 through 14 are in use by etd_data info iovar */ 75 TAG_TRAP_PCIE_Q = 15, /* PCIE Queue state during memory trap */ 76 TAG_TRAP_WLC_STATE = 16, /* WLAN state during memory trap */ 77 TAG_TRAP_MAC_WAKE = 17, /* Mac level wake issues */ 78 TAG_TRAP_PHYTXERR_THRESH = 18, /* Phy Tx Err */ 79 TAG_TRAP_HC_DATA = 19, /* Data collected by HC module */ 80 TAG_TRAP_LOG_DATA = 20, 81 TAG_TRAP_CODE = 21, /* The trap type */ 82 TAG_TRAP_HMAP = 22, /* HMAP violation Address and Info */ 83 TAG_TRAP_PCIE_ERR_ATTN = 23, /* PCIE error attn log */ 84 TAG_TRAP_AXI_ERROR = 24, /* AXI Error */ 85 TAG_TRAP_AXI_HOST_INFO = 25, /* AXI Host log */ 86 TAG_TRAP_AXI_SR_ERROR = 26, /* AXI SR error log */ 87 TAG_TRAP_LAST /* This must be the last entry */ 88 } hnd_ext_tag_trap_t; 89 90 typedef struct hnd_ext_trap_bp_err 91 { 92 uint32 error; 93 uint32 coreid; 94 uint32 baseaddr; 95 uint32 ioctrl; 96 uint32 iostatus; 97 uint32 resetctrl; 98 uint32 resetstatus; 99 uint32 resetreadid; 100 uint32 resetwriteid; 101 uint32 errlogctrl; 102 uint32 errlogdone; 103 uint32 errlogstatus; 104 uint32 errlogaddrlo; 105 uint32 errlogaddrhi; 106 uint32 errlogid; 107 uint32 errloguser; 108 uint32 errlogflags; 109 uint32 itipoobaout; 110 uint32 itipoobbout; 111 uint32 itipoobcout; 112 uint32 itipoobdout; 113 } hnd_ext_trap_bp_err_t; 114 115 #define HND_EXT_TRAP_AXISR_INFO_VER_1 1 116 typedef struct hnd_ext_trap_axi_sr_err_v1 117 { 118 uint8 version; 119 uint8 pad[3]; 120 uint32 error; 121 uint32 coreid; 122 uint32 baseaddr; 123 uint32 ioctrl; 124 uint32 iostatus; 125 uint32 resetctrl; 126 uint32 resetstatus; 127 uint32 resetreadid; 128 uint32 resetwriteid; 129 uint32 errlogctrl; 130 uint32 errlogdone; 131 uint32 errlogstatus; 132 uint32 errlogaddrlo; 133 uint32 errlogaddrhi; 134 uint32 errlogid; 135 uint32 errloguser; 136 uint32 errlogflags; 137 uint32 itipoobaout; 138 uint32 itipoobbout; 139 uint32 itipoobcout; 140 uint32 itipoobdout; 141 142 /* axi_sr_issue_debug */ 143 uint32 sr_pwr_control; 144 uint32 sr_corereset_wrapper_main; 145 uint32 sr_corereset_wrapper_aux; 146 uint32 sr_main_gci_status_0; 147 uint32 sr_aux_gci_status_0; 148 uint32 sr_dig_gci_status_0; 149 } hnd_ext_trap_axi_sr_err_v1_t; 150 151 #define HND_EXT_TRAP_PSMWD_INFO_VER 1 152 typedef struct hnd_ext_trap_psmwd_v1 { 153 uint16 xtag; 154 uint16 version; /* version of the information following this */ 155 uint32 i32_maccontrol; 156 uint32 i32_maccommand; 157 uint32 i32_macintstatus; 158 uint32 i32_phydebug; 159 uint32 i32_clk_ctl_st; 160 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1]; 161 uint16 i16_0x1a8; /* gated clock en */ 162 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 163 uint16 i16_0x408; /* Rx ctrl 1 */ 164 uint16 i16_0x41a; /* Rxe Status 1 */ 165 uint16 i16_0x41c; /* Rxe Status 2 */ 166 uint16 i16_0x424; /* rcv wrd count 0 */ 167 uint16 i16_0x426; /* rcv wrd count 1 */ 168 uint16 i16_0x456; /* RCV_LFIFO_STS */ 169 uint16 i16_0x480; /* PSM_SLP_TMR */ 170 uint16 i16_0x490; /* PSM BRC */ 171 uint16 i16_0x500; /* TXE CTRL */ 172 uint16 i16_0x50e; /* TXE Status */ 173 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 174 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 175 uint16 i16_0x690; /* IFS Stat */ 176 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 177 uint16 i16_0x694; /* IFS_TX_DUR */ 178 uint16 i16_0x6a0; /* SLow_CTL */ 179 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 180 uint16 i16_0x8c0; /* Dagg ctrl */ 181 uint16 shm_prewds_cnt; 182 uint16 shm_txtplufl_cnt; 183 uint16 shm_txphyerr_cnt; 184 uint16 pad; 185 } hnd_ext_trap_psmwd_v1_t; 186 187 typedef struct hnd_ext_trap_psmwd { 188 uint16 xtag; 189 uint16 version; /* version of the information following this */ 190 uint32 i32_maccontrol; 191 uint32 i32_maccommand; 192 uint32 i32_macintstatus; 193 uint32 i32_phydebug; 194 uint32 i32_clk_ctl_st; 195 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2]; 196 uint16 i16_0x4b8; /* psm_brwk_0 */ 197 uint16 i16_0x4ba; /* psm_brwk_1 */ 198 uint16 i16_0x4bc; /* psm_brwk_2 */ 199 uint16 i16_0x4be; /* psm_brwk_2 */ 200 uint16 i16_0x1a8; /* gated clock en */ 201 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 202 uint16 i16_0x408; /* Rx ctrl 1 */ 203 uint16 i16_0x41a; /* Rxe Status 1 */ 204 uint16 i16_0x41c; /* Rxe Status 2 */ 205 uint16 i16_0x424; /* rcv wrd count 0 */ 206 uint16 i16_0x426; /* rcv wrd count 1 */ 207 uint16 i16_0x456; /* RCV_LFIFO_STS */ 208 uint16 i16_0x480; /* PSM_SLP_TMR */ 209 uint16 i16_0x500; /* TXE CTRL */ 210 uint16 i16_0x50e; /* TXE Status */ 211 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 212 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 213 uint16 i16_0x690; /* IFS Stat */ 214 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 215 uint16 i16_0x694; /* IFS_TX_DUR */ 216 uint16 i16_0x6a0; /* SLow_CTL */ 217 uint16 i16_0x490; /* psm_brc */ 218 uint16 i16_0x4da; /* psm_brc_1 */ 219 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 220 uint16 i16_0x8c0; /* Dagg ctrl */ 221 uint16 shm_prewds_cnt; 222 uint16 shm_txtplufl_cnt; 223 uint16 shm_txphyerr_cnt; 224 } hnd_ext_trap_psmwd_t; 225 226 #define HEAP_HISTOGRAM_DUMP_LEN 6 227 #define HEAP_MAX_SZ_BLKS_LEN 2 228 229 /* Ignore chunks for which there are fewer than this many instances, irrespective of size */ 230 #define HEAP_HISTOGRAM_INSTANCE_MIN 4 231 232 /* 233 * Use the last two length values for chunks larger than this, or when we run out of 234 * histogram entries (because we have too many different sized chunks) to store "other" 235 */ 236 #define HEAP_HISTOGRAM_SPECIAL 0xfffeu 237 238 #define HEAP_HISTOGRAM_GRTR256K 0xffffu 239 240 typedef struct hnd_ext_trap_heap_err { 241 uint32 arena_total; 242 uint32 heap_free; 243 uint32 heap_inuse; 244 uint32 mf_count; 245 uint32 stack_lwm; 246 uint16 heap_histogm[HEAP_HISTOGRAM_DUMP_LEN * 2]; /* size/number */ 247 uint16 max_sz_free_blk[HEAP_MAX_SZ_BLKS_LEN]; 248 } hnd_ext_trap_heap_err_t; 249 250 #define MEM_TRAP_NUM_WLC_TX_QUEUES 6 251 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V2 2 252 253 typedef struct hnd_ext_trap_wlc_mem_err { 254 uint8 instance; 255 uint8 associated; 256 uint8 soft_ap_client_cnt; 257 uint8 peer_cnt; 258 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 259 } hnd_ext_trap_wlc_mem_err_t; 260 261 typedef struct hnd_ext_trap_wlc_mem_err_v2 { 262 uint16 version; 263 uint16 pad; 264 uint8 instance; 265 uint8 stas_associated; 266 uint8 aps_associated; 267 uint8 soft_ap_client_cnt; 268 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 269 } hnd_ext_trap_wlc_mem_err_v2_t; 270 271 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V3 3 272 273 typedef struct hnd_ext_trap_wlc_mem_err_v3 { 274 uint8 version; 275 uint8 instance; 276 uint8 stas_associated; 277 uint8 aps_associated; 278 uint8 soft_ap_client_cnt; 279 uint8 peer_cnt; 280 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 281 } hnd_ext_trap_wlc_mem_err_v3_t; 282 283 typedef struct hnd_ext_trap_pcie_mem_err { 284 uint16 d2h_queue_len; 285 uint16 d2h_req_queue_len; 286 } hnd_ext_trap_pcie_mem_err_t; 287 288 #define MAX_DMAFIFO_ENTRIES_V1 1 289 #define MAX_DMAFIFO_DESC_ENTRIES_V1 2 290 #define HND_EXT_TRAP_AXIERROR_SIGNATURE 0xbabebabe 291 #define HND_EXT_TRAP_AXIERROR_VERSION_1 1 292 293 /* Structure to collect debug info of descriptor entry for dma channel on encountering AXI Error */ 294 /* Below three structures are dependant, any change will bump version of all the three */ 295 296 typedef struct hnd_ext_trap_desc_entry_v1 { 297 uint32 ctrl1; /* descriptor entry at din < misc control bits > */ 298 uint32 ctrl2; /* descriptor entry at din <buffer count and address extension> */ 299 uint32 addrlo; /* descriptor entry at din <address of data buffer, bits 31:0> */ 300 uint32 addrhi; /* descriptor entry at din <address of data buffer, bits 63:32> */ 301 } dma_dentry_v1_t; 302 303 /* Structure to collect debug info about a dma channel on encountering AXI Error */ 304 typedef struct hnd_ext_trap_dma_fifo_v1 { 305 uint8 valid; /* no of valid desc entries filled, non zero = fifo entry valid */ 306 uint8 direction; /* TX=1, RX=2, currently only using TX */ 307 uint16 index; /* Index of the DMA channel in system */ 308 uint32 dpa; /* Expected Address of Descriptor table from software state */ 309 uint32 desc_lo; /* Low Address of Descriptor table programmed in DMA register */ 310 uint32 desc_hi; /* High Address of Descriptor table programmed in DMA register */ 311 uint16 din; /* rxin / txin */ 312 uint16 dout; /* rxout / txout */ 313 dma_dentry_v1_t dentry[MAX_DMAFIFO_DESC_ENTRIES_V1]; /* Descriptor Entires */ 314 } dma_fifo_v1_t; 315 316 typedef struct hnd_ext_trap_axi_error_v1 { 317 uint8 version; /* version = 1 */ 318 uint8 dma_fifo_valid_count; /* Number of valid dma_fifo entries */ 319 uint16 length; /* length of whole structure */ 320 uint32 signature; /* indicate that its filled with AXI Error data */ 321 uint32 axi_errorlog_status; /* errlog_status from slave wrapper */ 322 uint32 axi_errorlog_core; /* errlog_core from slave wrapper */ 323 uint32 axi_errorlog_lo; /* errlog_lo from slave wrapper */ 324 uint32 axi_errorlog_hi; /* errlog_hi from slave wrapper */ 325 uint32 axi_errorlog_id; /* errlog_id from slave wrapper */ 326 dma_fifo_v1_t dma_fifo[MAX_DMAFIFO_ENTRIES_V1]; 327 } hnd_ext_trap_axi_error_v1_t; 328 329 #define HND_EXT_TRAP_MACSUSP_INFO_VER 1 330 typedef struct hnd_ext_trap_macsusp { 331 uint16 xtag; 332 uint8 version; /* version of the information following this */ 333 uint8 trap_reason; 334 uint32 i32_maccontrol; 335 uint32 i32_maccommand; 336 uint32 i32_macintstatus; 337 uint32 i32_phydebug[4]; 338 uint32 i32_psmdebug[8]; 339 uint16 i16_0x41a; /* Rxe Status 1 */ 340 uint16 i16_0x41c; /* Rxe Status 2 */ 341 uint16 i16_0x490; /* PSM BRC */ 342 uint16 i16_0x50e; /* TXE Status */ 343 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 344 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 345 uint16 i16_0x690; /* IFS Stat */ 346 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 347 uint16 i16_0x694; /* IFS_TX_DUR */ 348 uint16 i16_0x7c0; /* WEP CTL */ 349 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 350 uint16 i16_0x880; /* MHP_status */ 351 uint16 shm_prewds_cnt; 352 uint16 shm_ucode_dbgst; 353 } hnd_ext_trap_macsusp_t; 354 355 #define HND_EXT_TRAP_MACENAB_INFO_VER 1 356 typedef struct hnd_ext_trap_macenab { 357 uint16 xtag; 358 uint8 version; /* version of the information following this */ 359 uint8 trap_reason; 360 uint32 i32_maccontrol; 361 uint32 i32_maccommand; 362 uint32 i32_macintstatus; 363 uint32 i32_psmdebug[8]; 364 uint32 i32_clk_ctl_st; 365 uint32 i32_powerctl; 366 uint16 i16_0x1a8; /* gated clock en */ 367 uint16 i16_0x480; /* PSM_SLP_TMR */ 368 uint16 i16_0x490; /* PSM BRC */ 369 uint16 i16_0x600; /* TSF CTL */ 370 uint16 i16_0x690; /* IFS Stat */ 371 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 372 uint16 i16_0x6a0; /* SLow_CTL */ 373 uint16 i16_0x6a6; /* SLow_FRAC */ 374 uint16 i16_0x6a8; /* fast power up delay */ 375 uint16 i16_0x6aa; /* SLow_PER */ 376 uint16 shm_ucode_dbgst; 377 uint16 PAD; 378 } hnd_ext_trap_macenab_t; 379 380 #define HND_EXT_TRAP_PHY_INFO_VER_1 (1) 381 typedef struct hnd_ext_trap_phydbg { 382 uint16 err; 383 uint16 RxFeStatus; 384 uint16 TxFIFOStatus0; 385 uint16 TxFIFOStatus1; 386 uint16 RfseqMode; 387 uint16 RfseqStatus0; 388 uint16 RfseqStatus1; 389 uint16 RfseqStatus_Ocl; 390 uint16 RfseqStatus_Ocl1; 391 uint16 OCLControl1; 392 uint16 TxError; 393 uint16 bphyTxError; 394 uint16 TxCCKError; 395 uint16 TxCtrlWrd0; 396 uint16 TxCtrlWrd1; 397 uint16 TxCtrlWrd2; 398 uint16 TxLsig0; 399 uint16 TxLsig1; 400 uint16 TxVhtSigA10; 401 uint16 TxVhtSigA11; 402 uint16 TxVhtSigA20; 403 uint16 TxVhtSigA21; 404 uint16 txPktLength; 405 uint16 txPsdulengthCtr; 406 uint16 gpioClkControl; 407 uint16 gpioSel; 408 uint16 pktprocdebug; 409 uint16 PAD; 410 uint32 gpioOut[3]; 411 } hnd_ext_trap_phydbg_t; 412 413 /* unique IDs for separate cores in SI */ 414 #define REGDUMP_MASK_MAC0 BCM_BIT(1) 415 #define REGDUMP_MASK_ARM BCM_BIT(2) 416 #define REGDUMP_MASK_PCIE BCM_BIT(3) 417 #define REGDUMP_MASK_MAC1 BCM_BIT(4) 418 #define REGDUMP_MASK_PMU BCM_BIT(5) 419 420 typedef struct { 421 uint16 reg_offset; 422 uint16 core_mask; 423 } reg_dump_config_t; 424 425 #define HND_EXT_TRAP_PHY_INFO_VER 2 426 typedef struct hnd_ext_trap_phydbg_v2 { 427 uint8 version; 428 uint8 len; 429 uint16 err; 430 uint16 RxFeStatus; 431 uint16 TxFIFOStatus0; 432 uint16 TxFIFOStatus1; 433 uint16 RfseqMode; 434 uint16 RfseqStatus0; 435 uint16 RfseqStatus1; 436 uint16 RfseqStatus_Ocl; 437 uint16 RfseqStatus_Ocl1; 438 uint16 OCLControl1; 439 uint16 TxError; 440 uint16 bphyTxError; 441 uint16 TxCCKError; 442 uint16 TxCtrlWrd0; 443 uint16 TxCtrlWrd1; 444 uint16 TxCtrlWrd2; 445 uint16 TxLsig0; 446 uint16 TxLsig1; 447 uint16 TxVhtSigA10; 448 uint16 TxVhtSigA11; 449 uint16 TxVhtSigA20; 450 uint16 TxVhtSigA21; 451 uint16 txPktLength; 452 uint16 txPsdulengthCtr; 453 uint16 gpioClkControl; 454 uint16 gpioSel; 455 uint16 pktprocdebug; 456 uint32 gpioOut[3]; 457 uint32 additional_regs[1]; 458 } hnd_ext_trap_phydbg_v2_t; 459 460 #define HND_EXT_TRAP_PHY_INFO_VER_3 (3) 461 typedef struct hnd_ext_trap_phydbg_v3 { 462 uint8 version; 463 uint8 len; 464 uint16 err; 465 uint16 RxFeStatus; 466 uint16 TxFIFOStatus0; 467 uint16 TxFIFOStatus1; 468 uint16 RfseqMode; 469 uint16 RfseqStatus0; 470 uint16 RfseqStatus1; 471 uint16 RfseqStatus_Ocl; 472 uint16 RfseqStatus_Ocl1; 473 uint16 OCLControl1; 474 uint16 TxError; 475 uint16 bphyTxError; 476 uint16 TxCCKError; 477 uint16 TxCtrlWrd0; 478 uint16 TxCtrlWrd1; 479 uint16 TxCtrlWrd2; 480 uint16 TxLsig0; 481 uint16 TxLsig1; 482 uint16 TxVhtSigA10; 483 uint16 TxVhtSigA11; 484 uint16 TxVhtSigA20; 485 uint16 TxVhtSigA21; 486 uint16 txPktLength; 487 uint16 txPsdulengthCtr; 488 uint16 gpioClkControl; 489 uint16 gpioSel; 490 uint16 pktprocdebug; 491 uint32 gpioOut[3]; 492 uint16 HESigURateFlagStatus; 493 uint16 HESigUsRateFlagStatus; 494 uint32 additional_regs[1]; 495 } hnd_ext_trap_phydbg_v3_t; 496 497 /* Phy TxErr Dump Structure */ 498 #define HND_EXT_TRAP_PHYTXERR_INFO_VER 1 499 #define HND_EXT_TRAP_PHYTXERR_INFO_VER_V2 2 500 typedef struct hnd_ext_trap_macphytxerr { 501 uint8 version; /* version of the information following this */ 502 uint8 trap_reason; 503 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 504 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 505 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 506 uint16 i16_0x846; /* TDC_FrmLen0 */ 507 uint16 i16_0x848; /* TDC_FrmLen1 */ 508 uint16 i16_0x84a; /* TDC_Txtime */ 509 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 510 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 511 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 512 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 513 uint16 i16_0x490; /* psm_brc */ 514 uint16 i16_0x4d8; /* psm_brc_1 */ 515 uint16 shm_txerr_reason; 516 uint16 shm_pctl0; 517 uint16 shm_pctl1; 518 uint16 shm_pctl2; 519 uint16 shm_lsig0; 520 uint16 shm_lsig1; 521 uint16 shm_plcp0; 522 uint16 shm_plcp1; 523 uint16 shm_plcp2; 524 uint16 shm_vht_sigb0; 525 uint16 shm_vht_sigb1; 526 uint16 shm_tx_tst; 527 uint16 shm_txerr_tm; 528 uint16 shm_curchannel; 529 uint16 shm_crx_rxtsf_pos; 530 uint16 shm_lasttx_tsf; 531 uint16 shm_s_rxtsftmrval; 532 uint16 i16_0x29; /* Phy indirect address */ 533 uint16 i16_0x2a; /* Phy indirect address */ 534 } hnd_ext_trap_macphytxerr_t; 535 536 typedef struct hnd_ext_trap_macphytxerr_v2 { 537 uint8 version; /* version of the information following this */ 538 uint8 trap_reason; 539 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 540 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 541 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 542 uint16 i16_0x846; /* TDC_FrmLen0 */ 543 uint16 i16_0x848; /* TDC_FrmLen1 */ 544 uint16 i16_0x84a; /* TDC_Txtime */ 545 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 546 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 547 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 548 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 549 uint16 i16_0x490; /* psm_brc */ 550 uint16 i16_0x4d8; /* psm_brc_1 */ 551 uint16 shm_txerr_reason; 552 uint16 shm_pctl0; 553 uint16 shm_pctl1; 554 uint16 shm_pctl2; 555 uint16 shm_lsig0; 556 uint16 shm_lsig1; 557 uint16 shm_plcp0; 558 uint16 shm_plcp1; 559 uint16 shm_plcp2; 560 uint16 shm_vht_sigb0; 561 uint16 shm_vht_sigb1; 562 uint16 shm_tx_tst; 563 uint16 shm_txerr_tm; 564 uint16 shm_curchannel; 565 uint16 shm_crx_rxtsf_pos; 566 uint16 shm_lasttx_tsf; 567 uint16 shm_s_rxtsftmrval; 568 uint16 i16_0x29; /* Phy indirect address */ 569 uint16 i16_0x2a; /* Phy indirect address */ 570 uint8 phyerr_bmac_cnt; /* number of times bmac raised phy tx err */ 571 uint8 phyerr_bmac_rsn; /* bmac reason for phy tx error */ 572 uint16 pad; 573 uint32 recv_fifo_status[3][2]; /* Rcv Status0 & Rcv Status1 for 3 Rx fifos */ 574 } hnd_ext_trap_macphytxerr_v2_t; 575 576 #define HND_EXT_TRAP_PCIE_ERR_ATTN_VER_1 (1u) 577 #define MAX_AER_HDR_LOG_REGS (4u) 578 typedef struct hnd_ext_trap_pcie_err_attn_v1 { 579 uint8 version; 580 uint8 pad[3]; 581 uint32 err_hdr_logreg1; 582 uint32 err_hdr_logreg2; 583 uint32 err_hdr_logreg3; 584 uint32 err_hdr_logreg4; 585 uint32 err_code_logreg; 586 uint32 err_type; 587 uint32 err_code_state; 588 uint32 last_err_attn_ts; 589 uint32 cfg_tlp_hdr[MAX_AER_HDR_LOG_REGS]; 590 } hnd_ext_trap_pcie_err_attn_v1_t; 591 592 #define MAX_EVENTLOG_BUFFERS 48 593 typedef struct eventlog_trapdata_info { 594 uint32 num_elements; 595 uint32 seq_num; 596 uint32 log_arr_addr; 597 } eventlog_trapdata_info_t; 598 599 typedef struct eventlog_trap_buf_info { 600 uint32 len; 601 uint32 buf_addr; 602 } eventlog_trap_buf_info_t; 603 604 #if defined(ETD) && !defined(WLETD) 605 #define ETD_SW_FLAG_MEM 0x00000001 606 607 int etd_init(osl_t *osh); 608 int etd_register_trap_ext_callback(void *cb, void *arg); 609 int (etd_register_trap_ext_callback_late)(void *cb, void *arg); 610 uint32 *etd_get_trap_ext_data(void); 611 uint32 etd_get_trap_ext_swflags(void); 612 void etd_set_trap_ext_swflag(uint32 flag); 613 void etd_notify_trap_ext_callback(trap_t *tr); 614 reg_dump_config_t *etd_get_reg_dump_config_tbl(void); 615 uint etd_get_reg_dump_config_len(void); 616 617 extern bool _etd_enab; 618 619 #define ETD_ENAB(pub) (_etd_enab) 620 621 #else 622 #define ETD_ENAB(pub) (0) 623 #endif /* WLETD */ 624 625 #endif /* !LANGUAGE_ASSEMBLY */ 626 627 #endif /* _ETD_H_ */ 628