1 /* 2 * Broadcom SDIO/PCMCIA 3 * Software-specific definitions shared between device and host side 4 * 5 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id$ 31 */ 32 33 #ifndef _bcmsdpcm_h_ 34 #define _bcmsdpcm_h_ 35 36 /* 37 * Software allocation of To SB Mailbox resources 38 */ 39 40 /* intstatus bits */ 41 #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ 42 #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ 43 #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ 44 #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ 45 46 #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 47 48 /* tosbmailbox bits corresponding to intstatus bits */ 49 #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ 50 #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ 51 #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ 52 #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ 53 #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ 54 55 /* tosbmailboxdata */ 56 57 #ifdef DS_PROT 58 /* Bit msgs for custom deep sleep protocol */ 59 #define SMB_DATA_D3INFORM 0x100 /* host announcing D3 entry */ 60 #define SMB_DATA_DSACK 0x200 /* host acking a deepsleep request */ 61 #define SMB_DATA_DSNACK 0x400 /* host nacking a deepsleep request */ 62 #endif /* DS_PROT */ 63 /* force a trap */ 64 #define SMB_DATA_TRAP 0x800 /* host forcing trap */ 65 66 #define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */ 67 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */ 68 69 /* 70 * Software allocation of To Host Mailbox resources 71 */ 72 73 /* intstatus bits */ 74 #define I_HMB_INT_ACK I_HMB_SW0 /* To Host Mailbox Dev Interrupt ACK */ 75 #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ 76 #define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ 77 #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ 78 #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ 79 80 #define I_TOHOSTMAIL (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT) 81 82 /* tohostmailbox bits corresponding to intstatus bits */ 83 #define HMB_INT_ACK (1 << 0) /* To Host Mailbox Dev Interrupt ACK */ 84 #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ 85 #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ 86 #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ 87 88 /* tohostmailboxdata */ 89 #define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */ 90 #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */ 91 #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ 92 #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ 93 #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ 94 95 #ifdef DS_PROT 96 /* Bit msgs for custom deep sleep protocol */ 97 #define HMB_DATA_DSREQ 0x100 /* firmware requesting deepsleep entry */ 98 #define HMB_DATA_DSEXIT 0x200 /* firmware announcing deepsleep exit */ 99 #define HMB_DATA_D3ACK 0x400 /* firmware acking a D3 notice from host */ 100 #define HMB_DATA_D3EXIT 0x800 /* firmware announcing D3 exit */ 101 #define HMB_DATA_DSPROT_MASK 0xf00 102 #endif /* DS_PROT */ 103 104 #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ 105 #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 106 107 #define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */ 108 #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */ 109 110 /* 111 * Software-defined protocol header 112 */ 113 114 /* Current protocol version */ 115 #define SDPCM_PROT_VERSION 4 116 117 /* SW frame header */ 118 #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 119 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 120 121 #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 122 #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 123 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 124 125 #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ 126 #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ 127 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 128 129 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */ 130 #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ 131 #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ 132 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ 133 #define SDPCM_NEXTLEN_OFFSET 2 134 135 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 136 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 137 #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 138 #define SDPCM_DOFFSET_MASK 0xff000000 139 #define SDPCM_DOFFSET_SHIFT 24 140 141 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 142 #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff) 143 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 144 #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 145 #define SDPCM_VERSION_OFFSET 6 /* Version # */ 146 #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) 147 #define SDPCM_UNUSED_OFFSET 7 /* Spare */ 148 #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) 149 150 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 151 152 /* logical channel numbers */ 153 #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 154 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 155 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 156 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ 157 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 158 #define SDPCM_MAX_CHANNEL 15 159 160 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */ 161 162 #define SDPCM_FLAG_RESVD0 0x01 163 #define SDPCM_FLAG_RESVD1 0x02 164 #define SDPCM_FLAG_GSPI_TXENAB 0x04 165 #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ 166 167 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ 168 #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) 169 170 #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) 171 172 /* For TEST_CHANNEL packets, define another 4-byte header */ 173 #define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); 174 * Semantics of Ext byte depend on command. 175 * Len is current or requested frame length, not 176 * including test header; sent little-endian. 177 */ 178 #define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */ 179 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 180 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 181 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 182 #define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count 183 * (Backward compatabilty) Set frame count in a 184 * 4 byte filed adjacent to the HDR 185 */ 186 #define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off 187 * Set frame count in a 4 byte filed adjacent to 188 * the HDR 189 */ 190 191 /* Handy macro for filling in datagen packets with a pattern */ 192 #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 193 194 /* 195 * Software counters (first part matches hardware counters) 196 */ 197 198 typedef volatile struct { 199 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 200 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 201 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 202 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 203 uint32 abort; /* AbortCount, SDIO: aborts */ 204 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 205 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 206 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 207 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 208 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 209 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 210 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 211 uint32 rxdescuflo; /* receive descriptor underflows */ 212 uint32 rxfifooflo; /* receive fifo overflows */ 213 uint32 txfifouflo; /* transmit fifo underflows */ 214 uint32 runt; /* runt (too short) frames recv'd from bus */ 215 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 216 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 217 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 218 uint32 rxfcrc; /* frame rx header indicates crc error */ 219 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 220 uint32 rxfwft; /* frame rx header indicates write frame termination */ 221 uint32 rxfabort; /* frame rx header indicates frame aborted */ 222 uint32 woosint; /* write out of sync interrupt */ 223 uint32 roosint; /* read out of sync interrupt */ 224 uint32 rftermint; /* read frame terminate interrupt */ 225 uint32 wftermint; /* write frame terminate interrupt */ 226 } sdpcmd_cnt_t; 227 228 /* 229 * Register Access Macros 230 */ 231 232 #define SDIODREV_IS(var, val) ((var) == (val)) 233 #define SDIODREV_GE(var, val) ((var) >= (val)) 234 #define SDIODREV_GT(var, val) ((var) > (val)) 235 #define SDIODREV_LT(var, val) ((var) < (val)) 236 #define SDIODREV_LE(var, val) ((var) <= (val)) 237 238 #define SDIODDMAREG32(h, dir, chnl) \ 239 ((dir) == DMA_TX ? \ 240 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \ 241 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) 242 243 #define SDIODDMAREG64(h, dir, chnl) \ 244 ((dir) == DMA_TX ? \ 245 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \ 246 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) 247 248 #define SDIODDMAREG(h, dir, chnl) \ 249 (SDIODREV_LT((h)->corerev, 1) ? \ 250 SDIODDMAREG32((h), (dir), (chnl)) : \ 251 SDIODDMAREG64((h), (dir), (chnl))) 252 253 #define PCMDDMAREG(h, dir, chnl) \ 254 ((dir) == DMA_TX ? \ 255 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \ 256 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv)) 257 258 #define SDPCMDMAREG(h, dir, chnl, coreid) \ 259 ((coreid) == SDIOD_CORE_ID ? \ 260 SDIODDMAREG(h, dir, chnl) : \ 261 PCMDDMAREG(h, dir, chnl)) 262 263 #define SDIODFIFOREG(h, corerev) \ 264 (SDIODREV_LT((corerev), 1) ? \ 265 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \ 266 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo))) 267 268 #define PCMDFIFOREG(h) \ 269 ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo)) 270 271 #define SDPCMFIFOREG(h, coreid, corerev) \ 272 ((coreid) == SDIOD_CORE_ID ? \ 273 SDIODFIFOREG(h, corerev) : \ 274 PCMDFIFOREG(h)) 275 276 /* 277 * Shared structure between dongle and the host. 278 * The structure contains pointers to trap or assert information. 279 */ 280 #define SDPCM_SHARED_VERSION 0x0001 281 #define SDPCM_SHARED_VERSION_MASK 0x00FF 282 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 283 #define SDPCM_SHARED_ASSERT 0x0200 284 #define SDPCM_SHARED_TRAP 0x0400 285 #define SDPCM_SHARED_IN_BRPT 0x0800 286 #define SDPCM_SHARED_SET_BRPT 0x1000 287 #define SDPCM_SHARED_PENDING_BRPT 0x2000 288 #define SDPCM_SHARED_FATAL_LOGBUF_VALID 0x100000 289 290 typedef struct { 291 uint32 flags; 292 uint32 trap_addr; 293 uint32 assert_exp_addr; 294 uint32 assert_file_addr; 295 uint32 assert_line; 296 uint32 console_addr; /* Address of hnd_cons_t */ 297 uint32 msgtrace_addr; 298 uint32 fwid; 299 uint32 device_fatal_logbuf_start; 300 uint32 debug_info_addr; /* Address of debug_info area */ 301 } sdpcm_shared_t; 302 303 /* Device F/W provides the following access function: 304 * sdpcm_shared_t *hnd_get_sdpcm_shared(void); 305 */ 306 307 #endif /* _bcmsdpcm_h_ */ 308