1 /* 2 * Broadcom PCIE 3 * Software-specific definitions shared between device and host side 4 * Explains the shared area between host and dongle 5 * 6 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 7 * 8 * Copyright (C) 1999-2017, Broadcom Corporation 9 * 10 * Unless you and Broadcom execute a separate written software license 11 * agreement governing use of this software, this software is licensed to you 12 * under the terms of the GNU General Public License version 2 (the "GPL"), 13 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 14 * following added to such license: 15 * 16 * As a special exception, the copyright holders of this software give you 17 * permission to link this software with independent modules, and to copy and 18 * distribute the resulting executable under terms of your choice, provided that 19 * you also meet, for each linked independent module, the terms and conditions of 20 * the license of that module. An independent module is a module which is not 21 * derived from this software. The special exception does not apply to any 22 * modifications of the software. 23 * 24 * Notwithstanding the above, under no circumstances may you combine this 25 * software in any way with any other Broadcom software provided under a license 26 * other than the GPL, without Broadcom's express prior written consent. 27 * 28 * 29 * <<Broadcom-WL-IPTag/Open:>> 30 * 31 * $Id$ 32 */ 33 34 #ifndef _bcmpcie_h_ 35 #define _bcmpcie_h_ 36 37 #include <typedefs.h> 38 39 #define ADDR_64(x) (x.addr) 40 #define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr)) 41 #define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr)) 42 43 typedef struct { 44 uint32 low_addr; 45 uint32 high_addr; 46 } sh_addr_t; 47 48 /* May be overridden by 43xxxxx-roml.mk */ 49 #if !defined(BCMPCIE_MAX_TX_FLOWS) 50 #define BCMPCIE_MAX_TX_FLOWS 40 51 #endif /* ! BCMPCIE_MAX_TX_FLOWS */ 52 53 #define PCIE_SHARED_VERSION_7 0x00007 54 #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ 55 #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ 56 /** 57 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that 58 * is located in device memory. 59 */ 60 #define PCIE_SHARED_VERSION_MASK 0x000FF 61 #define PCIE_SHARED_ASSERT_BUILT 0x00100 62 #define PCIE_SHARED_ASSERT 0x00200 63 #define PCIE_SHARED_TRAP 0x00400 64 #define PCIE_SHARED_IN_BRPT 0x00800 65 #define PCIE_SHARED_SET_BRPT 0x01000 66 #define PCIE_SHARED_PENDING_BRPT 0x02000 67 /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ 68 #define PCIE_SHARED_EVT_SEQNUM 0x08000 69 #define PCIE_SHARED_DMA_INDEX 0x10000 70 71 /** 72 * There are host types where a device interrupt can 'race ahead' of data written by the device into 73 * host memory. The dongle can avoid this condition using a variety of techniques (read barrier, 74 * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately 75 * these techniques have drawbacks on router platforms. For these platforms, it was decided to not 76 * avoid the condition, but to detect the condition instead and act on it. 77 * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM 78 */ 79 #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 80 #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 81 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ 82 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) 83 #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 84 #define PCIE_SHARED_2BYTE_INDICES 0x100000 85 86 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */ 87 #define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002 88 #define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */ 89 #define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 /* BT/WLAN snapshot upload support */ 90 #define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */ 91 #define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */ 92 #define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */ 93 #define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */ 94 #define PCIE_SHARED_EVENT_BUF_POOL_MAX 0x000000c0 /* event buffer pool max bits */ 95 #define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS 6 /* event buffer pool max bit position */ 96 97 /* dongle supports fatal buf log collection */ 98 #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 99 100 /* Implicit DMA with corerev 19 and after */ 101 #define PCIE_SHARED_IDMA 0x400000 102 103 /* MSI support */ 104 #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 105 106 /* IFRM with corerev 19 and after */ 107 #define PCIE_SHARED_IFRM 0x1000000 108 109 /** 110 * From Rev6 and above, suspend/resume can be done using two handshake methods. 111 * 1. Using ctrl post/ctrl cmpl messages (Default rev6) 112 * 2. Using Mailbox data (old method as used in rev5) 113 * This shared flag indicates whether to overide rev6 default method and use mailbox for 114 * suspend/resume. 115 */ 116 #define PCIE_SHARED_USE_MAILBOX 0x2000000 117 118 /* Firmware compiled for mfgbuild purposes */ 119 #define PCIE_SHARED_MFGBUILD_FW 0x4000000 120 121 /* Firmware could use DB0 value as host timestamp */ 122 #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 123 /* Firmware could use Hostready (IPC rev7) */ 124 #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 125 126 /* When set, Firmwar does not support OOB Device Wake based DS protocol */ 127 #define PCIE_SHARED_NO_OOB_DW 0x20000000 128 129 /* When set, Firmwar supports Inband DS protocol */ 130 #define PCIE_SHARED_INBAND_DS 0x40000000 131 132 /* use DAR registers */ 133 #define PCIE_SHARED_DAR 0x80000000 134 135 /** 136 * Following are the shared2 flags. All bits in flags have been used. A flags2 137 * field got added and the definition for these flags come here: 138 */ 139 /* WAR: D11 txstatus through unused status field of PCIe completion header */ 140 #define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000 141 #define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000 142 143 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 144 145 #define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002 146 147 /* BT logging support */ 148 #define PCIE_SHARED2_BT_LOGGING 0x00000004 149 /* BT/WLAN snapshot upload support */ 150 #define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 151 /* submission count WAR */ 152 #define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 153 154 /* Fast Delete ring support */ 155 #define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 156 157 /* Host SCB support */ 158 #define PCIE_SHARED2_HSCB 0x00000800 159 160 #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 161 #define PCIE_SHARED_H2D_MAGIC 0x12345678 162 163 #define PCIE_SHARED2_PKT_TX_STATUS 0x00000100 /* using flags2 to indicate 164 firmware support added to reuse 165 timesync to update PKT txstatus 166 */ 167 /* Support Enhanced Debug Lane */ 168 #define PCIE_SHARED2_EDL_RING 0x00001000 169 170 /* Timestamp in packet */ 171 #define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 172 173 /* HP2P feature */ 174 #define PCIE_SHARED2_HP2P 0x00010000u 175 176 /** 177 * Message rings convey messages between host and device. They are unidirectional, and are located 178 * in host memory. 179 * 180 * This is the minimal set of message rings, known as 'common message rings': 181 */ 182 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 183 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 184 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 185 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 186 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 187 #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 188 189 #define BCMPCIE_H2D_COMMON_MSGRINGS 2 190 #define BCMPCIE_D2H_COMMON_MSGRINGS 3 191 #define BCMPCIE_COMMON_MSGRINGS 5 192 193 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ 194 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) 195 196 /* different ring types */ 197 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 198 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 199 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 200 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 201 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 202 #define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6 203 204 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 205 #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 206 #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 207 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 208 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 209 #define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6 210 #define BCMPCIE_D2H_RING_TYPE_EDL 0x7 211 #define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8 212 #define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9 213 214 /** 215 * H2D and D2H, WR and RD index, are maintained in the following arrays: 216 * - Array of all H2D WR Indices 217 * - Array of all H2D RD Indices 218 * - Array of all D2H WR Indices 219 * - Array of all D2H RD Indices 220 * 221 * The offset of the WR or RD indexes (for common rings) in these arrays are 222 * listed below. Arrays ARE NOT indexed by a ring's id. 223 * 224 * D2H common rings WR and RD index start from 0, even though their ringids 225 * start from BCMPCIE_H2D_COMMON_MSGRINGS 226 */ 227 228 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) 229 230 enum h2dring_idx { 231 /* H2D common rings */ 232 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 233 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), 234 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 235 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), 236 237 /* First TxPost's WR or RD index starts after all H2D common rings */ 238 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 239 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) 240 }; 241 242 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ 243 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) 244 245 enum d2hring_idx { 246 /* D2H Common Rings */ 247 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 248 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), 249 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 250 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), 251 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 252 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) 253 }; 254 255 /** 256 * Macros for managing arrays of RD WR indices: 257 * rw_index_sz: 258 * - in dongle, rw_index_sz is known at compile time 259 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags 260 * 261 * ring_idx: See h2dring_idx and d2hring_idx 262 */ 263 264 /** Offset of a RD or WR index in H2D or D2H indices array */ 265 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ 266 ((rw_index_sz) * (ring_idx)) 267 268 /** Fetch the address of RD or WR index in H2D or D2H indices array */ 269 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ 270 (void *)((uint32)(indices_array_base) + \ 271 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) 272 273 /** H2D DMA Indices array size: given max flow rings */ 274 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ 275 ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows)) 276 277 /** D2H DMA Indices array size */ 278 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ 279 ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS) 280 281 /** 282 * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used 283 * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated 284 * both in host as well as device memory. 285 */ 286 typedef struct ring_mem { 287 uint16 idx; /* ring id */ 288 uint8 type; 289 uint8 rsvd; 290 uint16 max_item; /* Max number of items in flow ring */ 291 uint16 len_items; /* Items are fixed size. Length in bytes of one item */ 292 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ 293 } ring_mem_t; 294 295 /** 296 * Per flow ring, information is maintained in device memory, eg at what address the ringmem and 297 * ringstate are located. The flow ring itself can be instantiated in either host or device memory. 298 * 299 * Perhaps this type should be renamed to make clear that it resides in device memory only. 300 */ 301 typedef struct ring_info { 302 uint32 ringmem_ptr; /* ring mem location in dongle memory */ 303 304 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not 305 * by a ringid. 306 */ 307 308 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ 309 uint32 h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */ 310 uint32 h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */ 311 uint32 d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */ 312 uint32 d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */ 313 314 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. 315 * Host may directly fetch WR and RD indices from these host-side arrays. 316 * 317 * 64bit ptr to arrays of WR or RD indices for all rings in host memory. 318 */ 319 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ 320 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ 321 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ 322 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ 323 324 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ 325 uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */ 326 uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */ 327 uint16 max_vdevs; /* max number of virtual interfaces supported */ 328 329 sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ 330 } ring_info_t; 331 332 /** 333 * A structure located in TCM that is shared between host and device, primarily used during 334 * initialization. 335 */ 336 typedef struct { 337 /** shared area version captured at flags 7:0 */ 338 uint32 flags; 339 340 uint32 trap_addr; 341 uint32 assert_exp_addr; 342 uint32 assert_file_addr; 343 uint32 assert_line; 344 uint32 console_addr; /**< Address of hnd_cons_t */ 345 346 uint32 msgtrace_addr; 347 348 uint32 fwid; 349 350 /* Used for debug/flow control */ 351 uint16 total_lfrag_pkt_cnt; 352 uint16 max_host_rxbufs; /* rsvd in spec */ 353 354 uint32 dma_rxoffset; /* rsvd in spec */ 355 356 /** these will be used for sleep request/ack, d3 req/ack */ 357 uint32 h2d_mb_data_ptr; 358 uint32 d2h_mb_data_ptr; 359 360 /* information pertinent to host IPC/msgbuf channels */ 361 /** location in the TCM memory which has the ring_info */ 362 uint32 rings_info_ptr; 363 364 /** block of host memory for the scratch buffer */ 365 uint32 host_dma_scratch_buffer_len; 366 sh_addr_t host_dma_scratch_buffer; 367 368 /* location in host memory for scb host offload structures */ 369 sh_addr_t host_scb_addr; 370 uint32 host_scb_size; 371 372 /* anonymous union for overloading fields in structure */ 373 union { 374 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ 375 struct { 376 /* Host provided trap buffer length in words */ 377 uint16 device_trap_debug_buffer_len; 378 uint16 rsvd2; 379 }; 380 }; 381 382 /* rev6 compatible changes */ 383 uint32 flags2; 384 uint32 host_cap; 385 386 /* location in the host address space to write trap indication. 387 * At this point for the current rev of the spec, firmware will 388 * support only indications to 32 bit host addresses. 389 * This essentially is device_trap_debug_buffer_addr 390 */ 391 sh_addr_t host_trap_addr; 392 393 /* location for host fatal error log buffer start address */ 394 uint32 device_fatal_logbuf_start; 395 396 /* location in host memory for offloaded modules */ 397 sh_addr_t hoffload_addr; 398 uint32 debug_info_addr; /* Address of debug_info area */ 399 } pciedev_shared_t; 400 401 /* Device F/W provides the following access function: 402 * pciedev_shared_t *hnd_get_pciedev_shared(void); 403 */ 404 405 /* host capabilities */ 406 #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF 407 #define HOSTCAP_H2D_VALID_PHASE 0x00000100 408 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 409 #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 410 #define HOSTCAP_DB0_TIMESTAMP 0x00000800 411 #define HOSTCAP_DS_NO_OOB_DW 0x00001000 412 #define HOSTCAP_DS_INBAND_DW 0x00002000 413 #define HOSTCAP_H2D_IDMA 0x00004000 414 #define HOSTCAP_H2D_IFRM 0x00008000 415 #define HOSTCAP_H2D_DAR 0x00010000 416 #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 417 #define HOSTCAP_TXSTATUS_METADATA 0x00040000 418 #define HOSTCAP_BT_LOGGING 0x00080000 419 #define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000 420 #define HOSTCAP_FAST_DELETE_RING 0x00200000 421 #define HOSTCAP_PKT_TXSTATUS 0x00400000 422 #define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */ 423 #define HOSTCAP_HSCB 0x02000000 424 /* Host support for extended device trap debug buffer */ 425 #define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000 426 /* Host support for enhanced debug lane */ 427 #define HOSTCAP_EDL_RING 0x10000000 428 #define HOSTCAP_PKT_TIMESTAMP 0x20000000 429 #define HOSTCAP_PKT_HP2P 0x40000000 430 431 /* extended trap debug buffer allocation sizes. Note that this buffer can be used for 432 * other trap related purposes also. 433 */ 434 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u) 435 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u) 436 437 /** 438 * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware 439 * support. 440 */ 441 442 /* H2D mail box Data */ 443 #define H2D_HOST_D3_INFORM 0x00000001 444 #define H2D_HOST_DS_ACK 0x00000002 445 #define H2D_HOST_DS_NAK 0x00000004 446 #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 447 #define H2D_HOST_D0_INFORM 0x00000010 448 #define H2DMB_DS_ACTIVE 0x00000020 449 #define H2DMB_DS_DEVICE_WAKE 0x00000040 450 #define H2D_HOST_IDMA_INITED 0x00000080 451 #define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */ 452 #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ 453 #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ 454 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM 455 #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK 456 #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK 457 #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE 458 #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM 459 #define H2DMB_FW_TRAP H2D_FW_TRAP 460 #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT 461 #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE 462 #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE 463 464 /* D2H mail box Data */ 465 #define D2H_DEV_D3_ACK 0x00000001 466 #define D2H_DEV_DS_ENTER_REQ 0x00000002 467 #define D2H_DEV_DS_EXIT_NOTE 0x00000004 468 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 469 #define D2H_DEV_IDMA_INITED 0x00000010 470 #define D2H_DEV_FWHALT 0x10000000 471 #define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000 472 #define D2H_DEV_EXT_TRAP_DATA 0x20000000 473 #define D2H_DEV_TRAP_IN_TRAP 0x40000000 474 #define D2H_DEV_TRAP_DUE_TO_BT 0x01000000 475 /* Indicates trap due to HMAP violation */ 476 #define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000 477 /* Indicates whether HMAP violation was Write */ 478 #define D2H_DEV_TRAP_HMAP_WRITE 0x04000000 479 480 #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK 481 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ 482 #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE 483 #define D2HMB_FWHALT D2H_DEV_FWHALT 484 #define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP 485 #define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA 486 #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ 487 #define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \ 488 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \ 489 D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA | D2H_DEV_TRAP_IN_TRAP) 490 #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) 491 492 /* Size of Extended Trap data Buffer */ 493 #define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096 494 495 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */ 496 #define PREVTXP(i, d) (((i) == 0) ? ((d) - 1) : ((i) - 1)) 497 #define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1)) 498 #define NEXTNTXP(i, n, d) ((((i)+(n)) >= (d)) ? 0 : ((i)+(n))) 499 #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w))) 500 #define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1) 501 502 /* Function can be used to notify host of FW halt */ 503 #define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r)) 504 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) 505 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) 506 #define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \ 507 (uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \ 508 (uint32)((d) - (w) - 1) : (uint32)((d) - (w)) 509 510 #define CHECK_NOWRITE_SPACE(r, w, d) \ 511 (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1)))) 512 513 #define WRT_PEND(x) ((x)->wr_pending) 514 #define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ 515 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) 516 517 #define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ 518 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) 519 520 #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) 521 522 #define RING_READ_PTR(x) ((x)->ringstate->r_offset) 523 #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) 524 #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) 525 #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) 526 #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) 527 #define HOST_RING_BASE(x) ((x)->dma_buf.va) 528 #define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \ 529 ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x)))) 530 531 /* Trap types copied in the pciedev_shared.trap_addr */ 532 #define FW_INITIATED_TRAP_TYPE (0x1 << 7) 533 #define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6) 534 535 #endif /* _bcmpcie_h_ */ 536