1 /* 2 * Basic types and constants relating to 802.11ax/HE STA 3 * This is a portion of 802.11ax definition. The rest are in 802.11.h. 4 * 5 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id$ 31 */ 32 33 #ifndef _802_11ax_h_ 34 #define _802_11ax_h_ 35 36 #include <typedefs.h> 37 38 /* This marks the start of a packed structure section. */ 39 #include <packed_section_start.h> 40 41 /* special STA-IDs (Section 27.11.1) */ 42 #define HE_STAID_BSS_BCAST 0 43 #define HE_STAID_UNASSOCIATED_STA 2045 44 #define HE_STAID_NO_USER 2046 45 #define HE_STAID_MBSS_BCAST 2047 46 #define HE_STAID_MASK 0x07FF 47 #define HE_AID12_MASK 0x0FFF 48 49 /* Deprecated */ 50 #define HE_STAID_RU_NODATA 2046 51 52 /** 53 * HE Capabilites element (sec 9.4.2.218) 54 */ 55 56 /* HE MAC Capabilities Information field (figure 9-589ck) */ 57 #define HE_MAC_CAP_INFO_SIZE 6 58 typedef uint8 he_mac_cap_t[HE_MAC_CAP_INFO_SIZE]; 59 60 /* bit position and field width */ 61 #define HE_MAC_HTC_HE_SUPPORT_IDX 0 /* HTC HE Support */ 62 #define HE_MAC_HTC_HE_SUPPORT_FSZ 1 63 #define HE_MAC_TWT_REQ_SUPPORT_IDX 1 /* TWT Requestor Support */ 64 #define HE_MAC_TWT_REQ_SUPPORT_FSZ 1 65 #define HE_MAC_TWT_RESP_SUPPORT_IDX 2 /* TWT Responder Support */ 66 #define HE_MAC_TWT_RESP_SUPPORT_FSZ 1 67 #define HE_MAC_FRAG_SUPPORT_IDX 3 /* Fragmentation Support */ 68 #define HE_MAC_FRAG_SUPPORT_FSZ 2 69 #define HE_MAC_MAX_MSDU_AMSDU_FRAGS_IDX 5 /* Max. Fragmented MSDUs/AMSDUs Exponent */ 70 #define HE_MAC_MAX_MSDU_AMSDU_FRAGS_FSZ 3 71 #define HE_MAC_MIN_FRAG_SIZE_IDX 8 /* Min. Fragment Size */ 72 #define HE_MAC_MIN_FRAG_SIZE_FSZ 2 73 #define HE_MAC_TRG_PAD_DUR_IDX 10 /* Trigger Frame MAC Pad Dur */ 74 #define HE_MAC_TRG_PAD_DUR_FSZ 2 75 #define HE_MAC_MULTI_TID_RX_AGG_IDX 12 /* Multi TID RX Aggregation */ 76 #define HE_MAC_MULTI_TID_RX_AGG_FSZ 3 77 #define HE_MAC_LINK_ADAPT_IDX 15 /* HE Link Adaptation */ 78 #define HE_MAC_LINK_ADAPT_FSZ 2 79 #define HE_MAC_ALL_ACK_SUPPORT_IDX 17 /* All Ack Support */ 80 #define HE_MAC_ALL_ACK_SUPPORT_FSZ 1 81 #define HE_MAC_TRS_SUPPORT_IDX 18 /* TRS Support */ 82 #define HE_MAC_TRS_SUPPORT_FSZ 1 83 #define HE_MAC_A_BSR_IDX 19 /* A-BSR Support */ 84 #define HE_MAC_A_BSR_FSZ 1 85 #define HE_MAC_BCAST_TWT_SUPPORT_IDX 20 /* Broadcast TWT Support */ 86 #define HE_MAC_BCAST_TWT_SUPPORT_FSZ 1 87 #define HE_MAC_BA_32BITMAP_SUPPORT_IDX 21 /* 32-bit BA Bitmap Support */ 88 #define HE_MAC_BA_32BITMAP_SUPPORT_FSZ 1 89 #define HE_MAC_MU_CASCADE_SUPPORT_IDX 22 /* MU Cascade Support */ 90 #define HE_MAC_MU_CASCADE_SUPPORT_FSZ 1 91 #define HE_MAC_MULTI_TID_AGG_ACK_IDX 23 /* Ack Enabled Multi TID Agg. */ 92 #define HE_MAC_MULTI_TID_AGG_ACK_FSZ 1 93 #define HE_MAC_RESVD1_IDX 24 /* Reserved Bit */ 94 #define HE_MAC_RESVD1_FSZ 1 95 #define HE_MAC_OMI_ACONTROL_SUPPORT_IDX 25 /* OMI A-Control Support */ 96 #define HE_MAC_OMI_ACONTROL_SUPPORT_FSZ 1 97 #define HE_MAC_OFDMA_RA_SUPPORT_IDX 26 /* OFDMA RA Support */ 98 #define HE_MAC_OFDMA_RA_SUPPORT_FSZ 1 99 #define HE_MAC_MAX_AMPDU_LEN_EXP_EXT_IDX 27 /* Max AMPDU Length Exponent Extention */ 100 #define HE_MAC_MAX_AMPDU_LEN_EXP_EXT_FSZ 2 101 #define HE_MAC_AMSDU_FRAG_SUPPORT_IDX 29 /* AMSDU Fragementation Support */ 102 #define HE_MAC_AMSDU_FRAG_SUPPORT_FSZ 1 103 #define HE_MAC_FLEX_TWT_SCHEDULE_IDX 30 /* Flexible TWT Schedule Support */ 104 #define HE_MAC_FLEX_TWT_SCHEDULE_FSZ 1 105 #define HE_MAC_RX_MBSS_CTL_FRAME_IDX 31 /* Rx of Control frames of MBSS */ 106 #define HE_MAC_RX_MBSS_CTL_FRAME_FSZ 1 107 #define HE_MAC_RX_AGG_BSRP_IDX 32 /* Support Rx of aggregated BSRP BQRP */ 108 #define HE_MAC_RX_AGG_BSRP_FSZ 1 109 #define HE_MAC_QTP_SUPPORT_IDX 33 /* Support Quiet time period */ 110 #define HE_MAC_QTP_SUPPORT_FSZ 1 111 #define HE_MAC_ABQR_SUPPORT_IDX 34 /* Support aggregated BQR */ 112 #define HE_MAC_ABQR_SUPPORT_FSZ 1 113 #define HE_MAC_SRP_RSPNDR_IDX 35 /* SRP responder */ 114 #define HE_MAC_SRP_RSPNDR_FSZ 1 115 #define HE_MAC_NDP_FDBCK_SUPPORT_IDX 36 /* NDP feedback report */ 116 #define HE_MAC_NDP_FDBCK_SUPPORT_FSZ 1 117 #define HE_MAC_OPS_SUPPORT_IDX 37 /* OPS support */ 118 #define HE_MAC_OPS_SUPPORT_FSZ 1 119 #define HE_MAC_AMSDU_IN_AMPDU_IDX 38 /* AMSDU in AMPDU support */ 120 #define HE_MAC_AMSDU_IN_AMPDU_FSZ 1 121 #define HE_MAC_MULTI_TID_TX_AGG_IDX 39 /* Multi TID TX Aggregation */ 122 #define HE_MAC_MULTI_TID_TX_AGG_FSZ 3 123 #define HE_MAC_SUBCH_SEL_TR_SUPPORT_IDX 42 /* HE Subchl Selective Trns Sup */ 124 #define HE_MAC_SUBCH_SEL_TR_SUPPORT_FSZ 1 125 #define HE_MAC_UL_TONE_RU_SUPPORT_IDX 43 /* UL tone RUSupport */ 126 #define HE_MAC_UL_TONE_RU_SUPPORT_FSZ 1 127 #define HE_MAC_OMC_UL_MU_DIS_RX_IDX 44 /* OM Control ULMUData Dis RX Sup */ 128 #define HE_MAC_OMC_UL_MU_DIS_RX_FSZ 1 129 #define HE_MAC_HE_DSMPS_SUPPORT_IDX 45 /* HE Dynamic SM Power Save Sup */ 130 #define HE_MAC_HE_DSMPS_SUPPORT_FSZ 1 131 #define HE_MAC_PUNC_SOUND_SUPPORT_IDX 46 /* Punctured Sounding Sup */ 132 #define HE_MAC_PUNC_SOUND_SUPPORT_FSZ 1 133 #define HE_MAC_NONAX_TFRX_SUPPORT_IDX 47 /* HT and VHT TriggerFrame Rx Sup */ 134 #define HE_MAC_NONAX_TFRX_SUPPORT_FSZ 1 135 136 /* bit position and field width */ 137 #define HE_SU_PPDU_FORMAT_IDX 0 138 #define HE_SU_PPDU_FORMAT_FSZ 1 139 #define HE_SU_PPDU_BEAM_CHANGE_IDX 1 140 #define HE_SU_PPDU_BEAM_CHANGE_FSZ 1 141 #define HE_SU_PPDU_DL_UL_IDX 2 142 #define HE_SU_PPDU_DL_UL_FSZ 1 143 #define HE_SU_PPDU_MCS_IDX 3 144 #define HE_SU_PPDU_MCS_FSZ 4 145 #define HE_SU_PPDU_DCM_IDX 7 146 #define HE_SU_PPDU_DCM_FSZ 1 147 #define HE_SU_PPDU_BSS_COLOR_IDX 8 148 #define HE_SU_PPDU_BSS_COLOR_FSZ 6 149 #define HE_SU_PPDU_SR_IDX 15 150 #define HE_SU_PPDU_SR_FSZ 4 151 #define HE_SU_PPDU_BW_IDX 19 152 #define HE_SU_PPDU_BW_FSZ 2 153 #define HE_SU_PPDU_LTF_IDX 21 154 #define HE_SU_PPDU_LTF_FSZ 2 155 #define HE_SU_PPDU_NSTS_IDX 23 156 #define HE_SU_PPDU_NSTS_FSZ 3 157 #define HE_SU_PPDU_TXOP_IDX 26 158 #define HE_SU_PPDU_TXOP_FSZ 7 159 #define HE_SU_PPDU_CODING_IDX 33 160 #define HE_SU_PPDU_CODING_FSZ 1 161 #define HE_SU_PPDU_LDPC_IDX 34 162 #define HE_SU_PPDU_LDPC_FSZ 1 163 #define HE_SU_PPDU_STBC_IDX 35 164 #define HE_SU_PPDU_STBC_FSZ 1 165 #define HE_SU_PPDU_TXBF_IDX 36 166 #define HE_SU_PPDU_TXBF_FSZ 1 167 168 /* HT Control Field: (Table 9-9a) */ 169 #define HTC_HE_VARIANT 0x3F 170 /* HT Control IDs: (Table 9-18a) */ 171 #define HTC_HE_CTLID_SHIFT 0x2 172 #define HTC_HE_CTLID_TRS 0x0 173 #define HTC_HE_CTLID_OMI 0x1 174 #define HTC_HE_CTLID_HLA 0x2 175 #define HTC_HE_CTLID_BSR 0x3 176 #define HTC_HE_CTLID_UPH 0x4 177 #define HTC_HE_CTLID_BQR 0x5 178 #define HTC_HE_CTLID_CAS 0x6 179 #define HTC_HE_CTLID_NONE 0xF 180 181 #define HE_LTF_1_GI_1_6us (0) 182 #define HE_LTF_2_GI_0_8us (1) 183 #define HE_LTF_2_GI_1_6us (2) 184 #define HE_LTF_4_GI_3_2us (3) 185 186 /* max. # of spacial streams */ 187 #define HE_CAP_MCS_MAP_NSS_MAX 8 188 189 /* HE PHY Capabilities Information field (figure 9-589cl) */ 190 #define HE_PHY_CAP_INFO_SIZE 11 191 typedef uint8 he_phy_cap_t[HE_PHY_CAP_INFO_SIZE]; 192 193 /* PHY Ccapabilites for D3.0 */ 194 #define HE_PHY_RESVD1_IDX 0 /* Reserved */ 195 #define HE_PHY_RESVD1_FSZ 1 196 #define HE_PHY_CH_WIDTH_SET_IDX 1 /* Channel Width Set */ 197 #define HE_PHY_CH_WIDTH_SET_FSZ 7 198 #define HE_PHY_PREAMBLE_PUNCT_RX_IDX 8 /* Preamble Puncturing Rx */ 199 #define HE_PHY_PREAMBLE_PUNCT_RX_FSZ 4 200 #define HE_PHY_DEVICE_CLASS_IDX 12 /* Device Class */ 201 #define HE_PHY_DEVICE_CLASS_FSZ 1 202 #define HE_PHY_LDPC_PYLD_IDX 13 /* LDPC Coding In Payload */ 203 #define HE_PHY_LDPC_PYLD_FSZ 1 204 #define HE_PHY_SU_PPDU_1x_LTF_0_8_GI_IDX 14 /* SU PPDU 1x LTF GI 0.8 us */ 205 #define HE_PHY_SU_PPDU_1x_LTF_0_8_GI_FSZ 1 206 #define HE_PHY_MIDAMBLE_RX_MAX_NSTS_IDX 15 /* Midamble Tx/Rx Max NSTS */ 207 #define HE_PHY_MIDAMBLE_RX_MAX_NSTS_FSZ 2 208 #define HE_PHY_NDP_4x_LTF_3_2_GI_RX_IDX 17 /* NDP with 4xLTF 3.2us GI Rx */ 209 #define HE_PHY_NDP_4x_LTF_3_2_GI_RX_FSZ 1 210 #define HE_PHY_STBC_TX_LESS_EQ_80_IDX 18 /* STBC Tx <= 80 MHz */ 211 #define HE_PHY_STBC_TX_LESS_EQ_80_FSZ 1 212 #define HE_PHY_STBC_RX_LESS_EQ_80_IDX 19 /* STBC Rx <= 80 MHz */ 213 #define HE_PHY_STBC_RX_LESS_EQ_80_FSZ 1 214 #define HE_PHY_DOPPLER_TX_IDX 20 /* Doppler Tx */ 215 #define HE_PHY_DOPPLER_TX_FSZ 1 216 #define HE_PHY_DOPPLER_RX_IDX 21 /* Doppler Rx */ 217 #define HE_PHY_DOPPLER_RX_FSZ 1 218 #define HE_PHY_FULL_BW_UL_MU_IDX 22 /* Full bandwidth UL MU */ 219 #define HE_PHY_FULL_BW_UL_MU_FSZ 1 220 #define HE_PHY_PART_BW_UL_MU_IDX 23 /* Partial bandwidth UL MU */ 221 #define HE_PHY_PART_BW_UL_MU_FSZ 1 222 #define HE_PHY_DCM_MAX_CONST_TX_IDX 24 /* DCM Max constellation */ 223 #define HE_PHY_DCM_MAX_CONST_TX_FSZ 2 224 #define HE_PHY_DCM_NSS_TX_IDX 26 /* DCM Encoding Tx */ 225 #define HE_PHY_DCM_NSS_TX_FSZ 1 226 #define HE_PHY_DCM_MAX_CONST_RX_IDX 27 /* DCM Max constellation */ 227 #define HE_PHY_DCM_MAX_CONST_RX_FSZ 2 228 #define HE_PHY_DCM_NSS_RX_IDX 29 /* DCM Encoding Rx */ 229 #define HE_PHY_DCM_NSS_RX_FSZ 1 230 #define HE_PHY_RX_MUPPDU_NON_AP_STA_IDX 30 /* Rx HE MMPDUE from Non-AP */ 231 #define HE_PHY_RX_MUPPDU_NON_AP_STA_FSZ 1 232 #define HE_PHY_SU_BEAMFORMER_IDX 31 /* SU Beamformer */ 233 #define HE_PHY_SU_BEAMFORMER_FSZ 1 234 #define HE_PHY_SU_BEAMFORMEE_IDX 32 /* SU Beamformee */ 235 #define HE_PHY_SU_BEAMFORMEE_FSZ 1 236 #define HE_PHY_MU_BEAMFORMER_IDX 33 /* MU Beamformer */ 237 #define HE_PHY_MU_BEAMFORMER_FSZ 1 238 #define HE_PHY_BEAMFORMEE_STS_BELOW80MHZ_IDX 34 /* Beamformee STS For <= 80MHz */ 239 #define HE_PHY_BEAMFORMEE_STS_BELOW80MHZ_FSZ 3 240 #define HE_PHY_BEAMFORMEE_STS_ABOVE80MHZ_IDX 37 /* Beamformee STS For >80 MHz */ 241 #define HE_PHY_BEAMFORMEE_STS_ABOVE80MHZ_FSZ 3 242 #define HE_PHY_SOUND_DIM_BELOW80MHZ_IDX 40 /* Num. Sounding Dim.<= 80 MHz */ 243 #define HE_PHY_SOUND_DIM_BELOW80MHZ_FSZ 3 244 #define HE_PHY_SOUND_DIM_ABOVE80MHZ_IDX 43 /* Num. Sounding Dim.> 80 MHz */ 245 #define HE_PHY_SOUND_DIM_ABOVE80MHZ_FSZ 3 246 #define HE_PHY_SU_FEEDBACK_NG16_SUPPORT_IDX 46 /* Ng=16 For SU Feedback */ 247 #define HE_PHY_SU_FEEDBACK_NG16_SUPPORT_FSZ 1 248 #define HE_PHY_MU_FEEDBACK_NG16_SUPPORT_IDX 47 /* Ng=16 For MU Feedback */ 249 #define HE_PHY_MU_FEEDBACK_NG16_SUPPORT_FSZ 1 250 #define HE_PHY_SU_CODEBOOK_SUPPORT_IDX 48 /* Codebook Sz {4, 2} For SU */ 251 #define HE_PHY_SU_CODEBOOK_SUPPORT_FSZ 1 252 #define HE_PHY_MU_CODEBOOK_SUPPORT_IDX 49 /* Codebook Size {7, 5} For MU */ 253 #define HE_PHY_MU_CODEBOOK_SUPPORT_FSZ 1 254 #define HE_PHY_TRG_SU_BFM_FEEDBACK_IDX 50 /* Triggered SU TXBF Feedback */ 255 #define HE_PHY_TRG_SU_BFM_FEEDBACK_FSZ 1 256 #define HE_PHY_TRG_MU_BFM_FEEDBACK_IDX 51 /* Triggered MU TXBF Feedback */ 257 #define HE_PHY_TRG_MU_BFM_FEEDBACK_FSZ 1 258 #define HE_PHY_TRG_CQI_FEEDBACK_IDX 52 /* Triggered CQI Feedback */ 259 #define HE_PHY_TRG_CQI_FEEDBACK_FSZ 1 260 #define HE_PHY_EXT_RANGE_SU_PYLD_IDX 53 /* HE ER SU PPDU Payload */ 261 #define HE_PHY_EXT_RANGE_SU_PYLD_FSZ 1 262 #define HE_PHY_DL_MU_MIMO_PART_BW_IDX 54 /* DL MUMIMO On Partial BW */ 263 #define HE_PHY_DL_MU_MIMO_PART_BW_FSZ 1 264 #define HE_PHY_PPE_THRESH_PRESENT_IDX 55 /* PPE Threshold Present */ 265 #define HE_PHY_PPE_THRESH_PRESENT_FSZ 1 266 #define HE_PHY_SRP_SR_SUPPORT_IDX 56 /* SRP based SR Support */ 267 #define HE_PHY_SRP_SR_SUPPORT_FSZ 1 268 #define HE_PHY_POWER_BOOST_FACTOR_IDX 57 /* Power Boost Factor Support */ 269 #define HE_PHY_POWER_BOOST_FACTOR_FSZ 1 270 #define HE_PHY_LONG_LTF_SHORT_GI_SU_PPDU_IDX 58 /* HE SU - Long LTF Short GI */ 271 #define HE_PHY_LONG_LTF_SHORT_GI_SU_PPDU_FSZ 1 272 #define HE_PHY_MAX_NC_IDX 59 /* Max Nc */ 273 #define HE_PHY_MAX_NC_FSZ 3 274 #define HE_PHY_STBC_GT80_TX_IDX 62 /* STBC Tx > 80 MHz */ 275 #define HE_PHY_STBC_GT80_TX_FSZ 1 276 #define HE_PHY_STBC_GT80_RX_IDX 63 /* STBC Rx > 80 MHz */ 277 #define HE_PHY_STBC_GT80_RX_FSZ 1 278 #define HE_PHY_HE_ER_SU_PPDU_4X_RX_IDX 64 /* HEERSUPPDU With 4x HE-LTF & 0.8 GI */ 279 #define HE_PHY_HE_ER_SU_PPDU_4X_RX_FSZ 1 280 #define HE_PHY_20_40_HE_PPDU_IDX 65 /* 20MHz In 40MHz HEPPDU In 2.4GHz Band */ 281 #define HE_PHY_20_40_HE_PPDU_FSZ 1 282 #define HE_PHY_20_160_HE_PPDU_IDX 66 /* 20MHz In 160/80+80MHz HEPPDU */ 283 #define HE_PHY_20_160_HE_PPDU_FSZ 1 284 #define HE_PHY_80_160_HE_PPDU_IDX 67 /* 80MHz In 160/80+80MHz HEPPDU */ 285 #define HE_PHY_80_160_HE_PPDU_FSZ 1 286 #define HE_PHY_HE_ER_SU_PPDU_IDX 68 /* HEERSUPPDU With 1x HE-LTF & 0.8 GI */ 287 #define HE_PHY_HE_ER_SU_PPDU_FSZ 1 288 #define HE_PHY_MIDAMBLE_TX_RX_2X_1X_HE_LTF_IDX 69 /* Midamble RX 2x & 1x HE LTF */ 289 #define HE_PHY_MIDAMBLE_TX_RX_2X_1X_HE_LTF_FSZ 1 290 #define HE_PHY_DCM_MAX_BW_IDX 70 /* DCM Max BW */ 291 #define HE_PHY_DCM_MAX_BW_FSZ 2 292 #define HE_PHY_SIGB_SYM_GT16_RX_SUPPORT_IDX 72 /* Greater than 16 HESIG-B OFDM Symb Sup */ 293 #define HE_PHY_SIGB_SYM_GT16_RX_SUPPORT_FSZ 1 294 #define HE_PHY_NON_TRIG_CQI_FEEDBACK_IDX 73 /* Non- Triggered CQI Feedback */ 295 #define HE_PHY_NON_TRIG_CQI_FEEDBACK_FSZ 1 296 #define HE_PHY_1024QAM_TX_IN_RU_LT242_IDX 74 /* Tx 1024-QAM < 242-tone RU Support */ 297 #define HE_PHY_1024QAM_TX_IN_RU_LT242_FSZ 1 298 #define HE_PHY_1024QAM_RX_IN_RU_LT242_IDX 75 /* Rx 1024-QAM < 242-tone RU Support */ 299 #define HE_PHY_1024QAM_RX_IN_RU_LT242_FSZ 1 300 #define HE_PHY_RX_HE_MU_COMPR_SIGB_IDX 76 /* RxFull BWSU HEMUPPDU Wt CompSIGB */ 301 #define HE_PHY_RX_HE_MU_COMPR_SIGB_FSZ 1 302 #define HE_PHY_RX_HE_MU_NCOMP_SIGB_IDX 77 /* RxFull BWSU HEMUPPDU wt NCompSIGB */ 303 #define HE_PHY_RX_HE_MU_NCOMP_SIGB_FSZ 1 304 #define HE_PHY_RESVD2_IDX 78 /* Reserved */ 305 #define HE_PHY_RESVD2_FSZ 10 306 307 /* DCM */ 308 #define HE_PHY_CAP_DCM_NOT_SUPP 0x0 309 #define HE_PHY_CAP_DCM_BPSK 0x1 310 #define HE_PHY_CAP_DCM_QPSK 0x2 311 #define HE_PHY_CAP_DCM_16_QAM 0x3 312 #define HE_PHY_CAP_DCM_1SS 0x0 313 #define HE_PHY_CAP_DCM_2SS 0x1 314 315 /* HE Mac Capabilities values */ 316 317 /* b3-b4: Fragmentation Support field (table 9-262z) */ 318 #define HE_MAC_FRAG_NOSUPPORT 0 /* dynamic frag not supported */ 319 #define HE_MAC_FRAG_VHT_MPDU 1 /* Frag support for VHT single MPDU only */ 320 #define HE_MAC_FRAG_ONE_PER_AMPDU 2 /* 1 frag per MPDU in A-MPDU */ 321 #define HE_MAC_FRAG_MULTI_PER_AMPDU 3 /* 2+ frag per MPDU in A-MPDU */ 322 323 /* b8-b9: Minimum payload size of first fragment */ 324 /* no restriction on min. payload size */ 325 #define HE_MAC_MINFRAG_NO_RESTRICT 0 326 /* minimum payload size of 128 Bytes */ 327 #define HE_MAC_MINFRAG_SIZE_128 1 328 /* minimum payload size of 256 Bytes */ 329 #define HE_MAC_MINFRAG_SIZE_256 2 330 /* minimum payload size of 512 Bytes */ 331 #define HE_MAC_MINFRAG_SIZE_512 3 332 333 /* b15-b16: HE Link Adaptation */ 334 #define HE_MAC_SEND_NO_MFB 0 /* if STA does not provide HE MFB */ 335 #define HE_MAC_SEND_UNSOLICATED_MFB 2 /* if STA provides unsolicited HE MFB */ 336 #define HE_MAC_SEND_MFB_IN_RESPONSE 3 /* if STA can provide HE MFB in response to 337 * HE MRQ and if the STA provides unsolicited HE MFB. 338 */ 339 340 /* b27-b28: Max. AMPDU Length HE Exponent */ 341 /* Use Max AMPDU length exponent from VHT or HT */ 342 #define HE_MAC_MAX_AMPDU_EXP_ADOPT_VHT (0) 343 /* Max. AMPDU length = 344 * 2^(20 + MAX_AMPDU_LEN_HE_EXPO_1) -1 (if this value in VHT CAP is 7) or 345 * 2^(16 + MAX_AMPDU_LEN_HE_EXPO_1) -1 (if this value in HT CAP is 7). 346 */ 347 #define HE_MAC_MAX_AMPDU_EXP_HE_1 (1) 348 /* Max. AMPDU length = 349 * 2^(20 + MAX_AMPDU_LEN_HE_EXPO_2) -1 (if this value in VHT CAP is 7) or 350 * 2^(16 + MAX_AMPDU_LEN_HE_EXPO_2) -1 (if this value in HT CAP is 7). 351 */ 352 #define HE_MAC_MAX_AMPDU_EXP_HE_2 (2) 353 354 /* HE PHY Capabilities values */ 355 /* b1-b7: Channel Width Support field */ 356 #define HE_PHY_CH_WIDTH_2G_40 0x01 357 #define HE_PHY_CH_WIDTH_5G_80 0x02 358 #define HE_PHY_CH_WIDTH_6G_40_80 HE_PHY_CH_WIDTH_5G_80 359 #define HE_PHY_CH_WIDTH_5G_160 0x04 360 #define HE_PHY_CH_WIDTH_5G_80P80 0x08 361 #define HE_PHY_CH_WIDTH_2G_40_RU 0x10 362 #define HE_PHY_CH_WIDTH_5G_242_RU 0x20 363 364 /* b8-b11: Preamble puncturing Rx */ 365 #define HE_PHY_PREAMBLE_PUNC_RX_0 0x1 366 #define HE_PHY_PREAMBLE_PUNC_RX_1 0x2 367 #define HE_PHY_PREAMBLE_PUNC_RX_2 0x4 368 #define HE_PHY_PREAMBLE_PUNC_RX_3 0x8 369 370 /* b24-b29: DCM Encoding at Tx and Rx */ 371 #define HE_PHY_TX_DCM_ENC_NOSUPPORT 0x00 372 #define HE_PHY_TX_DCM_ENC_BPSK 0x01 373 #define HE_PHY_TX_DCM_ENC_QPSK 0x02 374 #define HE_PHY_TX_DCM_ENC_QAM 0x03 375 376 #define HE_PHY_TX_DCM_1_SS 0x00 377 #define HE_PHY_TX_DCM_2_SS 0x04 378 379 #define HE_PHY_RX_DCM_ENC_NOSUPPORT 0x00 380 #define HE_PHY_RX_DCM_ENC_BPSK 0x08 381 #define HE_PHY_RX_DCM_ENC_QPSK 0x10 382 #define HE_PHY_RX_DCM_ENC_QAM 0x18 383 384 #define HE_PHY_RX_DCM_1_SS 0x00 385 #define HE_PHY_RX_DCM_2_SS 0x20 386 387 /* HE Duration based RTS Threshold IEEE Draft P802.11ax D1.0 Figure 9-589cr */ 388 #define HE_RTS_THRES_DISABLED 1023 389 #define HE_RTS_THRES_ALL_FRAMES 0 390 #define HE_RTS_THRES_MASK 0x03ff 391 392 /* Tx Rx HE MCS Support field format : IEEE Draft P802.11ax D0.5 Table 9-589cm */ 393 #define HE_TX_RX_MCS_NSS_SUP_FIELD_MIN_SIZE 2 /* 2 bytes (16 bits) */ 394 395 /* Fixed portion of the support field */ 396 #define HE_MCS_NSS_MAX_NSS_M1_IDX 0 397 #define HE_MCS_NSS_MAX_NSS_M1_SZ 3 398 #define HE_MCS_NSS_MAX_MCS_IDX 3 399 #define HE_MCS_NSS_MAX_MCS_SZ 3 400 #define HE_MCS_NSS_TX_BW_BMP_IDX 6 401 #define HE_MCS_NSS_TX_BW_BMP_SZ 5 402 #define HE_MCS_NSS_RX_BW_BMP_IDX 11 403 #define HE_MCS_NSS_RX_BW_BMP_SZ 5 404 405 #define HE_CAP_MASK(idx, sz) (((1 << sz) - 1) << idx) 406 407 /* Descriptor format IEEE Draft P802.11ax_D1.1 Figure 9-589cn */ 408 #define HE_MCS_DESC_IDX 0 409 #define HE_MCS_DESC_SZ 4 410 #define HE_NSS_DESC_IDX 4 411 #define HE_NSS_DESC_SZ 3 412 #define HE_LAST_DESC_IDX 7 413 #define HE_LAST_DESC_SZ 1 414 415 #define HE_GET_DESC_MCS(desc) ((*((const uint8 *)desc) &\ 416 HE_CAP_MASK(HE_MCS_DESC_IDX, HE_MCS_DESC_SZ))\ 417 >> HE_MCS_DESC_IDX) 418 #define HE_GET_DESC_NSS(desc) ((*((const uint8 *)desc) &\ 419 HE_CAP_MASK(HE_NSS_DESC_IDX, HE_NSS_DESC_SZ))\ 420 >> HE_NSS_DESC_IDX) 421 422 /** 423 * Bandwidth configuration indices used in the HE TX-RX MCS support field 424 * IEEE Draft P802.11ax_D1.1 Section 9.4.2.218.4 425 */ 426 #define HE_BW20_CFG_IDX 0 427 #define HE_BW40_CFG_IDX 1 428 #define HE_BW80_CFG_IDX 2 429 #define HE_BW80P80_CFG_IDX 3 430 #define HE_BW160_CFG_IDX 4 431 #define HE_MAX_BW_CFG 5 432 433 #define HE_MCS_CODE_0_7 0u 434 #define HE_MCS_CODE_0_9 1u 435 #define HE_MCS_CODE_0_11 2u 436 #define HE_MCS_CODE_NONE 3u 437 #define HE_MCS_CODE_SIZE 2u /* num bits */ 438 #define HE_MCS_CODE_MASK 0x3u /* mask for 1-stream */ 439 440 /* Defines for The Max HE MCS For n SS subfield (where n = 1, ..., 8) */ 441 #define HE_MCS_MAP_NSS_MAX 8u /* Max number of streams possible */ 442 #define HE_MCS_NSS_SET_MASK 0xffffu /* Field is to be 16 bits long */ 443 #define HE_MCS_NSS_GET_SS_IDX(nss) (((nss)-1u) * HE_MCS_CODE_SIZE) 444 #define HE_MCS_NSS_GET_MCS(nss, mcs_nss_map) \ 445 (((mcs_nss_map) >> HE_MCS_NSS_GET_SS_IDX(nss)) & HE_MCS_CODE_MASK) 446 #define HE_MCS_NSS_SET_MCS(nss, mcs_code, mcs_nss_map) \ 447 do { \ 448 (mcs_nss_map) &= (~(HE_MCS_CODE_MASK << HE_MCS_NSS_GET_SS_IDX(nss))); \ 449 (mcs_nss_map) |= (((mcs_code) & HE_MCS_CODE_MASK) \ 450 << HE_MCS_NSS_GET_SS_IDX(nss)); \ 451 (mcs_nss_map) &= (HE_MCS_NSS_SET_MASK); \ 452 } while (0) 453 454 #define HE_BW80_ORDR_IDX 0u 455 #define HE_BW160_ORDR_IDX 1u 456 #define HE_BW80P80_ORDR_IDX 2u 457 458 #define HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN 2u /* 2 bytes */ 459 #define HE_MCS_NSS_SUP_FLD_UNIT_MAP_SZ (HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN * 8u) /* 16 bits */ 460 461 /* Two unit-maps (TX+RX) */ 462 #define HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN (HE_MCS_NSS_SUP_FLD_UNIT_MAP_LEN * 2u) 463 #define HE_MCS_NSS_SUP_FLD_TXRX_MAP_SZ (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN * 8u) /* 32 bits */ 464 465 /* One TX-RX unit-map (80 MHz) */ 466 #define HE_MCS_NSS_SUP_FLD_MIN_LEN (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN) 467 /* Three TX-RX unit-maps (80 MHz, 160MHz, 80+80MHz) */ 468 #define HE_MCS_NSS_SUP_FLD_MAX_LEN (HE_MCS_NSS_SUP_FLD_TXRX_MAP_LEN * 3u) 469 470 /* HE Capabilities element */ 471 BWL_PRE_PACKED_STRUCT struct he_cap_ie { 472 uint8 id; 473 uint8 len; 474 uint8 id_ext; 475 he_mac_cap_t mac_cap; /* MAC Capabilities Information */ 476 he_phy_cap_t phy_cap; /* PHY Capabilities Information */ 477 /* he_tx_rx_mcs_nss_sup_t txx_rx_mcs_nss_sup; */ /* Tx Rx HE MCS NSS Support (variable) */ 478 /* he_ppe_ths_t ppe_ths; */ /* PPE Thresholds (optional) */ 479 } BWL_POST_PACKED_STRUCT; 480 481 typedef struct he_cap_ie he_cap_ie_t; 482 483 /* Multiple BSSID element */ 484 BWL_PRE_PACKED_STRUCT struct nontrans_BSSID_cap { 485 uint8 id; /* 83 */ 486 uint8 len; 487 uint16 capability; 488 } BWL_POST_PACKED_STRUCT; 489 490 typedef struct nontrans_BSSID_cap nontrans_BSSID_cap_t; 491 492 BWL_PRE_PACKED_STRUCT struct multi_BSSID_index { 493 uint8 id; /* 85 */ 494 uint8 len; /* 3 in beacon, 1 in probe response */ 495 uint8 bssid_index; /* between 1 and 2^n - 1 */ 496 uint8 dtim_period; /* only valid in beacon */ 497 uint8 dtim_count; /* only valid in beacon */ 498 } BWL_POST_PACKED_STRUCT; 499 500 typedef struct multi_BSSID_index multi_BSSID_index_t; 501 502 BWL_PRE_PACKED_STRUCT struct fms_descriptor { 503 uint8 id; /* 86 */ 504 uint8 len; 505 uint8 num_FMS_counters; 506 uint8 *FMS_counters; 507 uint8 *FMSID; 508 } BWL_POST_PACKED_STRUCT; 509 510 typedef struct fms_descriptor fms_descriptor_t; 511 512 BWL_PRE_PACKED_STRUCT struct nontrans_BSSID_profile_subie { 513 uint8 subie_id; /* 0 */ 514 uint8 subie_len; 515 uint8 moreie[1]; 516 } BWL_POST_PACKED_STRUCT; 517 518 typedef struct nontrans_BSSID_profile_subie nontrans_BSSID_profile_subie_t; 519 520 BWL_PRE_PACKED_STRUCT struct multi_BSSID_ie { 521 uint8 id; 522 uint8 len; 523 uint8 maxBSSID_indicator; 524 nontrans_BSSID_profile_subie_t profile[1]; 525 } BWL_POST_PACKED_STRUCT; 526 527 typedef struct multi_BSSID_ie multi_BSSID_ie_t; 528 #define DOT11_MULTIPLE_BSSID_PROFILE_SUBID 0 529 530 /* IEEE Draft P802.11ax D0.5 Table 9-262ab, Highest MCS Supported subfield encoding */ 531 #define HE_CAP_MCS_CODE_0_7 0 532 #define HE_CAP_MCS_CODE_0_8 1 533 #define HE_CAP_MCS_CODE_0_9 2 534 #define HE_CAP_MCS_CODE_0_10 3 535 #define HE_CAP_MCS_CODE_0_11 4 536 #define HE_CAP_MCS_CODE_SIZE 3 /* num bits for 1-stream */ 537 #define HE_CAP_MCS_CODE_MASK 0x7 /* mask for 1-stream */ 538 539 /** 540 * IEEE Draft P802.11ax D0.5 Figure 9-589cm 541 * - Defines for TX & RX BW BITMAP 542 * 543 * (Size of TX BW bitmap = RX BW bitmap = 5 bits) 544 */ 545 #define HE_MCS_NSS_TX_BW_MASK 0x07c0 546 #define HE_MCS_NSS_TX_BW_SHIFT 6 547 548 #define HE_MCS_NSS_RX_BW_MASK 0xf800 549 #define HE_MCS_NSS_RX_BW_SHIFT 11 550 551 #define HE_CAP_MCS_MAP_NSS_MAX 8 /* Max number of streams possible */ 552 553 #define HE_MAX_RU_COUNT 4 /* Max number of RU allocation possible */ 554 555 #define HE_NSSM1_IDX 0 /* Offset of NSSM1 field */ 556 #define HE_NSSM1_LEN 3 /* length of NSSM1 field in bits */ 557 558 #define HE_RU_INDEX_MASK_IDX 3 /* Offset of RU index mask field */ 559 #define HE_RU_INDEX_MASK_LEN 4 /* length of RU Index mask field in bits */ 560 561 /* MU EDCA parameter set element */ 562 BWL_PRE_PACKED_STRUCT struct he_mu_ac_param_record { 563 uint8 aci_aifsn; 564 uint8 ecw_min_max; 565 uint8 muedca_timer; 566 } BWL_POST_PACKED_STRUCT; 567 568 typedef struct he_mu_ac_param_record he_mu_ac_param_record_t; 569 570 BWL_PRE_PACKED_STRUCT struct he_muedca_ie { 571 uint8 id; 572 uint8 len; 573 uint8 id_ext; 574 uint8 mu_qos_info; 575 he_mu_ac_param_record_t param_ac[AC_COUNT]; 576 } BWL_POST_PACKED_STRUCT; 577 578 typedef struct he_muedca_ie he_muedca_ie_t; 579 580 #define HE_MU_EDCA_PARAM_UPD_CNT_IDX 0u /* EDCA Parameter Set Update Count */ 581 #define HE_MU_EDCA_PARAM_UPD_CNT_LEN 4u 582 583 #define HE_MU_SIGA_SIGB_MCS_DPCU 0 584 #define HE_MU_SIGA_SIGB_SYMS_DPCU 3u 585 #define HE_MU_SIGA_GI_LTF_DPCU 3u 586 587 /* For HE SU/RE SIG A : PLCP0 bit fields [32bit] */ 588 #define HE_SU_RE_SIGA_FORMAT_MASK 0x00000001 589 #define HE_SU_RE_SIGA_RE_VAL 0x00000000 590 #define HE_SU_RE_SIGA_SU_VAL 0x00000001 591 #define HE_SU_RE_SIGA_FORMAT_SHIFT 0 592 #define HE_SU_RE_SIGA_UL_DL_SHIFT 2 593 #define HE_SU_RE_SIGA_MCS_MASK 0x00000078 594 #define HE_SU_RE_SIGA_MCS_SHIFT 3 595 #define HE_SU_RE_SIGA_DCM_MASK 0x00000080 596 #define HE_SU_RE_SIGA_DCM_SHIFT 7 597 #define HE_SU_RE_SIGA_BSS_COLOR_SHIFT 8 /* Bits 13:8 */ 598 #define HE_SU_RE_SIGA_BSS_COLOR_MASK 0x00003F00 599 #define HE_SU_RE_SIGA_RSVD_PLCP0_VAL 0x00004000 600 #define HE_SU_SIGA_BW_MASK 0x00180000 601 #define HE_SU_SIGA_BW_SHIFT 19 602 #define HE_RE_SIGA_TONE_MASK 0x00180000 603 #define HE_RE_SIGA_TONE_SHIFT 19 604 #define HE_SU_RE_SIGA_20MHZ_VAL 0x00000000 605 #define HE_SU_RE_SIGA_40MHZ_VAL 0x00080000 606 #define HE_SU_RE_SIGA_80MHZ_VAL 0x00100000 607 #define HE_SU_RE_SIGA_160MHZ_VAL 0x00180000 608 #define HE_SU_RE_SIGA_GI_LTF_MASK 0x00600000 609 #define HE_SU_RE_SIGA_1xLTF_GI8us_VAL 0x00000000 610 #define HE_SU_RE_SIGA_2xLTF_GI8us_VAL 0x00200000 611 #define HE_SU_RE_SIGA_2xLTF_GI16us_VAL 0x00400000 612 #define HE_SU_RE_SIGA_4xLTF_GI32us_VAL 0x00600000 613 #define HE_SU_RE_SIGA_GI_LTF_SHIFT 21 614 #define HE_SU_RE_SIGA_NSTS_MASK 0x03800000 615 #define HE_SU_RE_SIGA_NSTS_SHIFT 23 616 #define HE_SU_RE_SIGA_TXOP_PLCP0_MASK 0xFC000000 617 #define HE_SU_RE_SIGA_TXOP_PLCP0_SHIFT 26 618 619 /* For HE MU SIG A : PLCP0 bit fields [32bit] */ 620 #define HE_MU_SIGA_UL_DL_SHIFT 0 621 #define HE_MU_SIGA_UL_TB_PPDU 0 622 #define HE_MU_SIGA_SIGB_MCS_SHIFT 1 623 #define HE_MU_SIGA_SIGB_DCM_SHIFT 4 624 #define HE_MU_SIGA_SIGB_DCM_DISABLED 0 625 #define HE_MU_SIGA_BW_SHIFT 15 626 #define HE_MU_SIGA_BW_80_UNPUNCTURED 2 627 #define HE_MU_SIGA_BW_SEC_20_PUNCTURED 4 628 #define HE_MU_SIGA_BW_SEC_40_PUNCTURED 5 629 #define HE_MU_SIGA_SIGB_SYMS_SHIFT 18 630 #define HE_MU_SIGA_GI_LTF_SHIFT 23 631 632 /* PLCP1 starts with B6 of HE SIG A 2 */ 633 634 /* For HE SU/RE SIG A : PLCP1 bit fields [16bit] */ 635 #define HE_SU_RE_SIGA_TXOP_PLCP1_MASK 0x0001 636 #define HE_SU_RE_SIGA_TXOP_PLCP1_SHIFT 0 637 #define HE_SU_RE_SIGA_CODING_MASK 0x0002 638 #define HE_SU_RE_SIGA_CODING_SHIFT 1 639 #define HE_SU_RE_SIGA_STBC_MASK 0x0008 640 #define HE_SU_RE_SIGA_STBC_SHIFT 3 641 #define HE_SU_RE_SIGA_BEAMFORM_MASK 0x0010 642 #define HE_SU_RE_SIGA_BEAMFORM_SHIFT 4 643 #define HE_SU_RE_SIGA_RSVD_PLCP1_VAL 0x0100 644 645 /* For HE MU SIG A : PLCP1 bit fields [16bit] */ 646 #define HE_MU_SIGA_RSVD_SHIFT 1 647 #define HE_MU_SIGA_LTF_SYMS_SHIFT 2 648 649 /* PPE Threshold field (figure 9-589co) */ 650 #define HE_PPE_THRESH_NSS_RU_FSZ 3 651 652 /* PPE Threshold Info field (figure 9-589cp) */ 653 /* ruc: RU Count; NSSnM1: NSSn - 1; RUmM1: RUm - 1 */ 654 /* bit offset in PPE Threshold field */ 655 #define HE_PPET16_BIT_OFFSET(ruc, NSSnM1, RUmM1) \ 656 (HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((NSSnM1) * (ruc) + (RUmM1)) * 6) 657 658 #define HE_PPET8_BIT_OFFSET(ruc, NSSnM1, RUmM1) \ 659 (HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((NSSnM1) * (ruc) + (RUmM1)) * 6 + 3) 660 661 /* Total PPE Threshold field byte length (Figure 9-589cq) */ 662 #define HE_PPE_THRESH_LEN(nss, ruc) \ 663 (CEIL((HE_NSSM1_LEN + HE_RU_INDEX_MASK_LEN + ((nss) * (ruc) * 6)), 8)) 664 665 /* RU Allocation Index encoding (table 9-262ae) */ 666 #define HE_RU_ALLOC_IDX_242 0 /* RU alloc: 282 tones */ 667 #define HE_RU_ALLOC_IDX_484 1 /* RU alloc: 484 tones - 40Mhz */ 668 #define HE_RU_ALLOC_IDX_996 2 /* RU alloc: 996 tones - 80Mhz */ 669 #define HE_RU_ALLOC_IDX_2x996 3 /* RU alloc: 2x996 tones - 80p80/160Mhz */ 670 671 /* Constellation Index encoding (table 9-262ac) */ 672 #define HE_CONST_IDX_BPSK 0 673 #define HE_CONST_IDX_QPSK 1 674 #define HE_CONST_IDX_16QAM 2 675 #define HE_CONST_IDX_64QAM 3 676 #define HE_CONST_IDX_256QAM 4 677 #define HE_CONST_IDX_1024QAM 5 678 #define HE_CONST_IDX_RSVD 6 679 #define HE_CONST_IDX_NONE 7 680 681 /* Min HE cap ie length when only 80Mhz is supported */ 682 #define HE_CAP_IE_MIN_LEN (sizeof(he_cap_ie_t) - TLV_HDR_LEN + HE_MCS_NSS_SUP_FLD_MIN_LEN) 683 684 /* Max HE cap ie length considering MAX NSS and RU */ 685 #define HE_CAP_IE_MAX_LEN (sizeof(he_cap_ie_t) - TLV_HDR_LEN + HE_MCS_NSS_SUP_FLD_MAX_LEN + \ 686 HE_PPE_THRESH_LEN(HE_CAP_MCS_MAP_NSS_MAX, HE_MAX_RU_COUNT)) 687 /** 688 * HE Operation IE (sec 9.4.2.219) 689 */ 690 /* HE Operation Parameters field (figure 9-589cr) */ 691 #define HE_OP_PARAMS_SIZE 3 692 typedef uint8 he_op_parms_t[HE_OP_PARAMS_SIZE]; 693 694 #define HE_OP_BSS_COLOR_INFO 1 695 typedef uint8 he_op_bsscolorinfo_t[HE_OP_BSS_COLOR_INFO]; 696 697 #define HE_BASIC_MCS_NSS_SIZE 2 698 typedef uint8 he_basic_mcs_nss_set_t[HE_BASIC_MCS_NSS_SIZE]; 699 700 /* VHT_OP_INFO_LEN = 3 defined in 802.11.h file */ 701 typedef uint8 he_vht_opinfo_t[VHT_OP_INFO_LEN]; 702 703 #define HE_OP_MAX_BSSID_IND_LEN 1 704 typedef uint8 he_max_bssid_ind_t[HE_OP_MAX_BSSID_IND_LEN]; 705 706 /* 6G Operation Information Element field (Figure 9-788k) */ 707 #define HE_6G_OP_INFO 5 708 typedef uint8 he_6g_opinfo_t[HE_6G_OP_INFO]; 709 710 /* HE Operation Parameters for D3.0 */ 711 #define HE_OP_DEFAULT_PE_DUR_IDX 0 /* Default PE Duration */ 712 #define HE_OP_DEFAULT_PE_DUR_FSZ 3 713 #define HE_OP_TWT_REQUIRED_IDX 3 /* TWT Required */ 714 #define HE_OP_TWT_REQUIRED_FSZ 1 715 #define HE_OP_TXOP_DUR_RTS_THOLD_IDX 4 /* TXOP Duration RTS Threshold */ 716 #define HE_OP_TXOP_DUR_RTS_THOLD_FSZ 10 717 #define HE_OP_VHT_OP_INFO_PRESENT_IDX 14 /* VHT Operation Information Present */ 718 #define HE_OP_VHT_OP_INFO_PRESENT_FSZ 1 719 #define HE_OP_CO_LOCATED_BSS_IDX 15 /* Co-Located BSS */ 720 #define HE_OP_CO_LOCATED_BSS_FSZ 1 721 #define HE_OP_ER_SU_DISABLE_IDX 16 /* ER SU Disable */ 722 #define HE_OP_ER_SU_DISABLE_FSZ 1 723 #define HE_OP_6G_OP_INFO_PRESENT_IDX 17 /* 6G Operation Information Present */ 724 #define HE_OP_6G_OP_INFO_PRESENT_FSZ 1 725 #define HE_OP_RESERVED_IDX 18 /* Reserved */ 726 #define HE_OP_RESERVED_FSZ 6 727 728 /* BSS Color for D3.0 */ 729 #define HE_OP_BSS_COLOR_IDX 0 /* BSS Color */ 730 #define HE_OP_BSS_COLOR_FSZ 6 731 #define HE_OP_PARTIAL_BSS_COLOR_IDX 6 /* Partial BSS color */ 732 #define HE_OP_PARTIAL_BSS_COLOR_FSZ 1 733 #define HE_OP_BSS_COLOR_DIS_IDX 7 /* BSS Color Disabled */ 734 #define HE_OP_BSS_COLOR_DIS_FSZ 1 735 736 /* 6 Ghz Operation Information Element for D8.0 */ 737 #define HE_6G_OP_INFO_PRI_CHANNEL_IDX 0 /* Primary channel */ 738 #define HE_6G_OP_INFO_PRI_CHANNEL_FSZ 8 739 #define HE_6G_OP_INFO_CONTROL_IDX 8 /* Control Field */ 740 #define HE_6G_OP_INFO_CONTROL_FSZ 8 741 #define HE_6G_OP_INFO_FREQ_SEG0_IDX 16 /* Center Frequency segment0 */ 742 #define HE_6G_OP_INFO_FREQ_SEG0_FSZ 8 743 #define HE_6G_OP_INFO_FREQ_SEG1_IDX 24 /* Center Frequency segment1 */ 744 #define HE_6G_OP_INFO_FREQ_SEG1_FSZ 8 745 #define HE_6G_OP_INFO_MIN_RATE_IDX 32 /* Min Rate */ 746 #define HE_6G_OP_INFO_MIN_RATE_FSZ 8 747 #define HE_6G_OP_INFO_CONTROL_IDX_CW_FSZ 2 748 749 /* Control Field Format (Figure 9-788I) */ 750 #define HE_6G_CONTROL_CHANNEL_WIDTH_IDX 0 /* Channel Width */ 751 #define HE_6G_CONTROL_CHANNEL_WIDTH_FSZ 2 752 #define HE_6G_CONTROL_DUP_BCN_IDX 2 /* Duplicate beacon */ 753 #define HE_6G_CONTROL_DUP_BCN_FSZ 1 754 #define HE_6G_CONTROL_REG_INFO_IDX 3 /* Regulatory info */ 755 #define HE_6G_CONTROL_REG_INFO_FSZ 3 756 757 /* HE Operation element */ 758 BWL_PRE_PACKED_STRUCT struct he_op_ie { 759 uint8 id; 760 uint8 len; 761 uint8 id_ext; 762 he_op_parms_t parms; 763 he_op_bsscolorinfo_t bsscolorinfo; 764 he_basic_mcs_nss_set_t mcs_nss_op; /* Basic HE MCS & NSS Set */ 765 /* he_vht_opinfo_t vht_opinfo; */ /* VHT Operation Information element */ 766 /* he_max_bssid_ind_t max_bssid_ind; */ /* Max Co-Hosted BSSID Indicator element */ 767 /* he_6g_opinfo_t he_6g_opinfo; */ /* 6 GHz Operation Information element */ 768 } BWL_POST_PACKED_STRUCT; 769 770 typedef struct he_op_ie he_op_ie_t; 771 772 /* The Max HE MCS For n SS subfield (where n = 1, ..., 8) is encoded as follows: 773 * P802.11ax D1.1 P94L53 - P94L61: 774 */ 775 #define HE_OP_MCS_CODE_0_7 0 776 #define HE_OP_MCS_CODE_0_8 1 777 #define HE_OP_MCS_CODE_0_9 2 778 #define HE_OP_MCS_CODE_0_10 3 779 #define HE_OP_MCS_CODE_0_11 4 780 #define HE_OP_MCS_CODE_NONE 7 781 #define HE_OP_MCS_CODE_SIZE 3 /* num bits */ 782 #define HE_OP_MCS_CODE_MASK 0x7 /* mask for 1-stream */ 783 784 /* Defines for The Max HE MCS For n SS subfield (where n = 1, ..., 8) */ 785 #define HE_OP_MCS_NSS_SET_MASK 0x00ffffff /* Field is to be 24 bits long */ 786 #define HE_OP_MCS_NSS_GET_SS_IDX(nss) (((nss)-1) * HE_OP_MCS_CODE_SIZE) 787 #define HE_OP_MCS_NSS_GET_MCS(nss, mcs_nss_map) \ 788 (((mcs_nss_map) >> HE_OP_MCS_NSS_GET_SS_IDX(nss)) & HE_OP_MCS_CODE_MASK) 789 #define HE_OP_MCS_NSS_SET_MCS(nss, mcs_code, mcs_nss_map) \ 790 do { \ 791 (mcs_nss_map) &= (~(HE_OP_MCS_CODE_MASK << HE_OP_MCS_NSS_GET_SS_IDX(nss))); \ 792 (mcs_nss_map) |= (((mcs_code) & HE_OP_MCS_CODE_MASK) \ 793 << HE_OP_MCS_NSS_GET_SS_IDX(nss)); \ 794 (mcs_nss_map) &= (HE_OP_MCS_NSS_SET_MASK); \ 795 } while (0) 796 797 #define HE_OP_IE_MIN_LEN (sizeof(he_op_ie_t) - TLV_HDR_LEN) 798 #define HE_OP_IE_MAX_LEN (sizeof(he_op_ie_t) - TLV_HDR_LEN + VHT_OP_INFO_LEN +\ 799 HE_OP_MAX_BSSID_IND_LEN + HE_6G_OP_INFO) 800 801 /* bit position and field width */ 802 #define HE_BSSCOLOR_CHANGE_NEWCOLOR_IDX 0 /* New BSSColor info */ 803 #define HE_BSSCOLOR_CHANGE_NEWCOLOR_FSZ 6 804 805 /* HE Bsscolor change element */ 806 BWL_PRE_PACKED_STRUCT struct he_bsscolor_change_ie { 807 uint8 id; 808 uint8 len; 809 uint8 id_ext; 810 uint8 color_switch_cntdwn; 811 uint8 new_bsscolor_info; 812 } BWL_POST_PACKED_STRUCT; 813 814 typedef struct he_bsscolor_change_ie he_bsscolor_change_ie_t; 815 816 /* 817 * HE 6 GHz Band Capabilities element (sec 9.4.2.263) 818 * Capabilities Information field format (figure 9-788aj) 819 */ 820 821 #define HE_6GBAND_CAP_IE_SIZE 2 822 typedef uint8 he_6gband_cap_t[HE_6GBAND_CAP_IE_SIZE]; 823 824 /* HE 6 GHz Band Capabilities */ 825 #define HE_6GBAND_MPDU_STRT_SPACE_IDX 0 /* Minimum MPDU Start Spacing */ 826 #define HE_6GBAND_MPDU_STRT_SPACE_FSZ 3 827 #define HE_6GBAND_MAX_AMPDU_LENEXP_IDX 3 /* Maximum A-MPDU Length Exponent */ 828 #define HE_6GBAND_MAX_AMPDU_LENEXP_FSZ 3 829 #define HE_6GBAND_MAX_MPDU_LEN_IDX 6 /* Maximum MPDU Length */ 830 #define HE_6GBAND_MAX_MPDU_LEN_FSZ 2 831 /* B8 is reserved */ 832 #define HE_6GBAND_SM_PWRSAVE_IDX 9 /* SM Power Save */ 833 #define HE_6GBAND_SM_PWRSAVE_FSZ 2 834 #define HE_6GBAND_RD_RESP_IDX 11 /* RD Responder */ 835 #define HE_6GBAND_RD_RESP_FSZ 1 836 #define HE_6GBAND_RXANT_PAT_IDX 12 /* Rx Antenna Pattern Consistency */ 837 #define HE_6GBAND_RXANT_PAT_FSZ 1 838 #define HE_6GBAND_TXANT_PAT_IDX 13 /* Tx Antenna Pattern Consistency */ 839 #define HE_6GBAND_TXANT_PAT_FSZ 1 840 /* B14-15 are reserved */ 841 842 BWL_PRE_PACKED_STRUCT struct he_6gband_cap_ie { 843 uint8 id; 844 uint8 len; 845 uint8 id_ext; 846 he_6gband_cap_t he_6gband_cap; 847 } BWL_POST_PACKED_STRUCT; 848 849 typedef struct he_6gband_cap_ie he_6gband_cap_ie_t; 850 851 /* HE Action Frame */ 852 #define HE_AF_CAT_OFF 0 853 #define HE_AF_ACT_OFF 1 854 855 /* TWT Setup */ 856 #define HE_AF_TWT_SETUP_TOKEN_OFF 2 857 #define HE_AF_TWT_SETUP_TWT_IE_OFF 3 858 859 /* TWT Teardown */ 860 #define HE_AF_TWT_TEARDOWN_FLOW_OFF 2 861 862 /* TWT Information */ 863 #define HE_AF_TWT_INFO_OFF 2 864 865 /* HE Action ID */ 866 #define HE_ACTION_TWT_SETUP 1 867 #define HE_ACTION_TWT_TEARDOWN 2 868 #define HE_ACTION_TWT_INFO 3 869 870 /* HE Basic trigger frame common info fields */ 871 #define HE_TRIG_CMNINFO_SZ 8 872 typedef uint8 he_trig_cmninfo_set_t[HE_TRIG_CMNINFO_SZ]; 873 874 /* bit position and field width */ 875 #define HE_TRIG_CMNINFO_FRMTYPE_INDX 0 /* Trigger frame type */ 876 #define HE_TRIG_CMNINFO_FRMTYPE_FSZ 4 877 #define HE_TRIG_CMNINFO_LSIGLEN_INDX 4 /* L-sig length */ 878 #define HE_TRIG_CMNINFO_LSIGLEN_FSZ 12 879 #define HE_TRIG_CMNINFO_CASCADEIND_INDX 16 /* Cascade indication */ 880 #define HE_TRIG_CMNINFO_CASCADEIND_FSZ 1 881 #define HE_TRIG_CMNINFO_CSREQ_INDX 17 /* Carrier sense indication */ 882 #define HE_TRIG_CMNINFO_CSREQ_FSZ 1 883 #define HE_TRIG_CMNINFO_BWINFO_INDX 18 /* Bw info */ 884 #define HE_TRIG_CMNINFO_BWINFO_FSZ 2 885 #define HE_TRIG_CMNINFO_GI_LTF_INDX 20 /* Cp-LTF size */ 886 #define HE_TRIG_CMNINFO_GI_LTF_FSZ 2 887 #define HE_TRIG_CMNINFO_MUMIMO_LTF_INDX 22 /* HE-LTF mask enable */ 888 #define HE_TRIG_CMNINFO_MUMIMO_LTF_FSZ 1 889 #define HE_TRIG_CMNINFO_HELTF_SYM_INDX 23 /* He-LTF sumbols */ 890 #define HE_TRIG_CMNINFO_HELTF_SYM_FSZ 3 891 #define HE_TRIG_CMNINFO_STBC_INDX 26 /* STBC support */ 892 #define HE_TRIG_CMNINFO_STBC_FSZ 1 893 #define HE_TRIG_CMNINFO_LDPC_EXTSYM_INDX 27 /* LDPC extra symbol */ 894 #define HE_TRIG_CMNINFO_LDPC_EXTSYM_FSZ 1 895 #define HE_TRIG_CMNINFO_AP_TXPWR_INDX 28 /* AP TX power */ 896 #define HE_TRIG_CMNINFO_AP_TXPWR_FSZ 6 897 #define HE_TRIG_CMNINFO_AFACT_INDX 34 /* a-factor */ 898 #define HE_TRIG_CMNINFO_AFACT_FSZ 2 899 #define HE_TRIG_CMNINFO_PEDISAMBIG_INDX 36 /* PE disambiguity */ 900 #define HE_TRIG_CMNINFO_PEDISAMBIG_FSZ 1 901 #define HE_TRIG_CMNINFO_SPTIAL_REUSE_INDX 37 /* spatial re-use */ 902 #define HE_TRIG_CMNINFO_SPTIAL_REUSE_FSZ 16 903 #define HE_TRIG_CMNINFO_DOPPLER_INDX 53 /* doppler supoort */ 904 #define HE_TRIG_CMNINFO_DOPPLER_FSZ 1 905 #define HE_TRIG_CMNINFO_HESIGA_RSVD_INDX 54 /* rsvd bits from HE-SIGA */ 906 #define HE_TRIG_CMNINFO_HESIGA_RSVD_FSZ 9 907 #define HE_TRIG_CMNINFO_RSVD_INDX 63 /* reseved bit from HE-SIGA */ 908 #define HE_TRIG_CMNINFO_RSVD_FSZ 1 909 910 /* HE Basic trigger frame user info fields */ 911 #define HE_TRIG_USRINFO_SZ 5 912 typedef uint8 he_trig_usrinfo_set_t[HE_TRIG_USRINFO_SZ]; 913 914 /* bit position and field width */ 915 #define HE_TRIG_USRINFO_AID_INDX 0 /* AID */ 916 #define HE_TRIG_USRINFO_AID_FSZ 12 917 #define HE_TRIG_USRINFO_RU_ALLOC_INDX 12 /* RU allocation index */ 918 #define HE_TRIG_USRINFO_RU_ALLOC_FSZ 8 919 #define HE_TRIG_USRINFO_CODING_INDX 20 /* coding type (BCC/LDPC) */ 920 #define HE_TRIG_USRINFO_CODING_FSZ 1 921 #define HE_TRIG_USRINFO_MCS_INDX 21 /* MCS index value */ 922 #define HE_TRIG_USRINFO_MCS_FSZ 4 923 #define HE_TRIG_USRINFO_DCM_INDX 25 /* Dual carrier modulation */ 924 #define HE_TRIG_USRINFO_DCM_FSZ 1 925 #define HE_TRIG_USRINFO_SSALLOC_STRMOFFSET_INDX 26 /* stream offset */ 926 #define HE_TRIG_USRINFO_SSALLOC_STRMOFFSET_FSZ 3 927 #define HE_TRIG_USRINFO_SSALLOC_NSS_INDX 29 /* number of spatial streams */ 928 #define HE_TRIG_USRINFO_SSALLOC_NSS_FSZ 3 929 #define HE_TRIG_USRINFO_TARGET_RSSI_INDX 32 /* Target RSSI */ 930 #define HE_TRIG_USRINFO_TARGET_RSSI_FSZ 7 931 #define HE_TRIG_USRINFO_RSVD_INDX 39 /* Reserved bit */ 932 #define HE_TRIG_USRINFO_RSVD_FSZ 1 933 934 /* Different types of trigger frame */ 935 #define HE_TRIG_TYPE_BASIC_FRM 0 /* basic trigger frame */ 936 #define HE_TRIG_TYPE_BEAM_RPT_POLL_FRM 1 /* beamforming report poll frame */ 937 #define HE_TRIG_TYPE_MU_BAR_FRM 2 /* MU-BAR frame */ 938 #define HE_TRIG_TYPE_MU_RTS_FRM 3 /* MU-RTS frame */ 939 #define HE_TRIG_TYPE_BSR_FRM 4 /* Buffer status report poll */ 940 941 /* HE Timing related parameters (802.11ax D1.2 Table 28-9) */ 942 #define HE_T_LEG_STF 8 943 #define HE_T_LEG_LTF 8 944 #define HE_T_LEG_LSIG 4 945 #define HE_T_RL_SIG 4 946 #define HE_T_SIGA 8 947 #define HE_T_STF 4 /* STF for SU / MU HE PPDUs */ 948 #define HE_T_TB_PPDU_STF 8 /* STF for HE trigger based PPDUs */ 949 #define HE_T_LEG_PREAMBLE (HE_T_LEG_STF + HE_T_LEG_LTF + HE_T_LEG_LSIG) 950 #define HE_T_LEG_SYMB 4 951 #define HE_RU_26_TONE 26 952 #define HE_RU_52_TONE 52 953 #define HE_RU_106_TONE 106 954 #define HE_RU_242_TONE 242 955 #define HE_RU_484_TONE 484 956 #define HE_RU_996_TONE 996 957 #define HE_MAX_26_TONE_RU_INDX 36 958 #define HE_MAX_52_TONE_RU_INDX 52 959 #define HE_MAX_106_TONE_RU_INDX 60 960 #define HE_MAX_242_TONE_RU_INDX 64 961 #define HE_MAX_484_TONE_RU_INDX 66 962 963 /** 964 * Ref : (802.11ax D3.0 Figure 9-27 Page 85) 965 */ 966 #define HE_BAR_CONTROL_SZ 2 967 typedef uint8 he_bar_control_set_t[HE_BAR_CONTROL_SZ]; 968 969 /* bit position and field width */ 970 #define HE_BAR_CONTROL_ACK_POLICY_INDX 0 /* BAR ack policy */ 971 #define HE_BAR_CONTROL_ACK_POLICY_FSZ 1 972 #define HE_BAR_CONTROL_ACK_TYPE_INDX 1 /* BAR ack type */ 973 #define HE_BAR_CONTROL_ACK_TYPE_FSZ 4 974 #define HE_BAR_CONTROL_RSVD_INDX 5 /* Reserved */ 975 #define HE_BAR_CONTROL_RSVD_FSZ 7 976 #define HE_BAR_CONTROL_TID_INFO_INDX 12 /* BAR TID INFO */ 977 #define HE_BAR_CONTROL_TID_INFO_FSZ 4 978 979 #define BAR_TYPE_BASIC 0 980 #define BAR_TYPE_EXT_COMPRESSED 1 981 #define BAR_TYPE_COMPRESSED 2 982 #define BAR_TYPE_MULTI_TID 3 983 984 /** 985 * Ref : 802.11-2016.pdf Page 674 986 * Figure 9-28 Block Ack Starting Sequence Control subfield 987 */ 988 #define HE_BAR_INFO_SZ 2 989 typedef uint8 he_cba_bar_info_set_t[HE_BAR_INFO_SZ]; 990 991 /* bit position and field width */ 992 #define HE_CBA_BAR_INFO_FRAGNUM_INDX 0 /* Fragment Number */ 993 #define HE_CBA_BAR_INFO_FRAGNUM_FSZ 4 994 #define HE_CBA_BAR_INFO_SEQNUM_INDX 4 /* Starting Sequence Number */ 995 #define HE_CBA_BAR_INFO_SEQNUM_FSZ 12 996 997 /** 998 * ref: (802.11ax D1.2 Table 28-9 Page 285) 999 * 1000 * - for calculation purpose - in multiples of 10 (*10) 1001 */ 1002 #define HE_T_LTF_1X 32 1003 #define HE_T_LTF_2X 64 1004 #define HE_T_LTF_4X 128 1005 #define HE_T_SYM1 136 /* OFDM symbol duration with base GI */ 1006 #define HE_T_SYM2 144 /* OFDM symbol duration with double GI */ 1007 #define HE_T_SYM4 160 /* OFDM symbol duration with quad GI */ 1008 1009 #define HE_N_LEG_SYM 3 /* bytes per legacy symbol */ 1010 #define HE_N_TAIL 6 /* tail field bits for BCC */ 1011 #define HE_N_SERVICE 16 /* bits in service field */ 1012 #define HE_T_MAX_PE 16 /* max Packet extension duration */ 1013 1014 /* HE Transmit Power Envelope(TPE) IE related */ 1015 1016 /** 1017 * ref: (802.11ax D8.0 Figure 9-617 Page 176) 1018 * 1019 * Transmit Power Information field format 1020 */ 1021 #define HE_TPE_TX_PWR_INFO_COUNT_MASK 0x7 1022 #define HE_TPE_TX_PWR_INFO_COUNT_SHIFT 0 1023 #define HE_TPE_TX_PWR_INFO_INTERPRET_MASK 0x38 1024 #define HE_TPE_TX_PWR_INFO_INTERPRET_SHIFT 3 1025 #define HE_TPE_TX_PWR_INFO_CATEGORY_MASK 0xC0 1026 #define HE_TPE_TX_PWR_INFO_CATEGORY_SHIFT 6 1027 1028 /** 1029 * ref: (802.11ax D8.0 Table 9-275a Page 177) 1030 * 1031 * Maximum Transmit Power Interpretation subfield encoding 1032 */ 1033 #define HE_TPE_MAX_TX_PWR_INTERPRET_LOCAL_EIRP 0 1034 #define HE_TPE_MAX_TX_PWR_INTERPRET_LOCAL_EIRP_PSD 1 1035 #define HE_TPE_MAX_TX_PWR_INTERPRET_REGULATORY_EIRP 2 1036 #define HE_TPE_MAX_TX_PWR_INTERPRET_REGULATORY_EIRP_PSD 3 1037 1038 /** Set Maximum Transmit Power Interpretation on TX PWR INFO field */ 1039 #define HE_TX_PWR_INFO_LOC_EIRP ((HE_TPE_MAX_TX_PWR_INTERPRET_LOCAL_EIRP << \ 1040 HE_TPE_TX_PWR_INFO_INTERPRET_SHIFT) & HE_TPE_TX_PWR_INFO_INTERPRET_MASK) 1041 #define HE_TX_PWR_INFO_LOC_EIRP_PSD ((HE_TPE_MAX_TX_PWR_INTERPRET_LOCAL_EIRP_PSD << \ 1042 HE_TPE_TX_PWR_INFO_INTERPRET_SHIFT) & HE_TPE_TX_PWR_INFO_INTERPRET_MASK) 1043 #define HE_TX_PWR_INFO_REG_EIRP ((HE_TPE_MAX_TX_PWR_INTERPRET_REGULATORY_EIRP << \ 1044 HE_TPE_TX_PWR_INFO_INTERPRET_SHIFT) & HE_TPE_TX_PWR_INFO_INTERPRET_MASK) 1045 #define HE_TX_PWR_INFO_REG_EIRP_PSD ((HE_TPE_MAX_TX_PWR_INTERPRET_REGULATORY_EIRP_PSD << \ 1046 HE_TPE_TX_PWR_INFO_INTERPRET_SHIFT) & HE_TPE_TX_PWR_INFO_INTERPRET_MASK) 1047 1048 /** HE Transmit Power Envelope IE data structure */ 1049 BWL_PRE_PACKED_STRUCT struct he_transmit_power_envelope { 1050 uint8 id; /* id DOT11_MNG_TRANSMIT_POWER_ENVELOPE_ID */ 1051 uint8 len; /* length of IE */ 1052 uint8 transmit_power_info; 1053 union { 1054 uint8 max_transmit_power_20; 1055 uint8 max_transmit_psd_1; 1056 }; 1057 } BWL_POST_PACKED_STRUCT; 1058 typedef struct he_transmit_power_envelope he_transmit_power_envelope_ie_t; 1059 1060 /* This marks the end of a packed structure section. */ 1061 #include <packed_section_end.h> 1062 1063 #endif /* _802_11ax_h_ */ 1064