1 /* 2 * SDIO device core hardware definitions. 3 * sdio is a portion of the pcmcia core in core rev 3 - rev 8 4 * 5 * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode. 6 * 7 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 8 * 9 * Copyright (C) 1999-2017, Broadcom Corporation 10 * 11 * Unless you and Broadcom execute a separate written software license 12 * agreement governing use of this software, this software is licensed to you 13 * under the terms of the GNU General Public License version 2 (the "GPL"), 14 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 15 * following added to such license: 16 * 17 * As a special exception, the copyright holders of this software give you 18 * permission to link this software with independent modules, and to copy and 19 * distribute the resulting executable under terms of your choice, provided that 20 * you also meet, for each linked independent module, the terms and conditions of 21 * the license of that module. An independent module is a module which is not 22 * derived from this software. The special exception does not apply to any 23 * modifications of the software. 24 * 25 * Notwithstanding the above, under no circumstances may you combine this 26 * software in any way with any other Broadcom software provided under a license 27 * other than the GPL, without Broadcom's express prior written consent. 28 * 29 * 30 * <<Broadcom-WL-IPTag/Open:>> 31 * 32 * $Id: sbsdio.h 665717 2016-10-18 23:29:25Z $ 33 */ 34 35 #ifndef _SBSDIO_H 36 #define _SBSDIO_H 37 38 #define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */ 39 40 /* function 1 miscellaneous registers */ 41 #define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */ 42 #define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */ 43 #define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */ 44 #define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */ 45 #define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */ 46 #define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */ 47 #define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */ 48 #define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */ 49 #define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */ 50 #define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ 51 52 /* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */ 53 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */ 54 #define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */ 55 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */ 56 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */ 57 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */ 58 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */ 59 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */ 60 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */ 61 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */ 62 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */ 63 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D /* MesBusyCtl at 0x1001D (rev 11) */ 64 65 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 66 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */ 67 68 /* Sdio Core Rev 12 */ 69 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 70 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 71 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 72 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 73 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 74 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F 75 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 76 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 77 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 78 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 79 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 80 81 /* SBSDIO_SPROM_CS */ 82 #define SBSDIO_SPROM_IDLE 0 83 #define SBSDIO_SPROM_WRITE 1 84 #define SBSDIO_SPROM_READ 2 85 #define SBSDIO_SPROM_WEN 4 86 #define SBSDIO_SPROM_WDS 7 87 #define SBSDIO_SPROM_DONE 8 88 89 /* SBSDIO_SPROM_INFO */ 90 #define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ 91 #define SROM_BLANK 0x04 /* depreciated in corerev 6 */ 92 #define SROM_OTP 0x80 /* OTP present */ 93 94 /* SBSDIO_WATERMARK */ 95 #define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device 96 * to wait before sending data to host 97 */ 98 99 /* SBSDIO_MESBUSYCTRL */ 100 /* When RX FIFO has less entries than this & MBE is set 101 * => busy signal is asserted between data blocks. 102 */ 103 #define SBSDIO_MESBUSYCTRL_MASK 0x7f 104 #define SBSDIO_MESBUSYCTRL_ENAB 0x80 /* Enable busy capability for MES access */ 105 106 /* SBSDIO_DEVICE_CTL */ 107 #define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when 108 * receiving CMD53 109 */ 110 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is 111 * synchronous to the sdio clock 112 */ 113 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host 114 * except the chipActive (rev 8) 115 */ 116 #define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put 117 * external pads in tri-state; requires 118 * sdio bus power cycle to clear (rev 9) 119 */ 120 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10 /* Enable F2 Watermark */ 121 #define SBSDIO_DEVCTL_NONDAT_PADS_ISO 0x20 /* Isolate sdio clk and cmd (non-data) */ 122 #define SBSDIO_DEVCTL_ADDR_RESET 0x40 /* Reset SB Address to default value */ 123 124 /* SBSDIO_FUNC1_CHIPCLKCSR */ 125 #define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ 126 #define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */ 127 #define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */ 128 #define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */ 129 #define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */ 130 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */ 131 #define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */ 132 #define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */ 133 /* In rev8, actual avail bits followed original docs */ 134 #define SBSDIO_Rev8_HT_AVAIL 0x40 135 #define SBSDIO_Rev8_ALP_AVAIL 0x80 136 #define SBSDIO_CSR_MASK 0x1F 137 138 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 139 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 140 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 141 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 142 #define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \ 143 (alponly ? 1 : SBSDIO_HTAV(regval))) 144 145 /* SBSDIO_FUNC1_SDIOPULLUP */ 146 #define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */ 147 #define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */ 148 #define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */ 149 #define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */ 150 #define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */ 151 152 /* function 1 OCP space */ 153 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */ 154 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 155 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */ 156 157 /* some duplication with sbsdpcmdev.h here */ 158 /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ 159 #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ 160 #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ 161 #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ 162 #define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */ 163 164 /* direct(mapped) cis space */ 165 #define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */ 166 #ifdef BCMSPI 167 #define SBSDIO_CIS_SIZE_LIMIT 0x100 /* maximum bytes in one spi CIS */ 168 #else 169 #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */ 170 #endif /* !BCMSPI */ 171 #define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */ 172 173 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */ 174 175 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple, 176 * link bytes 177 */ 178 179 /* indirect cis access (in sprom) */ 180 #define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from 181 * 8th byte 182 */ 183 184 #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one 185 * data comamnd 186 */ 187 188 #define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */ 189 190 #endif /* _SBSDIO_H */ 191