1 /* 2 * MSGBUF network driver ioctl/indication encoding 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Definitions subject to change without notice. 6 * 7 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 8 * 9 * Copyright (C) 1999-2017, Broadcom Corporation 10 * 11 * Unless you and Broadcom execute a separate written software license 12 * agreement governing use of this software, this software is licensed to you 13 * under the terms of the GNU General Public License version 2 (the "GPL"), 14 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 15 * following added to such license: 16 * 17 * As a special exception, the copyright holders of this software give you 18 * permission to link this software with independent modules, and to copy and 19 * distribute the resulting executable under terms of your choice, provided that 20 * you also meet, for each linked independent module, the terms and conditions of 21 * the license of that module. An independent module is a module which is not 22 * derived from this software. The special exception does not apply to any 23 * modifications of the software. 24 * 25 * Notwithstanding the above, under no circumstances may you combine this 26 * software in any way with any other Broadcom software provided under a license 27 * other than the GPL, without Broadcom's express prior written consent. 28 * 29 * 30 * <<Broadcom-WL-IPTag/Open:>> 31 * 32 * $Id$ 33 */ 34 #ifndef _bcmmsgbuf_h_ 35 #define _bcmmsgbuf_h_ 36 37 #include <ethernet.h> 38 #include <wlioctl.h> 39 #include <bcmpcie.h> 40 41 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN 42 43 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */ 44 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1) 45 46 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */ 47 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1) 48 49 #define H2DRING_TXPOST_ITEMSIZE 48 50 #define H2DRING_RXPOST_ITEMSIZE 32 51 #define H2DRING_CTRL_SUB_ITEMSIZE 40 52 53 #define D2HRING_TXCMPLT_ITEMSIZE 24 54 #define D2HRING_RXCMPLT_ITEMSIZE 40 55 56 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16 57 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32 58 59 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24 60 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE 61 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE 62 63 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20 64 65 #define H2DRING_TXPOST_MAX_ITEM 512 66 #define H2DRING_RXPOST_MAX_ITEM 512 67 #define H2DRING_CTRL_SUB_MAX_ITEM 64 68 #define D2HRING_TXCMPLT_MAX_ITEM 1024 69 #define D2HRING_RXCMPLT_MAX_ITEM 512 70 71 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32 72 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32 73 74 #define D2HRING_EDL_HDR_SIZE 48u 75 #define D2HRING_EDL_ITEMSIZE 2048u 76 #define D2HRING_EDL_MAX_ITEM 256u 77 #define D2HRING_EDL_WATERMARK (D2HRING_EDL_MAX_ITEM >> 5u) 78 79 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64 80 81 enum { 82 DNGL_TO_HOST_MSGBUF, 83 HOST_TO_DNGL_MSGBUF 84 }; 85 86 enum { 87 HOST_TO_DNGL_TXP_DATA, 88 HOST_TO_DNGL_RXP_DATA, 89 HOST_TO_DNGL_CTRL, 90 DNGL_TO_HOST_DATA, 91 DNGL_TO_HOST_CTRL 92 }; 93 94 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE 95 #define PCIEDEV_FIRMWARE_TSINFO 0x1 96 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1 97 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2 98 #define PCIEDEV_BTLOG_POST 0x3 99 #define PCIEDEV_BT_SNAPSHOT_POST 0x4 100 101 #ifdef PCIE_API_REV1 102 103 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0) 104 105 #define BCMMSGBUF_API_IFIDX(a) 0 106 #define BCMMSGBUF_API_SEQNUM(a) 0 107 #define BCMMSGBUF_IOCTL_XTID(a) 0 108 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id) 109 110 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b) 111 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b) 112 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b)) 113 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b) 114 115 #else /* PCIE_API_REV1 */ 116 117 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id) 118 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id) 119 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no) 120 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id) 121 122 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b)) 123 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b)) 124 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b)) 125 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b)) 126 127 #endif /* PCIE_API_REV1 */ 128 129 /* utility data structures */ 130 131 union addr64 { 132 struct { 133 uint32 low; 134 uint32 high; 135 }; 136 struct { 137 uint32 low_addr; 138 uint32 high_addr; 139 }; 140 uint64 u64; 141 } DECLSPEC_ALIGN(8); 142 143 typedef union addr64 bcm_addr64_t; 144 145 /* IOCTL req Hdr */ 146 /* cmn Msg Hdr */ 147 typedef struct cmn_msg_hdr { 148 /** message type */ 149 uint8 msg_type; 150 /** interface index this is valid for */ 151 uint8 if_id; 152 /* flags */ 153 uint8 flags; 154 /** sequence number */ 155 uint8 epoch; 156 /** packet Identifier for the associated host buffer */ 157 uint32 request_id; 158 } cmn_msg_hdr_t; 159 160 /** message type */ 161 typedef enum bcmpcie_msgtype { 162 MSG_TYPE_GEN_STATUS = 0x1, 163 MSG_TYPE_RING_STATUS = 0x2, 164 MSG_TYPE_FLOW_RING_CREATE = 0x3, 165 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4, 166 /* Enum value as copied from BISON 7.15: new generic message */ 167 MSG_TYPE_RING_CREATE_CMPLT = 0x4, 168 MSG_TYPE_FLOW_RING_DELETE = 0x5, 169 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6, 170 /* Enum value as copied from BISON 7.15: new generic message */ 171 MSG_TYPE_RING_DELETE_CMPLT = 0x6, 172 MSG_TYPE_FLOW_RING_FLUSH = 0x7, 173 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8, 174 MSG_TYPE_IOCTLPTR_REQ = 0x9, 175 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA, 176 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB, 177 MSG_TYPE_IOCTL_CMPLT = 0xC, 178 MSG_TYPE_EVENT_BUF_POST = 0xD, 179 MSG_TYPE_WL_EVENT = 0xE, 180 MSG_TYPE_TX_POST = 0xF, 181 MSG_TYPE_TX_STATUS = 0x10, 182 MSG_TYPE_RXBUF_POST = 0x11, 183 MSG_TYPE_RX_CMPLT = 0x12, 184 MSG_TYPE_LPBK_DMAXFER = 0x13, 185 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14, 186 MSG_TYPE_FLOW_RING_RESUME = 0x15, 187 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16, 188 MSG_TYPE_FLOW_RING_SUSPEND = 0x17, 189 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18, 190 MSG_TYPE_INFO_BUF_POST = 0x19, 191 MSG_TYPE_INFO_BUF_CMPLT = 0x1A, 192 MSG_TYPE_H2D_RING_CREATE = 0x1B, 193 MSG_TYPE_D2H_RING_CREATE = 0x1C, 194 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D, 195 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E, 196 MSG_TYPE_H2D_RING_CONFIG = 0x1F, 197 MSG_TYPE_D2H_RING_CONFIG = 0x20, 198 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21, 199 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22, 200 MSG_TYPE_H2D_MAILBOX_DATA = 0x23, 201 MSG_TYPE_D2H_MAILBOX_DATA = 0x24, 202 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25, 203 MSG_TYPE_HOSTTIMSTAMP = 0x26, 204 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27, 205 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28, 206 MSG_TYPE_SNAPSHOT_UPLOAD = 0x29, 207 MSG_TYPE_SNAPSHOT_CMPLT = 0x2A, 208 MSG_TYPE_H2D_RING_DELETE = 0x2B, 209 MSG_TYPE_D2H_RING_DELETE = 0x2C, 210 MSG_TYPE_H2D_RING_DELETE_CMPLT = 0x2D, 211 MSG_TYPE_D2H_RING_DELETE_CMPLT = 0x2E, 212 MSG_TYPE_API_MAX_RSVD = 0x3F 213 } bcmpcie_msg_type_t; 214 215 typedef enum bcmpcie_msgtype_int { 216 MSG_TYPE_INTERNAL_USE_START = 0x40, 217 MSG_TYPE_EVENT_PYLD = 0x41, 218 MSG_TYPE_IOCT_PYLD = 0x42, 219 MSG_TYPE_RX_PYLD = 0x43, 220 MSG_TYPE_HOST_FETCH = 0x44, 221 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45, 222 MSG_TYPE_TXMETADATA_PYLD = 0x46, 223 MSG_TYPE_INDX_UPDATE = 0x47, 224 MSG_TYPE_INFO_PYLD = 0x48, 225 MSG_TYPE_TS_EVENT_PYLD = 0x49, 226 MSG_TYPE_PVT_BTLOG_CMPLT = 0x4A, 227 MSG_TYPE_BTLOG_PYLD = 0x4B, 228 MSG_TYPE_HMAPTEST_PYLD = 0x4C, 229 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT = 0x4D, 230 MSG_TYPE_BT_SNAPSHOT_PYLD = 0x4E 231 } bcmpcie_msgtype_int_t; 232 233 typedef enum bcmpcie_msgtype_u { 234 MSG_TYPE_TX_BATCH_POST = 0x80, 235 MSG_TYPE_IOCTL_REQ = 0x81, 236 MSG_TYPE_HOST_EVNT = 0x82, /* console related */ 237 MSG_TYPE_LOOPBACK = 0x83 238 } bcmpcie_msgtype_u_t; 239 240 /** 241 * D2H ring host wakeup soft doorbell, override the PCIE doorbell. 242 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE 243 * Transl0 to write specified value to host address. 244 * 245 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register 246 * and value is Core/Thread context. Host will ensure routing the 32bit address 247 * offerred to PCIE to the mapped register. 248 * 249 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL 250 */ 251 typedef struct bcmpcie_soft_doorbell { 252 uint32 value; /* host defined value to be written, eg HW threadid */ 253 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */ 254 uint16 items; /* interrupt coalescing: item count before wakeup */ 255 uint16 msecs; /* interrupt coalescing: timeout in millisecs */ 256 } bcmpcie_soft_doorbell_t; 257 258 /** 259 * D2H interrupt using MSI instead of INTX 260 * Host configures MSI vector offset for each D2H interrupt 261 * 262 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL 263 */ 264 typedef enum bcmpcie_msi_intr_idx { 265 MSI_INTR_IDX_CTRL_CMPL_RING = 0, 266 MSI_INTR_IDX_TXP_CMPL_RING = 1, 267 MSI_INTR_IDX_RXP_CMPL_RING = 2, 268 MSI_INTR_IDX_INFO_CMPL_RING = 3, 269 MSI_INTR_IDX_MAILBOX = 4, 270 MSI_INTR_IDX_MAX = 5 271 } bcmpcie_msi_intr_idx_t; 272 273 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0 274 typedef enum bcmpcie_msi_offset_type { 275 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2, 276 BCMPCIE_D2H_MSI_OFFSET_MB1 = 3, 277 BCMPCIE_D2H_MSI_OFFSET_DB0 = 4, 278 BCMPCIE_D2H_MSI_OFFSET_DB1 = 5, 279 BCMPCIE_D2H_MSI_OFFSET_H1_DB0 = 6, 280 BCMPCIE_D2H_MSI_OFFSET_MAX = 7 281 } bcmpcie_msi_offset_type_t; 282 283 typedef struct bcmpcie_msi_offset { 284 uint16 intr_idx; /* interrupt index */ 285 uint16 msi_offset; /* msi vector offset */ 286 } bcmpcie_msi_offset_t; 287 288 typedef struct bcmpcie_msi_offset_config { 289 uint32 len; 290 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX]; 291 } bcmpcie_msi_offset_config_t; 292 293 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1 294 295 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE 296 297 /* if_id */ 298 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5 299 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7 300 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \ 301 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 302 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0 303 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F 304 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \ 305 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 306 307 /* flags */ 308 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1 309 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2 310 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4 311 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80 312 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80 313 314 /* IOCTL request message */ 315 typedef struct ioctl_req_msg { 316 /** common message header */ 317 cmn_msg_hdr_t cmn_hdr; 318 /** ioctl command type */ 319 uint32 cmd; 320 /** ioctl transaction ID, to pair with a ioctl response */ 321 uint16 trans_id; 322 /** input arguments buffer len */ 323 uint16 input_buf_len; 324 /** expected output len */ 325 uint16 output_buf_len; 326 /** to align the host address on 8 byte boundary */ 327 uint16 rsvd[3]; 328 /** always align on 8 byte boundary */ 329 bcm_addr64_t host_input_buf_addr; 330 /* rsvd */ 331 uint32 rsvd1[2]; 332 } ioctl_req_msg_t; 333 334 /** buffer post messages for device to use to return IOCTL responses, Events */ 335 typedef struct ioctl_resp_evt_buf_post_msg { 336 /** common message header */ 337 cmn_msg_hdr_t cmn_hdr; 338 /** length of the host buffer supplied */ 339 uint16 host_buf_len; 340 /** to align the host address on 8 byte boundary */ 341 uint16 reserved[3]; 342 /** always align on 8 byte boundary */ 343 bcm_addr64_t host_buf_addr; 344 uint32 rsvd[4]; 345 } ioctl_resp_evt_buf_post_msg_t; 346 347 /* buffer post messages for device to use to return dbg buffers */ 348 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t; 349 350 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024) 351 352 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024) 353 354 /* An infobuf host buffer starts with a 32 bit (LE) version. */ 355 #define PCIE_INFOBUF_V1 1 356 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that 357 * is wrapped previously/also in a WLC_E_TRACE event. See structure 358 * msgrace_hdr_t in msgtrace.h. 359 */ 360 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1 361 362 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that 363 * is wrapped previously/also in a WLC_E_TRACE event. See structure 364 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE 365 * and a LOGTRACE is the "trace type" field.) 366 */ 367 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2 368 369 /* An infobuf version 1 host buffer has a single TLV. The information on the 370 * version 1 types follow this structure definition. (int's LE) 371 */ 372 typedef struct info_buf_payload_hdr_s { 373 uint16 type; 374 uint16 length; 375 } info_buf_payload_hdr_t; 376 377 /* BT logs/memory to DMA directly from BT memory to host */ 378 typedef struct info_buf_btlog_s { 379 void (*status_cb)(void *ctx, void *p, int error); /* obsolete - to be removed */ 380 void *ctx; 381 dma64addr_t src_addr; 382 uint32 length; 383 bool (*pcie_status_cb)(osl_t *osh, void *p, int error); 384 uint32 bt_intstatus; 385 int error; 386 } info_buf_btlog_t; 387 388 /** snapshot upload request message */ 389 typedef struct snapshot_upload_request_msg { 390 /** common message header */ 391 cmn_msg_hdr_t cmn_hdr; 392 /** length of the snaphost buffer supplied */ 393 uint32 snapshot_buf_len; 394 /** type of snapshot */ 395 uint8 snapshot_type; 396 /** snapshot param */ 397 uint8 snapshot_param; 398 /** to align the host address on 8 byte boundary */ 399 uint8 reserved[2]; 400 /** always align on 8 byte boundary */ 401 bcm_addr64_t host_buf_addr; 402 uint32 rsvd[4]; 403 } snapshot_upload_request_msg_t; 404 405 /** snapshot types */ 406 typedef enum bcmpcie_snapshot_type { 407 SNAPSHOT_TYPE_BT = 0, /* Bluetooth SRAM and patch RAM */ 408 SNAPSHOT_TYPE_WLAN_SOCRAM = 1, /* WLAN SOCRAM */ 409 SNAPSHOT_TYPE_WLAN_HEAP = 2, /* WLAN HEAP */ 410 SNAPSHOT_TYPE_WLAN_REGISTER = 3 /* WLAN registers */ 411 } bcmpcie_snapshot_type_t; 412 413 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF 414 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2 415 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3 416 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0 417 418 typedef struct pcie_dma_xfer_params { 419 /** common message header */ 420 cmn_msg_hdr_t cmn_hdr; 421 422 /** always align on 8 byte boundary */ 423 bcm_addr64_t host_input_buf_addr; 424 425 /** always align on 8 byte boundary */ 426 bcm_addr64_t host_ouput_buf_addr; 427 428 /** length of transfer */ 429 uint32 xfer_len; 430 /** delay before doing the src txfer */ 431 uint32 srcdelay; 432 /** delay before doing the dest txfer */ 433 uint32 destdelay; 434 uint8 rsvd[3]; 435 /* bit0: D11 DMA loopback flag */ 436 uint8 flags; 437 } pcie_dma_xfer_params_t; 438 439 #define BCMPCIE_FLOW_RING_INTF_HP2P 0x1 440 /** Complete msgbuf hdr for flow ring update from host to dongle */ 441 typedef struct tx_flowring_create_request { 442 cmn_msg_hdr_t msg; 443 uint8 da[ETHER_ADDR_LEN]; 444 uint8 sa[ETHER_ADDR_LEN]; 445 uint8 tid; 446 uint8 if_flags; 447 uint16 flow_ring_id; 448 uint8 tc; 449 /* priority_ifrmmask is to define core mask in ifrm mode. 450 * currently it is not used for priority. so uses solely for ifrm mask 451 */ 452 uint8 priority_ifrmmask; 453 uint16 int_vector; 454 uint16 max_items; 455 uint16 len_item; 456 bcm_addr64_t flow_ring_ptr; 457 } tx_flowring_create_request_t; 458 459 typedef struct tx_flowring_delete_request { 460 cmn_msg_hdr_t msg; 461 uint16 flow_ring_id; 462 uint16 reason; 463 uint32 rsvd[7]; 464 } tx_flowring_delete_request_t; 465 466 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t; 467 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t; 468 469 typedef struct tx_flowring_flush_request { 470 cmn_msg_hdr_t msg; 471 uint16 flow_ring_id; 472 uint16 reason; 473 uint32 rsvd[7]; 474 } tx_flowring_flush_request_t; 475 476 /** Subtypes for ring_config_req control message */ 477 typedef enum ring_config_subtype { 478 /** Default D2H PCIE doorbell override using ring_config_req msg */ 479 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */ 480 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */ 481 } ring_config_subtype_t; 482 483 typedef struct ring_config_req { 484 cmn_msg_hdr_t msg; 485 uint16 subtype; 486 uint16 ring_id; 487 uint32 rsvd; 488 union { 489 uint32 data[6]; 490 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */ 491 bcmpcie_soft_doorbell_t soft_doorbell; 492 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */ 493 bcmpcie_msi_offset_config_t msi_offset; 494 }; 495 } ring_config_req_t; 496 497 /* data structure to use to create on the fly d2h rings */ 498 typedef struct d2h_ring_create_req { 499 cmn_msg_hdr_t msg; 500 uint16 ring_id; 501 uint16 ring_type; 502 uint32 flags; 503 bcm_addr64_t ring_ptr; 504 uint16 max_items; 505 uint16 len_item; 506 uint32 rsvd[3]; 507 } d2h_ring_create_req_t; 508 509 /* data structure to use to create on the fly h2d rings */ 510 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4 511 typedef struct h2d_ring_create_req { 512 cmn_msg_hdr_t msg; 513 uint16 ring_id; 514 uint8 ring_type; 515 uint8 n_completion_ids; 516 uint32 flags; 517 bcm_addr64_t ring_ptr; 518 uint16 max_items; 519 uint16 len_item; 520 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED]; 521 uint32 rsvd; 522 } h2d_ring_create_req_t; 523 524 typedef struct d2h_ring_config_req { 525 cmn_msg_hdr_t msg; 526 uint16 d2h_ring_config_subtype; 527 uint16 d2h_ring_id; 528 uint32 d2h_ring_config_data[4]; 529 uint32 rsvd[3]; 530 } d2h_ring_config_req_t; 531 532 typedef struct h2d_ring_config_req { 533 cmn_msg_hdr_t msg; 534 uint16 h2d_ring_config_subtype; 535 uint16 h2d_ring_id; 536 uint32 h2d_ring_config_data; 537 uint32 rsvd[6]; 538 } h2d_ring_config_req_t; 539 540 typedef struct h2d_mailbox_data { 541 cmn_msg_hdr_t msg; 542 uint32 mail_box_data; 543 uint32 rsvd[7]; 544 } h2d_mailbox_data_t; 545 typedef struct host_timestamp_msg { 546 cmn_msg_hdr_t msg; 547 uint16 xt_id; /* transaction ID */ 548 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */ 549 uint16 seqnum; /* number of times host captured the timestamp */ 550 uint16 rsvd; 551 /* always align on 8 byte boundary */ 552 bcm_addr64_t host_buf_addr; 553 /* rsvd */ 554 uint32 rsvd1[4]; 555 } host_timestamp_msg_t; 556 557 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */ 558 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t; 559 560 typedef union ctrl_submit_item { 561 ioctl_req_msg_t ioctl_req; 562 ioctl_resp_evt_buf_post_msg_t resp_buf_post; 563 pcie_dma_xfer_params_t dma_xfer; 564 tx_flowring_create_request_t flow_create; 565 tx_flowring_delete_request_t flow_delete; 566 tx_flowring_flush_request_t flow_flush; 567 ring_config_req_t ring_config_req; 568 d2h_ring_create_req_t d2h_create; 569 h2d_ring_create_req_t h2d_create; 570 d2h_ring_config_req_t d2h_config; 571 h2d_ring_config_req_t h2d_config; 572 h2d_mailbox_data_t h2d_mailbox_data; 573 host_timestamp_msg_t host_ts; 574 ts_buf_post_msg_t ts_buf_post; 575 d2h_ring_delete_req_t d2h_delete; 576 h2d_ring_delete_req_t h2d_delete; 577 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE]; 578 } ctrl_submit_item_t; 579 580 typedef struct info_ring_submit_item { 581 info_buf_post_msg_t info_buf_post; 582 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE]; 583 } info_sumbit_item_t; 584 585 /** Control Completion messages (20 bytes) */ 586 typedef struct compl_msg_hdr { 587 /** status for the completion */ 588 int16 status; 589 /** submisison flow ring id which generated this status */ 590 union { 591 uint16 ring_id; 592 uint16 flow_ring_id; 593 }; 594 } compl_msg_hdr_t; 595 596 /** XOR checksum or a magic number to audit DMA done */ 597 typedef uint32 dma_done_t; 598 599 #define MAX_CLKSRC_ID 0xF 600 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF 601 #define TX_PKT_RETRY_CNT_0_SHIFT 0 602 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00 603 #define TX_PKT_RETRY_CNT_1_SHIFT 8 604 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000 605 #define TX_PKT_RETRY_CNT_2_SHIFT 16 606 #define TX_PKT_BAND_INFO 0x0F000000 607 #define TX_PKT_BAND_INFO_SHIFT 24 608 #define TX_PKT_VALID_INFO 0xF0000000 609 #define TX_PKT_VALID_INFO_SHIFT 28 610 611 typedef struct ts_timestamp_srcid { 612 union { 613 uint32 ts_low; /* time stamp low 32 bits */ 614 uint32 rate_spec; /* use ratespec */ 615 }; 616 union { 617 uint32 ts_high; /* time stamp high 28 bits */ 618 union { 619 uint32 ts_high_ext :28; /* time stamp high 28 bits */ 620 uint32 clk_id_ext :3; /* clock ID source */ 621 uint32 phase :1; /* Phase bit */ 622 dma_done_t marker_ext; 623 }; 624 uint32 tx_pkt_band_retry_info; 625 }; 626 } ts_timestamp_srcid_t; 627 628 typedef ts_timestamp_srcid_t ipc_timestamp_t; 629 630 typedef struct ts_timestamp { 631 uint32 low; 632 uint32 high; 633 } ts_timestamp_t; 634 635 typedef ts_timestamp_t tick_count_64_t; 636 typedef ts_timestamp_t ts_timestamp_ns_64_t; 637 typedef ts_timestamp_t ts_correction_m_t; 638 typedef ts_timestamp_t ts_correction_b_t; 639 640 /* completion header status codes */ 641 #define BCMPCIE_SUCCESS 0 642 #define BCMPCIE_NOTFOUND 1 643 #define BCMPCIE_NOMEM 2 644 #define BCMPCIE_BADOPTION 3 645 #define BCMPCIE_RING_IN_USE 4 646 #define BCMPCIE_RING_ID_INVALID 5 647 #define BCMPCIE_PKT_FLUSH 6 648 #define BCMPCIE_NO_EVENT_BUF 7 649 #define BCMPCIE_NO_RX_BUF 8 650 #define BCMPCIE_NO_IOCTLRESP_BUF 9 651 #define BCMPCIE_MAX_IOCTLRESP_BUF 10 652 #define BCMPCIE_MAX_EVENT_BUF 11 653 #define BCMPCIE_BAD_PHASE 12 654 #define BCMPCIE_INVALID_CPL_RINGID 13 655 #define BCMPCIE_RING_TYPE_INVALID 14 656 #define BCMPCIE_NO_TS_EVENT_BUF 15 657 #define BCMPCIE_MAX_TS_EVENT_BUF 16 658 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17 659 #define BCMPCIE_BT_DMA_ERR 18 660 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19 661 #define BCMPCIE_SNAPSHOT_ERR 20 662 #define BCMPCIE_NOT_READY 21 663 #define BCMPCIE_INVALID_DATA 22 664 #define BCMPCIE_NO_RESPONSE 23 665 #define BCMPCIE_NO_CLOCK 24 666 667 /** IOCTL completion response */ 668 typedef struct ioctl_compl_resp_msg { 669 /** common message header */ 670 cmn_msg_hdr_t cmn_hdr; 671 /** completion message header */ 672 compl_msg_hdr_t compl_hdr; 673 /** response buffer len where a host buffer is involved */ 674 uint16 resp_len; 675 /** transaction id to pair with a request */ 676 uint16 trans_id; 677 /** cmd id */ 678 uint32 cmd; 679 /** XOR checksum or a magic number to audit DMA done */ 680 dma_done_t marker; 681 } ioctl_comp_resp_msg_t; 682 683 /** IOCTL request acknowledgement */ 684 typedef struct ioctl_req_ack_msg { 685 /** common message header */ 686 cmn_msg_hdr_t cmn_hdr; 687 /** completion message header */ 688 compl_msg_hdr_t compl_hdr; 689 /** cmd id */ 690 uint32 cmd; 691 uint32 rsvd; 692 /** XOR checksum or a magic number to audit DMA done */ 693 dma_done_t marker; 694 } ioctl_req_ack_msg_t; 695 696 /** WL event message: send from device to host */ 697 typedef struct wlevent_req_msg { 698 /** common message header */ 699 cmn_msg_hdr_t cmn_hdr; 700 /** completion message header */ 701 compl_msg_hdr_t compl_hdr; 702 /** event data len valid with the event buffer */ 703 uint16 event_data_len; 704 /** sequence number */ 705 uint16 seqnum; 706 /** rsvd */ 707 uint32 rsvd; 708 /** XOR checksum or a magic number to audit DMA done */ 709 dma_done_t marker; 710 } wlevent_req_msg_t; 711 712 /** dma xfer complete message */ 713 typedef struct pcie_dmaxfer_cmplt { 714 /** common message header */ 715 cmn_msg_hdr_t cmn_hdr; 716 /** completion message header */ 717 compl_msg_hdr_t compl_hdr; 718 uint32 rsvd[2]; 719 /** XOR checksum or a magic number to audit DMA done */ 720 dma_done_t marker; 721 } pcie_dmaxfer_cmplt_t; 722 723 /** general status message */ 724 typedef struct pcie_gen_status { 725 /** common message header */ 726 cmn_msg_hdr_t cmn_hdr; 727 /** completion message header */ 728 compl_msg_hdr_t compl_hdr; 729 uint32 rsvd[2]; 730 /** XOR checksum or a magic number to audit DMA done */ 731 dma_done_t marker; 732 } pcie_gen_status_t; 733 734 /** ring status message */ 735 typedef struct pcie_ring_status { 736 /** common message header */ 737 cmn_msg_hdr_t cmn_hdr; 738 /** completion message header */ 739 compl_msg_hdr_t compl_hdr; 740 /** message which firmware couldn't decode */ 741 uint16 write_idx; 742 uint16 rsvd[3]; 743 /** XOR checksum or a magic number to audit DMA done */ 744 dma_done_t marker; 745 } pcie_ring_status_t; 746 747 typedef struct ring_create_response { 748 cmn_msg_hdr_t cmn_hdr; 749 compl_msg_hdr_t cmplt; 750 uint32 rsvd[2]; 751 /** XOR checksum or a magic number to audit DMA done */ 752 dma_done_t marker; 753 } ring_create_response_t; 754 755 typedef ring_create_response_t tx_flowring_create_response_t; 756 typedef ring_create_response_t h2d_ring_create_response_t; 757 typedef ring_create_response_t d2h_ring_create_response_t; 758 759 typedef struct tx_flowring_delete_response { 760 cmn_msg_hdr_t msg; 761 compl_msg_hdr_t cmplt; 762 uint16 read_idx; 763 uint16 rsvd[3]; 764 /** XOR checksum or a magic number to audit DMA done */ 765 dma_done_t marker; 766 } tx_flowring_delete_response_t; 767 768 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t; 769 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t; 770 771 typedef struct tx_flowring_flush_response { 772 cmn_msg_hdr_t msg; 773 compl_msg_hdr_t cmplt; 774 uint32 rsvd[2]; 775 /** XOR checksum or a magic number to audit DMA done */ 776 dma_done_t marker; 777 } tx_flowring_flush_response_t; 778 779 /** Common layout of all d2h control messages */ 780 typedef struct ctrl_compl_msg { 781 /** common message header */ 782 cmn_msg_hdr_t cmn_hdr; 783 /** completion message header */ 784 compl_msg_hdr_t compl_hdr; 785 uint32 rsvd[2]; 786 /** XOR checksum or a magic number to audit DMA done */ 787 dma_done_t marker; 788 } ctrl_compl_msg_t; 789 790 typedef struct ring_config_resp { 791 /** common message header */ 792 cmn_msg_hdr_t cmn_hdr; 793 /** completion message header */ 794 compl_msg_hdr_t compl_hdr; 795 uint16 subtype; 796 uint16 rsvd[3]; 797 /** XOR checksum or a magic number to audit DMA done */ 798 dma_done_t marker; 799 } ring_config_resp_t; 800 801 typedef struct d2h_mailbox_data { 802 cmn_msg_hdr_t msg; 803 compl_msg_hdr_t cmplt; 804 uint32 d2h_mailbox_data; 805 uint32 rsvd[1]; 806 /* XOR checksum or a magic number to audit DMA done */ 807 dma_done_t marker; 808 } d2h_mailbox_data_t; 809 810 /* dbg buf completion msg: send from device to host */ 811 typedef struct info_buf_resp { 812 /* common message header */ 813 cmn_msg_hdr_t cmn_hdr; 814 /* completion message header */ 815 compl_msg_hdr_t compl_hdr; 816 /* event data len valid with the event buffer */ 817 uint16 info_data_len; 818 /* sequence number */ 819 uint16 seqnum; 820 /* destination */ 821 uint8 dest; 822 /* rsvd */ 823 uint8 rsvd[3]; 824 /* XOR checksum or a magic number to audit DMA done */ 825 dma_done_t marker; 826 } info_buf_resp_t; 827 828 /* snapshot completion msg: send from device to host */ 829 typedef struct snapshot_resp { 830 /* common message header */ 831 cmn_msg_hdr_t cmn_hdr; 832 /* completion message header */ 833 compl_msg_hdr_t compl_hdr; 834 /* snapshot length uploaded */ 835 uint32 resp_len; 836 /* snapshot type */ 837 uint8 type; 838 /* rsvd */ 839 uint8 rsvd[3]; 840 /* XOR checksum or a magic number to audit DMA done */ 841 dma_done_t marker; 842 } snapshot_resp_t; 843 844 typedef struct info_ring_cpl_item { 845 info_buf_resp_t info_buf_post; 846 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE]; 847 } info_cpl_item_t; 848 849 typedef struct host_timestamp_msg_cpl { 850 cmn_msg_hdr_t msg; 851 compl_msg_hdr_t cmplt; 852 uint16 xt_id; /* transaction ID */ 853 uint16 rsvd; 854 uint32 rsvd1; 855 /* XOR checksum or a magic number to audit DMA done */ 856 dma_done_t marker; 857 } host_timestamp_msg_cpl_t; 858 859 typedef struct fw_timestamp_event_msg { 860 cmn_msg_hdr_t msg; 861 compl_msg_hdr_t cmplt; 862 /* fw captures time stamp info and passed that to host in TLVs */ 863 uint16 buf_len; /* length of the time stamp data copied in host buf */ 864 uint16 seqnum; /* number of times fw captured time stamp */ 865 uint32 rsvd; 866 /* XOR checksum or a magic number to audit DMA done */ 867 dma_done_t marker; 868 } fw_timestamp_event_msg_t; 869 870 typedef union ctrl_completion_item { 871 ioctl_comp_resp_msg_t ioctl_resp; 872 wlevent_req_msg_t event; 873 ioctl_req_ack_msg_t ioct_ack; 874 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt; 875 pcie_gen_status_t pcie_gen_status; 876 pcie_ring_status_t pcie_ring_status; 877 tx_flowring_create_response_t txfl_create_resp; 878 tx_flowring_delete_response_t txfl_delete_resp; 879 tx_flowring_flush_response_t txfl_flush_resp; 880 ctrl_compl_msg_t ctrl_compl; 881 ring_config_resp_t ring_config_resp; 882 d2h_mailbox_data_t d2h_mailbox_data; 883 info_buf_resp_t dbg_resp; 884 h2d_ring_create_response_t h2d_ring_create_resp; 885 d2h_ring_create_response_t d2h_ring_create_resp; 886 host_timestamp_msg_cpl_t host_ts_cpl; 887 fw_timestamp_event_msg_t fw_ts_event; 888 h2d_ring_delete_response_t h2d_ring_delete_resp; 889 d2h_ring_delete_response_t d2h_ring_delete_resp; 890 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE]; 891 } ctrl_completion_item_t; 892 893 /** H2D Rxpost ring work items */ 894 typedef struct host_rxbuf_post { 895 /** common message header */ 896 cmn_msg_hdr_t cmn_hdr; 897 /** provided meta data buffer len */ 898 uint16 metadata_buf_len; 899 /** provided data buffer len to receive data */ 900 uint16 data_buf_len; 901 /** alignment to make the host buffers start on 8 byte boundary */ 902 uint32 rsvd; 903 /** provided meta data buffer */ 904 bcm_addr64_t metadata_buf_addr; 905 /** provided data buffer to receive data */ 906 bcm_addr64_t data_buf_addr; 907 } host_rxbuf_post_t; 908 909 typedef union rxbuf_submit_item { 910 host_rxbuf_post_t rxpost; 911 unsigned char check[H2DRING_RXPOST_ITEMSIZE]; 912 } rxbuf_submit_item_t; 913 914 /* D2H Rxcompletion ring work items for IPC rev7 */ 915 typedef struct host_rxbuf_cmpl { 916 /** common message header */ 917 cmn_msg_hdr_t cmn_hdr; 918 /** completion message header */ 919 compl_msg_hdr_t compl_hdr; 920 /** filled up meta data len */ 921 uint16 metadata_len; 922 /** filled up buffer len to receive data */ 923 uint16 data_len; 924 /** offset in the host rx buffer where the data starts */ 925 uint16 data_offset; 926 /** Flags */ 927 uint16 flags; 928 /** rx status */ 929 uint32 rx_status_0; 930 uint32 rx_status_1; 931 /** XOR checksum or a magic number to audit DMA done */ 932 /* This is for rev6 only. For IPC rev7, this is a reserved field */ 933 dma_done_t marker; 934 /* timestamp */ 935 ipc_timestamp_t ts; 936 } host_rxbuf_cmpl_t; 937 938 typedef union rxbuf_complete_item { 939 host_rxbuf_cmpl_t rxcmpl; 940 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE]; 941 } rxbuf_complete_item_t; 942 943 typedef struct host_txbuf_post { 944 /** common message header */ 945 cmn_msg_hdr_t cmn_hdr; 946 /** eth header */ 947 uint8 txhdr[ETHER_HDR_LEN]; 948 /** flags */ 949 uint8 flags; 950 /** number of segments */ 951 uint8 seg_cnt; 952 953 /** provided meta data buffer for txstatus */ 954 bcm_addr64_t metadata_buf_addr; 955 /** provided data buffer to receive data */ 956 bcm_addr64_t data_buf_addr; 957 /** provided meta data buffer len */ 958 uint16 metadata_buf_len; 959 /** provided data buffer len to receive data */ 960 uint16 data_len; 961 union { 962 struct { 963 /** extended transmit flags */ 964 uint8 ext_flags; 965 uint8 rsvd1; 966 967 /** user defined rate */ 968 uint8 rate; 969 uint8 exp_time; 970 }; 971 /** XOR checksum or a magic number to audit DMA done */ 972 dma_done_t marker; 973 }; 974 } host_txbuf_post_t; 975 976 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01 977 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02 978 979 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */ 980 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR 0x02 /* Disable aggregation for this frame */ 981 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame */ 982 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */ 983 984 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */ 985 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */ 986 987 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5 988 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT) 989 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00 990 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01 991 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02 992 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03 993 #define BCMPCIE_PKT_FLAGS_NO_FORWARD 0x04 994 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8 995 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT) 996 997 /* These are added to fix up compile issues */ 998 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3 999 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11 1000 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT 1001 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK 1002 1003 /* H2D Txpost ring work items */ 1004 typedef union txbuf_submit_item { 1005 host_txbuf_post_t txpost; 1006 unsigned char check[H2DRING_TXPOST_ITEMSIZE]; 1007 } txbuf_submit_item_t; 1008 1009 /* D2H Txcompletion ring work items - extended for IOC rev7 */ 1010 typedef struct host_txbuf_cmpl { 1011 /** common message header */ 1012 cmn_msg_hdr_t cmn_hdr; 1013 /** completion message header */ 1014 compl_msg_hdr_t compl_hdr; 1015 union { 1016 struct { 1017 union { 1018 /** provided meta data len */ 1019 uint16 metadata_len; 1020 /** provided extended TX status */ 1021 uint16 tx_status_ext; 1022 }; 1023 /** WLAN side txstatus */ 1024 uint16 tx_status; 1025 }; 1026 /** XOR checksum or a magic number to audit DMA done */ 1027 /* This is for rev6 only. For IPC rev7, this is not used */ 1028 dma_done_t marker; 1029 }; 1030 /* timestamp */ 1031 ipc_timestamp_t ts; 1032 1033 } host_txbuf_cmpl_t; 1034 1035 typedef union txbuf_complete_item { 1036 host_txbuf_cmpl_t txcmpl; 1037 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE]; 1038 } txbuf_complete_item_t; 1039 1040 #define BCMPCIE_D2H_METADATA_HDRLEN 4 1041 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4) 1042 1043 /** ret buf struct */ 1044 typedef struct ret_buf_ptr { 1045 uint32 low_addr; 1046 uint32 high_addr; 1047 } ret_buf_t; 1048 1049 #ifdef PCIE_API_REV1 1050 1051 /* ioctl specific hdr */ 1052 typedef struct ioctl_hdr { 1053 uint16 cmd; 1054 uint16 retbuf_len; 1055 uint32 cmd_id; 1056 } ioctl_hdr_t; 1057 1058 typedef struct ioctlptr_hdr { 1059 uint16 cmd; 1060 uint16 retbuf_len; 1061 uint16 buflen; 1062 uint16 rsvd; 1063 uint32 cmd_id; 1064 } ioctlptr_hdr_t; 1065 1066 #else /* PCIE_API_REV1 */ 1067 1068 typedef struct ioctl_req_hdr { 1069 uint32 pkt_id; /**< Packet ID */ 1070 uint32 cmd; /**< IOCTL ID */ 1071 uint16 retbuf_len; 1072 uint16 buflen; 1073 uint16 xt_id; /**< transaction ID */ 1074 uint16 rsvd[1]; 1075 } ioctl_req_hdr_t; 1076 1077 #endif /* PCIE_API_REV1 */ 1078 1079 /** Complete msgbuf hdr for ioctl from host to dongle */ 1080 typedef struct ioct_reqst_hdr { 1081 cmn_msg_hdr_t msg; 1082 #ifdef PCIE_API_REV1 1083 ioctl_hdr_t ioct_hdr; 1084 #else 1085 ioctl_req_hdr_t ioct_hdr; 1086 #endif // endif 1087 ret_buf_t ret_buf; 1088 } ioct_reqst_hdr_t; 1089 1090 typedef struct ioctptr_reqst_hdr { 1091 cmn_msg_hdr_t msg; 1092 #ifdef PCIE_API_REV1 1093 ioctlptr_hdr_t ioct_hdr; 1094 #else 1095 ioctl_req_hdr_t ioct_hdr; 1096 #endif // endif 1097 ret_buf_t ret_buf; 1098 ret_buf_t ioct_buf; 1099 } ioctptr_reqst_hdr_t; 1100 1101 /** ioctl response header */ 1102 typedef struct ioct_resp_hdr { 1103 cmn_msg_hdr_t msg; 1104 #ifdef PCIE_API_REV1 1105 uint32 cmd_id; 1106 #else 1107 uint32 pkt_id; 1108 #endif // endif 1109 uint32 status; 1110 uint32 ret_len; 1111 uint32 inline_data; 1112 #ifdef PCIE_API_REV1 1113 #else 1114 uint16 xt_id; /**< transaction ID */ 1115 uint16 rsvd[1]; 1116 #endif // endif 1117 } ioct_resp_hdr_t; 1118 1119 /* ioct resp header used in dongle */ 1120 /* ret buf hdr will be stripped off inside dongle itself */ 1121 typedef struct msgbuf_ioctl_resp { 1122 ioct_resp_hdr_t ioct_hdr; 1123 ret_buf_t ret_buf; /**< ret buf pointers */ 1124 } msgbuf_ioct_resp_t; 1125 1126 /** WL event hdr info */ 1127 typedef struct wl_event_hdr { 1128 cmn_msg_hdr_t msg; 1129 uint16 event; 1130 uint8 flags; 1131 uint8 rsvd; 1132 uint16 retbuf_len; 1133 uint16 rsvd1; 1134 uint32 rxbufid; 1135 } wl_event_hdr_t; 1136 1137 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF 1138 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE 1139 1140 typedef struct txbatch_lenptr_tup { 1141 uint32 pktid; 1142 uint16 pktlen; 1143 uint16 rsvd; 1144 ret_buf_t ret_buf; /**< ret buf pointers */ 1145 } txbatch_lenptr_tup_t; 1146 1147 typedef struct txbatch_cmn_msghdr { 1148 cmn_msg_hdr_t msg; 1149 uint8 priority; 1150 uint8 hdrlen; 1151 uint8 pktcnt; 1152 uint8 flowid; 1153 uint8 txhdr[ETHER_HDR_LEN]; 1154 uint16 rsvd; 1155 } txbatch_cmn_msghdr_t; 1156 1157 typedef struct txbatch_msghdr { 1158 txbatch_cmn_msghdr_t txcmn; 1159 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */ 1160 } txbatch_msghdr_t; 1161 1162 /* TX desc posting header */ 1163 typedef struct tx_lenptr_tup { 1164 uint16 pktlen; 1165 uint16 rsvd; 1166 ret_buf_t ret_buf; /**< ret buf pointers */ 1167 } tx_lenptr_tup_t; 1168 1169 typedef struct txdescr_cmn_msghdr { 1170 cmn_msg_hdr_t msg; 1171 uint8 priority; 1172 uint8 hdrlen; 1173 uint8 descrcnt; 1174 uint8 flowid; 1175 uint32 pktid; 1176 } txdescr_cmn_msghdr_t; 1177 1178 typedef struct txdescr_msghdr { 1179 txdescr_cmn_msghdr_t txcmn; 1180 uint8 txhdr[ETHER_HDR_LEN]; 1181 uint16 rsvd; 1182 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */ 1183 } txdescr_msghdr_t; 1184 1185 /** Tx status header info */ 1186 typedef struct txstatus_hdr { 1187 cmn_msg_hdr_t msg; 1188 uint32 pktid; 1189 } txstatus_hdr_t; 1190 1191 /** RX bufid-len-ptr tuple */ 1192 typedef struct rx_lenptr_tup { 1193 uint32 rxbufid; 1194 uint16 len; 1195 uint16 rsvd2; 1196 ret_buf_t ret_buf; /**< ret buf pointers */ 1197 } rx_lenptr_tup_t; 1198 1199 /** Rx descr Post hdr info */ 1200 typedef struct rxdesc_msghdr { 1201 cmn_msg_hdr_t msg; 1202 uint16 rsvd0; 1203 uint8 rsvd1; 1204 uint8 descnt; 1205 rx_lenptr_tup_t rx_tup[0]; 1206 } rxdesc_msghdr_t; 1207 1208 /** RX complete tuples */ 1209 typedef struct rxcmplt_tup { 1210 uint16 retbuf_len; 1211 uint16 data_offset; 1212 uint32 rxstatus0; 1213 uint32 rxstatus1; 1214 uint32 rxbufid; 1215 } rxcmplt_tup_t; 1216 1217 /** RX complete messge hdr */ 1218 typedef struct rxcmplt_hdr { 1219 cmn_msg_hdr_t msg; 1220 uint16 rsvd0; 1221 uint16 rxcmpltcnt; 1222 rxcmplt_tup_t rx_tup[0]; 1223 } rxcmplt_hdr_t; 1224 1225 typedef struct hostevent_hdr { 1226 cmn_msg_hdr_t msg; 1227 uint32 evnt_pyld; 1228 } hostevent_hdr_t; 1229 1230 typedef struct dma_xfer_params { 1231 uint32 src_physaddr_hi; 1232 uint32 src_physaddr_lo; 1233 uint32 dest_physaddr_hi; 1234 uint32 dest_physaddr_lo; 1235 uint32 len; 1236 uint32 srcdelay; 1237 uint32 destdelay; 1238 } dma_xfer_params_t; 1239 1240 enum { 1241 HOST_EVENT_CONS_CMD = 1 1242 }; 1243 1244 /* defines for flags */ 1245 #define MSGBUF_IOC_ACTION_MASK 0x1 1246 1247 #define MAX_SUSPEND_REQ 15 1248 1249 typedef struct tx_idle_flowring_suspend_request { 1250 cmn_msg_hdr_t msg; 1251 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */ 1252 uint16 num; /* number of flowid's to suspend */ 1253 } tx_idle_flowring_suspend_request_t; 1254 1255 typedef struct tx_idle_flowring_suspend_response { 1256 cmn_msg_hdr_t msg; 1257 compl_msg_hdr_t cmplt; 1258 uint32 rsvd[2]; 1259 dma_done_t marker; 1260 } tx_idle_flowring_suspend_response_t; 1261 1262 typedef struct tx_idle_flowring_resume_request { 1263 cmn_msg_hdr_t msg; 1264 uint16 flow_ring_id; 1265 uint16 reason; 1266 uint32 rsvd[7]; 1267 } tx_idle_flowring_resume_request_t; 1268 1269 typedef struct tx_idle_flowring_resume_response { 1270 cmn_msg_hdr_t msg; 1271 compl_msg_hdr_t cmplt; 1272 uint32 rsvd[2]; 1273 dma_done_t marker; 1274 } tx_idle_flowring_resume_response_t; 1275 1276 /* timesync related additions */ 1277 1278 typedef struct _bcm_xtlv { 1279 uint16 id; /* TLV idenitifier */ 1280 uint16 len; /* TLV length in bytes */ 1281 } _bcm_xtlv_t; 1282 1283 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0 1284 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1 1285 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2 1286 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3 1287 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4 1288 #define BCMMSGBUF_MAX_TSYNC_TAG 5 1289 1290 /* Flags in fw clock info TLV */ 1291 #define CAP_DEVICE_TS (1 << 0) 1292 #define CAP_CORRECTED_TS (1 << 1) 1293 #define TS_CLK_ACTIVE (1 << 2) 1294 1295 typedef struct ts_fw_clock_info { 1296 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */ 1297 ts_timestamp_srcid_t ts; /* tick count */ 1298 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */ 1299 uint32 nominal_clock_freq; 1300 uint32 reset_cnt; 1301 uint8 flags; 1302 uint8 rsvd[3]; 1303 } ts_fw_clock_info_t; 1304 1305 typedef struct ts_host_clock_info { 1306 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1307 tick_count_64_t ticks; /* 64 bit host tick counter */ 1308 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */ 1309 } ts_host_clock_info_t; 1310 1311 typedef struct ts_host_clock_sel { 1312 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */ 1313 uint32 seqnum; /* number of times GPIO time sync toggled */ 1314 uint8 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1315 uint8 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1316 uint16 rsvd[1]; 1317 } ts_host_clock_sel_t; 1318 1319 typedef struct ts_d2h_clock_correction { 1320 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1321 uint8 clk_id; /* clock source in the device */ 1322 uint8 rsvd[3]; 1323 ts_correction_m_t m; /* y = 'm' x + b */ 1324 ts_correction_b_t b; /* y = 'm' x + 'c' */ 1325 } ts_d2h_clock_correction_t; 1326 1327 typedef struct ts_host_timestamping_config { 1328 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */ 1329 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */ 1330 uint16 period_ms; 1331 uint8 flags; 1332 uint8 post_delay; 1333 uint32 reset_cnt; 1334 } ts_host_timestamping_config_t; 1335 1336 /* Flags in host timestamping config TLV */ 1337 #define FLAG_HOST_RESET (1 << 0) 1338 #define IS_HOST_RESET(x) ((x) & FLAG_HOST_RESET) 1339 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET) 1340 1341 #define FLAG_CONFIG_NODROP (1 << 1) 1342 #define IS_CONFIG_NODROP(x) ((x) & FLAG_CONFIG_NODROP) 1343 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP) 1344 1345 #endif /* _bcmmsgbuf_h_ */ 1346