1 /* 2 * Broadcom device-specific manifest constants. 3 * 4 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: bcmdevs.h 701163 2017-05-23 22:21:03Z $ 30 */ 31 32 #ifndef _BCMDEVS_H 33 #define _BCMDEVS_H 34 35 /* PCI vendor IDs */ 36 #define VENDOR_EPIGRAM 0xfeda 37 #define VENDOR_BROADCOM 0x14e4 38 #define VENDOR_3COM 0x10b7 39 #define VENDOR_NETGEAR 0x1385 40 #define VENDOR_DIAMOND 0x1092 41 #define VENDOR_INTEL 0x8086 42 #define VENDOR_DELL 0x1028 43 #define VENDOR_HP 0x103c 44 #define VENDOR_HP_COMPAQ 0x0e11 45 #define VENDOR_APPLE 0x106b 46 #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ 47 #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ 48 #define VENDOR_TI 0x104c /* Texas Instruments */ 49 #define VENDOR_RICOH 0x1180 /* Ricoh */ 50 #define VENDOR_JMICRON 0x197b 51 #define VENDOR_CYPRESS 0x12BE 52 53 /* PCMCIA vendor IDs */ 54 #define VENDOR_BROADCOM_PCMCIA 0x02d0 55 56 /* SDIO vendor IDs */ 57 #define VENDOR_BROADCOM_SDIO 0x00BF 58 59 /* DONGLE VID/PIDs */ 60 #define CY_DNGL_VID 0x04b4 61 #define BCM_DNGL_VID 0x0a5c 62 #define BCM_DNGL_BL_PID_4328 0xbd12 63 #define BCM_DNGL_BL_PID_4322 0xbd13 64 #define BCM_DNGL_BL_PID_4319 0xbd16 65 #define BCM_DNGL_BL_PID_43236 0xbd17 66 #define BCM_DNGL_BL_PID_4332 0xbd18 67 #define BCM_DNGL_BL_PID_4360 0xbd1d 68 #define BCM_DNGL_BL_PID_43143 0xbd1e 69 #define BCM_DNGL_BL_PID_4335 0xbd20 70 #define BCM_DNGL_BL_PID_4350 0xbd23 71 #define BCM_DNGL_BL_PID_4345 0xbd24 72 #define BCM_DNGL_BL_PID_4349 0xbd25 73 #define BCM_DNGL_BL_PID_4354 0xbd26 74 #define BCM_DNGL_BL_PID_43569 0xbd27 75 #define BCM_DNGL_BL_PID_4373 0xbd29 76 77 #define BCM_DNGL_BDC_PID 0x0bdc 78 #define BCM_DNGL_JTAG_PID 0x4a44 79 80 #ifdef DEPRECATED 81 #define BCM_DNGL_BL_PID_43239 0xbd1b 82 #define BCM_DNGL_BL_PID_4324 0xbd1c 83 #define BCM_DNGL_BL_PID_43242 0xbd1f 84 #define BCM_DNGL_BL_PID_43909 0xbd28 85 #endif // endif 86 87 /* PCI Device IDs */ 88 #ifdef DEPRECATED /* These products have been deprecated */ 89 #define BCM4210_DEVICE_ID 0x1072 /* never used */ 90 #define BCM4230_DEVICE_ID 0x1086 /* never used */ 91 #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ 92 #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ 93 #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ 94 #define BCM4211_DEVICE_ID 0x4211 95 #define BCM4231_DEVICE_ID 0x4231 96 #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ 97 #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */ 98 #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */ 99 #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */ 100 #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */ 101 #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */ 102 #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */ 103 #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */ 104 #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */ 105 #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */ 106 #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */ 107 #define BCM4306_UART_ID 0x4322 /* 4306 uart */ 108 #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ 109 #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */ 110 #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */ 111 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */ 112 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */ 113 #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */ 114 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */ 115 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */ 116 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */ 117 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */ 118 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */ 119 #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */ 120 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */ 121 #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */ 122 #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */ 123 #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */ 124 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */ 125 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */ 126 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */ 127 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */ 128 #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */ 129 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */ 130 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */ 131 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */ 132 #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */ 133 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */ 134 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */ 135 #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */ 136 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */ 137 #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */ 138 #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */ 139 #define BCM43242_D11N_ID 0x4367 /* 43242 802.11n dualband device */ 140 #define BCM43242_D11N2G_ID 0x4368 /* 43242 802.11n 2.4G device */ 141 #define BCM43242_D11N5G_ID 0x4369 /* 43242 802.11n 5G device */ 142 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */ 143 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */ 144 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */ 145 #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */ 146 #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */ 147 #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */ 148 #define BCM43342_D11N_ID 0x4383 /* 43342 802.11n dualband device */ 149 #define BCM43342_D11N2G_ID 0x4384 /* 43342 802.11n 2.4G device */ 150 #define BCM43342_D11N5G_ID 0x4385 /* 43342 802.11n 5G device */ 151 #define BCM43341_D11N_ID 0x4386 /* 43341 802.11n dualband device */ 152 #define BCM43341_D11N2G_ID 0x4387 /* 43341 802.11n 2.4G device */ 153 #define BCM43341_D11N5G_ID 0x4388 /* 43341 802.11n 5G device */ 154 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */ 155 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */ 156 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */ 157 #define BCM43909_D11AC_ID 0x43d0 /* 43909 802.11ac dualband device */ 158 #define BCM43909_D11AC2G_ID 0x43d1 /* 43909 802.11ac 2.4G device */ 159 #define BCM43909_D11AC5G_ID 0x43d2 /* 43909 802.11ac 5G device */ 160 #endif /* DEPRECATED */ 161 /* DEPRECATED but used */ 162 #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ 163 #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ 164 #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ 165 #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */ 166 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */ 167 #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */ 168 #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */ 169 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */ 170 #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ 171 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */ 172 #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */ 173 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */ 174 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */ 175 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */ 176 /* DEPRECATED */ 177 178 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */ 179 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */ 180 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */ 181 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */ 182 #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */ 183 #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */ 184 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */ 185 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */ 186 #define BCM4360_D11AC_ID 0x43a0 187 #define BCM4360_D11AC2G_ID 0x43a1 188 #define BCM4360_D11AC5G_ID 0x43a2 189 #define BCM4345_D11AC_ID 0x43ab /* 4345 802.11ac dualband device */ 190 #define BCM4345_D11AC2G_ID 0x43ac /* 4345 802.11ac 2.4G device */ 191 #define BCM4345_D11AC5G_ID 0x43ad /* 4345 802.11ac 5G device */ 192 #define BCM43455_D11AC_ID 0x43e3 /* 43455 802.11ac dualband device */ 193 #define BCM43455_D11AC2G_ID 0x43e4 /* 43455 802.11ac 2.4G device */ 194 #define BCM43455_D11AC5G_ID 0x43e5 /* 43455 802.11ac 5G device */ 195 #define BCM4335_D11AC_ID 0x43ae 196 #define BCM4335_D11AC2G_ID 0x43af 197 #define BCM4335_D11AC5G_ID 0x43b0 198 #define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */ 199 #define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */ 200 #define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */ 201 #define BCM43602_D11AC_ID 0x43ba /* ac dualband PCI devid SPROM programmed */ 202 #define BCM43602_D11AC2G_ID 0x43bb /* 43602 802.11ac 2.4G device */ 203 #define BCM43602_D11AC5G_ID 0x43bc /* 43602 802.11ac 5G device */ 204 #define BCM4349_D11AC_ID 0x4349 /* 4349 802.11ac dualband device */ 205 #define BCM4349_D11AC2G_ID 0x43dd /* 4349 802.11ac 2.4G device */ 206 #define BCM4349_D11AC5G_ID 0x43de /* 4349 802.11ac 5G device */ 207 #define BCM53573_D11AC_ID 0x43b4 /* 53573 802.11ac dualband device */ 208 #define BCM53573_D11AC2G_ID 0x43b5 /* 53573 802.11ac 2.4G device */ 209 #define BCM53573_D11AC5G_ID 0x43b6 /* 53573 802.11ac 5G device */ 210 #define BCM47189_D11AC_ID 0x43c6 /* 47189 802.11ac dualband device */ 211 #define BCM47189_D11AC2G_ID 0x43c7 /* 47189 802.11ac 2.4G device */ 212 #define BCM47189_D11AC5G_ID 0x43c8 /* 47189 802.11ac 5G device */ 213 #define BCM4355_D11AC_ID 0x43dc /* 4355 802.11ac dualband device */ 214 #define BCM4355_D11AC2G_ID 0x43fc /* 4355 802.11ac 2.4G device */ 215 #define BCM4355_D11AC5G_ID 0x43fd /* 4355 802.11ac 5G device */ 216 #define BCM4359_D11AC_ID 0x43ef /* 4359 802.11ac dualband device */ 217 #define BCM4359_D11AC2G_ID 0x43fe /* 4359 802.11ac 2.4G device */ 218 #define BCM4359_D11AC5G_ID 0x43ff /* 4359 802.11ac 5G device */ 219 #define BCM43596_D11AC_ID 0x4415 /* 43596 802.11ac dualband device */ 220 #define BCM43596_D11AC2G_ID 0x4416 /* 43596 802.11ac 2.4G device */ 221 #define BCM43596_D11AC5G_ID 0x4417 /* 43596 802.11ac 5G device */ 222 #define BCM43597_D11AC_ID 0x441c /* 43597 802.11ac dualband device */ 223 #define BCM43597_D11AC2G_ID 0x441d /* 43597 802.11ac 2.4G device */ 224 #define BCM43597_D11AC5G_ID 0x441e /* 43597 802.11ac 5G device */ 225 #define BCM43012_D11N_ID 0xA804 /* 43012 802.11n dualband device */ 226 #define BCM43012_D11N2G_ID 0xA805 /* 43012 802.11n 2.4G device */ 227 #define BCM43012_D11N5G_ID 0xA806 /* 43012 802.11n 5G device */ 228 #define BCM43014_D11N_ID 0x4495 /* 43014 802.11n dualband device */ 229 #define BCM43014_D11N2G_ID 0x4496 /* 43014 802.11n 2.4G device */ 230 #define BCM43014_D11N5G_ID 0x4497 /* 43014 802.11n 5G device */ 231 232 /* PCI Subsystem ID */ 233 #define BCM94313HMGBL_SSID_VEN1 0x0608 234 #define BCM94313HMG_SSID_VEN1 0x0609 235 #define BCM943142HM_SSID_VEN1 0x0611 236 237 #define BCM4350_D11AC_ID 0x43a3 238 #define BCM4350_D11AC2G_ID 0x43a4 239 #define BCM4350_D11AC5G_ID 0x43a5 240 241 #define BCM43556_D11AC_ID 0x43b7 242 #define BCM43556_D11AC2G_ID 0x43b8 243 #define BCM43556_D11AC5G_ID 0x43b9 244 245 #define BCM43558_D11AC_ID 0x43c0 246 #define BCM43558_D11AC2G_ID 0x43c1 247 #define BCM43558_D11AC5G_ID 0x43c2 248 249 #define BCM43566_D11AC_ID 0x43d3 250 #define BCM43566_D11AC2G_ID 0x43d4 251 #define BCM43566_D11AC5G_ID 0x43d5 252 253 #define BCM43568_D11AC_ID 0x43d6 254 #define BCM43568_D11AC2G_ID 0x43d7 255 #define BCM43568_D11AC5G_ID 0x43d8 256 257 #define BCM43569_D11AC_ID 0x43d9 258 #define BCM43569_D11AC2G_ID 0x43da 259 #define BCM43569_D11AC5G_ID 0x43db 260 261 #define BCM43570_D11AC_ID 0x43d9 262 #define BCM43570_D11AC2G_ID 0x43da 263 #define BCM43570_D11AC5G_ID 0x43db 264 265 #define BCM4354_D11AC_ID 0x43df /* 4354 802.11ac dualband device */ 266 #define BCM4354_D11AC2G_ID 0x43e0 /* 4354 802.11ac 2.4G device */ 267 #define BCM4354_D11AC5G_ID 0x43e1 /* 4354 802.11ac 5G device */ 268 #define BCM43430_D11N2G_ID 0x43e2 /* 43430 802.11n 2.4G device */ 269 #define BCM43018_D11N2G_ID 0x441b /* 43018 802.11n 2.4G device */ 270 271 #define BCM4347_D11AC_ID 0x440a /* 4347 802.11ac dualband device */ 272 #define BCM4347_D11AC2G_ID 0x440b /* 4347 802.11ac 2.4G device */ 273 #define BCM4347_D11AC5G_ID 0x440c /* 4347 802.11ac 5G device */ 274 275 #ifdef CHIPS_CUSTOMER_HW6 276 #define BCM4376_D11AC_ID 0x4435 /* 4376 802.11ac dualband device */ 277 #define BCM4376_D11AC2G_ID 0x4436 /* 4376 802.11ac 2.4G device */ 278 #define BCM4376_D11AC5G_ID 0x4437 /* 4376 802.11ac 5G device */ 279 280 #define BCM4378_D11AC_ID 0x4425 /* 4378 802.11ac dualband device */ 281 #define BCM4378_D11AC2G_ID 0x4426 /* 4378 802.11ac 2.4G device */ 282 #define BCM4378_D11AC5G_ID 0x4427 /* 4378 802.11ac 5G device */ 283 #endif /* CHIPS_CUSTOMER_HW6 */ 284 285 #define BCM4361_D11AC_ID 0x441f /* 4361 802.11ac dualband device */ 286 #define BCM4361_D11AC2G_ID 0x4420 /* 4361 802.11ac 2.4G device */ 287 #define BCM4361_D11AC5G_ID 0x4421 /* 4361 802.11ac 5G device */ 288 289 #define BCM4362_D11AX_ID 0x4490 /* 4362 802.11ax dualband device */ 290 #define BCM4362_D11AX2G_ID 0x4491 /* 4362 802.11ax 2.4G device */ 291 #define BCM4362_D11AX5G_ID 0x4492 /* 4362 802.11ax 5G device */ 292 #define BCM43751_D11AX_ID 0x4490 /* 43751 802.11ax dualband device */ 293 #define BCM43751_D11AX2G_ID 0x4491 /* 43751 802.11ax 2.4G device */ 294 #define BCM43751_D11AX5G_ID 0x4492 /* 43751 802.11ax 5G device */ 295 296 #define BCM4364_D11AC_ID 0x4464 /* 4364 802.11ac dualband device */ 297 #define BCM4364_D11AC2G_ID 0x446a /* 4364 802.11ac 2.4G device */ 298 #define BCM4364_D11AC5G_ID 0x446b /* 4364 802.11ac 5G device */ 299 300 #define BCM4365_D11AC_ID 0x43ca 301 #define BCM4365_D11AC2G_ID 0x43cb 302 #define BCM4365_D11AC5G_ID 0x43cc 303 304 #define BCM4366_D11AC_ID 0x43c3 305 #define BCM4366_D11AC2G_ID 0x43c4 306 #define BCM4366_D11AC5G_ID 0x43c5 307 308 /* TBD change below values */ 309 #define BCM4369_D11AX_ID 0x4470 /* 4369 802.11ax dualband device */ 310 #define BCM4369_D11AX2G_ID 0x4471 /* 4369 802.11ax 2.4G device */ 311 #define BCM4369_D11AX5G_ID 0x4472 /* 4369 802.11ax 5G device */ 312 313 #define BCM4375_D11AX_ID 0x4475 /* 4375 802.11ax dualband device */ 314 #define BCM4375_D11AX2G_ID 0x4476 /* 4375 802.11ax 2.4G device */ 315 #define BCM4375_D11AX5G_ID 0x4477 /* 4375 802.11ax 5G device */ 316 317 #ifdef CHIPS_CUSTOMER_HW6 318 #define BCM4377_D11AX_ID 0x4480 /* 4377 802.11ax dualband device */ 319 #define BCM4377_D11AX2G_ID 0x4481 /* 4377 802.11ax 2.4G device */ 320 #define BCM4377_D11AX5G_ID 0x4482 /* 4377 802.11ax 5G device */ 321 322 #define BCM4377_M_D11AX_ID 0x4488 /* 4377 802.11ax dualband device with multifunction */ 323 324 /* TBD change below values */ 325 #define BCM4367_D11AC_ID 0x4422 326 #define BCM4367_D11AC2G_ID 0x4423 327 #define BCM4367_D11AC5G_ID 0x4424 328 #endif /* CHIPS_CUSTOMER_HW6 */ 329 330 #ifdef CHIPS_CUSTOMER_HW6 331 #define BCM4368_D11AC_ID 0x442f 332 #define BCM4368_D11AC2G_ID 0x4430 333 #define BCM4368_D11AC5G_ID 0x4431 334 #define BCM4368_D11ACBT_ID 0x5f30 335 #endif /* CHIPS_CUSTOMER_HW6 */ 336 337 #define BCM43349_D11N_ID 0x43e6 /* 43349 802.11n dualband id */ 338 #define BCM43349_D11N2G_ID 0x43e7 /* 43349 802.11n 2.4Ghz band id */ 339 #define BCM43349_D11N5G_ID 0x43e8 /* 43349 802.11n 5Ghz band id */ 340 341 #define BCM4358_D11AC_ID 0x43e9 /* 4358 802.11ac dualband device */ 342 #define BCM4358_D11AC2G_ID 0x43ea /* 4358 802.11ac 2.4G device */ 343 #define BCM4358_D11AC5G_ID 0x43eb /* 4358 802.11ac 5G device */ 344 345 #define BCM4356_D11AC_ID 0x43ec /* 4356 802.11ac dualband device */ 346 #define BCM4356_D11AC2G_ID 0x43ed /* 4356 802.11ac 2.4G device */ 347 #define BCM4356_D11AC5G_ID 0x43ee /* 4356 802.11ac 5G device */ 348 349 #define BCM4371_D11AC_ID 0x440d /* 4371 802.11ac dualband device */ 350 #define BCM4371_D11AC2G_ID 0x440e /* 4371 802.11ac 2.4G device */ 351 #define BCM4371_D11AC5G_ID 0x440f /* 4371 802.11ac 5G device */ 352 #define BCM7271_D11AC_ID 0x4410 /* 7271 802.11ac dualband device */ 353 #define BCM7271_D11AC2G_ID 0x4411 /* 7271 802.11ac 2.4G device */ 354 #define BCM7271_D11AC5G_ID 0x4412 /* 7271 802.11ac 5G device */ 355 356 #define BCM4373_D11AC_ID 0x4418 /* 4373 802.11ac dualband device */ 357 #define BCM4373_D11AC2G_ID 0x4419 /* 4373 802.11ac 2.4G device */ 358 #define BCM4373_D11AC5G_ID 0x441a /* 4373 802.11ac 5G device */ 359 360 #define CYW55560_WLAN_ID 0xBD31 /* CYW55560 802.11ax WLAN device ID */ 361 #define CYW89570_WLAN_ID 0xBD3f /* CYW89570 802.11ax WLAN device ID */ 362 #define CYW55560_BT_ID 0xBD37 /* CYW55560 802.11ax BT device ID */ 363 364 #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ 365 #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ 366 #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */ 367 #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */ 368 #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */ 369 #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */ 370 #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */ 371 #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */ 372 #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */ 373 #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */ 374 #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */ 375 #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */ 376 #define BCM4402_ENET_ID 0x4402 /* 4402 enet */ 377 #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ 378 #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ 379 #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ 380 #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ 381 #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ 382 #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ 383 #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ 384 #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */ 385 #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ 386 #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ 387 #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ 388 #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */ 389 #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ 390 #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ 391 #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ 392 #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ 393 #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ 394 #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ 395 #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */ 396 #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */ 397 #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */ 398 #ifdef DEPRECATED /* These products have been deprecated */ 399 #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ 400 #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */ 401 #endif /* DEPRECATED */ 402 #define BCM47XX_USB30H_ID 0x472a /* 47xx usb 3.0 host */ 403 #define BCM47XX_USB30D_ID 0x472b /* 47xx usb 3.0 device */ 404 #define BCM47XX_USBHUB_ID 0x472c /* 47xx usb hub */ 405 #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */ 406 #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */ 407 #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ 408 #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ 409 #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */ 410 #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */ 411 #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */ 412 #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */ 413 #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ 414 #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */ 415 416 #define BCM43452_D11AC_ID 0x47ab /* 43452 802.11ac dualband device */ 417 #define BCM43452_D11AC2G_ID 0x47ac /* 43452 802.11ac 2.4G device */ 418 #define BCM43452_D11AC5G_ID 0x47ad /* 43452 802.11ac 5G device */ 419 420 /* Chip IDs */ 421 #ifdef DEPRECATED /* These products have been deprecated */ 422 #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */ 423 #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */ 424 #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */ 425 #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */ 426 #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */ 427 #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */ 428 #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */ 429 #define BCM43143_CHIP_ID 43143 /* 43143 chipcommon chipid */ 430 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */ 431 #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */ 432 #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */ 433 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */ 434 #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */ 435 #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */ 436 #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */ 437 #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */ 438 #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */ 439 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */ 440 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */ 441 #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */ 442 #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */ 443 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */ 444 #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */ 445 #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */ 446 #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */ 447 #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */ 448 #define BCM43242_CHIP_ID 43242 /* 43242 chipcommon chipid */ 449 #define BCM43243_CHIP_ID 43243 /* 43243 chipcommon chipid */ 450 #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */ 451 #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */ 452 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */ 453 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */ 454 #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */ 455 #define BCM43349_CHIP_ID 43349 /* 43349(0xA955) chipcommon chipid */ 456 #define BCM43340_CHIP_ID 43340 /* 43340 chipcommon chipid */ 457 #define BCM43341_CHIP_ID 43341 /* 43341 chipcommon chipid */ 458 #define BCM43342_CHIP_ID 43342 /* 43342 chipcommon chipid */ 459 #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ 460 #define BCM43420_CHIP_ID 43420 /* 43420 chipcommon chipid (OTP, RBBU) */ 461 #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ 462 #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ 463 #define BCM43909_CHIP_ID 0xab85 /* 43909 chipcommon chipid */ 464 #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */ 465 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */ 466 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ 467 #endif /* DEPRECATED */ 468 469 /* DEPRECATED but still referenced in components - start */ 470 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */ 471 #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */ 472 /* DEPRECATED but still referenced in components - end */ 473 474 #define BCM43217_CHIP_ID 43217 /* 43217 chip id (OTP chipid) */ 475 #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */ 476 #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */ 477 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */ 478 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */ 479 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */ 480 #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ 481 #define BCM43460_CHIP_ID 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ 482 #define BCM43465_CHIP_ID 43465 /* 4366 chipcommon chipid (OTP, RBBU) */ 483 #define BCM43525_CHIP_ID 43525 /* 4365 chipcommon chipid (OTP, RBBU) */ 484 #define BCM47452_CHIP_ID 47452 /* 53573 chipcommon chipid (OTP, RBBU) */ 485 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */ 486 #define BCM4335_CHIP_ID 0x4335 /* 4335 chipcommon chipid */ 487 #define BCM4339_CHIP_ID 0x4339 /* 4339 chipcommon chipid */ 488 #define BCM4360_CHIP_ID 0x4360 /* 4360 chipcommon chipid */ 489 #define BCM4364_CHIP_ID 0x4364 /* 4364 chipcommon chipid */ 490 #define BCM4352_CHIP_ID 0x4352 /* 4352 chipcommon chipid */ 491 #define BCM43526_CHIP_ID 0xAA06 492 #define BCM4350_CHIP_ID 0x4350 /* 4350 chipcommon chipid */ 493 #define BCM4354_CHIP_ID 0x4354 /* 4354 chipcommon chipid */ 494 #define BCM4356_CHIP_ID 0x4356 /* 4356 chipcommon chipid */ 495 #define BCM4371_CHIP_ID 0x4371 /* 4371 chipcommon chipid */ 496 #define BCM43556_CHIP_ID 0xAA24 /* 43556 chipcommon chipid */ 497 #define BCM43558_CHIP_ID 0xAA26 /* 43558 chipcommon chipid */ 498 #define BCM43562_CHIP_ID 0xAA2A /* 43562 chipcommon chipid */ 499 #define BCM43566_CHIP_ID 0xAA2E /* 43566 chipcommon chipid */ 500 #define BCM43567_CHIP_ID 0xAA2F /* 43567 chipcommon chipid */ 501 #define BCM43568_CHIP_ID 0xAA30 /* 43568 chipcommon chipid */ 502 #define BCM43569_CHIP_ID 0xAA31 /* 43569 chipcommon chipid */ 503 #define BCM43570_CHIP_ID 0xAA32 /* 43570 chipcommon chipid */ 504 #define BCM4358_CHIP_ID 0x4358 /* 4358 chipcommon chipid */ 505 #define BCM43012_CHIP_ID 0xA804 /* 43012 chipcommon chipid */ 506 #define BCM43014_CHIP_ID 0xA806 /* 43014 chipcommon chipid */ 507 #define BCM4369_CHIP_ID 0x4369 /* 4369 chipcommon chipid */ 508 509 #define BCM4350_CHIP(chipid) ((CHIPID(chipid) == BCM4350_CHIP_ID) || \ 510 (CHIPID(chipid) == BCM4354_CHIP_ID) || \ 511 (CHIPID(chipid) == BCM43556_CHIP_ID) || \ 512 (CHIPID(chipid) == BCM43558_CHIP_ID) || \ 513 (CHIPID(chipid) == BCM43566_CHIP_ID) || \ 514 (CHIPID(chipid) == BCM43567_CHIP_ID) || \ 515 (CHIPID(chipid) == BCM43568_CHIP_ID) || \ 516 (CHIPID(chipid) == BCM43569_CHIP_ID) || \ 517 (CHIPID(chipid) == BCM43570_CHIP_ID) || \ 518 (CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */ 519 520 #define BCM4345_CHIP_ID 0x4345 /* 4345 chipcommon chipid */ 521 #define BCM43454_CHIP_ID 43454 /* 43454 chipcommon chipid */ 522 #define BCM43455_CHIP_ID 43455 /* 43455 chipcommon chipid */ 523 #define BCM43457_CHIP_ID 43457 /* 43457 chipcommon chipid */ 524 #define BCM43458_CHIP_ID 43458 /* 43458 chipcommon chipid */ 525 526 #define BCM4345_CHIP(chipid) (CHIPID(chipid) == BCM4345_CHIP_ID || \ 527 CHIPID(chipid) == BCM43454_CHIP_ID || \ 528 CHIPID(chipid) == BCM43455_CHIP_ID || \ 529 CHIPID(chipid) == BCM43457_CHIP_ID || \ 530 CHIPID(chipid) == BCM43458_CHIP_ID) 531 532 #define CASE_BCM4345_CHIP case BCM4345_CHIP_ID: /* fallthrough */ \ 533 case BCM43454_CHIP_ID: /* fallthrough */ \ 534 case BCM43455_CHIP_ID: /* fallthrough */ \ 535 case BCM43457_CHIP_ID: /* fallthrough */ \ 536 case BCM43458_CHIP_ID 537 538 #define BCM43430_CHIP_ID 43430 /* 43430 chipcommon chipid */ 539 #define BCM43018_CHIP_ID 43018 /* 43018 chipcommon chipid */ 540 #define BCM4349_CHIP_ID 0x4349 /* 4349 chipcommon chipid */ 541 #define BCM4355_CHIP_ID 0x4355 /* 4355 chipcommon chipid */ 542 #define BCM4359_CHIP_ID 0x4359 /* 4359 chipcommon chipid */ 543 #define BCM4349_CHIP(chipid) ((CHIPID(chipid) == BCM4349_CHIP_ID) || \ 544 (CHIPID(chipid) == BCM4355_CHIP_ID) || \ 545 (CHIPID(chipid) == BCM4359_CHIP_ID)) 546 547 #define BCM4355_CHIP(chipid) (CHIPID(chipid) == BCM4355_CHIP_ID) 548 549 #define BCM4349_CHIP_GRPID BCM4349_CHIP_ID: \ 550 case BCM4355_CHIP_ID: \ 551 case BCM4359_CHIP_ID 552 #define BCM43596_CHIP_ID 43596 /* 43596 chipcommon chipid */ 553 554 #ifdef CHIPS_CUSTOMER_HW6 555 #define BCM4368_CHIP_ID 0x4368 /* 4368 chipcommon chipid */ 556 #define BCM4368_CHIP(chipid) (CHIPID(chipid) == BCM4368_CHIP_ID) 557 #define BCM4368_CHIP_GRPID BCM4367_CHIP_ID: \ 558 case BCM4368_CHIP_ID 559 #endif /* CHIPS_CUSTOMER_HW6 */ 560 561 #define BCM4347_CHIP_ID 0x4347 /* 4347 chipcommon chipid */ 562 #define BCM4357_CHIP_ID 0x4357 /* 4357 chipcommon chipid */ 563 #define BCM4361_CHIP_ID 0x4361 /* 4361 chipcommon chipid */ 564 #define BCM4369_CHIP_ID 0x4369 /* 4369/ chipcommon chipid */ 565 #define BCM4373_CHIP_ID 0x4373 /* 4373/ chipcommon chipid */ 566 #define BCM4375_CHIP_ID 0x4375 /* 4375/ chipcommon chipid */ 567 #define BCM4377_CHIP_ID 0x4377 /* 4377/ chipcommon chipid */ 568 #define BCM4362_CHIP_ID 0x4362 /* 4362 chipcommon chipid */ 569 #define BCM43751_CHIP_ID 0xAAE7 /* 43751 chipcommon chipid */ 570 #ifdef CHIPS_CUSTOMER_HW6 571 #define BCM4369_CHIP_ID 0x4369 /* 4369/ chipcommon chipid */ 572 #define BCM4375_CHIP_ID 0x4375 /* 4375/ chipcommon chipid */ 573 #define BCM4376_CHIP_ID 0x4376 /* 4376 chipcommon chipid */ 574 #define BCM4377_CHIP_ID 0x4377 /* 4377/ chipcommon chipid */ 575 #define BCM4378_CHIP_ID 0x4378 /* 4378 chipcommon chipid */ 576 #define BCM4387_CHIP_ID 0x4387 /* 4387 chipcommon chipid */ 577 #endif /* CHIPS_CUSTOMER_HW6 */ 578 579 #define CYW55500_CHIP_ID 0xD8CC /* CYW55500 chipcommon chipid */ 580 #define CYW55560_CHIP_ID 0xD908 /* CYW55560 chipcommon chipid */ 581 582 #define BCM4347_CHIP(chipid) ((CHIPID(chipid) == BCM4347_CHIP_ID) || \ 583 (CHIPID(chipid) == BCM4357_CHIP_ID) || \ 584 (CHIPID(chipid) == BCM4361_CHIP_ID)) 585 #define BCM4347_CHIP_GRPID BCM4347_CHIP_ID: \ 586 case BCM4357_CHIP_ID: \ 587 case BCM4361_CHIP_ID 588 589 #define BCM4369_CHIP(chipid) ((CHIPID(chipid) == BCM4369_CHIP_ID) || \ 590 (CHIPID(chipid) == BCM4377_CHIP_ID)) 591 #define BCM4369_CHIP_GRPID BCM4369_CHIP_ID: \ 592 case BCM4377_CHIP_ID 593 594 #define BCM4362_CHIP(chipid) (CHIPID(chipid) == BCM4362_CHIP_ID) 595 #define BCM4362_CHIP_GRPID BCM4362_CHIP_ID 596 597 #ifdef CHIPS_CUSTOMER_HW6 598 #define BCM4378_CHIP(chipid) ((CHIPID(chipid) == BCM4378_CHIP_ID) || \ 599 (CHIPID(chipid) == BCM4376_CHIP_ID)) 600 #define BCM4378_CHIP_GRPID BCM4378_CHIP_ID: \ 601 case BCM4376_CHIP_ID 602 603 /* BCM4367 */ 604 #define BCM4367_CHIP_ID 0x4367 /* 4367 chipcommon chipid */ 605 #define CASE_BCM4367_CHIP case BCM4367_CHIP_ID 606 #define BCM4367_CHIP(chipid) (CHIPID(chipid) == BCM4367_CHIP_ID) 607 608 #define BCM4387_CHIP(chipid) (CHIPID(chipid) == BCM4387_CHIP_ID) 609 #define BCM4387_CHIP_GRPID BCM4387_CHIP_ID 610 #endif /* CHIPS_CUSTOMER_HW6 */ 611 612 #define BCM4365_CHIP_ID 0x4365 /* 4365 chipcommon chipid */ 613 #define BCM4366_CHIP_ID 0x4366 /* 4366 chipcommon chipid */ 614 #define BCM43664_CHIP_ID 43664 /* 4366E chipcommon chipid */ 615 #define BCM43666_CHIP_ID 43666 /* 4365E chipcommon chipid */ 616 #define BCM4365_CHIP(chipid) ((CHIPID(chipid) == BCM4365_CHIP_ID) || \ 617 (CHIPID(chipid) == BCM4366_CHIP_ID) || \ 618 (CHIPID(chipid) == BCM43664_CHIP_ID) || \ 619 (CHIPID(chipid) == BCM43666_CHIP_ID)) 620 #define CASE_BCM4365_CHIP case BCM4365_CHIP_ID: /* fallthrough */ \ 621 case BCM4366_CHIP_ID: /* fallthrough */ \ 622 case BCM43664_CHIP_ID: /* fallthrough */ \ 623 case BCM43666_CHIP_ID 624 625 #define BCM43602_CHIP_ID 0xaa52 /* 43602 chipcommon chipid */ 626 #define BCM43462_CHIP_ID 0xa9c6 /* 43462 chipcommon chipid */ 627 #define BCM43522_CHIP_ID 0xaa02 /* 43522 chipcommon chipid */ 628 #define BCM43602_CHIP(chipid) ((CHIPID(chipid) == BCM43602_CHIP_ID) || \ 629 (CHIPID(chipid) == BCM43462_CHIP_ID) || \ 630 (CHIPID(chipid) == BCM43522_CHIP_ID)) /* 43602 variations */ 631 #define BCM43012_CHIP(chipid) (CHIPID(chipid) == BCM43012_CHIP_ID) 632 #define CASE_BCM43602_CHIP case BCM43602_CHIP_ID: /* fallthrough */ \ 633 case BCM43462_CHIP_ID: /* fallthrough */ \ 634 case BCM43522_CHIP_ID 635 636 #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */ 637 #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */ 638 #define BCM4707_CHIP_ID 53010 /* 4707 chipcommon chipid */ 639 #define BCM47094_CHIP_ID 53030 /* 47094 chipcommon chipid */ 640 #define BCM53018_CHIP_ID 53018 /* 53018 chipcommon chipid */ 641 #define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || \ 642 ((chipid) == BCM53018_CHIP_ID) || \ 643 ((chipid) == BCM47094_CHIP_ID)) 644 #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */ 645 #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */ 646 #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */ 647 #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */ 648 #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */ 649 #define BCM53573_CHIP_ID 53573 /* 53573 chipcommon chipid */ 650 #define BCM53574_CHIP_ID 53574 /* 53574 chipcommon chipid */ 651 #define BCM53573_CHIP(chipid) ((CHIPID(chipid) == BCM53573_CHIP_ID) || \ 652 (CHIPID(chipid) == BCM53574_CHIP_ID) || \ 653 (CHIPID(chipid) == BCM47452_CHIP_ID)) 654 #define BCM53573_CHIP_GRPID BCM53573_CHIP_ID : \ 655 case BCM53574_CHIP_ID : \ 656 case BCM47452_CHIP_ID 657 #define BCM53573_DEVICE(devid) (((devid) == BCM53573_D11AC_ID) || \ 658 ((devid) == BCM53573_D11AC2G_ID) || \ 659 ((devid) == BCM53573_D11AC5G_ID) || \ 660 ((devid) == BCM47189_D11AC_ID) || \ 661 ((devid) == BCM47189_D11AC2G_ID) || \ 662 ((devid) == BCM47189_D11AC5G_ID)) 663 664 #define BCM7271_CHIP_ID 0x05c9 /* 7271 chipcommon chipid */ 665 #define BCM7271_CHIP(chipid) ((CHIPID(chipid) == BCM7271_CHIP_ID)) 666 667 #define BCM4373_CHIP_ID 0x4373 /* 4373 chipcommon chipid */ 668 669 /* Package IDs */ 670 #ifdef DEPRECATED /* These products have been deprecated */ 671 #define BCM4303_PKG_ID 2 /* 4303 package id */ 672 #define BCM4309_PKG_ID 1 /* 4309 package id */ 673 #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ 674 #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ 675 #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ 676 #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */ 677 #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */ 678 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */ 679 #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */ 680 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */ 681 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */ 682 #define BCM5354E_PKG_ID 1 /* 5354E package id */ 683 #define BCM4716_PKG_ID 8 /* 4716 package id */ 684 #define BCM4717_PKG_ID 9 /* 4717 package id */ 685 #define BCM4718_PKG_ID 10 /* 4718 package id */ 686 #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */ 687 #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */ 688 #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */ 689 #endif /* DEPRECATED */ 690 #define BCM47189_PKG_ID 1 /* 47189 package id */ 691 #define BCM53573_PKG_ID 0 /* 53573 package id */ 692 693 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ 694 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */ 695 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */ 696 697 #define BCM4707_PKG_ID 1 /* 4707 package id */ 698 #define BCM4708_PKG_ID 2 /* 4708 package id */ 699 #define BCM4709_PKG_ID 0 /* 4709 package id */ 700 701 #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */ 702 #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */ 703 704 #define BCM4335_WLCSP_PKG_ID (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ 705 #define BCM4335_FCBGA_PKG_ID (0x1) /* FCBGA PC/Embeded/Media PCIE/SDIO */ 706 #define BCM4335_WLBGA_PKG_ID (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ 707 #define BCM4335_FCBGAD_PKG_ID (0x3) /* FCBGA Debug Debug/Dev All if's. */ 708 #define BCM4335_PKG_MASK (0x3) 709 #define BCM43602_12x12_PKG_ID (0x1) /* 12x12 pins package, used for e.g. router designs */ 710 711 /* boardflags */ 712 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ 713 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ 714 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ 715 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio radio disable indication */ 716 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ 717 #define BFL_DIS_256QAM 0x00000008 718 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ 719 #define BFL_TSSIAVG 0x00000010 /* TSSI averaging for ACPHY chips */ 720 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ 721 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ 722 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ 723 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ 724 #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */ 725 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 726 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */ 727 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 728 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */ 729 #define BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios */ 730 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ 731 #define BFL_NOPA 0x00010000 /* Board has no PA */ 732 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ 733 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ 734 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ 735 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ 736 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ 737 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ 738 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ 739 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ 740 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */ 741 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ 742 #define BFL_FASTPWR 0x08000000 743 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ 744 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 745 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ 746 #define BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 747 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ 748 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field 749 * when this flag is set 750 */ 751 #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ 752 753 /* boardflags2 */ 754 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ 755 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 756 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ 757 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ 758 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ 759 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ 760 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ 761 #define BFL2_WLCX_ATLAS 0x00000040 /* Board flag to initialize ECI for WLCX on FL-ATLAS */ 762 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ 763 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace 764 * BFL2_BTC3WIRE 765 */ 766 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ 767 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ 768 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ 769 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ 770 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 771 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ 772 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ 773 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ 774 #define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000 /* Reducing DAC Spurs */ 775 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ 776 #define BFL2_REDUCED_PA_TURNONTIME 0x00010000 /* Flag to reduce PA turn on Time */ 777 #define BFL2_IPALVLSHIFT_3P3 0x00020000 778 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ 779 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ 780 /* Most drivers will turn it off without this flag */ 781 /* to save power. */ 782 783 #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ 784 #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ 785 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ 786 #define BFL2_BT_SHARE_ANT0 0x00800000 /* share core0 antenna with BT */ 787 #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value 788 * than programmed. The exact delta is decided by 789 * driver per chip/boardtype. This can be used 790 * when tempsense qualification happens after shipment 791 */ 792 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ 793 #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ 794 #define BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save */ 795 /* ucode control of eLNA during Tx */ 796 #define BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ 797 #define BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ 798 #define BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ 799 #define BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ 800 801 /* SROM 11 - 11ac boardflag definitions */ 802 #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ 803 #define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ 804 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 805 #define BFL_SROM11_EPA_TURNON_TIME 0x00018000 /* 2 bits for different PA turn on times */ 806 #define BFL_SROM11_EPA_TURNON_TIME_SHIFT 15 807 #define BFL_SROM11_PRECAL_TX_IDX 0x00040000 /* Dedicated TX IQLOCAL IDX values */ 808 /* per subband, as derived from 43602A1 MCH5 */ 809 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 810 #define BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 811 #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 812 #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ 813 #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ 814 #define BFL2_SROM11_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 815 #define BFL2_SROM11_EPA_ON_DURING_TXIQLOCAL 0x00020000 /* Keep ext. PA's on in TX IQLO CAL */ 816 817 /* boardflags3 */ 818 #define BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ 819 #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ 820 #define BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ 821 #define BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ 822 #define BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Seperate paparam for 20/40/80 */ 823 #define BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Seperate paparam for 20/40/80 shift bit */ 824 #define BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ 825 #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ 826 #define BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ 827 #define BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ 828 #define BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ 829 #define BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ 830 #define BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ 831 #define BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ 832 #define BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ 833 #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ 834 #define BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ 835 #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ 836 #define BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ 837 #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ 838 /* acphy, to use backed off gaintbl for lte-coex */ 839 #define BFL3_LTECOEX_GAINTBL_EN 0x00060000 840 /* acphy, to use backed off gaintbl for lte-coex */ 841 #define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17 842 #define BFL3_5G_SPUR_WAR 0x00080000 /* acphy, enable spur WAR in 5G band */ 843 #define BFL3_1X1_RSDB_ANT 0x01000000 /* to find if 2-ant RSDB board or 1-ant RSDB board */ 844 #define BFL3_1X1_RSDB_ANT_SHIFT 24 845 846 /* acphy: lpmode2g and lpmode_5g related boardflags */ 847 #define BFL3_ACPHY_LPMODE_2G 0x00300000 /* bits 20:21 for lpmode_2g choice */ 848 #define BFL3_ACPHY_LPMODE_2G_SHIFT 20 849 850 #define BFL3_ACPHY_LPMODE_5G 0x00C00000 /* bits 22:23 for lpmode_5g choice */ 851 #define BFL3_ACPHY_LPMODE_5G_SHIFT 22 852 853 #define BFL3_EXT_LPO_ISCLOCK 0x02000000 /* External LPO is clock, not x-tal */ 854 #define BFL3_FORCE_INT_LPO_SEL 0x04000000 /* Force internal lpo */ 855 #define BFL3_FORCE_EXT_LPO_SEL 0x08000000 /* Force external lpo */ 856 857 #define BFL3_EN_BRCM_IMPBF 0x10000000 /* acphy, Allow BRCM Implicit TxBF */ 858 #define BFL3_AVVMID_FROM_NVRAM 0x40000000 /* Read Av Vmid from NVRAM */ 859 #define BFL3_VLIN_EN_FROM_NVRAM 0x80000000 /* Read Vlin En from NVRAM */ 860 861 #define BFL3_AVVMID_FROM_NVRAM_SHIFT 30 /* Read Av Vmid from NVRAM */ 862 #define BFL3_VLIN_EN_FROM_NVRAM_SHIFT 31 /* Enable Vlin from NVRAM */ 863 864 /* boardflags4 for SROM12/SROM13 */ 865 #define BFL4_SROM12_4dBPAD (1 << 0) /* To distinguigh between normal and 4dB pad board */ 866 #define BFL4_SROM12_2G_DETTYPE (1 << 1) /* Determine power detector type for 2G */ 867 #define BFL4_SROM12_5G_DETTYPE (1 << 2) /* Determine power detector type for 5G */ 868 #define BFL4_SROM13_DETTYPE_EN (1 << 3) /* using pa_dettype from SROM13 flags */ 869 #define BFL4_SROM13_CCK_SPUR_EN (1 << 4) /* using cck spur reduction setting in 4366 */ 870 #define BFL4_SROM13_1P5V_CBUCK (1 << 7) /* using 1.5V cbuck board in 4366 */ 871 #define BFL4_SROM13_EN_SW_TXRXCHAIN_MASK (1 << 8) /* Enable/disable bit for sw chain mask */ 872 873 #define BFL4_4364_HARPOON 0x0100 /* Harpoon module 4364 */ 874 #define BFL4_4364_GODZILLA 0x0200 /* Godzilla module 4364 */ 875 #define BFL4_BTCOEX_OVER_SECI 0x00000400 /* Enable btcoex over gci seci */ 876 877 /* papd params */ 878 #define PAPD_TX_ATTN_2G 0xFF 879 #define PAPD_TX_ATTN_5G 0xFF00 880 #define PAPD_TX_ATTN_5G_SHIFT 8 881 #define PAPD_RX_ATTN_2G 0xFF 882 #define PAPD_RX_ATTN_5G 0xFF00 883 #define PAPD_RX_ATTN_5G_SHIFT 8 884 #define PAPD_CAL_IDX_2G 0xFF 885 #define PAPD_CAL_IDX_5G 0xFF00 886 #define PAPD_CAL_IDX_5G_SHIFT 8 887 #define PAPD_BBMULT_2G 0xFF 888 #define PAPD_BBMULT_5G 0xFF00 889 #define PAPD_BBMULT_5G_SHIFT 8 890 #define TIA_GAIN_MODE_2G 0xFF 891 #define TIA_GAIN_MODE_5G 0xFF00 892 #define TIA_GAIN_MODE_5G_SHIFT 8 893 #define PAPD_EPS_OFFSET_2G 0xFFFF 894 #define PAPD_EPS_OFFSET_5G 0xFFFF0000 895 #define PAPD_EPS_OFFSET_5G_SHIFT 16 896 #define PAPD_CALREF_DB_2G 0xFF 897 #define PAPD_CALREF_DB_5G 0xFF00 898 #define PAPD_CALREF_DB_5G_SHIFT 8 899 900 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ 901 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ 902 #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ 903 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ 904 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ 905 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ 906 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ 907 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ 908 #define BOARD_GPIO_12 0x1000 /* gpio 12 */ 909 #define BOARD_GPIO_13 0x2000 /* gpio 13 */ 910 #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */ 911 #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ 912 #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ 913 #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ 914 #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ 915 #define BOARD_GPIO_2_WLAN_PWR 0x04 /* throttle WLAN power on X29C board */ 916 #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ 917 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ 918 #define BOARD_GPIO_13_WLAN_PWR 0x2000 /* throttle WLAN power on X14 board */ 919 920 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ 921 922 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 923 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ 924 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 925 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */ 926 927 /* power control defines */ 928 #define PLL_DELAY 150 /* us pll on delay */ 929 #define FREF_DELAY 200 /* us fref change delay */ 930 #define MIN_SLOW_CLK 32 /* us Slow clock period */ 931 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ 932 933 /* 43012 wlbga Board */ 934 #define BCM943012WLREF_SSID 0x07d7 935 936 /* 43012 fcbga Board */ 937 #define BCM943012FCREF_SSID 0x07d4 938 939 /* 43602 Boards, unclear yet what boards will be created. */ 940 #define BCM943602RSVD1_SSID 0x06a5 941 #define BCM943602RSVD2_SSID 0x06a6 942 #define BCM943602X87 0X0133 943 #define BCM943602X87P2 0X0152 944 #define BCM943602X87P3 0X0153 945 #define BCM943602X238 0X0132 946 #define BCM943602X238D 0X014A 947 #define BCM943602X238DP2 0X0155 948 #define BCM943602X238DP3 0X0156 949 #define BCM943602X100 0x0761 950 #define BCM943602X100GS 0x0157 951 #define BCM943602X100P2 0x015A 952 953 /* # of GPIO pins */ 954 #define GPIO_NUMPINS 32 955 956 /* These values are used by dhd host driver. */ 957 #define RDL_RAM_BASE_4319 0x60000000 958 #define RDL_RAM_BASE_4329 0x60000000 959 #define RDL_RAM_SIZE_4319 0x48000 960 #define RDL_RAM_SIZE_4329 0x48000 961 #define RDL_RAM_SIZE_43236 0x70000 962 #define RDL_RAM_BASE_43236 0x60000000 963 #define RDL_RAM_SIZE_4328 0x60000 964 #define RDL_RAM_BASE_4328 0x80000000 965 #define RDL_RAM_SIZE_4322 0x60000 966 #define RDL_RAM_BASE_4322 0x60000000 967 #define RDL_RAM_SIZE_4360 0xA0000 968 #define RDL_RAM_BASE_4360 0x60000000 969 #define RDL_RAM_SIZE_43143 0x70000 970 #define RDL_RAM_BASE_43143 0x60000000 971 #define RDL_RAM_SIZE_4350 0xC0000 972 #define RDL_RAM_BASE_4350 0x180800 973 974 /* generic defs for nvram "muxenab" bits 975 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. 976 */ 977 #define MUXENAB_UART 0x00000001 978 #define MUXENAB_GPIO 0x00000002 979 #define MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ 980 #define MUXENAB_JTAG 0x00000008 981 #define MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ 982 #define MUXENAB_I2S_EN 0x00000020 983 #define MUXENAB_I2S_MASTER 0x00000040 984 #define MUXENAB_I2S_FULL 0x00000080 985 #define MUXENAB_SFLASH 0x00000100 986 #define MUXENAB_RFSWCTRL0 0x00000200 987 #define MUXENAB_RFSWCTRL1 0x00000400 988 #define MUXENAB_RFSWCTRL2 0x00000800 989 #define MUXENAB_SECI 0x00001000 990 #define MUXENAB_BT_LEGACY 0x00002000 991 #define MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ 992 993 /* Boot flags */ 994 #define FLASH_KERNEL_NFLASH 0x00000001 995 #define FLASH_BOOT_NFLASH 0x00000002 996 997 #endif /* _BCMDEVS_H */ 998