1 /** @file mlan_decl.h 2 * 3 * @brief This file declares the generic data structures and APIs. 4 * 5 * 6 * Copyright 2008-2022 NXP 7 * 8 * This software file (the File) is distributed by NXP 9 * under the terms of the GNU General Public License Version 2, June 1991 10 * (the License). You may use, redistribute and/or modify the File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 * 21 */ 22 23 #ifndef _MLAN_DECL_H_ 24 #define _MLAN_DECL_H_ 25 26 /** MLAN release version */ 27 #define MLAN_RELEASE_VERSION "366.p5" 28 29 /** Re-define generic data types for MLAN/MOAL */ 30 /** Signed char (1-byte) */ 31 typedef signed char t_s8, *t_ps8; 32 /** Unsigned char (1-byte) */ 33 typedef unsigned char t_u8, *t_pu8; 34 /** Signed short (2-bytes) */ 35 typedef short t_s16, *t_ps16; 36 /** Unsigned short (2-bytes) */ 37 typedef unsigned short t_u16, *t_pu16; 38 /** Signed long (4-bytes) */ 39 typedef int t_s32, *t_ps32; 40 /** Unsigned long (4-bytes) */ 41 typedef unsigned int t_u32, *t_pu32; 42 /** Signed long long 8-bytes) */ 43 typedef long long t_s64, *t_ps64; 44 /** Unsigned long long 8-bytes) */ 45 typedef unsigned long long t_u64, *t_pu64; 46 /** Void pointer (4-bytes) */ 47 typedef void t_void, *t_pvoid; 48 /** Size type */ 49 typedef t_u32 t_size; 50 /** Boolean type */ 51 typedef t_u8 t_bool; 52 53 #ifdef MLAN_64BIT 54 /** Pointer type (64-bit) */ 55 typedef t_u64 t_ptr; 56 /** Signed value (64-bit) */ 57 typedef t_s64 t_sval; 58 #else 59 /** Pointer type (32-bit) */ 60 typedef t_u32 t_ptr; 61 /** Signed value (32-bit) */ 62 typedef t_s32 t_sval; 63 #endif 64 65 /** Constants below */ 66 67 #ifdef __GNUC__ 68 /** Structure packing begins */ 69 #define MLAN_PACK_START 70 /** Structure packeing end */ 71 #define MLAN_PACK_END __attribute__((packed)) 72 #else /* !__GNUC__ */ 73 #ifdef PRAGMA_PACK 74 /** Structure packing begins */ 75 #define MLAN_PACK_START 76 /** Structure packeing end */ 77 #define MLAN_PACK_END 78 #else /* !PRAGMA_PACK */ 79 /** Structure packing begins */ 80 #define MLAN_PACK_START __packed 81 /** Structure packing end */ 82 #define MLAN_PACK_END 83 #endif /* PRAGMA_PACK */ 84 #endif /* __GNUC__ */ 85 86 #ifndef INLINE 87 #ifdef __GNUC__ 88 /** inline directive */ 89 #define INLINE inline 90 #else 91 /** inline directive */ 92 #define INLINE __inline 93 #endif 94 #endif 95 96 /** MLAN TRUE */ 97 #define MTRUE (1) 98 /** MLAN FALSE */ 99 #define MFALSE (0) 100 101 #define CHANNEL_SPEC_SNIFFER_MODE 1 102 103 #ifndef MACSTR 104 /** MAC address security format */ 105 #define MACSTR "%02x:XX:XX:XX:%02x:%02x" 106 #endif 107 108 #ifndef MAC2STR 109 /** MAC address security print arguments */ 110 #define MAC2STR(a) (a)[0], (a)[4], (a)[5] 111 #endif 112 113 #ifndef FULL_MACSTR 114 #define FULL_MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" 115 #endif 116 #ifndef FULL_MAC2STR 117 #define FULL_MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] 118 #endif 119 120 /** Macros for Data Alignment : size */ 121 #define ALIGN_SZ(p, a) (((p) + ((a)-1)) & ~((a)-1)) 122 123 /** Macros for Data Alignment : address */ 124 #define ALIGN_ADDR(p, a) \ 125 ((((t_ptr)(p)) + (((t_ptr)(a)) - 1)) & ~(((t_ptr)(a)) - 1)) 126 127 /** Return the byte offset of a field in the given structure */ 128 #define MLAN_FIELD_OFFSET(type, field) ((t_u32)(t_ptr) & (((type *)0)->field)) 129 /** Return aligned offset */ 130 #define OFFSET_ALIGN_ADDR(p, a) (t_u32)(ALIGN_ADDR(p, a) - (t_ptr)p) 131 132 /** Maximum BSS numbers */ 133 #define MLAN_MAX_BSS_NUM (16) 134 135 /** NET IP alignment */ 136 #define MLAN_NET_IP_ALIGN 2 137 138 /** US country code */ 139 #define COUNTRY_CODE_US 0x10 140 141 /** DMA alignment */ 142 /* SDIO3.0 Inrevium Adapter require 32 bit DMA alignment */ 143 #define DMA_ALIGNMENT 32 144 145 /** max size of TxPD */ 146 #define MAX_TXPD_SIZE 32 147 148 /** Minimum data header length */ 149 #define MLAN_MIN_DATA_HEADER_LEN (DMA_ALIGNMENT + MAX_TXPD_SIZE) 150 151 /** rx data header length */ 152 #define MLAN_RX_HEADER_LEN MLAN_MIN_DATA_HEADER_LEN 153 154 /** This is current limit on Maximum Tx AMPDU allowed */ 155 #define MLAN_MAX_TX_BASTREAM_SUPPORTED 16 156 #define MLAN_MAX_TX_BASTREAM_DEFAULT 2 157 /** This is current limit on Maximum Rx AMPDU allowed */ 158 #define MLAN_MAX_RX_BASTREAM_SUPPORTED 16 159 160 #ifdef STA_SUPPORT 161 /** Default Win size attached during ADDBA request */ 162 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 64 163 /** Default Win size attached during ADDBA response */ 164 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 64 165 /** RX winsize for COEX */ 166 #define MLAN_STA_COEX_AMPDU_DEF_RXWINSIZE 16 167 #endif /* STA_SUPPORT */ 168 #ifdef UAP_SUPPORT 169 /** Default Win size attached during ADDBA request */ 170 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 64 171 /** Default Win size attached during ADDBA response */ 172 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 64 173 /** RX winsize for COEX */ 174 #define MLAN_UAP_COEX_AMPDU_DEF_RXWINSIZE 16 175 #endif /* UAP_SUPPORT */ 176 177 #ifdef WIFI_DIRECT_SUPPORT 178 /** WFD use the same window size for tx/rx */ 179 #define MLAN_WFD_AMPDU_DEF_TXRXWINSIZE 64 180 /** RX winsize for COEX */ 181 #define MLAN_WFD_COEX_AMPDU_DEF_RXWINSIZE 16 182 #endif 183 184 /** Block ack timeout value */ 185 #define MLAN_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff 186 /** Maximum Tx Win size configured for ADDBA request [10 bits] */ 187 #define MLAN_AMPDU_MAX_TXWINSIZE 0x3ff 188 /** Maximum Rx Win size configured for ADDBA request [10 bits] */ 189 #define MLAN_AMPDU_MAX_RXWINSIZE 0x3ff 190 191 /** Rate index for HR/DSSS 0 */ 192 #define MLAN_RATE_INDEX_HRDSSS0 0 193 /** Rate index for HR/DSSS 3 */ 194 #define MLAN_RATE_INDEX_HRDSSS3 3 195 /** Rate index for OFDM 0 */ 196 #define MLAN_RATE_INDEX_OFDM0 4 197 /** Rate index for OFDM 7 */ 198 #define MLAN_RATE_INDEX_OFDM7 11 199 /** Rate index for MCS 0 */ 200 #define MLAN_RATE_INDEX_MCS0 0 201 /** Rate index for MCS 2 */ 202 #define MLAN_RATE_INDEX_MCS2 2 203 /** Rate index for MCS 4 */ 204 #define MLAN_RATE_INDEX_MCS4 4 205 /** Rate index for MCS 7 */ 206 #define MLAN_RATE_INDEX_MCS7 7 207 /** Rate index for MCS 9 */ 208 #define MLAN_RATE_INDEX_MCS9 9 209 /** Rate index for MCS11 */ 210 #define MLAN_RATE_INDEX_MCS11 11 211 /** Rate index for MCS15 */ 212 #define MLAN_RATE_INDEX_MCS15 15 213 /** Rate index for MCS 32 */ 214 #define MLAN_RATE_INDEX_MCS32 32 215 /** Rate index for MCS 127 */ 216 #define MLAN_RATE_INDEX_MCS127 127 217 #define MLAN_RATE_NSS1 1 218 #define MLAN_RATE_NSS2 2 219 220 /** Rate bitmap for OFDM 0 */ 221 #define MLAN_RATE_BITMAP_OFDM0 16 222 /** Rate bitmap for OFDM 7 */ 223 #define MLAN_RATE_BITMAP_OFDM7 23 224 /** Rate bitmap for MCS 0 */ 225 #define MLAN_RATE_BITMAP_MCS0 32 226 /** Rate bitmap for MCS 127 */ 227 #define MLAN_RATE_BITMAP_MCS127 159 228 #define MLAN_RATE_BITMAP_NSS1_MCS0 160 229 #define MLAN_RATE_BITMAP_NSS1_MCS9 169 230 #define MLAN_RATE_BITMAP_NSS2_MCS0 176 231 #define MLAN_RATE_BITMAP_NSS2_MCS9 185 232 233 /** MU beamformer */ 234 #define DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK (MBIT(19)) 235 236 /** Size of rx data buffer 3839+256 */ 237 #define MLAN_RX_DATA_BUF_SIZE 4096 238 239 /** Size of command buffer */ 240 /** because cal_data_size 2.4 k */ 241 #define MRVDRV_SIZE_OF_CMD_BUFFER (3 * 1024) 242 /** Size of rx command buffer */ 243 #define MLAN_RX_CMD_BUF_SIZE MRVDRV_SIZE_OF_CMD_BUFFER 244 /** Upload size */ 245 #define WLAN_UPLD_SIZE MRVDRV_SIZE_OF_CMD_BUFFER 246 247 #if defined(PCIE) 248 #define MLAN_SSU_MAX_PKT_SIZE (283 * 4) 249 #define MLAN_SSU_HEADER_SIZE 256 250 /** 251 * Size of DMA buffer to collect 10ms SSU data: 252 * 2500 spectral packets, plus header 253 */ 254 #define MLAN_SSU_BUF_SIZE_1MS (MLAN_SSU_MAX_PKT_SIZE * 250) 255 #define MLAN_SSU_BUF_SIZE (MLAN_SSU_HEADER_SIZE + MLAN_SSU_BUF_SIZE_1MS * 10) 256 #define MLAN_SSU_BUF_SIZE_HOST (MLAN_SSU_BUF_SIZE) 257 #endif 258 259 /** driver initial the fw reset */ 260 #define FW_RELOAD_SDIO_INBAND_RESET 1 261 /** out band reset trigger reset, no interface re-emulation */ 262 #define FW_RELOAD_NO_EMULATION 2 263 /** out band reset with interface re-emulation */ 264 #define FW_RELOAD_WITH_EMULATION 3 265 #ifdef PCIE 266 /** pcie card reset */ 267 #define FW_RELOAD_PCIE_RESET 4 268 #endif 269 #define FW_RELOAD_SDIO_HW_RESET 5 270 271 #ifdef USB 272 #define MLAN_USB_BLOCK_SIZE (512) 273 #define MLAN_USB_AGGR_MODE_NUM (0) 274 #define MLAN_USB_AGGR_MODE_LEN (1) 275 #define MLAN_USB_AGGR_MODE_LEN_V2 (2) 276 #define MLAN_USB_TX_AGGR_MAX_LEN (16000) 277 #define MLAN_USB_TX_AGGR_MAX_NUM 10 278 #define MLAN_USB_TX_AGGR_V2_ALIGN 4 279 #define MLAN_USB_TX_AGGR_HEADER 4 280 #define MLAN_USB_MAX_PKT_SIZE (MLAN_USB_BLOCK_SIZE * 4) 281 282 #define MLAN_USB_RX_ALIGN_SIZE MLAN_USB_BLOCK_SIZE 283 #define MLAN_USB_RX_MAX_AGGR_NUM (8) 284 #define MLAN_USB_RX_DEAGGR_TIMEOUT_USEC (200) 285 286 #define MLAN_USB_TX_AGGR_ALIGN (MLAN_USB_BLOCK_SIZE * 4) 287 #define MLAN_USB_TX_MAX_AGGR_NUM (8) 288 #define MLAN_USB_TX_MAX_AGGR_SIZE \ 289 (MLAN_USB_BLOCK_SIZE * 4 * MLAN_USB_TX_MAX_AGGR_NUM) 290 #define MLAN_USB_TX_MIN_AGGR_TIMEOUT (1) 291 #define MLAN_USB_TX_MAX_AGGR_TIMEOUT (4) 292 #define MLAN_USB_TX_AGGR_TIMEOUT_MSEC MLAN_USB_TX_MIN_AGGR_TIMEOUT 293 #define MLAN_USB_TX_AGGR_TIMEOUT_DYN (0xFFFF) 294 #endif /*USB*/ 295 296 /** MLAN MAC Address Length */ 297 #define MLAN_MAC_ADDR_LENGTH (6) 298 /** MLAN 802.11 MAC Address */ 299 typedef t_u8 mlan_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH]; 300 301 /** MLAN Maximum SSID Length */ 302 #define MLAN_MAX_SSID_LENGTH (32) 303 304 /** RTS/FRAG related defines */ 305 /** Minimum RTS value */ 306 #define MLAN_RTS_MIN_VALUE (0) 307 /** Maximum RTS value */ 308 #define MLAN_RTS_MAX_VALUE (2347) 309 /** Minimum FRAG value */ 310 #define MLAN_FRAG_MIN_VALUE (256) 311 /** Maximum FRAG value */ 312 #define MLAN_FRAG_MAX_VALUE (2346) 313 314 /** Minimum tx retry count */ 315 #define MLAN_TX_RETRY_MIN (0) 316 /** Maximum tx retry count */ 317 #define MLAN_TX_RETRY_MAX (14) 318 319 /** max Wmm AC queues */ 320 #define MAX_AC_QUEUES 4 321 322 #ifdef SDIO 323 /** define SDIO block size for data Tx/Rx */ 324 /* We support up to 480-byte block size due to FW buffer limitation. */ 325 #define MLAN_SDIO_BLOCK_SIZE 256 326 327 /** define SDIO block size for firmware download */ 328 #define MLAN_SDIO_BLOCK_SIZE_FW_DNLD MLAN_SDIO_BLOCK_SIZE 329 330 /** define allocated buffer size */ 331 #define ALLOC_BUF_SIZE MLAN_RX_DATA_BUF_SIZE 332 /** SDIO MP aggr pkt limit */ 333 #define SDIO_MP_AGGR_DEF_PKT_LIMIT (16) 334 /** SDIO MP aggr pkt limit 8 */ 335 #define SDIO_MP_AGGR_DEF_PKT_LIMIT_8 (8) 336 /** max SDIO MP aggr pkt limit */ 337 #define SDIO_MP_AGGR_DEF_PKT_LIMIT_MAX (16) 338 339 /** SDIO IO Port mask */ 340 #define MLAN_SDIO_IO_PORT_MASK 0xfffff 341 /** SDIO Block/Byte mode mask */ 342 #define MLAN_SDIO_BYTE_MODE_MASK 0x80000000 343 #endif /* SDIO */ 344 345 /** SD Interface */ 346 #define INTF_SD MBIT(0) 347 #define IS_SD(ct) (ct & (INTF_SD << 8)) 348 /** PCIE Interface */ 349 #define INTF_PCIE MBIT(1) 350 #define IS_PCIE(ct) (ct & (INTF_PCIE << 8)) 351 /** USB Interface */ 352 #define INTF_USB MBIT(2) 353 #define IS_USB(ct) (ct & (INTF_USB << 8)) 354 355 /** 8887 card type */ 356 #define CARD_TYPE_8887 0x01 357 /** 8897 card type */ 358 #define CARD_TYPE_8897 0x02 359 /** 8977 card type */ 360 #define CARD_TYPE_8977 0x03 361 /** 8997 card type */ 362 #define CARD_TYPE_8997 0x04 363 /** 8987 card type */ 364 #define CARD_TYPE_8987 0x05 365 /** 9098 card type */ 366 #define CARD_TYPE_9098 0x06 367 /** 9097 card type */ 368 #define CARD_TYPE_9097 0x07 369 /** 8978 card type */ 370 #define CARD_TYPE_8978 0x08 371 /** 9177 card type */ 372 #define CARD_TYPE_9177 0x09 373 /** 8801 card type */ 374 #define CARD_TYPE_8801 0x0a 375 /** OWL card type */ 376 #define CARD_TYPE_NW62X 0x0b 377 378 /** 9098 A0 reverion num */ 379 #define CHIP_9098_REV_A0 1 380 #define CHIP_9098_REV_A1 2 381 /** 9097 CHIP REV */ 382 #define CHIP_9097_REV_B0 1 383 384 #define INTF_MASK 0xff 385 #define CARD_TYPE_MASK 0xff 386 387 #ifdef SDIO 388 /** SD8887 card type */ 389 #define CARD_TYPE_SD8887 (CARD_TYPE_8887 | (INTF_SD << 8)) 390 /** SD8897 card type */ 391 #define CARD_TYPE_SD8897 (CARD_TYPE_8897 | (INTF_SD << 8)) 392 /** SD8977 card type */ 393 #define CARD_TYPE_SD8977 (CARD_TYPE_8977 | (INTF_SD << 8)) 394 /** SD8978 card type */ 395 #define CARD_TYPE_SD8978 (CARD_TYPE_8978 | (INTF_SD << 8)) 396 /** SD8997 card type */ 397 #define CARD_TYPE_SD8997 (CARD_TYPE_8997 | (INTF_SD << 8)) 398 /** SD8987 card type */ 399 #define CARD_TYPE_SD8987 (CARD_TYPE_8987 | (INTF_SD << 8)) 400 /** SD9097 card type */ 401 #define CARD_TYPE_SD9097 (CARD_TYPE_9097 | (INTF_SD << 8)) 402 /** SD9098 card type */ 403 #define CARD_TYPE_SD9098 (CARD_TYPE_9098 | (INTF_SD << 8)) 404 /** SD9177 card type */ 405 #define CARD_TYPE_SD9177 (CARD_TYPE_9177 | (INTF_SD << 8)) 406 /** SD8801 card type */ 407 #define CARD_TYPE_SD8801 (CARD_TYPE_8801 | (INTF_SD << 8)) 408 /** SD_NW62X card type */ 409 #define CARD_TYPE_SDNW62X (CARD_TYPE_NW62X | (INTF_SD << 8)) 410 411 #define IS_SD8887(ct) (CARD_TYPE_SD8887 == (ct)) 412 #define IS_SD8897(ct) (CARD_TYPE_SD8897 == (ct)) 413 #define IS_SD8977(ct) (CARD_TYPE_SD8977 == (ct)) 414 #define IS_SD8978(ct) (CARD_TYPE_SD8978 == (ct)) 415 #define IS_SD8997(ct) (CARD_TYPE_SD8997 == (ct)) 416 #define IS_SD8987(ct) (CARD_TYPE_SD8987 == (ct)) 417 #define IS_SD9097(ct) (CARD_TYPE_SD9097 == (ct)) 418 #define IS_SD9098(ct) (CARD_TYPE_SD9098 == (ct)) 419 #define IS_SD9177(ct) (CARD_TYPE_SD9177 == (ct)) 420 #define IS_SD8801(ct) (CARD_TYPE_SD8801 == (ct)) 421 #define IS_SDNW62X(ct) (CARD_TYPE_SDNW62X == (ct)) 422 423 /** SD8887 Card */ 424 #define CARD_SD8887 "SD8887" 425 /** SD8897 Card */ 426 #define CARD_SD8897 "SD8897" 427 /** SD8977 Card */ 428 #define CARD_SD8977 "SD8977" 429 /** SD8978 Card */ 430 #define CARD_SD8978 "SDIW416" 431 /** SD8997 Card */ 432 #define CARD_SD8997 "SD8997" 433 /** SD8987 Card */ 434 #define CARD_SD8987 "SD8987" 435 /** SD9097 Card */ 436 #define CARD_SD9097 "SDIW620" 437 /** SD9098 Card */ 438 #define CARD_SD9098 "SD9098" 439 /** SD9177 Card */ 440 #define CARD_SD9177 "SDIW612" 441 /** SD8801 Card */ 442 #define CARD_SD8801 "SD8801" 443 /** SDNW62X Card */ 444 #define CARD_SDNW62X "SDNW62X" 445 #endif 446 447 #ifdef PCIE 448 /** PCIE8897 card type */ 449 #define CARD_TYPE_PCIE8897 (CARD_TYPE_8897 | (INTF_PCIE << 8)) 450 /** PCIE8997 card type */ 451 #define CARD_TYPE_PCIE8997 (CARD_TYPE_8997 | (INTF_PCIE << 8)) 452 /** PCIE9097 card type */ 453 #define CARD_TYPE_PCIE9097 (CARD_TYPE_9097 | (INTF_PCIE << 8)) 454 /** PCIE9098 card type */ 455 #define CARD_TYPE_PCIE9098 (CARD_TYPE_9098 | (INTF_PCIE << 8)) 456 /** PCIENW62X card type */ 457 #define CARD_TYPE_PCIENW62X (CARD_TYPE_NW62X | (INTF_PCIE << 8)) 458 459 #define IS_PCIE8897(ct) (CARD_TYPE_PCIE8897 == (ct)) 460 #define IS_PCIE8997(ct) (CARD_TYPE_PCIE8997 == (ct)) 461 #define IS_PCIE9097(ct) (CARD_TYPE_PCIE9097 == (ct)) 462 #define IS_PCIE9098(ct) (CARD_TYPE_PCIE9098 == (ct)) 463 #define IS_PCIENW62X(ct) (CARD_TYPE_PCIENW62X == (ct)) 464 465 /** PCIE8897 Card */ 466 #define CARD_PCIE8897 "PCIE8897" 467 /** PCIE8997 Card */ 468 #define CARD_PCIE8997 "PCIE8997" 469 /** PCIE9097 Card */ 470 #define CARD_PCIE9097 "PCIEIW620" 471 /** PCIE9000S Card */ 472 #define CARD_PCIE9000S "PCIE9000S" 473 /** PCIE9098 Card */ 474 #define CARD_PCIE9098 "PCIE9098" 475 /** PCIEAW690 Card */ 476 #define CARD_PCIEAW690 "PCIEAW690" 477 /** PCIENW62X Card */ 478 #define CARD_PCIENW62X "PCIENW62X" 479 /** PCIEIW629 Card */ 480 #define CARD_PCIEIW629 "PCIEIW629" 481 #endif 482 483 #ifdef USB 484 /** USB8801 card type */ 485 #define CARD_TYPE_USB8801 (CARD_TYPE_8801 | (INTF_USB << 8)) 486 /** USB8897 card type */ 487 #define CARD_TYPE_USB8897 (CARD_TYPE_8897 | (INTF_USB << 8)) 488 /** USB8997 card type */ 489 #define CARD_TYPE_USB8997 (CARD_TYPE_8997 | (INTF_USB << 8)) 490 /** USB8978 card type */ 491 #define CARD_TYPE_USB8978 (CARD_TYPE_8978 | (INTF_USB << 8)) 492 /** USB9098 card type */ 493 #define CARD_TYPE_USB9098 (CARD_TYPE_9098 | (INTF_USB << 8)) 494 /** USB9097 card type */ 495 #define CARD_TYPE_USB9097 (CARD_TYPE_9097 | (INTF_USB << 8)) 496 /** USBNW62X card type */ 497 #define CARD_TYPE_USBNW62X (CARD_TYPE_NW62X | (INTF_USB << 8)) 498 499 #define IS_USB8801(ct) (CARD_TYPE_USB8801 == (ct)) 500 #define IS_USB8897(ct) (CARD_TYPE_USB8897 == (ct)) 501 #define IS_USB8997(ct) (CARD_TYPE_USB8997 == (ct)) 502 #define IS_USB8978(ct) (CARD_TYPE_USB8978 == (ct)) 503 #define IS_USB9098(ct) (CARD_TYPE_USB9098 == (ct)) 504 #define IS_USB9097(ct) (CARD_TYPE_USB9097 == (ct)) 505 #define IS_USBNW62X(ct) (CARD_TYPE_USBNW62X == (ct)) 506 507 /** USB8801 Card */ 508 #define CARD_USB8801 "USB8801" 509 /** USB8897 Card */ 510 #define CARD_USB8897 "USB8897" 511 /** USB8997 Card */ 512 #define CARD_USB8997 "USB8997" 513 /** USB8978 Card */ 514 #define CARD_USB8978 "USBIW416" 515 /** USB9098 Card */ 516 #define CARD_USB9098 "USB9098" 517 /** USB9097 Card */ 518 #define CARD_USB9097 "USBIW620" 519 /** USBNW62X Card */ 520 #define CARD_USBNW62X "USBNW62X" 521 #endif 522 523 #define IS_CARD8801(ct) (CARD_TYPE_8801 == ((ct)&0xf)) 524 #define IS_CARD8887(ct) (CARD_TYPE_8887 == ((ct)&0xf)) 525 #define IS_CARD8897(ct) (CARD_TYPE_8897 == ((ct)&0xf)) 526 #define IS_CARD8977(ct) (CARD_TYPE_8977 == ((ct)&0xf)) 527 #define IS_CARD8997(ct) (CARD_TYPE_8997 == ((ct)&0xf)) 528 #define IS_CARD8987(ct) (CARD_TYPE_8987 == ((ct)&0xf)) 529 #define IS_CARD9098(ct) (CARD_TYPE_9098 == ((ct)&0xf)) 530 #define IS_CARD9097(ct) (CARD_TYPE_9097 == ((ct)&0xf)) 531 #define IS_CARD9177(ct) (CARD_TYPE_9177 == ((ct)&0xf)) 532 #define IS_CARDNW62X(ct) (CARD_TYPE_NW62X == ((ct)&0xf)) 533 534 typedef struct _card_type_entry { 535 t_u16 card_type; 536 t_u16 func_id; 537 char *name; 538 } card_type_entry; 539 540 #if defined(SDIO) || defined(PCIE) 541 /** Max retry number of IO write */ 542 #define MAX_WRITE_IOMEM_RETRY 2 543 #endif /* SDIO || PCIE */ 544 545 #ifdef PCIE 546 typedef enum { 547 PCIE_INT_MODE_LEGACY = 0, 548 PCIE_INT_MODE_MSI, 549 PCIE_INT_MODE_MSIX, 550 PCIE_INT_MODE_MAX, 551 } PCIE_INT_MODE; 552 #endif /* PCIE */ 553 554 /** IN parameter */ 555 #define IN 556 /** OUT parameter */ 557 #define OUT 558 559 /** BIT value */ 560 #define MBIT(x) (((t_u32)1) << (x)) 561 562 /** Buffer flag for requeued packet */ 563 #define MLAN_BUF_FLAG_REQUEUED_PKT MBIT(0) 564 /** Buffer flag for transmit buf from moal */ 565 #define MLAN_BUF_FLAG_MOAL_TX_BUF MBIT(1) 566 /** Buffer flag for malloc mlan_buffer */ 567 #define MLAN_BUF_FLAG_MALLOC_BUF MBIT(2) 568 569 /** Buffer flag for bridge packet */ 570 #define MLAN_BUF_FLAG_BRIDGE_BUF MBIT(3) 571 572 #ifdef USB 573 /** Buffer flag for deaggregated rx packet */ 574 #define MLAN_BUF_FLAG_RX_DEAGGR MBIT(5) 575 576 /** Buffer flag for sleep confirm resp packet */ 577 #define MLAN_BUF_FLAG_SLEEPCFM_RESP MBIT(6) 578 579 /** Buffer flag for USB TX AGGR */ 580 #define MLAN_BUF_FLAG_USB_TX_AGGR MBIT(7) 581 #endif 582 583 /** Buffer flag for TDLS */ 584 #define MLAN_BUF_FLAG_TDLS MBIT(8) 585 586 /** Buffer flag for TCP_ACK */ 587 #define MLAN_BUF_FLAG_TCP_ACK MBIT(9) 588 589 /** Buffer flag for TX_STATUS */ 590 #define MLAN_BUF_FLAG_TX_STATUS MBIT(10) 591 592 /** Buffer flag for NET_MONITOR */ 593 #define MLAN_BUF_FLAG_NET_MONITOR MBIT(11) 594 595 /** Buffer flag for NULL data packet */ 596 #define MLAN_BUF_FLAG_NULL_PKT MBIT(12) 597 /** Buffer flag for Diag pkt */ 598 #define MLAN_BUF_FLAG_DIAG_BUF MBIT(13) 599 600 #define MLAN_BUF_FLAG_TX_CTRL MBIT(14) 601 602 #define MLAN_BUF_FLAG_MC_AGGR_PKT MBIT(17) 603 604 #ifdef DEBUG_LEVEL1 605 /** Debug level bit definition */ 606 #define MMSG MBIT(0) 607 #define MFATAL MBIT(1) 608 #define MERROR MBIT(2) 609 #define MDATA MBIT(3) 610 #define MCMND MBIT(4) 611 #define MEVENT MBIT(5) 612 #define MINTR MBIT(6) 613 #define MIOCTL MBIT(7) 614 615 #define MREG_D MBIT(9) 616 617 #define MMPA_D MBIT(15) 618 #define MDAT_D MBIT(16) 619 #define MCMD_D MBIT(17) 620 #define MEVT_D MBIT(18) 621 #define MFW_D MBIT(19) 622 #define MIF_D MBIT(20) 623 624 #define MENTRY MBIT(28) 625 #define MWARN MBIT(29) 626 #define MINFO MBIT(30) 627 #define MHEX_DUMP MBIT(31) 628 #endif /* DEBUG_LEVEL1 */ 629 630 /** Memory allocation type: DMA */ 631 #define MLAN_MEM_DMA MBIT(0) 632 /** Memory allocation flag: ATOMIC */ 633 #define MLAN_MEM_FLAG_ATOMIC MBIT(1) 634 635 /** Default memory allocation flag */ 636 #define MLAN_MEM_DEF 0 637 638 /** mlan_status */ 639 typedef enum _mlan_status { 640 MLAN_STATUS_FAILURE = 0xffffffff, 641 MLAN_STATUS_SUCCESS = 0, 642 MLAN_STATUS_PENDING, 643 MLAN_STATUS_RESOURCE, 644 #ifdef USB 645 /* Status pending and no resource */ 646 MLAN_STATUS_PRESOURCE, 647 #endif 648 MLAN_STATUS_COMPLETE, 649 MLAN_STATUS_FILE_ERR, 650 } mlan_status; 651 652 /** mlan_error_code */ 653 typedef enum _mlan_error_code { 654 /** No error */ 655 MLAN_ERROR_NO_ERROR = 0, 656 /** Firmware/device errors below (MSB=0) */ 657 MLAN_ERROR_FW_NOT_READY = 0x00000001, 658 MLAN_ERROR_FW_BUSY = 0x00000002, 659 MLAN_ERROR_FW_CMDRESP = 0x00000003, 660 MLAN_ERROR_DATA_TX_FAIL = 0x00000004, 661 MLAN_ERROR_DATA_RX_FAIL = 0x00000005, 662 /** Driver errors below (MSB=1) */ 663 MLAN_ERROR_PKT_SIZE_INVALID = 0x80000001, 664 MLAN_ERROR_PKT_TIMEOUT = 0x80000002, 665 MLAN_ERROR_PKT_INVALID = 0x80000003, 666 MLAN_ERROR_CMD_INVALID = 0x80000004, 667 MLAN_ERROR_CMD_TIMEOUT = 0x80000005, 668 MLAN_ERROR_CMD_DNLD_FAIL = 0x80000006, 669 MLAN_ERROR_CMD_CANCEL = 0x80000007, 670 MLAN_ERROR_CMD_RESP_FAIL = 0x80000008, 671 MLAN_ERROR_CMD_ASSOC_FAIL = 0x80000009, 672 MLAN_ERROR_CMD_SCAN_FAIL = 0x8000000A, 673 MLAN_ERROR_IOCTL_INVALID = 0x8000000B, 674 MLAN_ERROR_IOCTL_FAIL = 0x8000000C, 675 MLAN_ERROR_EVENT_UNKNOWN = 0x8000000D, 676 MLAN_ERROR_INVALID_PARAMETER = 0x8000000E, 677 MLAN_ERROR_NO_MEM = 0x8000000F, 678 /** More to add */ 679 } mlan_error_code; 680 681 /** mlan_buf_type */ 682 typedef enum _mlan_buf_type { 683 MLAN_BUF_TYPE_CMD = 1, 684 MLAN_BUF_TYPE_DATA, 685 MLAN_BUF_TYPE_EVENT, 686 MLAN_BUF_TYPE_RAW_DATA, 687 #ifdef SDIO 688 MLAN_BUF_TYPE_SPA_DATA, 689 #endif 690 } mlan_buf_type; 691 692 #define SCAN_STATE_SCAN_START MBIT(0) 693 #define SCAN_STATE_EXT_SCAN MBIT(1) 694 #define SCAN_STATE_EXT_SCAN_ENH MBIT(2) 695 #define SCAN_STATE_EXT_SCAN_CANCEL MBIT(3) 696 #define SCAN_STATE_EXT_SCAN_CMDRESP MBIT(4) 697 #define SCAN_STATE_EXT_SCAN_ENH_CMDRESP MBIT(5) 698 #define SCAN_STATE_EXT_SCAN_CANCEL_CMDRESP MBIT(6) 699 #define SCAN_STATE_EXT_SCAN_RESULT MBIT(7) 700 #define SCAN_STATE_LAST_EXT_SCAN_RESULT MBIT(8) 701 #define SCAN_STATE_EXT_SCAN_STATUS MBIT(9) 702 #define SCAN_STATE_SCAN_COMPLETE MBIT(10) 703 704 #ifdef USB 705 /** mlan_usb_ep */ 706 typedef enum _mlan_usb_ep { 707 MLAN_USB_EP_CTRL = 0, 708 MLAN_USB_EP_CMD_EVENT = 1, 709 MLAN_USB_EP_DATA = 2, 710 MLAN_USB_EP_DATA_CH2 = 3, 711 MLAN_USB_EP_CMD_EVENT_IF2 = 4, 712 MLAN_USB_EP_DATA_IF2 = 5, 713 MLAN_USB_EP_DATA_CH2_IF2 = 6, 714 } mlan_usb_ep; 715 716 /** Timeout in milliseconds for usb_bulk_msg function */ 717 #define MLAN_USB_BULK_MSG_TIMEOUT 100 718 #endif /* USB */ 719 720 /** MLAN BSS type */ 721 typedef enum _mlan_bss_type { 722 MLAN_BSS_TYPE_STA = 0, 723 MLAN_BSS_TYPE_UAP = 1, 724 #ifdef WIFI_DIRECT_SUPPORT 725 MLAN_BSS_TYPE_WIFIDIRECT = 2, 726 #endif 727 MLAN_BSS_TYPE_DFS = 8, 728 MLAN_BSS_TYPE_ANY = 0xff, 729 } mlan_bss_type; 730 731 /** MLAN BSS role */ 732 typedef enum _mlan_bss_role { 733 MLAN_BSS_ROLE_STA = 0, 734 MLAN_BSS_ROLE_UAP = 1, 735 MLAN_BSS_ROLE_ANY = 0xff, 736 } mlan_bss_role; 737 738 /** BSS role mask */ 739 #define BSS_ROLE_MASK (MBIT(0) | MBIT(1)) 740 741 /** Get BSS role */ 742 #define GET_BSS_ROLE(priv) ((priv)->bss_role & BSS_ROLE_MASK) 743 744 /** mlan_data_frame_type */ 745 typedef enum _mlan_data_frame_type { 746 MLAN_DATA_FRAME_TYPE_ETH_II = 0, 747 MLAN_DATA_FRAME_TYPE_802_11, 748 } mlan_data_frame_type; 749 750 /** mlan_event_id */ 751 typedef enum _mlan_event_id { 752 /* Event generated by firmware (MSB=0) */ 753 MLAN_EVENT_ID_FW_UNKNOWN = 0x00000001, 754 MLAN_EVENT_ID_FW_ADHOC_LINK_SENSED = 0x00000002, 755 MLAN_EVENT_ID_FW_ADHOC_LINK_LOST = 0x00000003, 756 MLAN_EVENT_ID_FW_DISCONNECTED = 0x00000004, 757 MLAN_EVENT_ID_FW_MIC_ERR_UNI = 0x00000005, 758 MLAN_EVENT_ID_FW_MIC_ERR_MUL = 0x00000006, 759 MLAN_EVENT_ID_FW_BCN_RSSI_LOW = 0x00000007, 760 MLAN_EVENT_ID_FW_BCN_RSSI_HIGH = 0x00000008, 761 MLAN_EVENT_ID_FW_BCN_SNR_LOW = 0x00000009, 762 MLAN_EVENT_ID_FW_BCN_SNR_HIGH = 0x0000000A, 763 MLAN_EVENT_ID_FW_MAX_FAIL = 0x0000000B, 764 MLAN_EVENT_ID_FW_DATA_RSSI_LOW = 0x0000000C, 765 MLAN_EVENT_ID_FW_DATA_RSSI_HIGH = 0x0000000D, 766 MLAN_EVENT_ID_FW_DATA_SNR_LOW = 0x0000000E, 767 MLAN_EVENT_ID_FW_DATA_SNR_HIGH = 0x0000000F, 768 MLAN_EVENT_ID_FW_LINK_QUALITY = 0x00000010, 769 MLAN_EVENT_ID_FW_PORT_RELEASE = 0x00000011, 770 MLAN_EVENT_ID_FW_PRE_BCN_LOST = 0x00000012, 771 MLAN_EVENT_ID_FW_DEBUG_INFO = 0x00000013, 772 MLAN_EVENT_ID_FW_WMM_CONFIG_CHANGE = 0x0000001A, 773 MLAN_EVENT_ID_FW_HS_WAKEUP = 0x0000001B, 774 MLAN_EVENT_ID_FW_BG_SCAN = 0x0000001D, 775 MLAN_EVENT_ID_FW_BG_SCAN_STOPPED = 0x0000001E, 776 MLAN_EVENT_ID_FW_WEP_ICV_ERR = 0x00000020, 777 MLAN_EVENT_ID_FW_STOP_TX = 0x00000021, 778 MLAN_EVENT_ID_FW_START_TX = 0x00000022, 779 MLAN_EVENT_ID_FW_CHANNEL_SWITCH_ANN = 0x00000023, 780 MLAN_EVENT_ID_FW_RADAR_DETECTED = 0x00000024, 781 MLAN_EVENT_ID_FW_CHANNEL_REPORT_RDY = 0x00000025, 782 MLAN_EVENT_ID_FW_BW_CHANGED = 0x00000026, 783 MLAN_EVENT_ID_FW_REMAIN_ON_CHAN_EXPIRED = 0x0000002B, 784 785 #ifdef UAP_SUPPORT 786 MLAN_EVENT_ID_UAP_FW_BSS_START = 0x0000002C, 787 MLAN_EVENT_ID_UAP_FW_BSS_ACTIVE = 0x0000002D, 788 MLAN_EVENT_ID_UAP_FW_BSS_IDLE = 0x0000002E, 789 MLAN_EVENT_ID_UAP_FW_MIC_COUNTERMEASURES = 0x0000002F, 790 MLAN_EVENT_ID_UAP_FW_STA_CONNECT = 0x00000030, 791 MLAN_EVENT_ID_UAP_FW_STA_DISCONNECT = 0x00000031, 792 #endif 793 794 MLAN_EVENT_ID_FW_DUMP_INFO = 0x00000033, 795 796 MLAN_EVENT_ID_FW_TX_STATUS = 0x00000034, 797 MLAN_EVENT_ID_FW_CHAN_SWITCH_COMPLETE = 0x00000036, 798 #if defined(PCIE) 799 MLAN_EVENT_ID_SSU_DUMP_FILE = 0x00000039, 800 #endif /* SSU_SUPPORT */ 801 MLAN_EVENT_ID_CSI = 0x00000040, 802 /* Event generated by MLAN driver (MSB=1) */ 803 MLAN_EVENT_ID_DRV_CONNECTED = 0x80000001, 804 MLAN_EVENT_ID_DRV_DEFER_HANDLING = 0x80000002, 805 MLAN_EVENT_ID_DRV_HS_ACTIVATED = 0x80000003, 806 MLAN_EVENT_ID_DRV_HS_DEACTIVATED = 0x80000004, 807 MLAN_EVENT_ID_DRV_MGMT_FRAME = 0x80000005, 808 MLAN_EVENT_ID_DRV_OBSS_SCAN_PARAM = 0x80000006, 809 MLAN_EVENT_ID_DRV_PASSTHRU = 0x80000007, 810 MLAN_EVENT_ID_DRV_SCAN_REPORT = 0x80000009, 811 MLAN_EVENT_ID_DRV_MEAS_REPORT = 0x8000000A, 812 MLAN_EVENT_ID_DRV_ASSOC_FAILURE_REPORT = 0x8000000B, 813 MLAN_EVENT_ID_DRV_REPORT_STRING = 0x8000000F, 814 MLAN_EVENT_ID_DRV_DBG_DUMP = 0x80000012, 815 MLAN_EVENT_ID_DRV_BGSCAN_RESULT = 0x80000013, 816 MLAN_EVENT_ID_DRV_FLUSH_RX_WORK = 0x80000015, 817 MLAN_EVENT_ID_DRV_DEFER_RX_WORK = 0x80000016, 818 MLAN_EVENT_ID_DRV_TDLS_TEARDOWN_REQ = 0x80000017, 819 MLAN_EVENT_ID_DRV_FT_RESPONSE = 0x80000018, 820 MLAN_EVENT_ID_DRV_FLUSH_MAIN_WORK = 0x80000019, 821 #ifdef UAP_SUPPORT 822 MLAN_EVENT_ID_DRV_UAP_CHAN_INFO = 0x80000020, 823 #endif 824 MLAN_EVENT_ID_FW_ROAM_OFFLOAD_RESULT = 0x80000023, 825 MLAN_EVENT_ID_DRV_ASSOC_FAILURE_LOGGER = 0x80000026, 826 MLAN_EVENT_ID_DRV_ASSOC_SUCC_LOGGER = 0x80000027, 827 MLAN_EVENT_ID_DRV_DISCONNECT_LOGGER = 0x80000028, 828 MLAN_EVENT_ID_DRV_WIFI_STATUS = 0x80000029, 829 MLAN_EVENT_ID_STORE_HOST_CMD_RESP = 0x80000030, 830 } mlan_event_id; 831 832 /** Data Structures */ 833 /** mlan_image data structure */ 834 typedef struct _mlan_fw_image { 835 /** Firmware image buffer pointer */ 836 t_u8 *pfw_buf; 837 /** Firmware image length */ 838 t_u32 fw_len; 839 /** Firmware reload flag */ 840 t_u8 fw_reload; 841 } mlan_fw_image, *pmlan_fw_image; 842 843 /** MrvlIEtypesHeader_t */ 844 typedef MLAN_PACK_START struct _MrvlIEtypesHeader { 845 /** Header type */ 846 t_u16 type; 847 /** Header length */ 848 t_u16 len; 849 } MLAN_PACK_END MrvlIEtypesHeader_t; 850 851 /** MrvlExtIEtypesHeader_t */ 852 typedef MLAN_PACK_START struct _MrvlExtIEtypesHeader { 853 /** Header type */ 854 t_u16 type; 855 /** Header length */ 856 t_u16 len; 857 /** ext id */ 858 t_u8 ext_id; 859 } MLAN_PACK_END MrvlExtIEtypesHeader_t; 860 861 /** MrvlIEtypes_Data_t */ 862 typedef MLAN_PACK_START struct _MrvlExtIEtypes_Data_t { 863 /** Header */ 864 MrvlExtIEtypesHeader_t header; 865 /** Data */ 866 t_u8 data[]; 867 } MLAN_PACK_END MrvlExtIEtypes_Data_t; 868 869 /** MrvlIEtypes_Data_t */ 870 typedef MLAN_PACK_START struct _MrvlIEtypes_Data_t { 871 /** Header */ 872 MrvlIEtypesHeader_t header; 873 /** Data */ 874 t_u8 data[]; 875 } MLAN_PACK_END MrvlIEtypes_Data_t; 876 877 #define OID_TYPE_CAL 0x2 878 #define OID_TYPE_DPD 0xa 879 #define UNKNOW_DPD_LENGTH 0xffffffff 880 881 /** Custom data structure */ 882 typedef struct _mlan_init_param { 883 /** DPD data buffer pointer */ 884 t_u8 *pdpd_data_buf; 885 /** DPD data length */ 886 t_u32 dpd_data_len; 887 /** region txpowerlimit cfg data buffer pointer */ 888 t_u8 *ptxpwr_data_buf; 889 /** region txpowerlimit cfg data length */ 890 t_u32 txpwr_data_len; 891 /** Cal data buffer pointer */ 892 t_u8 *pcal_data_buf; 893 /** Cal data length */ 894 t_u32 cal_data_len; 895 /** Other custom data */ 896 } mlan_init_param, *pmlan_init_param; 897 898 /** channel type */ 899 enum mlan_channel_type { 900 CHAN_NO_HT, 901 CHAN_HT20, 902 CHAN_HT40MINUS, 903 CHAN_HT40PLUS, 904 CHAN_VHT80 905 }; 906 907 /** channel band */ 908 enum { BAND_2GHZ = 0, 909 BAND_5GHZ = 1, 910 BAND_6GHZ = 2, 911 BAND_4GHZ = 3, 912 }; 913 914 /** channel offset */ 915 enum { SEC_CHAN_NONE = 0, 916 SEC_CHAN_ABOVE = 1, 917 SEC_CHAN_5MHZ = 2, 918 SEC_CHAN_BELOW = 3 }; 919 920 /** channel bandwidth */ 921 enum { CHAN_BW_20MHZ = 0, 922 CHAN_BW_10MHZ, 923 CHAN_BW_40MHZ, 924 CHAN_BW_80MHZ, 925 }; 926 927 /** scan mode */ 928 enum { SCAN_MODE_MANUAL = 0, 929 SCAN_MODE_ACS, 930 SCAN_MODE_USER, 931 }; 932 933 /** DFS state */ 934 typedef enum _dfs_state_t { 935 /** Channel can be used, CAC (Channel Availability Check) must be done 936 before using it */ 937 DFS_USABLE = 0, 938 /** Channel is not available, radar was detected */ 939 DFS_UNAVAILABLE = 1, 940 /** Channel is Available, CAC is done and is free of radar */ 941 DFS_AVAILABLE = 2, 942 } dfs_state_t; 943 944 /** max cac time 10 minutes */ 945 #define MAX_CAC_DWELL_TIME 600000 946 /** default cac time 60 seconds */ 947 #define DEF_CAC_DWELL_TIME 60000 948 /** start freq for 5G */ 949 #define START_FREQ_11A_BAND 5000 950 951 typedef enum _dfs_w53_cfg_t { 952 /** DFS W53 Default Fw Value */ 953 DFS_W53_DEFAULT_FW = 0, 954 /** DFS W53 New W53 Rules/Standard */ 955 DFS_W53_NEW = 1, 956 /** DFS W53 Old W53 Rules/Standard */ 957 DFS_W53_OLD = 2 958 } dfs_w53_cfg_t; 959 960 typedef enum _dfs_moe_t { 961 /** driver default DFS behavior */ 962 DFS_MODE_DEFAULT = 0, 963 /* disable DFS master when uap and station operate in same DFS channel 964 */ 965 DFS_MODE_ENH = 1, 966 } dfs_mode_t; 967 968 /** Band_Config_t */ 969 typedef MLAN_PACK_START struct _Band_Config_t { 970 #ifdef BIG_ENDIAN_SUPPORT 971 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=user*/ 972 t_u8 scanMode : 2; 973 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 974 t_u8 chan2Offset : 2; 975 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 976 t_u8 chanWidth : 2; 977 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 978 t_u8 chanBand : 2; 979 #else 980 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 981 t_u8 chanBand : 2; 982 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 983 t_u8 chanWidth : 2; 984 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 985 t_u8 chan2Offset : 2; 986 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=Adoption mode*/ 987 t_u8 scanMode : 2; 988 #endif 989 } MLAN_PACK_END Band_Config_t; 990 991 /** channel_band_t */ 992 typedef MLAN_PACK_START struct _chan_band_info { 993 /** Band Configuration */ 994 Band_Config_t bandcfg; 995 /** channel */ 996 t_u8 channel; 997 /** 11n flag */ 998 t_u8 is_11n_enabled; 999 /** center channel */ 1000 t_u8 center_chan; 1001 /** dfs channel flag */ 1002 t_u8 is_dfs_chan; 1003 } MLAN_PACK_END chan_band_info; 1004 1005 /** Channel usability flags */ 1006 #define NXP_CHANNEL_NO_OFDM MBIT(9) 1007 #define NXP_CHANNEL_NO_CCK MBIT(8) 1008 #define NXP_CHANNEL_DISABLED MBIT(7) 1009 /* BIT 5/6 resevered for FW */ 1010 #define NXP_CHANNEL_NOHT160 MBIT(4) 1011 #define NXP_CHANNEL_NOHT80 MBIT(3) 1012 #define NXP_CHANNEL_NOHT40 MBIT(2) 1013 #define NXP_CHANNEL_DFS MBIT(1) 1014 #define NXP_CHANNEL_PASSIVE MBIT(0) 1015 1016 /** CFP dynamic (non-const) elements */ 1017 typedef struct _cfp_dyn_t { 1018 /** extra flags to specify channel usability 1019 * bit 9 : if set, channel is non-OFDM 1020 * bit 8 : if set, channel is non-CCK 1021 * bit 7 : if set, channel is disabled 1022 * bit 5/6 resevered for FW 1023 * bit 4 : if set, 160MHz on channel is disabled 1024 * bit 3 : if set, 80MHz on channel is disabled 1025 * bit 2 : if set, 40MHz on channel is disabled 1026 * bit 1 : if set, channel is DFS channel 1027 * bit 0 : if set, channel is passive 1028 */ 1029 t_u16 flags; 1030 /** TRUE: Channel is blacklisted (do not use) */ 1031 t_bool blacklist; 1032 /** DFS state of the channel 1033 * 0:DFS_USABLE 1:DFS_AVAILABLE 2:DFS_UNAVAILABLE */ 1034 dfs_state_t dfs_state; 1035 } cfp_dyn_t; 1036 1037 /** Chan-Freq-TxPower mapping table*/ 1038 typedef struct _chan_freq_power_t { 1039 /** Channel Number */ 1040 t_u16 channel; 1041 /** Frequency of this Channel */ 1042 t_u32 freq; 1043 /** Max allowed Tx power level */ 1044 t_u16 max_tx_power; 1045 /** TRUE:radar detect required for BAND A or passive scan for BAND B/G; 1046 * FALSE:radar detect not required for BAND A or active scan for BAND 1047 * B/G*/ 1048 t_bool passive_scan_or_radar_detect; 1049 /** Elements associated to cfp that change at run-time */ 1050 cfp_dyn_t dynamic; 1051 } chan_freq_power_t; 1052 1053 /** mlan_event data structure */ 1054 typedef struct _mlan_event { 1055 /** BSS index number for multiple BSS support */ 1056 t_u32 bss_index; 1057 /** Event ID */ 1058 mlan_event_id event_id; 1059 /** Event length */ 1060 t_u32 event_len; 1061 /** Event buffer */ 1062 t_u8 event_buf[]; 1063 } mlan_event, *pmlan_event; 1064 1065 /** mlan_cmdresp_event data structure */ 1066 typedef struct _mlan_cmdresp_event { 1067 /** BSS index number for multiple BSS support */ 1068 t_u32 bss_index; 1069 /** Event ID */ 1070 mlan_event_id event_id; 1071 /** Event length */ 1072 t_u32 event_len; 1073 /** resp buffer pointer */ 1074 t_u8 *resp; 1075 } mlan_cmdresp_event, *pmlan_cmdresp_event; 1076 1077 /** csi event data structure */ 1078 typedef MLAN_PACK_START struct _csi_record_ds { 1079 /** Length in DWORDS, including header */ 1080 t_u16 Len; 1081 /** CSI signature. 0xABCD fixed */ 1082 t_u16 CSI_Sign; 1083 /** User defined HeaderID */ 1084 t_u32 CSI_HeaderID; 1085 /** Packet info field */ 1086 t_u16 PKT_info; 1087 /** Frame control field for the received packet*/ 1088 t_u16 FCF; 1089 /** Timestamp when packet received */ 1090 t_u64 TSF; 1091 /** Received Packet Destination MAC Address */ 1092 t_u8 Dst_MAC[6]; 1093 /** Received Packet Source MAC Address */ 1094 t_u8 Src_MAC[6]; 1095 /** RSSI for antenna A */ 1096 t_u8 Rx_RSSI_A; 1097 /** RSSI for antenna B */ 1098 t_u8 Rx_RSSI_B; 1099 /** Noise floor for antenna A */ 1100 t_u8 Rx_NF_A; 1101 /** Noise floor for antenna A */ 1102 t_u8 Rx_NF_B; 1103 /** Rx signal strength above noise floor */ 1104 t_u8 Rx_SINR; 1105 /** Channel */ 1106 t_u8 channel; 1107 /** user defined Chip ID */ 1108 t_u16 chip_id; 1109 /** Reserved */ 1110 t_u32 rsvd; 1111 /** CSI data length in DWORDs */ 1112 t_u32 CSI_Data_Length; 1113 /** Start of CSI data */ 1114 t_u8 CSI_Data[0]; 1115 /** At the end of CSI raw data, user defined TailID of 4 bytes*/ 1116 } MLAN_PACK_END csi_record_ds, *pcsi_record_ds; 1117 1118 /** mlan_ioctl_req data structure */ 1119 typedef struct _mlan_ioctl_req { 1120 /** Pointer to previous mlan_ioctl_req */ 1121 struct _mlan_ioctl_req *pprev; 1122 /** Pointer to next mlan_ioctl_req */ 1123 struct _mlan_ioctl_req *pnext; 1124 /** Status code from firmware/driver */ 1125 t_u32 status_code; 1126 /** BSS index number for multiple BSS support */ 1127 t_u32 bss_index; 1128 /** Request id */ 1129 t_u32 req_id; 1130 /** Action: set or get */ 1131 t_u32 action; 1132 /** Pointer to buffer */ 1133 t_u8 *pbuf; 1134 /** Length of buffer */ 1135 t_u32 buf_len; 1136 /** Length of the data read/written in buffer */ 1137 t_u32 data_read_written; 1138 /** Length of buffer needed */ 1139 t_u32 buf_len_needed; 1140 /** Reserved for MOAL module */ 1141 t_ptr reserved_1; 1142 } mlan_ioctl_req, *pmlan_ioctl_req; 1143 1144 typedef MLAN_PACK_START struct _mix_rate_info { 1145 /** bit0: LGI: gi=0, SGI: gi= 1 */ 1146 /** bit1-2: 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */ 1147 /** bit3-4: LG: format=0, HT: format=1, VHT: format=2 */ 1148 /** bit5: LDPC: 0-not support, 1-support */ 1149 /** bit6-7:reserved */ 1150 t_u8 rate_info; 1151 /** MCS index */ 1152 t_u8 mcs_index; 1153 /** bitrate, in 500Kbps */ 1154 t_u16 bitrate; 1155 } MLAN_PACK_END mix_rate_info, *pmix_rate_info; 1156 1157 typedef MLAN_PACK_START struct _rxpd_extra_info { 1158 /** flags */ 1159 t_u8 flags; 1160 /** channel.flags */ 1161 t_u16 channel_flags; 1162 /** mcs.known */ 1163 t_u8 mcs_known; 1164 /** mcs.flags */ 1165 t_u8 mcs_flags; 1166 /** vht sig1 */ 1167 t_u32 vht_sig1; 1168 /** vht sig2 */ 1169 t_u32 vht_sig2; 1170 } MLAN_PACK_END rxpd_extra_info, *prxpd_extra_info; 1171 1172 typedef MLAN_PACK_START struct _radiotap_info { 1173 /** Rate Info */ 1174 mix_rate_info rate_info; 1175 /** SNR */ 1176 t_s8 snr; 1177 /** Noise Floor */ 1178 t_s8 nf; 1179 /** band config */ 1180 t_u8 band_config; 1181 /** chan number */ 1182 t_u8 chan_num; 1183 t_u8 antenna; 1184 /** extra rxpd info from FW */ 1185 rxpd_extra_info extra_info; 1186 } MLAN_PACK_END radiotap_info, *pradiotap_info; 1187 1188 /** txpower structure */ 1189 typedef MLAN_PACK_START struct { 1190 #ifdef BIG_ENDIAN_SUPPORT 1191 /** Host tx power ctrl: 1192 0x0: use fw setting for TX power 1193 0x1: value specified in bit[6] and bit[5:0] are valid */ 1194 t_u8 hostctl : 1; 1195 /** Sign of the power specified in bit[5:0] */ 1196 t_u8 sign : 1; 1197 /** Power to be used for transmission(in dBm) */ 1198 t_u8 abs_val : 6; 1199 #else 1200 /** Power to be used for transmission(in dBm) */ 1201 t_u8 abs_val : 6; 1202 /** Sign of the power specified in bit[5:0] */ 1203 t_u8 sign : 1; 1204 /** Host tx power ctrl: 1205 0x0: use fw setting for TX power 1206 0x1: value specified in bit[6] and bit[5:0] are valid */ 1207 t_u8 hostctl : 1; 1208 #endif 1209 } MLAN_PACK_END tx_power_t; 1210 /* pkt_txctrl */ 1211 typedef MLAN_PACK_START struct _pkt_txctrl { 1212 /**Data rate in unit of 0.5Mbps */ 1213 t_u16 data_rate; 1214 /*Channel number to transmit the frame */ 1215 t_u8 channel; 1216 /** Bandwidth to transmit the frame*/ 1217 t_u8 bw; 1218 /** Power to be used for transmission*/ 1219 union { 1220 tx_power_t tp; 1221 t_u8 val; 1222 } tx_power; 1223 /** Retry time of tx transmission*/ 1224 t_u8 retry_limit; 1225 } MLAN_PACK_END pkt_txctrl, *ppkt_txctrl; 1226 1227 /** pkt_rxinfo */ 1228 typedef MLAN_PACK_START struct _pkt_rxinfo { 1229 /** Data rate of received paccket*/ 1230 t_u16 data_rate; 1231 /** Channel on which packet was received*/ 1232 t_u8 channel; 1233 /** Rx antenna*/ 1234 t_u8 antenna; 1235 /** Rx Rssi*/ 1236 t_u8 rssi; 1237 } MLAN_PACK_END pkt_rxinfo, *ppkt_rxinfo; 1238 1239 #define MC_FLAG_RETRY MBIT(0) 1240 #define MC_FLAG_START_CYCLE MBIT(1) 1241 #define MC_FLAG_END_CYCLE MBIT(2) 1242 #define MC_FLAG_START_AMPDU MBIT(3) 1243 #define MC_FLAG_END_AMPDU MBIT(4) 1244 /* mc pkt txcontrol */ 1245 typedef MLAN_PACK_START struct _mc_txcontrol { 1246 /** Data rate in mcs index, 0-7 */ 1247 t_u8 mcs_index; 1248 /** band width 0-20Mhz, 1-40Mhz */ 1249 t_u8 bandwidth; 1250 /** seq_num */ 1251 t_u16 seq_num; 1252 /** packet expiry time */ 1253 t_u32 pkt_expiry; 1254 /** mc_pkt_flags */ 1255 t_u8 mc_pkt_flags; 1256 } MLAN_PACK_END mc_txcontrol, *pmc_txcontrol; 1257 1258 /** mlan_buffer data structure */ 1259 typedef struct _mlan_buffer { 1260 /** Pointer to previous mlan_buffer */ 1261 struct _mlan_buffer *pprev; 1262 /** Pointer to next mlan_buffer */ 1263 struct _mlan_buffer *pnext; 1264 /** Status code from firmware/driver */ 1265 t_u32 status_code; 1266 /** Flags for this buffer */ 1267 t_u32 flags; 1268 /** BSS index number for multiple BSS support */ 1269 t_u32 bss_index; 1270 /** Buffer descriptor, e.g. skb in Linux */ 1271 t_void *pdesc; 1272 /** Pointer to buffer */ 1273 t_u8 *pbuf; 1274 #ifdef PCIE 1275 /** Physical address of the pbuf pointer */ 1276 t_u64 buf_pa; 1277 t_u32 total_pcie_buf_len; 1278 #endif 1279 /** Offset to data */ 1280 t_u32 data_offset; 1281 /** Data length */ 1282 t_u32 data_len; 1283 /** Buffer type: data, cmd, event etc. */ 1284 mlan_buf_type buf_type; 1285 1286 /** Fields below are valid for data packet only */ 1287 /** QoS priority */ 1288 t_u32 priority; 1289 /** Time stamp when packet is received (seconds) */ 1290 t_u32 in_ts_sec; 1291 /** Time stamp when packet is received (micro seconds) */ 1292 t_u32 in_ts_usec; 1293 /** Time stamp when packet is processed (seconds) */ 1294 t_u32 out_ts_sec; 1295 /** Time stamp when packet is processed (micro seconds) */ 1296 t_u32 out_ts_usec; 1297 /** tx_seq_num */ 1298 t_u32 tx_seq_num; 1299 /** Time stamp when packet is deque from rx_q(seconds) */ 1300 t_u32 extra_ts_sec; 1301 /** Time stamp when packet is dequed from rx_q(micro seconds) */ 1302 t_u32 extra_ts_usec; 1303 /** Fields below are valid for MLAN module only */ 1304 /** Pointer to parent mlan_buffer */ 1305 struct _mlan_buffer *pparent; 1306 /** Use count for this buffer */ 1307 t_u32 use_count; 1308 union { 1309 mc_txcontrol mc_tx_info; 1310 pkt_txctrl tx_info; 1311 pkt_rxinfo rx_info; 1312 } u; 1313 } mlan_buffer, *pmlan_buffer, **ppmlan_buffer; 1314 1315 /** mlan_hw_info data structure */ 1316 typedef struct _mlan_hw_info { 1317 t_u32 fw_cap; 1318 t_u32 fw_cap_ext; 1319 } mlan_hw_info, *pmlan_hw_info; 1320 1321 /** mlan_bss_attr data structure */ 1322 typedef struct _mlan_bss_attr { 1323 /** BSS type */ 1324 t_u32 bss_type; 1325 /** Data frame type: Ethernet II, 802.11, etc. */ 1326 t_u32 frame_type; 1327 /** The BSS is active (non-0) or not (0). */ 1328 t_u32 active; 1329 /** BSS Priority */ 1330 t_u32 bss_priority; 1331 /** BSS number */ 1332 t_u32 bss_num; 1333 /** The BSS is virtual */ 1334 t_u32 bss_virtual; 1335 } mlan_bss_attr, *pmlan_bss_attr; 1336 1337 /** bss tbl data structure */ 1338 typedef struct _mlan_bss_tbl { 1339 /** BSS Attributes */ 1340 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 1341 } mlan_bss_tbl, *pmlan_bss_tbl; 1342 1343 #ifdef PRAGMA_PACK 1344 #pragma pack(push, 1) 1345 #endif 1346 1347 /** Type enumeration for the command result */ 1348 typedef MLAN_PACK_START enum _mlan_cmd_result_e { 1349 MLAN_CMD_RESULT_SUCCESS = 0, 1350 MLAN_CMD_RESULT_FAILURE = 1, 1351 MLAN_CMD_RESULT_TIMEOUT = 2, 1352 MLAN_CMD_RESULT_INVALID_DATA = 3 1353 } MLAN_PACK_END mlan_cmd_result_e; 1354 1355 /** Type enumeration of WMM AC_QUEUES */ 1356 typedef MLAN_PACK_START enum _mlan_wmm_ac_e { 1357 WMM_AC_BK, 1358 WMM_AC_BE, 1359 WMM_AC_VI, 1360 WMM_AC_VO 1361 } MLAN_PACK_END mlan_wmm_ac_e; 1362 1363 /** Type enumeration for the action field in the Queue Config command */ 1364 typedef MLAN_PACK_START enum _mlan_wmm_queue_config_action_e { 1365 MLAN_WMM_QUEUE_CONFIG_ACTION_GET = 0, 1366 MLAN_WMM_QUEUE_CONFIG_ACTION_SET = 1, 1367 MLAN_WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2, 1368 MLAN_WMM_QUEUE_CONFIG_ACTION_MAX 1369 } MLAN_PACK_END mlan_wmm_queue_config_action_e; 1370 1371 /** Type enumeration for the action field in the queue stats command */ 1372 typedef MLAN_PACK_START enum _mlan_wmm_queue_stats_action_e { 1373 MLAN_WMM_STATS_ACTION_START = 0, 1374 MLAN_WMM_STATS_ACTION_STOP = 1, 1375 MLAN_WMM_STATS_ACTION_GET_CLR = 2, 1376 MLAN_WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */ 1377 MLAN_WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */ 1378 MLAN_WMM_STATS_ACTION_MAX 1379 } MLAN_PACK_END mlan_wmm_queue_stats_action_e; 1380 1381 /** 1382 * @brief IOCTL structure for a Traffic stream status. 1383 * 1384 */ 1385 typedef MLAN_PACK_START struct { 1386 /** TSID: Range: 0->7 */ 1387 t_u8 tid; 1388 /** TSID specified is valid */ 1389 t_u8 valid; 1390 /** AC TSID is active on */ 1391 t_u8 access_category; 1392 /** UP specified for the TSID */ 1393 t_u8 user_priority; 1394 /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */ 1395 t_u8 psb; 1396 /** Upstream(0), Downlink(1), Bidirectional(3) */ 1397 t_u8 flow_dir; 1398 /** Medium time granted for the TSID */ 1399 t_u16 medium_time; 1400 } MLAN_PACK_END wlan_ioctl_wmm_ts_status_t, 1401 /** Type definition of mlan_ds_wmm_ts_status for 1402 MLAN_OID_WMM_CFG_TS_STATUS */ 1403 mlan_ds_wmm_ts_status, *pmlan_ds_wmm_ts_status; 1404 1405 /** Max Ie length */ 1406 #define MAX_IE_SIZE 256 1407 1408 /** custom IE */ 1409 typedef MLAN_PACK_START struct _custom_ie { 1410 /** IE Index */ 1411 t_u16 ie_index; 1412 /** Mgmt Subtype Mask */ 1413 t_u16 mgmt_subtype_mask; 1414 /** IE Length */ 1415 t_u16 ie_length; 1416 /** IE buffer */ 1417 t_u8 ie_buffer[MAX_IE_SIZE]; 1418 } MLAN_PACK_END custom_ie; 1419 1420 /** Max IE index to FW */ 1421 #define MAX_MGMT_IE_INDEX_TO_FW 4 1422 /** Max IE index per BSS */ 1423 #define MAX_MGMT_IE_INDEX 26 1424 1425 /** custom IE info */ 1426 typedef MLAN_PACK_START struct _custom_ie_info { 1427 /** size of buffer */ 1428 t_u16 buf_size; 1429 /** no of buffers of buf_size */ 1430 t_u16 buf_count; 1431 } MLAN_PACK_END custom_ie_info; 1432 1433 /** TLV buffer : Max Mgmt IE */ 1434 typedef MLAN_PACK_START struct _tlvbuf_max_mgmt_ie { 1435 /** Type */ 1436 t_u16 type; 1437 /** Length */ 1438 t_u16 len; 1439 /** No of tuples */ 1440 t_u16 count; 1441 /** custom IE info tuples */ 1442 custom_ie_info info[MAX_MGMT_IE_INDEX]; 1443 } MLAN_PACK_END tlvbuf_max_mgmt_ie; 1444 1445 /** TLV buffer : custom IE */ 1446 typedef MLAN_PACK_START struct _tlvbuf_custom_ie { 1447 /** Type */ 1448 t_u16 type; 1449 /** Length */ 1450 t_u16 len; 1451 /** IE data */ 1452 custom_ie ie_data_list[MAX_MGMT_IE_INDEX_TO_FW]; 1453 /** Max mgmt IE TLV */ 1454 tlvbuf_max_mgmt_ie max_mgmt_ie; 1455 } MLAN_PACK_END mlan_ds_misc_custom_ie; 1456 1457 /** Max TDLS config data length */ 1458 #define MAX_TDLS_DATA_LEN 1024 1459 1460 /** Action commands for TDLS enable/disable */ 1461 #define WLAN_TDLS_CONFIG 0x00 1462 /** Action commands for TDLS configuration :Set */ 1463 #define WLAN_TDLS_SET_INFO 0x01 1464 /** Action commands for TDLS configuration :Discovery Request */ 1465 #define WLAN_TDLS_DISCOVERY_REQ 0x02 1466 /** Action commands for TDLS configuration :Setup Request */ 1467 #define WLAN_TDLS_SETUP_REQ 0x03 1468 /** Action commands for TDLS configuration :Tear down Request */ 1469 #define WLAN_TDLS_TEAR_DOWN_REQ 0x04 1470 /** Action ID for TDLS power mode */ 1471 #define WLAN_TDLS_POWER_MODE 0x05 1472 /**Action ID for init TDLS Channel Switch*/ 1473 #define WLAN_TDLS_INIT_CHAN_SWITCH 0x06 1474 /** Action ID for stop TDLS Channel Switch */ 1475 #define WLAN_TDLS_STOP_CHAN_SWITCH 0x07 1476 /** Action ID for configure CS related parameters */ 1477 #define WLAN_TDLS_CS_PARAMS 0x08 1478 /** Action ID for Disable CS */ 1479 #define WLAN_TDLS_CS_DISABLE 0x09 1480 /** Action ID for TDLS link status */ 1481 #define WLAN_TDLS_LINK_STATUS 0x0A 1482 /** Action ID for Host TDLS config uapsd and CS */ 1483 #define WLAN_HOST_TDLS_CONFIG 0x0D 1484 /** Action ID for TDLS CS immediate return */ 1485 #define WLAN_TDLS_DEBUG_CS_RET_IM 0xFFF7 1486 /** Action ID for TDLS Stop RX */ 1487 #define WLAN_TDLS_DEBUG_STOP_RX 0xFFF8 1488 /** Action ID for TDLS Allow weak security for links establish */ 1489 #define WLAN_TDLS_DEBUG_ALLOW_WEAK_SECURITY 0xFFF9 1490 /** Action ID for TDLS Ignore key lifetime expiry */ 1491 #define WLAN_TDLS_DEBUG_IGNORE_KEY_EXPIRY 0xFFFA 1492 /** Action ID for TDLS Higher/Lower mac Test */ 1493 #define WLAN_TDLS_DEBUG_HIGHER_LOWER_MAC 0xFFFB 1494 /** Action ID for TDLS Prohibited Test */ 1495 #define WLAN_TDLS_DEBUG_SETUP_PROHIBITED 0xFFFC 1496 /** Action ID for TDLS Existing link Test */ 1497 #define WLAN_TDLS_DEBUG_SETUP_SAME_LINK 0xFFFD 1498 /** Action ID for TDLS Fail Setup Confirm */ 1499 #define WLAN_TDLS_DEBUG_FAIL_SETUP_CONFIRM 0xFFFE 1500 /** Action commands for TDLS debug: Wrong BSS Request */ 1501 #define WLAN_TDLS_DEBUG_WRONG_BSS 0xFFFF 1502 1503 /** tdls each link rate information */ 1504 typedef MLAN_PACK_START struct _tdls_link_rate_info { 1505 /** Tx Data Rate */ 1506 t_u8 tx_data_rate; 1507 /** Tx Rate HT info*/ 1508 t_u8 tx_rate_htinfo; 1509 } MLAN_PACK_END tdls_link_rate_info; 1510 1511 /** tdls each link status */ 1512 typedef MLAN_PACK_START struct _tdls_each_link_status { 1513 /** peer mac Address */ 1514 t_u8 peer_mac[MLAN_MAC_ADDR_LENGTH]; 1515 /** Link Flags */ 1516 t_u8 link_flags; 1517 /** Traffic Status */ 1518 t_u8 traffic_status; 1519 /** Tx Failure Count */ 1520 t_u8 tx_fail_count; 1521 /** Channel Number */ 1522 t_u32 active_channel; 1523 /** Last Data RSSI in dBm */ 1524 t_s16 data_rssi_last; 1525 /** Last Data NF in dBm */ 1526 t_s16 data_nf_last; 1527 /** AVG DATA RSSI in dBm */ 1528 t_s16 data_rssi_avg; 1529 /** AVG DATA NF in dBm */ 1530 t_s16 data_nf_avg; 1531 union { 1532 /** tdls rate info */ 1533 tdls_link_rate_info rate_info; 1534 /** tdls link final rate*/ 1535 t_u16 final_data_rate; 1536 } u; 1537 /** Security Method */ 1538 t_u8 security_method; 1539 /** Key Lifetime in milliseconds */ 1540 t_u32 key_lifetime; 1541 /** Key Length */ 1542 t_u8 key_length; 1543 /** actual key */ 1544 t_u8 key[1]; 1545 } MLAN_PACK_END tdls_each_link_status; 1546 1547 /** TDLS configuration data */ 1548 typedef MLAN_PACK_START struct _tdls_all_config { 1549 union { 1550 /** TDLS state enable disable */ 1551 MLAN_PACK_START struct _tdls_config { 1552 /** enable or disable */ 1553 t_u16 enable; 1554 } MLAN_PACK_END tdls_config; 1555 /** Host tdls config */ 1556 MLAN_PACK_START struct _host_tdls_cfg { 1557 /** support uapsd */ 1558 t_u8 uapsd_support; 1559 /** channel_switch */ 1560 t_u8 cs_support; 1561 /** TLV length */ 1562 t_u16 tlv_len; 1563 /** tdls info */ 1564 t_u8 tlv_buffer[]; 1565 } MLAN_PACK_END host_tdls_cfg; 1566 /** TDLS set info */ 1567 MLAN_PACK_START struct _tdls_set_data { 1568 /** (tlv + capInfo) length */ 1569 t_u16 tlv_length; 1570 /** Cap Info */ 1571 t_u16 cap_info; 1572 /** TLV buffer */ 1573 t_u8 tlv_buffer[]; 1574 } MLAN_PACK_END tdls_set; 1575 1576 /** TDLS discovery and others having mac argument */ 1577 MLAN_PACK_START struct _tdls_discovery_data { 1578 /** peer mac Address */ 1579 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1580 } MLAN_PACK_END tdls_discovery, tdls_stop_chan_switch, 1581 tdls_link_status_req; 1582 1583 /** TDLS discovery Response */ 1584 MLAN_PACK_START struct _tdls_discovery_resp { 1585 /** payload length */ 1586 t_u16 payload_len; 1587 /** peer mac Address */ 1588 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1589 /** RSSI */ 1590 t_s8 rssi; 1591 /** Cap Info */ 1592 t_u16 cap_info; 1593 /** TLV buffer */ 1594 t_u8 tlv_buffer[]; 1595 } MLAN_PACK_END tdls_discovery_resp; 1596 1597 /** TDLS setup request */ 1598 MLAN_PACK_START struct _tdls_setup_data { 1599 /** peer mac Address */ 1600 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1601 /** timeout value in milliseconds */ 1602 t_u32 setup_timeout; 1603 /** key lifetime in milliseconds */ 1604 t_u32 key_lifetime; 1605 } MLAN_PACK_END tdls_setup; 1606 1607 /** TDLS tear down info */ 1608 MLAN_PACK_START struct _tdls_tear_down_data { 1609 /** peer mac Address */ 1610 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1611 /** reason code */ 1612 t_u16 reason_code; 1613 } MLAN_PACK_END tdls_tear_down, tdls_cmd_resp; 1614 1615 /** TDLS power mode info */ 1616 MLAN_PACK_START struct _tdls_power_mode_data { 1617 /** peer mac Address */ 1618 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1619 /** Power Mode */ 1620 t_u16 power_mode; 1621 } MLAN_PACK_END tdls_power_mode; 1622 1623 /** TDLS channel switch info */ 1624 MLAN_PACK_START struct _tdls_chan_switch { 1625 /** peer mac Address */ 1626 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1627 /** Channel Switch primary channel no */ 1628 t_u8 primary_channel; 1629 /** Channel Switch secondary channel offset */ 1630 t_u8 secondary_channel_offset; 1631 /** Channel Switch Band */ 1632 t_u8 band; 1633 /** Channel Switch time in milliseconds */ 1634 t_u16 switch_time; 1635 /** Channel Switch timeout in milliseconds */ 1636 t_u16 switch_timeout; 1637 /** Channel Regulatory class*/ 1638 t_u8 regulatory_class; 1639 /** peridicity flag*/ 1640 t_u8 periodicity; 1641 } MLAN_PACK_END tdls_chan_switch; 1642 1643 /** TDLS channel switch paramters */ 1644 MLAN_PACK_START struct _tdls_cs_params { 1645 /** unit time, multiples of 10ms */ 1646 t_u8 unit_time; 1647 /** threshold for other link */ 1648 t_u8 threshold_otherlink; 1649 /** threshold for direct link */ 1650 t_u8 threshold_directlink; 1651 } MLAN_PACK_END tdls_cs_params; 1652 1653 /** tdls disable channel switch */ 1654 MLAN_PACK_START struct _tdls_disable_cs { 1655 /** Data*/ 1656 t_u16 data; 1657 } MLAN_PACK_END tdls_disable_cs; 1658 /** TDLS debug data */ 1659 MLAN_PACK_START struct _tdls_debug_data { 1660 /** debug data */ 1661 t_u16 debug_data; 1662 } MLAN_PACK_END tdls_debug_data; 1663 1664 /** TDLS link status Response */ 1665 MLAN_PACK_START struct _tdls_link_status_resp { 1666 /** payload length */ 1667 t_u16 payload_len; 1668 /** number of links */ 1669 t_u8 active_links; 1670 /** structure for link status */ 1671 tdls_each_link_status link_stats[1]; 1672 } MLAN_PACK_END tdls_link_status_resp; 1673 1674 } u; 1675 } MLAN_PACK_END tdls_all_config; 1676 1677 /** TDLS configuration buffer */ 1678 typedef MLAN_PACK_START struct _buf_tdls_config { 1679 /** TDLS Action */ 1680 t_u16 tdls_action; 1681 /** TDLS data */ 1682 t_u8 tdls_data[MAX_TDLS_DATA_LEN]; 1683 } MLAN_PACK_END mlan_ds_misc_tdls_config; 1684 1685 /** Event structure for tear down */ 1686 typedef struct _tdls_tear_down_event { 1687 /** Peer mac address */ 1688 t_u8 peer_mac_addr[MLAN_MAC_ADDR_LENGTH]; 1689 /** Reason code */ 1690 t_u16 reason_code; 1691 } tdls_tear_down_event; 1692 1693 /** channel width */ 1694 typedef enum wifi_channel_width { 1695 WIFI_CHAN_WIDTH_20 = 0, 1696 WIFI_CHAN_WIDTH_40 = 1, 1697 WIFI_CHAN_WIDTH_80 = 2, 1698 WIFI_CHAN_WIDTH_160 = 3, 1699 WIFI_CHAN_WIDTH_80P80 = 4, 1700 WIFI_CHAN_WIDTH_5 = 5, 1701 WIFI_CHAN_WIDTH_10 = 6, 1702 WIFI_CHAN_WIDTH_INVALID = -1 1703 } wifi_channel_width_t; 1704 1705 /** channel information */ 1706 typedef struct { 1707 /** channel width (20, 40, 80, 80+80, 160) */ 1708 wifi_channel_width_t width; 1709 /** primary 20 MHz channel */ 1710 int center_freq; 1711 /** center frequency (MHz) first segment */ 1712 int center_freq0; 1713 /** center frequency (MHz) second segment */ 1714 int center_freq1; 1715 } wifi_channel_info; 1716 1717 /** wifi rate */ 1718 typedef struct { 1719 /** 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved */ 1720 t_u32 preamble : 3; 1721 /** 0:1x1, 1:2x2, 3:3x3, 4:4x4 */ 1722 t_u32 nss : 2; 1723 /** 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz */ 1724 t_u32 bw : 3; 1725 /** OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps 1726 */ 1727 /** HT/VHT it would be mcs index */ 1728 t_u32 rateMcsIdx : 8; 1729 /** reserved */ 1730 t_u32 reserved : 16; 1731 /** units of 100 Kbps */ 1732 t_u32 bitrate; 1733 } wifi_rate; 1734 1735 /** wifi Preamble type */ 1736 typedef enum { 1737 WIFI_PREAMBLE_LEGACY = 0x1, 1738 WIFI_PREAMBLE_HT = 0x2, 1739 WIFI_PREAMBLE_VHT = 0x4 1740 } wifi_preamble; 1741 1742 /** timeval */ 1743 typedef struct { 1744 /** Time (seconds) */ 1745 t_u32 time_sec; 1746 /** Time (micro seconds) */ 1747 t_u32 time_usec; 1748 } wifi_timeval; 1749 1750 #define MAX_NUM_RATE 32 1751 #define MAX_RADIO 2 1752 #define MAX_NUM_CHAN 1 1753 #define VHT_NUM_SUPPORT_MCS 10 1754 #define MCS_NUM_SUPP 16 1755 1756 #define BUF_MAXLEN 4096 1757 /** connection state */ 1758 typedef enum { 1759 MLAN_DISCONNECTED = 0, 1760 MLAN_AUTHENTICATING = 1, 1761 MLAN_ASSOCIATING = 2, 1762 MLAN_ASSOCIATED = 3, 1763 /** if done by firmware/driver */ 1764 MLAN_EAPOL_STARTED = 4, 1765 /** if done by firmware/driver */ 1766 MLAN_EAPOL_COMPLETED = 5, 1767 } mlan_connection_state; 1768 /** roam state */ 1769 typedef enum { 1770 MLAN_ROAMING_IDLE = 0, 1771 MLAN_ROAMING_ACTIVE = 1, 1772 } mlan_roam_state; 1773 /** interface mode */ 1774 typedef enum { 1775 MLAN_INTERFACE_STA = 0, 1776 MLAN_INTERFACE_SOFTAP = 1, 1777 MLAN_INTERFACE_IBSS = 2, 1778 MLAN_INTERFACE_P2P_CLIENT = 3, 1779 MLAN_INTERFACE_P2P_GO = 4, 1780 MLAN_INTERFACE_NAN = 5, 1781 MLAN_INTERFACE_MESH = 6, 1782 } mlan_interface_mode; 1783 1784 /** set for QOS association */ 1785 #define MLAN_CAPABILITY_QOS 0x00000001 1786 /** set for protected association (802.11 beacon frame control protected bit 1787 * set) */ 1788 #define MLAN_CAPABILITY_PROTECTED 0x00000002 1789 /** set if 802.11 Extended Capabilities element interworking bit is set */ 1790 #define MLAN_CAPABILITY_INTERWORKING 0x00000004 1791 /** set for HS20 association */ 1792 #define MLAN_CAPABILITY_HS20 0x00000008 1793 /** set is 802.11 Extended Capabilities element UTF-8 SSID bit is set */ 1794 #define MLAN_CAPABILITY_SSID_UTF8 0x00000010 1795 /** set is 802.11 Country Element is present */ 1796 #define MLAN_CAPABILITY_COUNTRY 0x00000020 1797 1798 /** link layer status */ 1799 typedef struct { 1800 /** interface mode */ 1801 mlan_interface_mode mode; 1802 /** interface mac address (self) */ 1803 t_u8 mac_addr[6]; 1804 /** connection state (valid for STA, CLI only) */ 1805 mlan_connection_state state; 1806 /** roaming state */ 1807 mlan_roam_state roaming; 1808 /** WIFI_CAPABILITY_XXX (self) */ 1809 t_u32 capabilities; 1810 /** null terminated SSID */ 1811 t_u8 ssid[33]; 1812 /** bssid */ 1813 t_u8 bssid[6]; 1814 /** country string advertised by AP */ 1815 t_u8 ap_country_str[3]; 1816 /** country string for this association */ 1817 t_u8 country_str[3]; 1818 } mlan_interface_link_layer_info, *mlan_interface_handle; 1819 1820 /** channel statistics */ 1821 typedef struct { 1822 /** channel */ 1823 wifi_channel_info channel; 1824 /** msecs the radio is awake (32 bits number accruing over time) */ 1825 t_u32 on_time; 1826 /** msecs the CCA register is busy (32 bits number accruing over time) 1827 */ 1828 t_u32 cca_busy_time; 1829 } wifi_channel_stat; 1830 1831 #define timeval_to_msec(timeval) \ 1832 (t_u64)((t_u64)(timeval.time_sec) * 1000 + \ 1833 (t_u64)(timeval.time_usec) / 1000) 1834 #define timeval_to_usec(timeval) \ 1835 (t_u64)((t_u64)(timeval.time_sec) * 1000 * 1000 + \ 1836 (t_u64)(timeval.time_usec)) 1837 #define is_zero_timeval(timeval) \ 1838 ((timeval.time_sec == 0) && (timeval.time_usec == 0)) 1839 1840 /** radio statistics */ 1841 typedef struct { 1842 /** wifi radio (if multiple radio supported) */ 1843 int radio; 1844 /** msecs the radio is awake (32 bits number accruing over time) */ 1845 t_u32 on_time; 1846 /** msecs the radio is transmitting (32 bits number accruing over time) 1847 */ 1848 t_u32 tx_time; 1849 /** TBD: num_tx_levels: number of radio transmit power levels */ 1850 t_u32 reserved0; 1851 /** TBD: tx_time_per_levels: pointer to an array of radio transmit per 1852 * power levels in msecs accured over time */ 1853 /* t_u32 *reserved1;*/ 1854 /** msecs the radio is in active receive (32 bits number accruing over 1855 * time) */ 1856 t_u32 rx_time; 1857 /** msecs the radio is awake due to all scan (32 bits number accruing 1858 * over time) */ 1859 t_u32 on_time_scan; 1860 /** msecs the radio is awake due to NAN (32 bits number accruing over 1861 * time) */ 1862 t_u32 on_time_nbd; 1863 /** msecs the radio is awake due to G?scan (32 bits number accruing over 1864 * time) */ 1865 t_u32 on_time_gscan; 1866 /** msecs the radio is awake due to roam?scan (32 bits number accruing 1867 * over time) */ 1868 t_u32 on_time_roam_scan; 1869 /** msecs the radio is awake due to PNO scan (32 bits number accruing 1870 * over time) */ 1871 t_u32 on_time_pno_scan; 1872 /** msecs the radio is awake due to HS2.0 scans and GAS exchange (32 1873 * bits number accruing over time) */ 1874 t_u32 on_time_hs20; 1875 /** number of channels */ 1876 t_u32 num_channels; 1877 /** channel statistics */ 1878 wifi_channel_stat channels[MAX_NUM_CHAN]; 1879 } wifi_radio_stat; 1880 1881 /** per rate statistics */ 1882 typedef struct { 1883 /** rate information */ 1884 wifi_rate rate; 1885 /** number of successfully transmitted data pkts (ACK rcvd) */ 1886 t_u32 tx_mpdu; 1887 /** number of received data pkts */ 1888 t_u32 rx_mpdu; 1889 /** number of data packet losses (no ACK) */ 1890 t_u32 mpdu_lost; 1891 /** total number of data pkt retries */ 1892 t_u32 retries; 1893 /** number of short data pkt retries */ 1894 t_u32 retries_short; 1895 /** number of long data pkt retries */ 1896 t_u32 retries_long; 1897 } wifi_rate_stat; 1898 1899 /** wifi peer type */ 1900 typedef enum { 1901 WIFI_PEER_STA, 1902 WIFI_PEER_AP, 1903 WIFI_PEER_P2P_GO, 1904 WIFI_PEER_P2P_CLIENT, 1905 WIFI_PEER_NAN, 1906 WIFI_PEER_TDLS, 1907 WIFI_PEER_INVALID, 1908 } wifi_peer_type; 1909 1910 /** per peer statistics */ 1911 typedef struct { 1912 /** peer type (AP, TDLS, GO etc.) */ 1913 wifi_peer_type type; 1914 /** mac address */ 1915 t_u8 peer_mac_address[6]; 1916 /** peer WIFI_CAPABILITY_XXX */ 1917 t_u32 capabilities; 1918 /** number of rates */ 1919 t_u32 num_rate; 1920 /** per rate statistics, number of entries = num_rate */ 1921 wifi_rate_stat rate_stats[]; 1922 } wifi_peer_info; 1923 1924 /** per access category statistics */ 1925 typedef struct { 1926 /** access category (VI, VO, BE, BK) */ 1927 mlan_wmm_ac_e ac; 1928 /** number of successfully transmitted unicast data pkts (ACK rcvd) */ 1929 t_u32 tx_mpdu; 1930 /** number of received unicast mpdus */ 1931 t_u32 rx_mpdu; 1932 /** number of succesfully transmitted multicast data packets */ 1933 /** STA case: implies ACK received from AP for the unicast packet in 1934 * which mcast pkt was sent */ 1935 t_u32 tx_mcast; 1936 /** number of received multicast data packets */ 1937 t_u32 rx_mcast; 1938 /** number of received unicast a-mpdus */ 1939 t_u32 rx_ampdu; 1940 /** number of transmitted unicast a-mpdus */ 1941 t_u32 tx_ampdu; 1942 /** number of data pkt losses (no ACK) */ 1943 t_u32 mpdu_lost; 1944 /** total number of data pkt retries */ 1945 t_u32 retries; 1946 /** number of short data pkt retries */ 1947 t_u32 retries_short; 1948 /** number of long data pkt retries */ 1949 t_u32 retries_long; 1950 /** data pkt min contention time (usecs) */ 1951 t_u32 contention_time_min; 1952 /** data pkt max contention time (usecs) */ 1953 t_u32 contention_time_max; 1954 /** data pkt avg contention time (usecs) */ 1955 t_u32 contention_time_avg; 1956 /** num of data pkts used for contention statistics */ 1957 t_u32 contention_num_samples; 1958 } wifi_wmm_ac_stat; 1959 1960 /** interface statistics */ 1961 typedef struct { 1962 /** wifi interface */ 1963 /* wifi_interface_handle iface;*/ 1964 /** current state of the interface */ 1965 mlan_interface_link_layer_info info; 1966 /** access point beacon received count from connected AP */ 1967 t_u32 beacon_rx; 1968 /** Average beacon offset encountered (beacon_TSF - TBTT) 1969 * the average_tsf_offset field is used so as to calculate the 1970 * typical beacon contention time on the channel as well may be 1971 * used to debug beacon synchronization and related power consumption 1972 * issue 1973 */ 1974 t_u64 average_tsf_offset; 1975 /** indicate that this AP typically leaks packets beyond the driver 1976 * guard time */ 1977 t_u32 leaky_ap_detected; 1978 /** average number of frame leaked by AP after frame with PM bit set was 1979 * ACK'ed by AP */ 1980 t_u32 leaky_ap_avg_num_frames_leaked; 1981 /** Guard time currently in force (when implementing IEEE power 1982 * management based on frame control PM bit), How long driver waits 1983 * before shutting down the radio and after receiving an ACK for a data 1984 * frame with PM bit set) 1985 */ 1986 t_u32 leaky_ap_guard_time; 1987 /** access point mgmt frames received count from connected AP (including 1988 * Beacon) */ 1989 t_u32 mgmt_rx; 1990 /** action frames received count */ 1991 t_u32 mgmt_action_rx; 1992 /** action frames transmit count */ 1993 t_u32 mgmt_action_tx; 1994 /** access Point Beacon and Management frames RSSI (averaged) */ 1995 t_s32 rssi_mgmt; 1996 /** access Point Data Frames RSSI (averaged) from connected AP */ 1997 t_s32 rssi_data; 1998 /** access Point ACK RSSI (averaged) from connected AP */ 1999 t_s32 rssi_ack; 2000 /** per ac data packet statistics */ 2001 wifi_wmm_ac_stat ac[MAX_AC_QUEUES]; 2002 /** number of peers */ 2003 t_u32 num_peers; 2004 /** per peer statistics */ 2005 wifi_peer_info peer_info[]; 2006 } wifi_iface_stat; 2007 2008 /** link layer stat configuration params */ 2009 typedef struct { 2010 /** threshold to classify the pkts as short or long */ 2011 t_u32 mpdu_size_threshold; 2012 /** wifi statistics bitmap */ 2013 t_u32 aggressive_statistics_gathering; 2014 } wifi_link_layer_params; 2015 2016 /** wifi statistics bitmap */ 2017 #define WIFI_STATS_RADIO 0x00000001 /** all radio statistics */ 2018 #define WIFI_STATS_RADIO_CCA \ 2019 0x00000002 /** cca_busy_time (within radio statistics) */ 2020 #define WIFI_STATS_RADIO_CHANNELS \ 2021 0x00000004 /** all channel statistics (within radio statistics) */ 2022 #define WIFI_STATS_RADIO_SCAN \ 2023 0x00000008 /** all scan statistics (within radio statistics) */ 2024 #define WIFI_STATS_IFACE 0x00000010 /** all interface statistics */ 2025 #define WIFI_STATS_IFACE_TXRATE \ 2026 0x00000020 /** all tx rate statistics (within interface statistics) */ 2027 #define WIFI_STATS_IFACE_AC \ 2028 0x00000040 /** all ac statistics (within interface statistics) */ 2029 #define WIFI_STATS_IFACE_CONTENTION \ 2030 0x00000080 /** all contention (min, max, avg) statistics (within ac \ 2031 statisctics) */ 2032 2033 /** station stats */ 2034 typedef struct _sta_stats { 2035 /** last_rx_in_msec */ 2036 t_u64 last_rx_in_msec; 2037 /** rx_packets */ 2038 t_u32 rx_packets; 2039 /** tx packets */ 2040 t_u32 tx_packets; 2041 /** rx bytes */ 2042 t_u32 rx_bytes; 2043 /** tx bytes */ 2044 t_u32 tx_bytes; 2045 } sta_stats; 2046 2047 #ifdef PRAGMA_PACK 2048 #pragma pack(pop) 2049 #endif 2050 2051 /** mlan_callbacks data structure */ 2052 typedef struct _mlan_callbacks { 2053 /** moal_get_fw_data */ 2054 mlan_status (*moal_get_fw_data)(t_void *pmoal, t_u32 offset, t_u32 len, 2055 t_u8 *pbuf); 2056 mlan_status (*moal_get_vdll_data)(t_void *pmoal, t_u32 len, t_u8 *pbuf); 2057 /** moal_get_hw_spec_complete */ 2058 mlan_status (*moal_get_hw_spec_complete)(t_void *pmoal, 2059 mlan_status status, 2060 pmlan_hw_info phw, 2061 pmlan_bss_tbl ptbl); 2062 /** moal_init_fw_complete */ 2063 mlan_status (*moal_init_fw_complete)(t_void *pmoal, mlan_status status); 2064 /** moal_shutdown_fw_complete */ 2065 mlan_status (*moal_shutdown_fw_complete)(t_void *pmoal, 2066 mlan_status status); 2067 /** moal_send_packet_complete */ 2068 mlan_status (*moal_send_packet_complete)(t_void *pmoal, 2069 pmlan_buffer pmbuf, 2070 mlan_status status); 2071 /** moal_recv_complete */ 2072 mlan_status (*moal_recv_complete)(t_void *pmoal, pmlan_buffer pmbuf, 2073 t_u32 port, mlan_status status); 2074 /** moal_recv_packet */ 2075 mlan_status (*moal_recv_packet)(t_void *pmoal, pmlan_buffer pmbuf); 2076 /** moal_recv_amsdu_packet */ 2077 mlan_status (*moal_recv_amsdu_packet)(t_void *pmoal, 2078 pmlan_buffer pmbuf); 2079 /** moal_recv_event */ 2080 mlan_status (*moal_recv_event)(t_void *pmoal, pmlan_event pmevent); 2081 /** moal_ioctl_complete */ 2082 mlan_status (*moal_ioctl_complete)(t_void *pmoal, 2083 pmlan_ioctl_req pioctl_req, 2084 mlan_status status); 2085 2086 /** moal_alloc_mlan_buffer */ 2087 mlan_status (*moal_alloc_mlan_buffer)(t_void *pmoal, t_u32 size, 2088 ppmlan_buffer pmbuf); 2089 /** moal_free_mlan_buffer */ 2090 mlan_status (*moal_free_mlan_buffer)(t_void *pmoal, pmlan_buffer pmbuf); 2091 2092 #ifdef USB 2093 /** moal_write_data_async */ 2094 mlan_status (*moal_write_data_async)(t_void *pmoal, pmlan_buffer pmbuf, 2095 t_u32 port); 2096 #endif /* USB */ 2097 #if defined(SDIO) || defined(PCIE) 2098 /** moal_write_reg */ 2099 mlan_status (*moal_write_reg)(t_void *pmoal, t_u32 reg, t_u32 data); 2100 /** moal_read_reg */ 2101 mlan_status (*moal_read_reg)(t_void *pmoal, t_u32 reg, t_u32 *data); 2102 #endif /* SDIO || PCIE */ 2103 /** moal_write_data_sync */ 2104 mlan_status (*moal_write_data_sync)(t_void *pmoal, pmlan_buffer pmbuf, 2105 t_u32 port, t_u32 timeout); 2106 /** moal_read_data_sync */ 2107 mlan_status (*moal_read_data_sync)(t_void *pmoal, pmlan_buffer pmbuf, 2108 t_u32 port, t_u32 timeout); 2109 /** moal_malloc */ 2110 mlan_status (*moal_malloc)(t_void *pmoal, t_u32 size, t_u32 flag, 2111 t_u8 **ppbuf); 2112 /** moal_mfree */ 2113 mlan_status (*moal_mfree)(t_void *pmoal, t_u8 *pbuf); 2114 /** moal_vmalloc */ 2115 mlan_status (*moal_vmalloc)(t_void *pmoal, t_u32 size, t_u8 **ppbuf); 2116 /** moal_vfree */ 2117 mlan_status (*moal_vfree)(t_void *pmoal, t_u8 *pbuf); 2118 #ifdef PCIE 2119 /** moal_malloc_consistent */ 2120 mlan_status (*moal_malloc_consistent)(t_void *pmoal, t_u32 size, 2121 t_u8 **ppbuf, t_u64 *pbuf_pa); 2122 /** moal_mfree_consistent */ 2123 mlan_status (*moal_mfree_consistent)(t_void *pmoal, t_u32 size, 2124 t_u8 *pbuf, t_u64 buf_pa); 2125 /** moal_map_memory */ 2126 mlan_status (*moal_map_memory)(t_void *pmoal, t_u8 *pbuf, 2127 t_u64 *pbuf_pa, t_u32 size, t_u32 flag); 2128 /** moal_unmap_memory */ 2129 mlan_status (*moal_unmap_memory)(t_void *pmoal, t_u8 *pbuf, 2130 t_u64 buf_pa, t_u32 size, t_u32 flag); 2131 #endif /* PCIE */ 2132 /** moal_memset */ 2133 t_void *(*moal_memset)(t_void *pmoal, t_void *pmem, t_u8 byte, 2134 t_u32 num); 2135 /** moal_memcpy */ 2136 t_void *(*moal_memcpy)(t_void *pmoal, t_void *pdest, const t_void *psrc, 2137 t_u32 num); 2138 /** moal_memcpy_ext */ 2139 t_void *(*moal_memcpy_ext)(t_void *pmoal, t_void *pdest, 2140 const t_void *psrc, t_u32 num, 2141 t_u32 dest_size); 2142 /** moal_memmove */ 2143 t_void *(*moal_memmove)(t_void *pmoal, t_void *pdest, 2144 const t_void *psrc, t_u32 num); 2145 /** moal_memcmp */ 2146 t_s32 (*moal_memcmp)(t_void *pmoal, const t_void *pmem1, 2147 const t_void *pmem2, t_u32 num); 2148 /** moal_udelay */ 2149 t_void (*moal_udelay)(t_void *pmoal, t_u32 udelay); 2150 /** moal_usleep_range */ 2151 t_void (*moal_usleep_range)(t_void *pmoal, t_u32 min_delay, 2152 t_u32 max_delay); 2153 /** moal_get_boot_ktime */ 2154 mlan_status (*moal_get_boot_ktime)(t_void *pmoal, t_u64 *pnsec); 2155 /** moal_get_system_time */ 2156 mlan_status (*moal_get_system_time)(t_void *pmoal, t_u32 *psec, 2157 t_u32 *pusec); 2158 /** moal_init_timer*/ 2159 mlan_status (*moal_init_timer)(t_void *pmoal, t_void **pptimer, 2160 IN t_void (*callback)(t_void *pcontext), 2161 t_void *pcontext); 2162 /** moal_free_timer */ 2163 mlan_status (*moal_free_timer)(t_void *pmoal, t_void *ptimer); 2164 /** moal_start_timer*/ 2165 mlan_status (*moal_start_timer)(t_void *pmoal, t_void *ptimer, 2166 t_u8 periodic, t_u32 msec); 2167 /** moal_stop_timer*/ 2168 mlan_status (*moal_stop_timer)(t_void *pmoal, t_void *ptimer); 2169 /** moal_init_lock */ 2170 mlan_status (*moal_init_lock)(t_void *pmoal, t_void **pplock); 2171 /** moal_free_lock */ 2172 mlan_status (*moal_free_lock)(t_void *pmoal, t_void *plock); 2173 /** moal_spin_lock */ 2174 mlan_status (*moal_spin_lock)(t_void *pmoal, t_void *plock); 2175 /** moal_spin_unlock */ 2176 mlan_status (*moal_spin_unlock)(t_void *pmoal, t_void *plock); 2177 /** moal_print */ 2178 t_void (*moal_print)(t_void *pmoal, t_u32 level, char *pformat, IN...); 2179 /** moal_print_netintf */ 2180 t_void (*moal_print_netintf)(t_void *pmoal, t_u32 bss_index, 2181 t_u32 level); 2182 /** moal_assert */ 2183 t_void (*moal_assert)(t_void *pmoal, t_u32 cond); 2184 2185 /** moal_hist_data_add */ 2186 t_void (*moal_hist_data_add)(t_void *pmoal, t_u32 bss_index, 2187 t_u16 rx_rate, t_s8 snr, t_s8 nflr, 2188 t_u8 antenna); 2189 t_void (*moal_updata_peer_signal)(t_void *pmoal, t_u32 bss_index, 2190 t_u8 *peer_addr, t_s8 snr, t_s8 nflr); 2191 t_u64 (*moal_do_div)(t_u64 num, t_u32 base); 2192 #if defined(DRV_EMBEDDED_AUTHENTICATOR) || defined(DRV_EMBEDDED_SUPPLICANT) 2193 mlan_status (*moal_wait_hostcmd_complete)(t_void *pmoal, 2194 t_u32 bss_index); 2195 mlan_status (*moal_notify_hostcmd_complete)(t_void *pmoal, 2196 t_u32 bss_index); 2197 #endif 2198 void (*moal_tp_accounting)(t_void *pmoal, t_void *buf, 2199 t_u32 drop_point); 2200 void (*moal_tp_accounting_rx_param)(t_void *pmoal, unsigned int type, 2201 unsigned int rsvd1); 2202 void (*moal_amsdu_tp_accounting)(t_void *pmoal, t_s32 delay, 2203 t_s32 copy_delay); 2204 } mlan_callbacks, *pmlan_callbacks; 2205 2206 /** Parameter unchanged, use MLAN default setting */ 2207 #define ROBUSTCOEX_GPIO_UNCHANGED 0 2208 /** Parameter enabled, override MLAN default setting */ 2209 #define ROBUSTCOEX_GPIO_CFG 1 2210 2211 #if defined(SDIO) 2212 /** Interrupt Mode SDIO */ 2213 #define INT_MODE_SDIO 0 2214 /** Interrupt Mode GPIO */ 2215 #define INT_MODE_GPIO 1 2216 /** New mode: GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1 2217 */ 2218 #define GPIO_INT_NEW_MODE 255 2219 #endif 2220 2221 /** Parameter unchanged, use MLAN default setting */ 2222 #define MLAN_INIT_PARA_UNCHANGED 0 2223 /** Parameter enabled, override MLAN default setting */ 2224 #define MLAN_INIT_PARA_ENABLED 1 2225 /** Parameter disabled, override MLAN default setting */ 2226 #define MLAN_INIT_PARA_DISABLED 2 2227 2228 /** Control bit for stream 2X2 */ 2229 #define FEATURE_CTRL_STREAM_2X2 MBIT(0) 2230 /** Control bit for DFS support */ 2231 #define FEATURE_CTRL_DFS_SUPPORT MBIT(1) 2232 #ifdef USB 2233 /** Control bit for winner check & not wait for FW ready event */ 2234 #define FEATURE_CTRL_USB_NEW_INIT MBIT(2) 2235 #endif 2236 /** Default feature control */ 2237 #define FEATURE_CTRL_DEFAULT 0xffffffff 2238 /** Check if stream 2X2 enabled */ 2239 #define IS_STREAM_2X2(x) ((x)&FEATURE_CTRL_STREAM_2X2) 2240 /** Check if DFS support enabled */ 2241 #define IS_DFS_SUPPORT(x) ((x)&FEATURE_CTRL_DFS_SUPPORT) 2242 #ifdef USB 2243 /** Check if winner check & not wait for FW ready event */ 2244 #define IS_USB_NEW_INIT(x) ((x)&FEATURE_CTRL_USB_NEW_INIT) 2245 #endif 2246 2247 /* 2248 #define DRV_MODE_NAN MBIT(4) 2249 #define DRV_MODE_11P MBIT(5) 2250 #define DRV_MODE_MAC80211 MBIT(6) 2251 #define DRV_MODE_DFS MBIT(7)*/ 2252 #define DRV_MODE_MASK (MBIT(4) | MBIT(5) | MBIT(6) | MBIT(7)) 2253 2254 /** mlan_device data structure */ 2255 typedef struct _mlan_device { 2256 /** MOAL Handle */ 2257 t_void *pmoal_handle; 2258 /** BSS Attributes */ 2259 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 2260 /** Callbacks */ 2261 mlan_callbacks callbacks; 2262 #ifdef MFG_CMD_SUPPORT 2263 /** MFG mode */ 2264 t_u32 mfg_mode; 2265 #endif 2266 #ifdef PCIE 2267 t_u16 ring_size; 2268 #endif 2269 #if defined(SDIO) 2270 /** SDIO interrupt mode (0: INT_MODE_SDIO, 1: INT_MODE_GPIO) */ 2271 t_u32 int_mode; 2272 /** GPIO interrupt pin number */ 2273 t_u32 gpio_pin; 2274 #endif 2275 #ifdef DEBUG_LEVEL1 2276 /** Driver debug bit masks */ 2277 t_u32 drvdbg; 2278 #endif 2279 /** allocate fixed buffer size for scan beacon buffer*/ 2280 t_u32 fixed_beacon_buffer; 2281 /** SDIO MPA Tx */ 2282 t_u32 mpa_tx_cfg; 2283 /** SDIO MPA Rx */ 2284 t_u32 mpa_rx_cfg; 2285 #ifdef SDIO 2286 /** SDIO Single port rx aggr */ 2287 t_u8 sdio_rx_aggr_enable; 2288 /* see blk_queue_max_segment_size */ 2289 t_u32 max_seg_size; 2290 /* see blk_queue_max_segments */ 2291 t_u16 max_segs; 2292 #endif 2293 /** Auto deep sleep */ 2294 t_u32 auto_ds; 2295 /** IEEE PS mode */ 2296 t_u32 ps_mode; 2297 /** Max Tx buffer size */ 2298 t_u32 max_tx_buf; 2299 #if defined(STA_SUPPORT) 2300 /** 802.11d configuration */ 2301 t_u32 cfg_11d; 2302 #endif 2303 /** Feature control bitmask */ 2304 t_u32 feature_control; 2305 /** enable/disable rx work */ 2306 t_u8 rx_work; 2307 /** dev cap mask */ 2308 t_u32 dev_cap_mask; 2309 /** oob independent reset */ 2310 t_u32 indrstcfg; 2311 /** dtim interval */ 2312 t_u16 multi_dtim; 2313 /** IEEE ps inactivity timeout value */ 2314 t_u16 inact_tmo; 2315 /** card type */ 2316 t_u16 card_type; 2317 /** card rev */ 2318 t_u8 card_rev; 2319 /** Host sleep wakeup interval */ 2320 t_u32 hs_wake_interval; 2321 /** GPIO to indicate wakeup source */ 2322 t_u8 indication_gpio; 2323 /** Dynamic MIMO-SISO switch for hscfg*/ 2324 t_u8 hs_mimo_switch; 2325 #ifdef USB 2326 /** Tx CMD endpoint address */ 2327 t_u8 tx_cmd_ep; 2328 /** Rx CMD/EVT endpoint address */ 2329 t_u8 rx_cmd_ep; 2330 2331 /** Rx data endpoint address */ 2332 t_u8 rx_data_ep; 2333 /** Tx data endpoint address */ 2334 t_u8 tx_data_ep; 2335 #endif 2336 /** passive to active scan */ 2337 t_u8 passive_to_active_scan; 2338 /** uap max supported station per chip */ 2339 t_u8 uap_max_sta; 2340 /** drv mode */ 2341 t_u32 drv_mode; 2342 /** dfs w53 cfg */ 2343 t_u8 dfs53cfg; 2344 /** dfs_offload */ 2345 t_u8 dfs_offload; 2346 /** extend enhance scan */ 2347 t_u8 ext_scan; 2348 /* mcs32 setting */ 2349 t_u8 mcs32; 2350 } mlan_device, *pmlan_device; 2351 2352 /** MLAN API function prototype */ 2353 #define MLAN_API 2354 2355 /** Registration */ 2356 MLAN_API mlan_status mlan_register(pmlan_device pmdevice, 2357 t_void **ppmlan_adapter); 2358 2359 /** Un-registration */ 2360 MLAN_API mlan_status mlan_unregister(t_void *padapter); 2361 2362 /** Firmware Downloading */ 2363 MLAN_API mlan_status mlan_dnld_fw(t_void *padapter, pmlan_fw_image pmfw); 2364 2365 /** Custom data pass API */ 2366 MLAN_API mlan_status mlan_set_init_param(t_void *padapter, 2367 pmlan_init_param pparam); 2368 2369 /** Firmware Initialization */ 2370 MLAN_API mlan_status mlan_init_fw(t_void *padapter); 2371 2372 /** Firmware Shutdown */ 2373 MLAN_API mlan_status mlan_shutdown_fw(t_void *padapter); 2374 2375 /** Main Process */ 2376 MLAN_API mlan_status mlan_main_process(t_void *padapter); 2377 2378 /** Rx process */ 2379 mlan_status mlan_rx_process(t_void *padapter, t_u8 *rx_pkts); 2380 2381 /** Packet Transmission */ 2382 MLAN_API mlan_status mlan_send_packet(t_void *padapter, pmlan_buffer pmbuf); 2383 2384 #ifdef USB 2385 /** mlan_write_data_async_complete */ 2386 MLAN_API mlan_status mlan_write_data_async_complete(t_void *padapter, 2387 pmlan_buffer pmbuf, 2388 t_u32 port, 2389 mlan_status status); 2390 2391 /** Packet Reception */ 2392 MLAN_API mlan_status mlan_recv(t_void *padapter, pmlan_buffer pmbuf, 2393 t_u32 port); 2394 #endif /* USB */ 2395 2396 /** Packet Reception complete callback */ 2397 MLAN_API mlan_status mlan_recv_packet_complete(t_void *padapter, 2398 pmlan_buffer pmbuf, 2399 mlan_status status); 2400 2401 /** handle amsdu deaggregated packet */ 2402 void mlan_process_deaggr_pkt(t_void *padapter, pmlan_buffer pmbuf, t_u8 *drop); 2403 2404 #if defined(SDIO) || defined(PCIE) 2405 /** interrupt handler */ 2406 MLAN_API mlan_status mlan_interrupt(t_u16 msg_id, t_void *padapter); 2407 2408 #if defined(SYSKT) 2409 /** GPIO IRQ callback function */ 2410 MLAN_API t_void mlan_hs_callback(t_void *pctx); 2411 #endif /* SYSKT_MULTI || SYSKT */ 2412 #endif /* SDIO || PCIE */ 2413 2414 MLAN_API t_void mlan_pm_wakeup_card(t_void *padapter, t_u8 keep_wakeup); 2415 2416 MLAN_API t_u8 mlan_is_main_process_running(t_void *adapter); 2417 #ifdef PCIE 2418 MLAN_API t_void mlan_set_int_mode(t_void *adapter, t_u32 int_mode, 2419 t_u8 func_num); 2420 #endif 2421 /** mlan ioctl */ 2422 MLAN_API mlan_status mlan_ioctl(t_void *padapter, pmlan_ioctl_req pioctl_req); 2423 /** mlan select wmm queue */ 2424 MLAN_API t_u8 mlan_select_wmm_queue(t_void *padapter, t_u8 bss_num, t_u8 tid); 2425 2426 /** mlan mask host interrupt */ 2427 MLAN_API mlan_status mlan_disable_host_int(t_void *padapter); 2428 /** mlan unmask host interrupt */ 2429 MLAN_API mlan_status mlan_enable_host_int(t_void *padapter); 2430 2431 #define CSI_SIGNATURE 0xABCD 2432 2433 #endif /* !_MLAN_DECL_H_ */ 2434