1 /*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2020, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: pv-drivers@vmware.com
24 *
25 */
26
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
29
30 #include "vmxnet3_int.h"
31
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
35 /*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
39 static const struct pci_device_id vmxnet3_pciid_table[] = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42 };
43
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
46 static int enable_mq = 1;
47
48 static void
49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
50
51 /*
52 * Enable/Disable the given intr
53 */
54 static void
vmxnet3_enable_intr(struct vmxnet3_adapter * adapter,unsigned intr_idx)55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
56 {
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
58 }
59
60
61 static void
vmxnet3_disable_intr(struct vmxnet3_adapter * adapter,unsigned intr_idx)62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
63 {
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
65 }
66
67
68 /*
69 * Enable/Disable all intrs used by the device
70 */
71 static void
vmxnet3_enable_all_intrs(struct vmxnet3_adapter * adapter)72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
73 {
74 int i;
75
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
80 }
81
82
83 static void
vmxnet3_disable_all_intrs(struct vmxnet3_adapter * adapter)84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
85 {
86 int i;
87
88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
92 }
93
94
95 static void
vmxnet3_ack_events(struct vmxnet3_adapter * adapter,u32 events)96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
97 {
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
99 }
100
101
102 static bool
vmxnet3_tq_stopped(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
104 {
105 return tq->stopped;
106 }
107
108
109 static void
vmxnet3_tq_start(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
111 {
112 tq->stopped = false;
113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
114 }
115
116
117 static void
vmxnet3_tq_wake(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
119 {
120 tq->stopped = false;
121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
122 }
123
124
125 static void
vmxnet3_tq_stop(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
127 {
128 tq->stopped = true;
129 tq->num_stop++;
130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
131 }
132
133
134 /*
135 * Check the link state. This may start or stop the tx queue.
136 */
137 static void
vmxnet3_check_link(struct vmxnet3_adapter * adapter,bool affectTxQueue)138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
139 {
140 u32 ret;
141 int i;
142 unsigned long flags;
143
144 spin_lock_irqsave(&adapter->cmd_lock, flags);
145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
148
149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
153 netif_carrier_on(adapter->netdev);
154
155 if (affectTxQueue) {
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
158 adapter);
159 }
160 } else {
161 netdev_info(adapter->netdev, "NIC Link is Down\n");
162 netif_carrier_off(adapter->netdev);
163
164 if (affectTxQueue) {
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
167 }
168 }
169 }
170
171 static void
vmxnet3_process_events(struct vmxnet3_adapter * adapter)172 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
173 {
174 int i;
175 unsigned long flags;
176 u32 events = le32_to_cpu(adapter->shared->ecr);
177 if (!events)
178 return;
179
180 vmxnet3_ack_events(adapter, events);
181
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
184 vmxnet3_check_link(adapter, true);
185
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
188 spin_lock_irqsave(&adapter->cmd_lock, flags);
189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
192
193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
205
206 schedule_work(&adapter->work);
207 }
208 }
209
210 #ifdef __BIG_ENDIAN_BITFIELD
211 /*
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
222 */
vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc * srcDesc,struct Vmxnet3_RxDesc * dstDesc)223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
225 {
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
231 }
232
vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc * srcDesc,struct Vmxnet3_TxDesc * dstDesc)233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
235 {
236 int i;
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
239
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
242 src--;
243 dst--;
244 *dst = cpu_to_le32(*src);
245 }
246 }
247
248
vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc * srcDesc,struct Vmxnet3_RxCompDesc * dstDesc)249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
251 {
252 int i = 0;
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
257 src++;
258 dst++;
259 }
260 }
261
262
263 /* Used to read bitfield values from double words. */
get_bitfield32(const __le32 * bitfield,u32 pos,u32 size)264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
265 {
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
268 temp &= mask;
269 temp >>= pos;
270 return temp;
271 }
272
273
274
275 #endif /* __BIG_ENDIAN_BITFIELD */
276
277 #ifdef __BIG_ENDIAN_BITFIELD
278
279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
291 (dstrcd) = (tmp); \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
293 } while (0)
294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
295 (dstrxd) = (tmp); \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
297 } while (0)
298
299 #else
300
301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
307
308 #endif /* __BIG_ENDIAN_BITFIELD */
309
310
311 static void
vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info * tbi,struct pci_dev * pdev)312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
314 {
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
317 PCI_DMA_TODEVICE);
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
320 PCI_DMA_TODEVICE);
321 else
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
323
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
325 }
326
327
328 static int
vmxnet3_unmap_pkt(u32 eop_idx,struct vmxnet3_tx_queue * tq,struct pci_dev * pdev,struct vmxnet3_adapter * adapter)329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
331 {
332 struct sk_buff *skb;
333 int entries = 0;
334
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
338
339 skb = tq->buf_info[eop_idx].skb;
340 BUG_ON(skb == NULL);
341 tq->buf_info[eop_idx].skb = NULL;
342
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
344
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
347 pdev);
348
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
353 */
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
355 entries++;
356 }
357
358 dev_kfree_skb_any(skb);
359 return entries;
360 }
361
362
363 static int
vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
366 {
367 int completed = 0;
368 union Vmxnet3_GenericDesc *gdesc;
369
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 /* Prevent any &gdesc->tcd field from being (speculatively)
373 * read before (&gdesc->tcd)->gen is read.
374 */
375 dma_rmb();
376
377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
378 &gdesc->tcd), tq, adapter->pdev,
379 adapter);
380
381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
383 }
384
385 if (completed) {
386 spin_lock(&tq->tx_lock);
387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
390 netif_carrier_ok(adapter->netdev))) {
391 vmxnet3_tq_wake(tq, adapter);
392 }
393 spin_unlock(&tq->tx_lock);
394 }
395 return completed;
396 }
397
398
399 static void
vmxnet3_tq_cleanup(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
401 struct vmxnet3_adapter *adapter)
402 {
403 int i;
404
405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
406 struct vmxnet3_tx_buf_info *tbi;
407
408 tbi = tq->buf_info + tq->tx_ring.next2comp;
409
410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
411 if (tbi->skb) {
412 dev_kfree_skb_any(tbi->skb);
413 tbi->skb = NULL;
414 }
415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
416 }
417
418 /* sanity check, verify all buffers are indeed unmapped and freed */
419 for (i = 0; i < tq->tx_ring.size; i++) {
420 BUG_ON(tq->buf_info[i].skb != NULL ||
421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
422 }
423
424 tq->tx_ring.gen = VMXNET3_INIT_GEN;
425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
426
427 tq->comp_ring.gen = VMXNET3_INIT_GEN;
428 tq->comp_ring.next2proc = 0;
429 }
430
431
432 static void
vmxnet3_tq_destroy(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
434 struct vmxnet3_adapter *adapter)
435 {
436 if (tq->tx_ring.base) {
437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
438 sizeof(struct Vmxnet3_TxDesc),
439 tq->tx_ring.base, tq->tx_ring.basePA);
440 tq->tx_ring.base = NULL;
441 }
442 if (tq->data_ring.base) {
443 dma_free_coherent(&adapter->pdev->dev,
444 tq->data_ring.size * tq->txdata_desc_size,
445 tq->data_ring.base, tq->data_ring.basePA);
446 tq->data_ring.base = NULL;
447 }
448 if (tq->comp_ring.base) {
449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
450 sizeof(struct Vmxnet3_TxCompDesc),
451 tq->comp_ring.base, tq->comp_ring.basePA);
452 tq->comp_ring.base = NULL;
453 }
454 if (tq->buf_info) {
455 dma_free_coherent(&adapter->pdev->dev,
456 tq->tx_ring.size * sizeof(tq->buf_info[0]),
457 tq->buf_info, tq->buf_info_pa);
458 tq->buf_info = NULL;
459 }
460 }
461
462
463 /* Destroy all tx queues */
464 void
vmxnet3_tq_destroy_all(struct vmxnet3_adapter * adapter)465 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
466 {
467 int i;
468
469 for (i = 0; i < adapter->num_tx_queues; i++)
470 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
471 }
472
473
474 static void
vmxnet3_tq_init(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)475 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
476 struct vmxnet3_adapter *adapter)
477 {
478 int i;
479
480 /* reset the tx ring contents to 0 and reset the tx ring states */
481 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
482 sizeof(struct Vmxnet3_TxDesc));
483 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
484 tq->tx_ring.gen = VMXNET3_INIT_GEN;
485
486 memset(tq->data_ring.base, 0,
487 tq->data_ring.size * tq->txdata_desc_size);
488
489 /* reset the tx comp ring contents to 0 and reset comp ring states */
490 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
491 sizeof(struct Vmxnet3_TxCompDesc));
492 tq->comp_ring.next2proc = 0;
493 tq->comp_ring.gen = VMXNET3_INIT_GEN;
494
495 /* reset the bookkeeping data */
496 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
497 for (i = 0; i < tq->tx_ring.size; i++)
498 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
499
500 /* stats are not reset */
501 }
502
503
504 static int
vmxnet3_tq_create(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)505 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
506 struct vmxnet3_adapter *adapter)
507 {
508 size_t sz;
509
510 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
511 tq->comp_ring.base || tq->buf_info);
512
513 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
514 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
515 &tq->tx_ring.basePA, GFP_KERNEL);
516 if (!tq->tx_ring.base) {
517 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
518 goto err;
519 }
520
521 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
522 tq->data_ring.size * tq->txdata_desc_size,
523 &tq->data_ring.basePA, GFP_KERNEL);
524 if (!tq->data_ring.base) {
525 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
526 goto err;
527 }
528
529 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
530 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
531 &tq->comp_ring.basePA, GFP_KERNEL);
532 if (!tq->comp_ring.base) {
533 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
534 goto err;
535 }
536
537 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
538 tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz,
539 &tq->buf_info_pa, GFP_KERNEL);
540 if (!tq->buf_info)
541 goto err;
542
543 return 0;
544
545 err:
546 vmxnet3_tq_destroy(tq, adapter);
547 return -ENOMEM;
548 }
549
550 static void
vmxnet3_tq_cleanup_all(struct vmxnet3_adapter * adapter)551 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
552 {
553 int i;
554
555 for (i = 0; i < adapter->num_tx_queues; i++)
556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
557 }
558
559 /*
560 * starting from ring->next2fill, allocate rx buffers for the given ring
561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
562 * are allocated or allocation fails
563 */
564
565 static int
vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue * rq,u32 ring_idx,int num_to_alloc,struct vmxnet3_adapter * adapter)566 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
567 int num_to_alloc, struct vmxnet3_adapter *adapter)
568 {
569 int num_allocated = 0;
570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
572 u32 val;
573
574 while (num_allocated <= num_to_alloc) {
575 struct vmxnet3_rx_buf_info *rbi;
576 union Vmxnet3_GenericDesc *gd;
577
578 rbi = rbi_base + ring->next2fill;
579 gd = ring->base + ring->next2fill;
580
581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
582 if (rbi->skb == NULL) {
583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
584 rbi->len,
585 GFP_KERNEL);
586 if (unlikely(rbi->skb == NULL)) {
587 rq->stats.rx_buf_alloc_failure++;
588 break;
589 }
590
591 rbi->dma_addr = dma_map_single(
592 &adapter->pdev->dev,
593 rbi->skb->data, rbi->len,
594 PCI_DMA_FROMDEVICE);
595 if (dma_mapping_error(&adapter->pdev->dev,
596 rbi->dma_addr)) {
597 dev_kfree_skb_any(rbi->skb);
598 rbi->skb = NULL;
599 rq->stats.rx_buf_alloc_failure++;
600 break;
601 }
602 } else {
603 /* rx buffer skipped by the device */
604 }
605 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
606 } else {
607 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
608 rbi->len != PAGE_SIZE);
609
610 if (rbi->page == NULL) {
611 rbi->page = alloc_page(GFP_ATOMIC);
612 if (unlikely(rbi->page == NULL)) {
613 rq->stats.rx_buf_alloc_failure++;
614 break;
615 }
616 rbi->dma_addr = dma_map_page(
617 &adapter->pdev->dev,
618 rbi->page, 0, PAGE_SIZE,
619 PCI_DMA_FROMDEVICE);
620 if (dma_mapping_error(&adapter->pdev->dev,
621 rbi->dma_addr)) {
622 put_page(rbi->page);
623 rbi->page = NULL;
624 rq->stats.rx_buf_alloc_failure++;
625 break;
626 }
627 } else {
628 /* rx buffers skipped by the device */
629 }
630 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
631 }
632
633 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
634 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
635 | val | rbi->len);
636
637 /* Fill the last buffer but dont mark it ready, or else the
638 * device will think that the queue is full */
639 if (num_allocated == num_to_alloc)
640 break;
641
642 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
643 num_allocated++;
644 vmxnet3_cmd_ring_adv_next2fill(ring);
645 }
646
647 netdev_dbg(adapter->netdev,
648 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
649 num_allocated, ring->next2fill, ring->next2comp);
650
651 /* so that the device can distinguish a full ring and an empty ring */
652 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
653
654 return num_allocated;
655 }
656
657
658 static void
vmxnet3_append_frag(struct sk_buff * skb,struct Vmxnet3_RxCompDesc * rcd,struct vmxnet3_rx_buf_info * rbi)659 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
660 struct vmxnet3_rx_buf_info *rbi)
661 {
662 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
663
664 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
665
666 __skb_frag_set_page(frag, rbi->page);
667 skb_frag_off_set(frag, 0);
668 skb_frag_size_set(frag, rcd->len);
669 skb->data_len += rcd->len;
670 skb->truesize += PAGE_SIZE;
671 skb_shinfo(skb)->nr_frags++;
672 }
673
674
675 static int
vmxnet3_map_pkt(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_tx_queue * tq,struct pci_dev * pdev,struct vmxnet3_adapter * adapter)676 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
677 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
678 struct vmxnet3_adapter *adapter)
679 {
680 u32 dw2, len;
681 unsigned long buf_offset;
682 int i;
683 union Vmxnet3_GenericDesc *gdesc;
684 struct vmxnet3_tx_buf_info *tbi = NULL;
685
686 BUG_ON(ctx->copy_size > skb_headlen(skb));
687
688 /* use the previous gen bit for the SOP desc */
689 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
690
691 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
692 gdesc = ctx->sop_txd; /* both loops below can be skipped */
693
694 /* no need to map the buffer if headers are copied */
695 if (ctx->copy_size) {
696 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
697 tq->tx_ring.next2fill *
698 tq->txdata_desc_size);
699 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
700 ctx->sop_txd->dword[3] = 0;
701
702 tbi = tq->buf_info + tq->tx_ring.next2fill;
703 tbi->map_type = VMXNET3_MAP_NONE;
704
705 netdev_dbg(adapter->netdev,
706 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
707 tq->tx_ring.next2fill,
708 le64_to_cpu(ctx->sop_txd->txd.addr),
709 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
710 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
711
712 /* use the right gen for non-SOP desc */
713 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
714 }
715
716 /* linear part can use multiple tx desc if it's big */
717 len = skb_headlen(skb) - ctx->copy_size;
718 buf_offset = ctx->copy_size;
719 while (len) {
720 u32 buf_size;
721
722 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
723 buf_size = len;
724 dw2 |= len;
725 } else {
726 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
727 /* spec says that for TxDesc.len, 0 == 2^14 */
728 }
729
730 tbi = tq->buf_info + tq->tx_ring.next2fill;
731 tbi->map_type = VMXNET3_MAP_SINGLE;
732 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
733 skb->data + buf_offset, buf_size,
734 PCI_DMA_TODEVICE);
735 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
736 return -EFAULT;
737
738 tbi->len = buf_size;
739
740 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
741 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
742
743 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
744 gdesc->dword[2] = cpu_to_le32(dw2);
745 gdesc->dword[3] = 0;
746
747 netdev_dbg(adapter->netdev,
748 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
749 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
750 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
751 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
752 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
753
754 len -= buf_size;
755 buf_offset += buf_size;
756 }
757
758 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
760 u32 buf_size;
761
762 buf_offset = 0;
763 len = skb_frag_size(frag);
764 while (len) {
765 tbi = tq->buf_info + tq->tx_ring.next2fill;
766 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
767 buf_size = len;
768 dw2 |= len;
769 } else {
770 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
771 /* spec says that for TxDesc.len, 0 == 2^14 */
772 }
773 tbi->map_type = VMXNET3_MAP_PAGE;
774 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
775 buf_offset, buf_size,
776 DMA_TO_DEVICE);
777 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
778 return -EFAULT;
779
780 tbi->len = buf_size;
781
782 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
783 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
784
785 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
786 gdesc->dword[2] = cpu_to_le32(dw2);
787 gdesc->dword[3] = 0;
788
789 netdev_dbg(adapter->netdev,
790 "txd[%u]: 0x%llx %u %u\n",
791 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
792 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
793 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
794 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
795
796 len -= buf_size;
797 buf_offset += buf_size;
798 }
799 }
800
801 ctx->eop_txd = gdesc;
802
803 /* set the last buf_info for the pkt */
804 tbi->skb = skb;
805 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
806
807 return 0;
808 }
809
810
811 /* Init all tx queues */
812 static void
vmxnet3_tq_init_all(struct vmxnet3_adapter * adapter)813 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
814 {
815 int i;
816
817 for (i = 0; i < adapter->num_tx_queues; i++)
818 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
819 }
820
821
822 /*
823 * parse relevant protocol headers:
824 * For a tso pkt, relevant headers are L2/3/4 including options
825 * For a pkt requesting csum offloading, they are L2/3 and may include L4
826 * if it's a TCP/UDP pkt
827 *
828 * Returns:
829 * -1: error happens during parsing
830 * 0: protocol headers parsed, but too big to be copied
831 * 1: protocol headers parsed and copied
832 *
833 * Other effects:
834 * 1. related *ctx fields are updated.
835 * 2. ctx->copy_size is # of bytes copied
836 * 3. the portion to be copied is guaranteed to be in the linear part
837 *
838 */
839 static int
vmxnet3_parse_hdr(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_adapter * adapter)840 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
841 struct vmxnet3_tx_ctx *ctx,
842 struct vmxnet3_adapter *adapter)
843 {
844 u8 protocol = 0;
845
846 if (ctx->mss) { /* TSO */
847 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
848 ctx->l4_offset = skb_inner_transport_offset(skb);
849 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
850 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
851 } else {
852 ctx->l4_offset = skb_transport_offset(skb);
853 ctx->l4_hdr_size = tcp_hdrlen(skb);
854 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
855 }
856 } else {
857 if (skb->ip_summed == CHECKSUM_PARTIAL) {
858 /* For encap packets, skb_checksum_start_offset refers
859 * to inner L4 offset. Thus, below works for encap as
860 * well as non-encap case
861 */
862 ctx->l4_offset = skb_checksum_start_offset(skb);
863
864 if (VMXNET3_VERSION_GE_4(adapter) &&
865 skb->encapsulation) {
866 struct iphdr *iph = inner_ip_hdr(skb);
867
868 if (iph->version == 4) {
869 protocol = iph->protocol;
870 } else {
871 const struct ipv6hdr *ipv6h;
872
873 ipv6h = inner_ipv6_hdr(skb);
874 protocol = ipv6h->nexthdr;
875 }
876 } else {
877 if (ctx->ipv4) {
878 const struct iphdr *iph = ip_hdr(skb);
879
880 protocol = iph->protocol;
881 } else if (ctx->ipv6) {
882 const struct ipv6hdr *ipv6h;
883
884 ipv6h = ipv6_hdr(skb);
885 protocol = ipv6h->nexthdr;
886 }
887 }
888
889 switch (protocol) {
890 case IPPROTO_TCP:
891 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
892 tcp_hdrlen(skb);
893 break;
894 case IPPROTO_UDP:
895 ctx->l4_hdr_size = sizeof(struct udphdr);
896 break;
897 default:
898 ctx->l4_hdr_size = 0;
899 break;
900 }
901
902 ctx->copy_size = min(ctx->l4_offset +
903 ctx->l4_hdr_size, skb->len);
904 } else {
905 ctx->l4_offset = 0;
906 ctx->l4_hdr_size = 0;
907 /* copy as much as allowed */
908 ctx->copy_size = min_t(unsigned int,
909 tq->txdata_desc_size,
910 skb_headlen(skb));
911 }
912
913 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
914 ctx->copy_size = skb->len;
915
916 /* make sure headers are accessible directly */
917 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
918 goto err;
919 }
920
921 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
922 tq->stats.oversized_hdr++;
923 ctx->copy_size = 0;
924 return 0;
925 }
926
927 return 1;
928 err:
929 return -1;
930 }
931
932 /*
933 * copy relevant protocol headers to the transmit ring:
934 * For a tso pkt, relevant headers are L2/3/4 including options
935 * For a pkt requesting csum offloading, they are L2/3 and may include L4
936 * if it's a TCP/UDP pkt
937 *
938 *
939 * Note that this requires that vmxnet3_parse_hdr be called first to set the
940 * appropriate bits in ctx first
941 */
942 static void
vmxnet3_copy_hdr(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_adapter * adapter)943 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
944 struct vmxnet3_tx_ctx *ctx,
945 struct vmxnet3_adapter *adapter)
946 {
947 struct Vmxnet3_TxDataDesc *tdd;
948
949 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
950 tq->tx_ring.next2fill *
951 tq->txdata_desc_size);
952
953 memcpy(tdd->data, skb->data, ctx->copy_size);
954 netdev_dbg(adapter->netdev,
955 "copy %u bytes to dataRing[%u]\n",
956 ctx->copy_size, tq->tx_ring.next2fill);
957 }
958
959
960 static void
vmxnet3_prepare_inner_tso(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx)961 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
962 struct vmxnet3_tx_ctx *ctx)
963 {
964 struct tcphdr *tcph = inner_tcp_hdr(skb);
965 struct iphdr *iph = inner_ip_hdr(skb);
966
967 if (iph->version == 4) {
968 iph->check = 0;
969 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
970 IPPROTO_TCP, 0);
971 } else {
972 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
973
974 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
975 IPPROTO_TCP, 0);
976 }
977 }
978
979 static void
vmxnet3_prepare_tso(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx)980 vmxnet3_prepare_tso(struct sk_buff *skb,
981 struct vmxnet3_tx_ctx *ctx)
982 {
983 struct tcphdr *tcph = tcp_hdr(skb);
984
985 if (ctx->ipv4) {
986 struct iphdr *iph = ip_hdr(skb);
987
988 iph->check = 0;
989 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
990 IPPROTO_TCP, 0);
991 } else if (ctx->ipv6) {
992 tcp_v6_gso_csum_prep(skb);
993 }
994 }
995
txd_estimate(const struct sk_buff * skb)996 static int txd_estimate(const struct sk_buff *skb)
997 {
998 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
999 int i;
1000
1001 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1002 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1003
1004 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1005 }
1006 return count;
1007 }
1008
1009 /*
1010 * Transmits a pkt thru a given tq
1011 * Returns:
1012 * NETDEV_TX_OK: descriptors are setup successfully
1013 * NETDEV_TX_OK: error occurred, the pkt is dropped
1014 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1015 *
1016 * Side-effects:
1017 * 1. tx ring may be changed
1018 * 2. tq stats may be updated accordingly
1019 * 3. shared->txNumDeferred may be updated
1020 */
1021
1022 static int
vmxnet3_tq_xmit(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter,struct net_device * netdev)1023 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1024 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1025 {
1026 int ret;
1027 u32 count;
1028 int num_pkts;
1029 int tx_num_deferred;
1030 unsigned long flags;
1031 struct vmxnet3_tx_ctx ctx;
1032 union Vmxnet3_GenericDesc *gdesc;
1033 #ifdef __BIG_ENDIAN_BITFIELD
1034 /* Use temporary descriptor to avoid touching bits multiple times */
1035 union Vmxnet3_GenericDesc tempTxDesc;
1036 #endif
1037
1038 count = txd_estimate(skb);
1039
1040 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1041 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1042
1043 ctx.mss = skb_shinfo(skb)->gso_size;
1044 if (ctx.mss) {
1045 if (skb_header_cloned(skb)) {
1046 if (unlikely(pskb_expand_head(skb, 0, 0,
1047 GFP_ATOMIC) != 0)) {
1048 tq->stats.drop_tso++;
1049 goto drop_pkt;
1050 }
1051 tq->stats.copy_skb_header++;
1052 }
1053 if (skb->encapsulation) {
1054 vmxnet3_prepare_inner_tso(skb, &ctx);
1055 } else {
1056 vmxnet3_prepare_tso(skb, &ctx);
1057 }
1058 } else {
1059 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1060
1061 /* non-tso pkts must not use more than
1062 * VMXNET3_MAX_TXD_PER_PKT entries
1063 */
1064 if (skb_linearize(skb) != 0) {
1065 tq->stats.drop_too_many_frags++;
1066 goto drop_pkt;
1067 }
1068 tq->stats.linearized++;
1069
1070 /* recalculate the # of descriptors to use */
1071 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1072 }
1073 }
1074
1075 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1076 if (ret >= 0) {
1077 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1078 /* hdrs parsed, check against other limits */
1079 if (ctx.mss) {
1080 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1081 VMXNET3_MAX_TX_BUF_SIZE)) {
1082 tq->stats.drop_oversized_hdr++;
1083 goto drop_pkt;
1084 }
1085 } else {
1086 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1087 if (unlikely(ctx.l4_offset +
1088 skb->csum_offset >
1089 VMXNET3_MAX_CSUM_OFFSET)) {
1090 tq->stats.drop_oversized_hdr++;
1091 goto drop_pkt;
1092 }
1093 }
1094 }
1095 } else {
1096 tq->stats.drop_hdr_inspect_err++;
1097 goto drop_pkt;
1098 }
1099
1100 spin_lock_irqsave(&tq->tx_lock, flags);
1101
1102 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1103 tq->stats.tx_ring_full++;
1104 netdev_dbg(adapter->netdev,
1105 "tx queue stopped on %s, next2comp %u"
1106 " next2fill %u\n", adapter->netdev->name,
1107 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1108
1109 vmxnet3_tq_stop(tq, adapter);
1110 spin_unlock_irqrestore(&tq->tx_lock, flags);
1111 return NETDEV_TX_BUSY;
1112 }
1113
1114
1115 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1116
1117 /* fill tx descs related to addr & len */
1118 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1119 goto unlock_drop_pkt;
1120
1121 /* setup the EOP desc */
1122 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1123
1124 /* setup the SOP desc */
1125 #ifdef __BIG_ENDIAN_BITFIELD
1126 gdesc = &tempTxDesc;
1127 gdesc->dword[2] = ctx.sop_txd->dword[2];
1128 gdesc->dword[3] = ctx.sop_txd->dword[3];
1129 #else
1130 gdesc = ctx.sop_txd;
1131 #endif
1132 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1133 if (ctx.mss) {
1134 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1135 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1136 gdesc->txd.om = VMXNET3_OM_ENCAP;
1137 gdesc->txd.msscof = ctx.mss;
1138
1139 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1140 gdesc->txd.oco = 1;
1141 } else {
1142 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1143 gdesc->txd.om = VMXNET3_OM_TSO;
1144 gdesc->txd.msscof = ctx.mss;
1145 }
1146 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1147 } else {
1148 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1149 if (VMXNET3_VERSION_GE_4(adapter) &&
1150 skb->encapsulation) {
1151 gdesc->txd.hlen = ctx.l4_offset +
1152 ctx.l4_hdr_size;
1153 gdesc->txd.om = VMXNET3_OM_ENCAP;
1154 gdesc->txd.msscof = 0; /* Reserved */
1155 } else {
1156 gdesc->txd.hlen = ctx.l4_offset;
1157 gdesc->txd.om = VMXNET3_OM_CSUM;
1158 gdesc->txd.msscof = ctx.l4_offset +
1159 skb->csum_offset;
1160 }
1161 } else {
1162 gdesc->txd.om = 0;
1163 gdesc->txd.msscof = 0;
1164 }
1165 num_pkts = 1;
1166 }
1167 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1168 tx_num_deferred += num_pkts;
1169
1170 if (skb_vlan_tag_present(skb)) {
1171 gdesc->txd.ti = 1;
1172 gdesc->txd.tci = skb_vlan_tag_get(skb);
1173 }
1174
1175 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1176 * all other writes to &gdesc->txd.
1177 */
1178 dma_wmb();
1179
1180 /* finally flips the GEN bit of the SOP desc. */
1181 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1182 VMXNET3_TXD_GEN);
1183 #ifdef __BIG_ENDIAN_BITFIELD
1184 /* Finished updating in bitfields of Tx Desc, so write them in original
1185 * place.
1186 */
1187 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1188 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1189 gdesc = ctx.sop_txd;
1190 #endif
1191 netdev_dbg(adapter->netdev,
1192 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1193 (u32)(ctx.sop_txd -
1194 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1195 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1196
1197 spin_unlock_irqrestore(&tq->tx_lock, flags);
1198
1199 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1200 tq->shared->txNumDeferred = 0;
1201 VMXNET3_WRITE_BAR0_REG(adapter,
1202 VMXNET3_REG_TXPROD + tq->qid * 8,
1203 tq->tx_ring.next2fill);
1204 }
1205
1206 return NETDEV_TX_OK;
1207
1208 unlock_drop_pkt:
1209 spin_unlock_irqrestore(&tq->tx_lock, flags);
1210 drop_pkt:
1211 tq->stats.drop_total++;
1212 dev_kfree_skb_any(skb);
1213 return NETDEV_TX_OK;
1214 }
1215
1216
1217 static netdev_tx_t
vmxnet3_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1218 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1219 {
1220 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1221
1222 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1223 return vmxnet3_tq_xmit(skb,
1224 &adapter->tx_queue[skb->queue_mapping],
1225 adapter, netdev);
1226 }
1227
1228
1229 static void
vmxnet3_rx_csum(struct vmxnet3_adapter * adapter,struct sk_buff * skb,union Vmxnet3_GenericDesc * gdesc)1230 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1231 struct sk_buff *skb,
1232 union Vmxnet3_GenericDesc *gdesc)
1233 {
1234 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1235 if (gdesc->rcd.v4 &&
1236 (le32_to_cpu(gdesc->dword[3]) &
1237 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1238 skb->ip_summed = CHECKSUM_UNNECESSARY;
1239 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1240 !(le32_to_cpu(gdesc->dword[0]) &
1241 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1242 WARN_ON_ONCE(gdesc->rcd.frg &&
1243 !(le32_to_cpu(gdesc->dword[0]) &
1244 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1245 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1246 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1247 skb->ip_summed = CHECKSUM_UNNECESSARY;
1248 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1249 !(le32_to_cpu(gdesc->dword[0]) &
1250 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1251 WARN_ON_ONCE(gdesc->rcd.frg &&
1252 !(le32_to_cpu(gdesc->dword[0]) &
1253 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1254 } else {
1255 if (gdesc->rcd.csum) {
1256 skb->csum = htons(gdesc->rcd.csum);
1257 skb->ip_summed = CHECKSUM_PARTIAL;
1258 } else {
1259 skb_checksum_none_assert(skb);
1260 }
1261 }
1262 } else {
1263 skb_checksum_none_assert(skb);
1264 }
1265 }
1266
1267
1268 static void
vmxnet3_rx_error(struct vmxnet3_rx_queue * rq,struct Vmxnet3_RxCompDesc * rcd,struct vmxnet3_rx_ctx * ctx,struct vmxnet3_adapter * adapter)1269 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1270 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1271 {
1272 rq->stats.drop_err++;
1273 if (!rcd->fcs)
1274 rq->stats.drop_fcs++;
1275
1276 rq->stats.drop_total++;
1277
1278 /*
1279 * We do not unmap and chain the rx buffer to the skb.
1280 * We basically pretend this buffer is not used and will be recycled
1281 * by vmxnet3_rq_alloc_rx_buf()
1282 */
1283
1284 /*
1285 * ctx->skb may be NULL if this is the first and the only one
1286 * desc for the pkt
1287 */
1288 if (ctx->skb)
1289 dev_kfree_skb_irq(ctx->skb);
1290
1291 ctx->skb = NULL;
1292 }
1293
1294
1295 static u32
vmxnet3_get_hdr_len(struct vmxnet3_adapter * adapter,struct sk_buff * skb,union Vmxnet3_GenericDesc * gdesc)1296 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1297 union Vmxnet3_GenericDesc *gdesc)
1298 {
1299 u32 hlen, maplen;
1300 union {
1301 void *ptr;
1302 struct ethhdr *eth;
1303 struct vlan_ethhdr *veth;
1304 struct iphdr *ipv4;
1305 struct ipv6hdr *ipv6;
1306 struct tcphdr *tcp;
1307 } hdr;
1308 BUG_ON(gdesc->rcd.tcp == 0);
1309
1310 maplen = skb_headlen(skb);
1311 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1312 return 0;
1313
1314 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1315 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1316 hlen = sizeof(struct vlan_ethhdr);
1317 else
1318 hlen = sizeof(struct ethhdr);
1319
1320 hdr.eth = eth_hdr(skb);
1321 if (gdesc->rcd.v4) {
1322 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1323 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1324 hdr.ptr += hlen;
1325 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1326 hlen = hdr.ipv4->ihl << 2;
1327 hdr.ptr += hdr.ipv4->ihl << 2;
1328 } else if (gdesc->rcd.v6) {
1329 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1330 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1331 hdr.ptr += hlen;
1332 /* Use an estimated value, since we also need to handle
1333 * TSO case.
1334 */
1335 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1336 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1337 hlen = sizeof(struct ipv6hdr);
1338 hdr.ptr += sizeof(struct ipv6hdr);
1339 } else {
1340 /* Non-IP pkt, dont estimate header length */
1341 return 0;
1342 }
1343
1344 if (hlen + sizeof(struct tcphdr) > maplen)
1345 return 0;
1346
1347 return (hlen + (hdr.tcp->doff << 2));
1348 }
1349
1350 static int
vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter,int quota)1351 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1352 struct vmxnet3_adapter *adapter, int quota)
1353 {
1354 static const u32 rxprod_reg[2] = {
1355 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1356 };
1357 u32 num_pkts = 0;
1358 bool skip_page_frags = false;
1359 bool encap_lro = false;
1360 struct Vmxnet3_RxCompDesc *rcd;
1361 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1362 u16 segCnt = 0, mss = 0;
1363 #ifdef __BIG_ENDIAN_BITFIELD
1364 struct Vmxnet3_RxDesc rxCmdDesc;
1365 struct Vmxnet3_RxCompDesc rxComp;
1366 #endif
1367 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1368 &rxComp);
1369 while (rcd->gen == rq->comp_ring.gen) {
1370 struct vmxnet3_rx_buf_info *rbi;
1371 struct sk_buff *skb, *new_skb = NULL;
1372 struct page *new_page = NULL;
1373 dma_addr_t new_dma_addr;
1374 int num_to_alloc;
1375 struct Vmxnet3_RxDesc *rxd;
1376 u32 idx, ring_idx;
1377 struct vmxnet3_cmd_ring *ring = NULL;
1378 if (num_pkts >= quota) {
1379 /* we may stop even before we see the EOP desc of
1380 * the current pkt
1381 */
1382 break;
1383 }
1384
1385 /* Prevent any rcd field from being (speculatively) read before
1386 * rcd->gen is read.
1387 */
1388 dma_rmb();
1389
1390 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1391 rcd->rqID != rq->dataRingQid);
1392 idx = rcd->rxdIdx;
1393 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1394 ring = rq->rx_ring + ring_idx;
1395 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1396 &rxCmdDesc);
1397 rbi = rq->buf_info[ring_idx] + idx;
1398
1399 BUG_ON(rxd->addr != rbi->dma_addr ||
1400 rxd->len != rbi->len);
1401
1402 if (unlikely(rcd->eop && rcd->err)) {
1403 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1404 goto rcd_done;
1405 }
1406
1407 if (rcd->sop) { /* first buf of the pkt */
1408 bool rxDataRingUsed;
1409 u16 len;
1410
1411 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1412 (rcd->rqID != rq->qid &&
1413 rcd->rqID != rq->dataRingQid));
1414
1415 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1416 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1417
1418 if (unlikely(rcd->len == 0)) {
1419 /* Pretend the rx buffer is skipped. */
1420 BUG_ON(!(rcd->sop && rcd->eop));
1421 netdev_dbg(adapter->netdev,
1422 "rxRing[%u][%u] 0 length\n",
1423 ring_idx, idx);
1424 goto rcd_done;
1425 }
1426
1427 skip_page_frags = false;
1428 ctx->skb = rbi->skb;
1429
1430 rxDataRingUsed =
1431 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1432 len = rxDataRingUsed ? rcd->len : rbi->len;
1433 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1434 len);
1435 if (new_skb == NULL) {
1436 /* Skb allocation failed, do not handover this
1437 * skb to stack. Reuse it. Drop the existing pkt
1438 */
1439 rq->stats.rx_buf_alloc_failure++;
1440 ctx->skb = NULL;
1441 rq->stats.drop_total++;
1442 skip_page_frags = true;
1443 goto rcd_done;
1444 }
1445
1446 if (rxDataRingUsed) {
1447 size_t sz;
1448
1449 BUG_ON(rcd->len > rq->data_ring.desc_size);
1450
1451 ctx->skb = new_skb;
1452 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1453 memcpy(new_skb->data,
1454 &rq->data_ring.base[sz], rcd->len);
1455 } else {
1456 ctx->skb = rbi->skb;
1457
1458 new_dma_addr =
1459 dma_map_single(&adapter->pdev->dev,
1460 new_skb->data, rbi->len,
1461 PCI_DMA_FROMDEVICE);
1462 if (dma_mapping_error(&adapter->pdev->dev,
1463 new_dma_addr)) {
1464 dev_kfree_skb(new_skb);
1465 /* Skb allocation failed, do not
1466 * handover this skb to stack. Reuse
1467 * it. Drop the existing pkt.
1468 */
1469 rq->stats.rx_buf_alloc_failure++;
1470 ctx->skb = NULL;
1471 rq->stats.drop_total++;
1472 skip_page_frags = true;
1473 goto rcd_done;
1474 }
1475
1476 dma_unmap_single(&adapter->pdev->dev,
1477 rbi->dma_addr,
1478 rbi->len,
1479 PCI_DMA_FROMDEVICE);
1480
1481 /* Immediate refill */
1482 rbi->skb = new_skb;
1483 rbi->dma_addr = new_dma_addr;
1484 rxd->addr = cpu_to_le64(rbi->dma_addr);
1485 rxd->len = rbi->len;
1486 }
1487
1488 #ifdef VMXNET3_RSS
1489 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1490 (adapter->netdev->features & NETIF_F_RXHASH))
1491 skb_set_hash(ctx->skb,
1492 le32_to_cpu(rcd->rssHash),
1493 PKT_HASH_TYPE_L3);
1494 #endif
1495 skb_put(ctx->skb, rcd->len);
1496
1497 if (VMXNET3_VERSION_GE_2(adapter) &&
1498 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1499 struct Vmxnet3_RxCompDescExt *rcdlro;
1500 union Vmxnet3_GenericDesc *gdesc;
1501
1502 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1503 gdesc = (union Vmxnet3_GenericDesc *)rcd;
1504
1505 segCnt = rcdlro->segCnt;
1506 WARN_ON_ONCE(segCnt == 0);
1507 mss = rcdlro->mss;
1508 if (unlikely(segCnt <= 1))
1509 segCnt = 0;
1510 encap_lro = (le32_to_cpu(gdesc->dword[0]) &
1511 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT));
1512 } else {
1513 segCnt = 0;
1514 }
1515 } else {
1516 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1517
1518 /* non SOP buffer must be type 1 in most cases */
1519 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1520 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1521
1522 /* If an sop buffer was dropped, skip all
1523 * following non-sop fragments. They will be reused.
1524 */
1525 if (skip_page_frags)
1526 goto rcd_done;
1527
1528 if (rcd->len) {
1529 new_page = alloc_page(GFP_ATOMIC);
1530 /* Replacement page frag could not be allocated.
1531 * Reuse this page. Drop the pkt and free the
1532 * skb which contained this page as a frag. Skip
1533 * processing all the following non-sop frags.
1534 */
1535 if (unlikely(!new_page)) {
1536 rq->stats.rx_buf_alloc_failure++;
1537 dev_kfree_skb(ctx->skb);
1538 ctx->skb = NULL;
1539 skip_page_frags = true;
1540 goto rcd_done;
1541 }
1542 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1543 new_page,
1544 0, PAGE_SIZE,
1545 PCI_DMA_FROMDEVICE);
1546 if (dma_mapping_error(&adapter->pdev->dev,
1547 new_dma_addr)) {
1548 put_page(new_page);
1549 rq->stats.rx_buf_alloc_failure++;
1550 dev_kfree_skb(ctx->skb);
1551 ctx->skb = NULL;
1552 skip_page_frags = true;
1553 goto rcd_done;
1554 }
1555
1556 dma_unmap_page(&adapter->pdev->dev,
1557 rbi->dma_addr, rbi->len,
1558 PCI_DMA_FROMDEVICE);
1559
1560 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1561
1562 /* Immediate refill */
1563 rbi->page = new_page;
1564 rbi->dma_addr = new_dma_addr;
1565 rxd->addr = cpu_to_le64(rbi->dma_addr);
1566 rxd->len = rbi->len;
1567 }
1568 }
1569
1570
1571 skb = ctx->skb;
1572 if (rcd->eop) {
1573 u32 mtu = adapter->netdev->mtu;
1574 skb->len += skb->data_len;
1575
1576 vmxnet3_rx_csum(adapter, skb,
1577 (union Vmxnet3_GenericDesc *)rcd);
1578 skb->protocol = eth_type_trans(skb, adapter->netdev);
1579 if ((!rcd->tcp && !encap_lro) ||
1580 !(adapter->netdev->features & NETIF_F_LRO))
1581 goto not_lro;
1582
1583 if (segCnt != 0 && mss != 0) {
1584 skb_shinfo(skb)->gso_type = rcd->v4 ?
1585 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1586 skb_shinfo(skb)->gso_size = mss;
1587 skb_shinfo(skb)->gso_segs = segCnt;
1588 } else if ((segCnt != 0 || skb->len > mtu) && !encap_lro) {
1589 u32 hlen;
1590
1591 hlen = vmxnet3_get_hdr_len(adapter, skb,
1592 (union Vmxnet3_GenericDesc *)rcd);
1593 if (hlen == 0)
1594 goto not_lro;
1595
1596 skb_shinfo(skb)->gso_type =
1597 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1598 if (segCnt != 0) {
1599 skb_shinfo(skb)->gso_segs = segCnt;
1600 skb_shinfo(skb)->gso_size =
1601 DIV_ROUND_UP(skb->len -
1602 hlen, segCnt);
1603 } else {
1604 skb_shinfo(skb)->gso_size = mtu - hlen;
1605 }
1606 }
1607 not_lro:
1608 if (unlikely(rcd->ts))
1609 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1610
1611 if (adapter->netdev->features & NETIF_F_LRO)
1612 netif_receive_skb(skb);
1613 else
1614 napi_gro_receive(&rq->napi, skb);
1615
1616 ctx->skb = NULL;
1617 encap_lro = false;
1618 num_pkts++;
1619 }
1620
1621 rcd_done:
1622 /* device may have skipped some rx descs */
1623 ring->next2comp = idx;
1624 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1625 ring = rq->rx_ring + ring_idx;
1626
1627 /* Ensure that the writes to rxd->gen bits will be observed
1628 * after all other writes to rxd objects.
1629 */
1630 dma_wmb();
1631
1632 while (num_to_alloc) {
1633 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1634 &rxCmdDesc);
1635 BUG_ON(!rxd->addr);
1636
1637 /* Recv desc is ready to be used by the device */
1638 rxd->gen = ring->gen;
1639 vmxnet3_cmd_ring_adv_next2fill(ring);
1640 num_to_alloc--;
1641 }
1642
1643 /* if needed, update the register */
1644 if (unlikely(rq->shared->updateRxProd)) {
1645 VMXNET3_WRITE_BAR0_REG(adapter,
1646 rxprod_reg[ring_idx] + rq->qid * 8,
1647 ring->next2fill);
1648 }
1649
1650 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1651 vmxnet3_getRxComp(rcd,
1652 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1653 }
1654
1655 return num_pkts;
1656 }
1657
1658
1659 static void
vmxnet3_rq_cleanup(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1660 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1661 struct vmxnet3_adapter *adapter)
1662 {
1663 u32 i, ring_idx;
1664 struct Vmxnet3_RxDesc *rxd;
1665
1666 /* ring has already been cleaned up */
1667 if (!rq->rx_ring[0].base)
1668 return;
1669
1670 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1671 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1672 #ifdef __BIG_ENDIAN_BITFIELD
1673 struct Vmxnet3_RxDesc rxDesc;
1674 #endif
1675 vmxnet3_getRxDesc(rxd,
1676 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1677
1678 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1679 rq->buf_info[ring_idx][i].skb) {
1680 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1681 rxd->len, PCI_DMA_FROMDEVICE);
1682 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1683 rq->buf_info[ring_idx][i].skb = NULL;
1684 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1685 rq->buf_info[ring_idx][i].page) {
1686 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1687 rxd->len, PCI_DMA_FROMDEVICE);
1688 put_page(rq->buf_info[ring_idx][i].page);
1689 rq->buf_info[ring_idx][i].page = NULL;
1690 }
1691 }
1692
1693 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1694 rq->rx_ring[ring_idx].next2fill =
1695 rq->rx_ring[ring_idx].next2comp = 0;
1696 }
1697
1698 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1699 rq->comp_ring.next2proc = 0;
1700 }
1701
1702
1703 static void
vmxnet3_rq_cleanup_all(struct vmxnet3_adapter * adapter)1704 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1705 {
1706 int i;
1707
1708 for (i = 0; i < adapter->num_rx_queues; i++)
1709 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1710 }
1711
1712
vmxnet3_rq_destroy(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1713 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1714 struct vmxnet3_adapter *adapter)
1715 {
1716 int i;
1717 int j;
1718
1719 /* all rx buffers must have already been freed */
1720 for (i = 0; i < 2; i++) {
1721 if (rq->buf_info[i]) {
1722 for (j = 0; j < rq->rx_ring[i].size; j++)
1723 BUG_ON(rq->buf_info[i][j].page != NULL);
1724 }
1725 }
1726
1727
1728 for (i = 0; i < 2; i++) {
1729 if (rq->rx_ring[i].base) {
1730 dma_free_coherent(&adapter->pdev->dev,
1731 rq->rx_ring[i].size
1732 * sizeof(struct Vmxnet3_RxDesc),
1733 rq->rx_ring[i].base,
1734 rq->rx_ring[i].basePA);
1735 rq->rx_ring[i].base = NULL;
1736 }
1737 }
1738
1739 if (rq->data_ring.base) {
1740 dma_free_coherent(&adapter->pdev->dev,
1741 rq->rx_ring[0].size * rq->data_ring.desc_size,
1742 rq->data_ring.base, rq->data_ring.basePA);
1743 rq->data_ring.base = NULL;
1744 }
1745
1746 if (rq->comp_ring.base) {
1747 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1748 * sizeof(struct Vmxnet3_RxCompDesc),
1749 rq->comp_ring.base, rq->comp_ring.basePA);
1750 rq->comp_ring.base = NULL;
1751 }
1752
1753 if (rq->buf_info[0]) {
1754 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1755 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1756 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1757 rq->buf_info_pa);
1758 rq->buf_info[0] = rq->buf_info[1] = NULL;
1759 }
1760 }
1761
1762 static void
vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter * adapter)1763 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1764 {
1765 int i;
1766
1767 for (i = 0; i < adapter->num_rx_queues; i++) {
1768 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1769
1770 if (rq->data_ring.base) {
1771 dma_free_coherent(&adapter->pdev->dev,
1772 (rq->rx_ring[0].size *
1773 rq->data_ring.desc_size),
1774 rq->data_ring.base,
1775 rq->data_ring.basePA);
1776 rq->data_ring.base = NULL;
1777 rq->data_ring.desc_size = 0;
1778 }
1779 }
1780 }
1781
1782 static int
vmxnet3_rq_init(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1783 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1784 struct vmxnet3_adapter *adapter)
1785 {
1786 int i;
1787
1788 /* initialize buf_info */
1789 for (i = 0; i < rq->rx_ring[0].size; i++) {
1790
1791 /* 1st buf for a pkt is skbuff */
1792 if (i % adapter->rx_buf_per_pkt == 0) {
1793 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1794 rq->buf_info[0][i].len = adapter->skb_buf_size;
1795 } else { /* subsequent bufs for a pkt is frag */
1796 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1797 rq->buf_info[0][i].len = PAGE_SIZE;
1798 }
1799 }
1800 for (i = 0; i < rq->rx_ring[1].size; i++) {
1801 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1802 rq->buf_info[1][i].len = PAGE_SIZE;
1803 }
1804
1805 /* reset internal state and allocate buffers for both rings */
1806 for (i = 0; i < 2; i++) {
1807 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1808
1809 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1810 sizeof(struct Vmxnet3_RxDesc));
1811 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1812 }
1813 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1814 adapter) == 0) {
1815 /* at least has 1 rx buffer for the 1st ring */
1816 return -ENOMEM;
1817 }
1818 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1819
1820 /* reset the comp ring */
1821 rq->comp_ring.next2proc = 0;
1822 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1823 sizeof(struct Vmxnet3_RxCompDesc));
1824 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1825
1826 /* reset rxctx */
1827 rq->rx_ctx.skb = NULL;
1828
1829 /* stats are not reset */
1830 return 0;
1831 }
1832
1833
1834 static int
vmxnet3_rq_init_all(struct vmxnet3_adapter * adapter)1835 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1836 {
1837 int i, err = 0;
1838
1839 for (i = 0; i < adapter->num_rx_queues; i++) {
1840 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1841 if (unlikely(err)) {
1842 dev_err(&adapter->netdev->dev, "%s: failed to "
1843 "initialize rx queue%i\n",
1844 adapter->netdev->name, i);
1845 break;
1846 }
1847 }
1848 return err;
1849
1850 }
1851
1852
1853 static int
vmxnet3_rq_create(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1854 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1855 {
1856 int i;
1857 size_t sz;
1858 struct vmxnet3_rx_buf_info *bi;
1859
1860 for (i = 0; i < 2; i++) {
1861
1862 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1863 rq->rx_ring[i].base = dma_alloc_coherent(
1864 &adapter->pdev->dev, sz,
1865 &rq->rx_ring[i].basePA,
1866 GFP_KERNEL);
1867 if (!rq->rx_ring[i].base) {
1868 netdev_err(adapter->netdev,
1869 "failed to allocate rx ring %d\n", i);
1870 goto err;
1871 }
1872 }
1873
1874 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1875 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1876 rq->data_ring.base =
1877 dma_alloc_coherent(&adapter->pdev->dev, sz,
1878 &rq->data_ring.basePA,
1879 GFP_KERNEL);
1880 if (!rq->data_ring.base) {
1881 netdev_err(adapter->netdev,
1882 "rx data ring will be disabled\n");
1883 adapter->rxdataring_enabled = false;
1884 }
1885 } else {
1886 rq->data_ring.base = NULL;
1887 rq->data_ring.desc_size = 0;
1888 }
1889
1890 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1891 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1892 &rq->comp_ring.basePA,
1893 GFP_KERNEL);
1894 if (!rq->comp_ring.base) {
1895 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1896 goto err;
1897 }
1898
1899 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1900 rq->rx_ring[1].size);
1901 bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1902 GFP_KERNEL);
1903 if (!bi)
1904 goto err;
1905
1906 rq->buf_info[0] = bi;
1907 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1908
1909 return 0;
1910
1911 err:
1912 vmxnet3_rq_destroy(rq, adapter);
1913 return -ENOMEM;
1914 }
1915
1916
1917 static int
vmxnet3_rq_create_all(struct vmxnet3_adapter * adapter)1918 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1919 {
1920 int i, err = 0;
1921
1922 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1923
1924 for (i = 0; i < adapter->num_rx_queues; i++) {
1925 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1926 if (unlikely(err)) {
1927 dev_err(&adapter->netdev->dev,
1928 "%s: failed to create rx queue%i\n",
1929 adapter->netdev->name, i);
1930 goto err_out;
1931 }
1932 }
1933
1934 if (!adapter->rxdataring_enabled)
1935 vmxnet3_rq_destroy_all_rxdataring(adapter);
1936
1937 return err;
1938 err_out:
1939 vmxnet3_rq_destroy_all(adapter);
1940 return err;
1941
1942 }
1943
1944 /* Multiple queue aware polling function for tx and rx */
1945
1946 static int
vmxnet3_do_poll(struct vmxnet3_adapter * adapter,int budget)1947 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1948 {
1949 int rcd_done = 0, i;
1950 if (unlikely(adapter->shared->ecr))
1951 vmxnet3_process_events(adapter);
1952 for (i = 0; i < adapter->num_tx_queues; i++)
1953 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1954
1955 for (i = 0; i < adapter->num_rx_queues; i++)
1956 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1957 adapter, budget);
1958 return rcd_done;
1959 }
1960
1961
1962 static int
vmxnet3_poll(struct napi_struct * napi,int budget)1963 vmxnet3_poll(struct napi_struct *napi, int budget)
1964 {
1965 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1966 struct vmxnet3_rx_queue, napi);
1967 int rxd_done;
1968
1969 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1970
1971 if (rxd_done < budget) {
1972 napi_complete_done(napi, rxd_done);
1973 vmxnet3_enable_all_intrs(rx_queue->adapter);
1974 }
1975 return rxd_done;
1976 }
1977
1978 /*
1979 * NAPI polling function for MSI-X mode with multiple Rx queues
1980 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1981 */
1982
1983 static int
vmxnet3_poll_rx_only(struct napi_struct * napi,int budget)1984 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1985 {
1986 struct vmxnet3_rx_queue *rq = container_of(napi,
1987 struct vmxnet3_rx_queue, napi);
1988 struct vmxnet3_adapter *adapter = rq->adapter;
1989 int rxd_done;
1990
1991 /* When sharing interrupt with corresponding tx queue, process
1992 * tx completions in that queue as well
1993 */
1994 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1995 struct vmxnet3_tx_queue *tq =
1996 &adapter->tx_queue[rq - adapter->rx_queue];
1997 vmxnet3_tq_tx_complete(tq, adapter);
1998 }
1999
2000 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
2001
2002 if (rxd_done < budget) {
2003 napi_complete_done(napi, rxd_done);
2004 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
2005 }
2006 return rxd_done;
2007 }
2008
2009
2010 #ifdef CONFIG_PCI_MSI
2011
2012 /*
2013 * Handle completion interrupts on tx queues
2014 * Returns whether or not the intr is handled
2015 */
2016
2017 static irqreturn_t
vmxnet3_msix_tx(int irq,void * data)2018 vmxnet3_msix_tx(int irq, void *data)
2019 {
2020 struct vmxnet3_tx_queue *tq = data;
2021 struct vmxnet3_adapter *adapter = tq->adapter;
2022
2023 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2024 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2025
2026 /* Handle the case where only one irq is allocate for all tx queues */
2027 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2028 int i;
2029 for (i = 0; i < adapter->num_tx_queues; i++) {
2030 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2031 vmxnet3_tq_tx_complete(txq, adapter);
2032 }
2033 } else {
2034 vmxnet3_tq_tx_complete(tq, adapter);
2035 }
2036 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2037
2038 return IRQ_HANDLED;
2039 }
2040
2041
2042 /*
2043 * Handle completion interrupts on rx queues. Returns whether or not the
2044 * intr is handled
2045 */
2046
2047 static irqreturn_t
vmxnet3_msix_rx(int irq,void * data)2048 vmxnet3_msix_rx(int irq, void *data)
2049 {
2050 struct vmxnet3_rx_queue *rq = data;
2051 struct vmxnet3_adapter *adapter = rq->adapter;
2052
2053 /* disable intr if needed */
2054 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2055 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2056 napi_schedule(&rq->napi);
2057
2058 return IRQ_HANDLED;
2059 }
2060
2061 /*
2062 *----------------------------------------------------------------------------
2063 *
2064 * vmxnet3_msix_event --
2065 *
2066 * vmxnet3 msix event intr handler
2067 *
2068 * Result:
2069 * whether or not the intr is handled
2070 *
2071 *----------------------------------------------------------------------------
2072 */
2073
2074 static irqreturn_t
vmxnet3_msix_event(int irq,void * data)2075 vmxnet3_msix_event(int irq, void *data)
2076 {
2077 struct net_device *dev = data;
2078 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2079
2080 /* disable intr if needed */
2081 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2082 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2083
2084 if (adapter->shared->ecr)
2085 vmxnet3_process_events(adapter);
2086
2087 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2088
2089 return IRQ_HANDLED;
2090 }
2091
2092 #endif /* CONFIG_PCI_MSI */
2093
2094
2095 /* Interrupt handler for vmxnet3 */
2096 static irqreturn_t
vmxnet3_intr(int irq,void * dev_id)2097 vmxnet3_intr(int irq, void *dev_id)
2098 {
2099 struct net_device *dev = dev_id;
2100 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2101
2102 if (adapter->intr.type == VMXNET3_IT_INTX) {
2103 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2104 if (unlikely(icr == 0))
2105 /* not ours */
2106 return IRQ_NONE;
2107 }
2108
2109
2110 /* disable intr if needed */
2111 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2112 vmxnet3_disable_all_intrs(adapter);
2113
2114 napi_schedule(&adapter->rx_queue[0].napi);
2115
2116 return IRQ_HANDLED;
2117 }
2118
2119 #ifdef CONFIG_NET_POLL_CONTROLLER
2120
2121 /* netpoll callback. */
2122 static void
vmxnet3_netpoll(struct net_device * netdev)2123 vmxnet3_netpoll(struct net_device *netdev)
2124 {
2125 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2126
2127 switch (adapter->intr.type) {
2128 #ifdef CONFIG_PCI_MSI
2129 case VMXNET3_IT_MSIX: {
2130 int i;
2131 for (i = 0; i < adapter->num_rx_queues; i++)
2132 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2133 break;
2134 }
2135 #endif
2136 case VMXNET3_IT_MSI:
2137 default:
2138 vmxnet3_intr(0, adapter->netdev);
2139 break;
2140 }
2141
2142 }
2143 #endif /* CONFIG_NET_POLL_CONTROLLER */
2144
2145 static int
vmxnet3_request_irqs(struct vmxnet3_adapter * adapter)2146 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2147 {
2148 struct vmxnet3_intr *intr = &adapter->intr;
2149 int err = 0, i;
2150 int vector = 0;
2151
2152 #ifdef CONFIG_PCI_MSI
2153 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2154 for (i = 0; i < adapter->num_tx_queues; i++) {
2155 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2156 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2157 adapter->netdev->name, vector);
2158 err = request_irq(
2159 intr->msix_entries[vector].vector,
2160 vmxnet3_msix_tx, 0,
2161 adapter->tx_queue[i].name,
2162 &adapter->tx_queue[i]);
2163 } else {
2164 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2165 adapter->netdev->name, vector);
2166 }
2167 if (err) {
2168 dev_err(&adapter->netdev->dev,
2169 "Failed to request irq for MSIX, %s, "
2170 "error %d\n",
2171 adapter->tx_queue[i].name, err);
2172 return err;
2173 }
2174
2175 /* Handle the case where only 1 MSIx was allocated for
2176 * all tx queues */
2177 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2178 for (; i < adapter->num_tx_queues; i++)
2179 adapter->tx_queue[i].comp_ring.intr_idx
2180 = vector;
2181 vector++;
2182 break;
2183 } else {
2184 adapter->tx_queue[i].comp_ring.intr_idx
2185 = vector++;
2186 }
2187 }
2188 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2189 vector = 0;
2190
2191 for (i = 0; i < adapter->num_rx_queues; i++) {
2192 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2193 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2194 adapter->netdev->name, vector);
2195 else
2196 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2197 adapter->netdev->name, vector);
2198 err = request_irq(intr->msix_entries[vector].vector,
2199 vmxnet3_msix_rx, 0,
2200 adapter->rx_queue[i].name,
2201 &(adapter->rx_queue[i]));
2202 if (err) {
2203 netdev_err(adapter->netdev,
2204 "Failed to request irq for MSIX, "
2205 "%s, error %d\n",
2206 adapter->rx_queue[i].name, err);
2207 return err;
2208 }
2209
2210 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2211 }
2212
2213 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2214 adapter->netdev->name, vector);
2215 err = request_irq(intr->msix_entries[vector].vector,
2216 vmxnet3_msix_event, 0,
2217 intr->event_msi_vector_name, adapter->netdev);
2218 intr->event_intr_idx = vector;
2219
2220 } else if (intr->type == VMXNET3_IT_MSI) {
2221 adapter->num_rx_queues = 1;
2222 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2223 adapter->netdev->name, adapter->netdev);
2224 } else {
2225 #endif
2226 adapter->num_rx_queues = 1;
2227 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2228 IRQF_SHARED, adapter->netdev->name,
2229 adapter->netdev);
2230 #ifdef CONFIG_PCI_MSI
2231 }
2232 #endif
2233 intr->num_intrs = vector + 1;
2234 if (err) {
2235 netdev_err(adapter->netdev,
2236 "Failed to request irq (intr type:%d), error %d\n",
2237 intr->type, err);
2238 } else {
2239 /* Number of rx queues will not change after this */
2240 for (i = 0; i < adapter->num_rx_queues; i++) {
2241 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2242 rq->qid = i;
2243 rq->qid2 = i + adapter->num_rx_queues;
2244 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2245 }
2246
2247 /* init our intr settings */
2248 for (i = 0; i < intr->num_intrs; i++)
2249 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2250 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2251 adapter->intr.event_intr_idx = 0;
2252 for (i = 0; i < adapter->num_tx_queues; i++)
2253 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2254 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2255 }
2256
2257 netdev_info(adapter->netdev,
2258 "intr type %u, mode %u, %u vectors allocated\n",
2259 intr->type, intr->mask_mode, intr->num_intrs);
2260 }
2261
2262 return err;
2263 }
2264
2265
2266 static void
vmxnet3_free_irqs(struct vmxnet3_adapter * adapter)2267 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2268 {
2269 struct vmxnet3_intr *intr = &adapter->intr;
2270 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2271
2272 switch (intr->type) {
2273 #ifdef CONFIG_PCI_MSI
2274 case VMXNET3_IT_MSIX:
2275 {
2276 int i, vector = 0;
2277
2278 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2279 for (i = 0; i < adapter->num_tx_queues; i++) {
2280 free_irq(intr->msix_entries[vector++].vector,
2281 &(adapter->tx_queue[i]));
2282 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2283 break;
2284 }
2285 }
2286
2287 for (i = 0; i < adapter->num_rx_queues; i++) {
2288 free_irq(intr->msix_entries[vector++].vector,
2289 &(adapter->rx_queue[i]));
2290 }
2291
2292 free_irq(intr->msix_entries[vector].vector,
2293 adapter->netdev);
2294 BUG_ON(vector >= intr->num_intrs);
2295 break;
2296 }
2297 #endif
2298 case VMXNET3_IT_MSI:
2299 free_irq(adapter->pdev->irq, adapter->netdev);
2300 break;
2301 case VMXNET3_IT_INTX:
2302 free_irq(adapter->pdev->irq, adapter->netdev);
2303 break;
2304 default:
2305 BUG();
2306 }
2307 }
2308
2309
2310 static void
vmxnet3_restore_vlan(struct vmxnet3_adapter * adapter)2311 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2312 {
2313 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2314 u16 vid;
2315
2316 /* allow untagged pkts */
2317 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2318
2319 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2320 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2321 }
2322
2323
2324 static int
vmxnet3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2325 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2326 {
2327 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2328
2329 if (!(netdev->flags & IFF_PROMISC)) {
2330 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2331 unsigned long flags;
2332
2333 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2334 spin_lock_irqsave(&adapter->cmd_lock, flags);
2335 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2336 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2337 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2338 }
2339
2340 set_bit(vid, adapter->active_vlans);
2341
2342 return 0;
2343 }
2344
2345
2346 static int
vmxnet3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2347 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2348 {
2349 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2350
2351 if (!(netdev->flags & IFF_PROMISC)) {
2352 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2353 unsigned long flags;
2354
2355 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2356 spin_lock_irqsave(&adapter->cmd_lock, flags);
2357 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2358 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2359 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2360 }
2361
2362 clear_bit(vid, adapter->active_vlans);
2363
2364 return 0;
2365 }
2366
2367
2368 static u8 *
vmxnet3_copy_mc(struct net_device * netdev)2369 vmxnet3_copy_mc(struct net_device *netdev)
2370 {
2371 u8 *buf = NULL;
2372 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2373
2374 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2375 if (sz <= 0xffff) {
2376 /* We may be called with BH disabled */
2377 buf = kmalloc(sz, GFP_ATOMIC);
2378 if (buf) {
2379 struct netdev_hw_addr *ha;
2380 int i = 0;
2381
2382 netdev_for_each_mc_addr(ha, netdev)
2383 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2384 ETH_ALEN);
2385 }
2386 }
2387 return buf;
2388 }
2389
2390
2391 static void
vmxnet3_set_mc(struct net_device * netdev)2392 vmxnet3_set_mc(struct net_device *netdev)
2393 {
2394 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2395 unsigned long flags;
2396 struct Vmxnet3_RxFilterConf *rxConf =
2397 &adapter->shared->devRead.rxFilterConf;
2398 u8 *new_table = NULL;
2399 dma_addr_t new_table_pa = 0;
2400 bool new_table_pa_valid = false;
2401 u32 new_mode = VMXNET3_RXM_UCAST;
2402
2403 if (netdev->flags & IFF_PROMISC) {
2404 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2405 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2406
2407 new_mode |= VMXNET3_RXM_PROMISC;
2408 } else {
2409 vmxnet3_restore_vlan(adapter);
2410 }
2411
2412 if (netdev->flags & IFF_BROADCAST)
2413 new_mode |= VMXNET3_RXM_BCAST;
2414
2415 if (netdev->flags & IFF_ALLMULTI)
2416 new_mode |= VMXNET3_RXM_ALL_MULTI;
2417 else
2418 if (!netdev_mc_empty(netdev)) {
2419 new_table = vmxnet3_copy_mc(netdev);
2420 if (new_table) {
2421 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2422
2423 rxConf->mfTableLen = cpu_to_le16(sz);
2424 new_table_pa = dma_map_single(
2425 &adapter->pdev->dev,
2426 new_table,
2427 sz,
2428 PCI_DMA_TODEVICE);
2429 if (!dma_mapping_error(&adapter->pdev->dev,
2430 new_table_pa)) {
2431 new_mode |= VMXNET3_RXM_MCAST;
2432 new_table_pa_valid = true;
2433 rxConf->mfTablePA = cpu_to_le64(
2434 new_table_pa);
2435 }
2436 }
2437 if (!new_table_pa_valid) {
2438 netdev_info(netdev,
2439 "failed to copy mcast list, setting ALL_MULTI\n");
2440 new_mode |= VMXNET3_RXM_ALL_MULTI;
2441 }
2442 }
2443
2444 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2445 rxConf->mfTableLen = 0;
2446 rxConf->mfTablePA = 0;
2447 }
2448
2449 spin_lock_irqsave(&adapter->cmd_lock, flags);
2450 if (new_mode != rxConf->rxMode) {
2451 rxConf->rxMode = cpu_to_le32(new_mode);
2452 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2453 VMXNET3_CMD_UPDATE_RX_MODE);
2454 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2455 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2456 }
2457
2458 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2459 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2460 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2461
2462 if (new_table_pa_valid)
2463 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2464 rxConf->mfTableLen, PCI_DMA_TODEVICE);
2465 kfree(new_table);
2466 }
2467
2468 void
vmxnet3_rq_destroy_all(struct vmxnet3_adapter * adapter)2469 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2470 {
2471 int i;
2472
2473 for (i = 0; i < adapter->num_rx_queues; i++)
2474 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2475 }
2476
2477
2478 /*
2479 * Set up driver_shared based on settings in adapter.
2480 */
2481
2482 static void
vmxnet3_setup_driver_shared(struct vmxnet3_adapter * adapter)2483 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2484 {
2485 struct Vmxnet3_DriverShared *shared = adapter->shared;
2486 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2487 struct Vmxnet3_TxQueueConf *tqc;
2488 struct Vmxnet3_RxQueueConf *rqc;
2489 int i;
2490
2491 memset(shared, 0, sizeof(*shared));
2492
2493 /* driver settings */
2494 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2495 devRead->misc.driverInfo.version = cpu_to_le32(
2496 VMXNET3_DRIVER_VERSION_NUM);
2497 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2498 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2499 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2500 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2501 *((u32 *)&devRead->misc.driverInfo.gos));
2502 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2503 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2504
2505 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2506 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2507
2508 /* set up feature flags */
2509 if (adapter->netdev->features & NETIF_F_RXCSUM)
2510 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2511
2512 if (adapter->netdev->features & NETIF_F_LRO) {
2513 devRead->misc.uptFeatures |= UPT1_F_LRO;
2514 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2515 }
2516 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2517 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2518
2519 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2520 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2521 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2522
2523 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2524 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2525 devRead->misc.queueDescLen = cpu_to_le32(
2526 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2527 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2528
2529 /* tx queue settings */
2530 devRead->misc.numTxQueues = adapter->num_tx_queues;
2531 for (i = 0; i < adapter->num_tx_queues; i++) {
2532 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2533 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2534 tqc = &adapter->tqd_start[i].conf;
2535 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2536 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2537 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2538 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
2539 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2540 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2541 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2542 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2543 tqc->ddLen = cpu_to_le32(
2544 sizeof(struct vmxnet3_tx_buf_info) *
2545 tqc->txRingSize);
2546 tqc->intrIdx = tq->comp_ring.intr_idx;
2547 }
2548
2549 /* rx queue settings */
2550 devRead->misc.numRxQueues = adapter->num_rx_queues;
2551 for (i = 0; i < adapter->num_rx_queues; i++) {
2552 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2553 rqc = &adapter->rqd_start[i].conf;
2554 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2555 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2556 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2557 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
2558 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2559 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2560 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2561 rqc->ddLen = cpu_to_le32(
2562 sizeof(struct vmxnet3_rx_buf_info) *
2563 (rqc->rxRingSize[0] +
2564 rqc->rxRingSize[1]));
2565 rqc->intrIdx = rq->comp_ring.intr_idx;
2566 if (VMXNET3_VERSION_GE_3(adapter)) {
2567 rqc->rxDataRingBasePA =
2568 cpu_to_le64(rq->data_ring.basePA);
2569 rqc->rxDataRingDescSize =
2570 cpu_to_le16(rq->data_ring.desc_size);
2571 }
2572 }
2573
2574 #ifdef VMXNET3_RSS
2575 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2576
2577 if (adapter->rss) {
2578 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2579
2580 devRead->misc.uptFeatures |= UPT1_F_RSS;
2581 devRead->misc.numRxQueues = adapter->num_rx_queues;
2582 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2583 UPT1_RSS_HASH_TYPE_IPV4 |
2584 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2585 UPT1_RSS_HASH_TYPE_IPV6;
2586 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2587 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2588 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2589 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2590
2591 for (i = 0; i < rssConf->indTableSize; i++)
2592 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2593 i, adapter->num_rx_queues);
2594
2595 devRead->rssConfDesc.confVer = 1;
2596 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2597 devRead->rssConfDesc.confPA =
2598 cpu_to_le64(adapter->rss_conf_pa);
2599 }
2600
2601 #endif /* VMXNET3_RSS */
2602
2603 /* intr settings */
2604 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2605 VMXNET3_IMM_AUTO;
2606 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2607 for (i = 0; i < adapter->intr.num_intrs; i++)
2608 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2609
2610 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2611 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2612
2613 /* rx filter settings */
2614 devRead->rxFilterConf.rxMode = 0;
2615 vmxnet3_restore_vlan(adapter);
2616 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2617
2618 /* the rest are already zeroed */
2619 }
2620
2621 static void
vmxnet3_init_coalesce(struct vmxnet3_adapter * adapter)2622 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2623 {
2624 struct Vmxnet3_DriverShared *shared = adapter->shared;
2625 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2626 unsigned long flags;
2627
2628 if (!VMXNET3_VERSION_GE_3(adapter))
2629 return;
2630
2631 spin_lock_irqsave(&adapter->cmd_lock, flags);
2632 cmdInfo->varConf.confVer = 1;
2633 cmdInfo->varConf.confLen =
2634 cpu_to_le32(sizeof(*adapter->coal_conf));
2635 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2636
2637 if (adapter->default_coal_mode) {
2638 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2639 VMXNET3_CMD_GET_COALESCE);
2640 } else {
2641 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2642 VMXNET3_CMD_SET_COALESCE);
2643 }
2644
2645 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2646 }
2647
2648 static void
vmxnet3_init_rssfields(struct vmxnet3_adapter * adapter)2649 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2650 {
2651 struct Vmxnet3_DriverShared *shared = adapter->shared;
2652 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2653 unsigned long flags;
2654
2655 if (!VMXNET3_VERSION_GE_4(adapter))
2656 return;
2657
2658 spin_lock_irqsave(&adapter->cmd_lock, flags);
2659
2660 if (adapter->default_rss_fields) {
2661 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2662 VMXNET3_CMD_GET_RSS_FIELDS);
2663 adapter->rss_fields =
2664 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2665 } else {
2666 cmdInfo->setRssFields = adapter->rss_fields;
2667 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2668 VMXNET3_CMD_SET_RSS_FIELDS);
2669 /* Not all requested RSS may get applied, so get and
2670 * cache what was actually applied.
2671 */
2672 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2673 VMXNET3_CMD_GET_RSS_FIELDS);
2674 adapter->rss_fields =
2675 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2676 }
2677
2678 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2679 }
2680
2681 int
vmxnet3_activate_dev(struct vmxnet3_adapter * adapter)2682 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2683 {
2684 int err, i;
2685 u32 ret;
2686 unsigned long flags;
2687
2688 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2689 " ring sizes %u %u %u\n", adapter->netdev->name,
2690 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2691 adapter->tx_queue[0].tx_ring.size,
2692 adapter->rx_queue[0].rx_ring[0].size,
2693 adapter->rx_queue[0].rx_ring[1].size);
2694
2695 vmxnet3_tq_init_all(adapter);
2696 err = vmxnet3_rq_init_all(adapter);
2697 if (err) {
2698 netdev_err(adapter->netdev,
2699 "Failed to init rx queue error %d\n", err);
2700 goto rq_err;
2701 }
2702
2703 err = vmxnet3_request_irqs(adapter);
2704 if (err) {
2705 netdev_err(adapter->netdev,
2706 "Failed to setup irq for error %d\n", err);
2707 goto irq_err;
2708 }
2709
2710 vmxnet3_setup_driver_shared(adapter);
2711
2712 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2713 adapter->shared_pa));
2714 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2715 adapter->shared_pa));
2716 spin_lock_irqsave(&adapter->cmd_lock, flags);
2717 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2718 VMXNET3_CMD_ACTIVATE_DEV);
2719 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2720 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2721
2722 if (ret != 0) {
2723 netdev_err(adapter->netdev,
2724 "Failed to activate dev: error %u\n", ret);
2725 err = -EINVAL;
2726 goto activate_err;
2727 }
2728
2729 vmxnet3_init_coalesce(adapter);
2730 vmxnet3_init_rssfields(adapter);
2731
2732 for (i = 0; i < adapter->num_rx_queues; i++) {
2733 VMXNET3_WRITE_BAR0_REG(adapter,
2734 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2735 adapter->rx_queue[i].rx_ring[0].next2fill);
2736 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2737 (i * VMXNET3_REG_ALIGN)),
2738 adapter->rx_queue[i].rx_ring[1].next2fill);
2739 }
2740
2741 /* Apply the rx filter settins last. */
2742 vmxnet3_set_mc(adapter->netdev);
2743
2744 /*
2745 * Check link state when first activating device. It will start the
2746 * tx queue if the link is up.
2747 */
2748 vmxnet3_check_link(adapter, true);
2749 for (i = 0; i < adapter->num_rx_queues; i++)
2750 napi_enable(&adapter->rx_queue[i].napi);
2751 vmxnet3_enable_all_intrs(adapter);
2752 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2753 return 0;
2754
2755 activate_err:
2756 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2757 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2758 vmxnet3_free_irqs(adapter);
2759 irq_err:
2760 rq_err:
2761 /* free up buffers we allocated */
2762 vmxnet3_rq_cleanup_all(adapter);
2763 return err;
2764 }
2765
2766
2767 void
vmxnet3_reset_dev(struct vmxnet3_adapter * adapter)2768 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2769 {
2770 unsigned long flags;
2771 spin_lock_irqsave(&adapter->cmd_lock, flags);
2772 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2773 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2774 }
2775
2776
2777 int
vmxnet3_quiesce_dev(struct vmxnet3_adapter * adapter)2778 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2779 {
2780 int i;
2781 unsigned long flags;
2782 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2783 return 0;
2784
2785
2786 spin_lock_irqsave(&adapter->cmd_lock, flags);
2787 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2788 VMXNET3_CMD_QUIESCE_DEV);
2789 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2790 vmxnet3_disable_all_intrs(adapter);
2791
2792 for (i = 0; i < adapter->num_rx_queues; i++)
2793 napi_disable(&adapter->rx_queue[i].napi);
2794 netif_tx_disable(adapter->netdev);
2795 adapter->link_speed = 0;
2796 netif_carrier_off(adapter->netdev);
2797
2798 vmxnet3_tq_cleanup_all(adapter);
2799 vmxnet3_rq_cleanup_all(adapter);
2800 vmxnet3_free_irqs(adapter);
2801 return 0;
2802 }
2803
2804
2805 static void
vmxnet3_write_mac_addr(struct vmxnet3_adapter * adapter,u8 * mac)2806 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2807 {
2808 u32 tmp;
2809
2810 tmp = *(u32 *)mac;
2811 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2812
2813 tmp = (mac[5] << 8) | mac[4];
2814 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2815 }
2816
2817
2818 static int
vmxnet3_set_mac_addr(struct net_device * netdev,void * p)2819 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2820 {
2821 struct sockaddr *addr = p;
2822 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2823
2824 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2825 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2826
2827 return 0;
2828 }
2829
2830
2831 /* ==================== initialization and cleanup routines ============ */
2832
2833 static int
vmxnet3_alloc_pci_resources(struct vmxnet3_adapter * adapter)2834 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2835 {
2836 int err;
2837 unsigned long mmio_start, mmio_len;
2838 struct pci_dev *pdev = adapter->pdev;
2839
2840 err = pci_enable_device(pdev);
2841 if (err) {
2842 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2843 return err;
2844 }
2845
2846 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2847 vmxnet3_driver_name);
2848 if (err) {
2849 dev_err(&pdev->dev,
2850 "Failed to request region for adapter: error %d\n", err);
2851 goto err_enable_device;
2852 }
2853
2854 pci_set_master(pdev);
2855
2856 mmio_start = pci_resource_start(pdev, 0);
2857 mmio_len = pci_resource_len(pdev, 0);
2858 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2859 if (!adapter->hw_addr0) {
2860 dev_err(&pdev->dev, "Failed to map bar0\n");
2861 err = -EIO;
2862 goto err_ioremap;
2863 }
2864
2865 mmio_start = pci_resource_start(pdev, 1);
2866 mmio_len = pci_resource_len(pdev, 1);
2867 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2868 if (!adapter->hw_addr1) {
2869 dev_err(&pdev->dev, "Failed to map bar1\n");
2870 err = -EIO;
2871 goto err_bar1;
2872 }
2873 return 0;
2874
2875 err_bar1:
2876 iounmap(adapter->hw_addr0);
2877 err_ioremap:
2878 pci_release_selected_regions(pdev, (1 << 2) - 1);
2879 err_enable_device:
2880 pci_disable_device(pdev);
2881 return err;
2882 }
2883
2884
2885 static void
vmxnet3_free_pci_resources(struct vmxnet3_adapter * adapter)2886 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2887 {
2888 BUG_ON(!adapter->pdev);
2889
2890 iounmap(adapter->hw_addr0);
2891 iounmap(adapter->hw_addr1);
2892 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2893 pci_disable_device(adapter->pdev);
2894 }
2895
2896
2897 static void
vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter * adapter)2898 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2899 {
2900 size_t sz, i, ring0_size, ring1_size, comp_size;
2901 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2902 VMXNET3_MAX_ETH_HDR_SIZE) {
2903 adapter->skb_buf_size = adapter->netdev->mtu +
2904 VMXNET3_MAX_ETH_HDR_SIZE;
2905 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2906 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2907
2908 adapter->rx_buf_per_pkt = 1;
2909 } else {
2910 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2911 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2912 VMXNET3_MAX_ETH_HDR_SIZE;
2913 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2914 }
2915
2916 /*
2917 * for simplicity, force the ring0 size to be a multiple of
2918 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2919 */
2920 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2921 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2922 ring0_size = (ring0_size + sz - 1) / sz * sz;
2923 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2924 sz * sz);
2925 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2926 ring1_size = (ring1_size + sz - 1) / sz * sz;
2927 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2928 sz * sz);
2929 comp_size = ring0_size + ring1_size;
2930
2931 for (i = 0; i < adapter->num_rx_queues; i++) {
2932 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2933
2934 rq->rx_ring[0].size = ring0_size;
2935 rq->rx_ring[1].size = ring1_size;
2936 rq->comp_ring.size = comp_size;
2937 }
2938 }
2939
2940
2941 int
vmxnet3_create_queues(struct vmxnet3_adapter * adapter,u32 tx_ring_size,u32 rx_ring_size,u32 rx_ring2_size,u16 txdata_desc_size,u16 rxdata_desc_size)2942 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2943 u32 rx_ring_size, u32 rx_ring2_size,
2944 u16 txdata_desc_size, u16 rxdata_desc_size)
2945 {
2946 int err = 0, i;
2947
2948 for (i = 0; i < adapter->num_tx_queues; i++) {
2949 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2950 tq->tx_ring.size = tx_ring_size;
2951 tq->data_ring.size = tx_ring_size;
2952 tq->comp_ring.size = tx_ring_size;
2953 tq->txdata_desc_size = txdata_desc_size;
2954 tq->shared = &adapter->tqd_start[i].ctrl;
2955 tq->stopped = true;
2956 tq->adapter = adapter;
2957 tq->qid = i;
2958 err = vmxnet3_tq_create(tq, adapter);
2959 /*
2960 * Too late to change num_tx_queues. We cannot do away with
2961 * lesser number of queues than what we asked for
2962 */
2963 if (err)
2964 goto queue_err;
2965 }
2966
2967 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2968 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2969 vmxnet3_adjust_rx_ring_size(adapter);
2970
2971 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2972 for (i = 0; i < adapter->num_rx_queues; i++) {
2973 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2974 /* qid and qid2 for rx queues will be assigned later when num
2975 * of rx queues is finalized after allocating intrs */
2976 rq->shared = &adapter->rqd_start[i].ctrl;
2977 rq->adapter = adapter;
2978 rq->data_ring.desc_size = rxdata_desc_size;
2979 err = vmxnet3_rq_create(rq, adapter);
2980 if (err) {
2981 if (i == 0) {
2982 netdev_err(adapter->netdev,
2983 "Could not allocate any rx queues. "
2984 "Aborting.\n");
2985 goto queue_err;
2986 } else {
2987 netdev_info(adapter->netdev,
2988 "Number of rx queues changed "
2989 "to : %d.\n", i);
2990 adapter->num_rx_queues = i;
2991 err = 0;
2992 break;
2993 }
2994 }
2995 }
2996
2997 if (!adapter->rxdataring_enabled)
2998 vmxnet3_rq_destroy_all_rxdataring(adapter);
2999
3000 return err;
3001 queue_err:
3002 vmxnet3_tq_destroy_all(adapter);
3003 return err;
3004 }
3005
3006 static int
vmxnet3_open(struct net_device * netdev)3007 vmxnet3_open(struct net_device *netdev)
3008 {
3009 struct vmxnet3_adapter *adapter;
3010 int err, i;
3011
3012 adapter = netdev_priv(netdev);
3013
3014 for (i = 0; i < adapter->num_tx_queues; i++)
3015 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3016
3017 if (VMXNET3_VERSION_GE_3(adapter)) {
3018 unsigned long flags;
3019 u16 txdata_desc_size;
3020
3021 spin_lock_irqsave(&adapter->cmd_lock, flags);
3022 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3023 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3024 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3025 VMXNET3_REG_CMD);
3026 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3027
3028 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3029 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3030 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3031 adapter->txdata_desc_size =
3032 sizeof(struct Vmxnet3_TxDataDesc);
3033 } else {
3034 adapter->txdata_desc_size = txdata_desc_size;
3035 }
3036 } else {
3037 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3038 }
3039
3040 err = vmxnet3_create_queues(adapter,
3041 adapter->tx_ring_size,
3042 adapter->rx_ring_size,
3043 adapter->rx_ring2_size,
3044 adapter->txdata_desc_size,
3045 adapter->rxdata_desc_size);
3046 if (err)
3047 goto queue_err;
3048
3049 err = vmxnet3_activate_dev(adapter);
3050 if (err)
3051 goto activate_err;
3052
3053 return 0;
3054
3055 activate_err:
3056 vmxnet3_rq_destroy_all(adapter);
3057 vmxnet3_tq_destroy_all(adapter);
3058 queue_err:
3059 return err;
3060 }
3061
3062
3063 static int
vmxnet3_close(struct net_device * netdev)3064 vmxnet3_close(struct net_device *netdev)
3065 {
3066 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3067
3068 /*
3069 * Reset_work may be in the middle of resetting the device, wait for its
3070 * completion.
3071 */
3072 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3073 usleep_range(1000, 2000);
3074
3075 vmxnet3_quiesce_dev(adapter);
3076
3077 vmxnet3_rq_destroy_all(adapter);
3078 vmxnet3_tq_destroy_all(adapter);
3079
3080 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3081
3082
3083 return 0;
3084 }
3085
3086
3087 void
vmxnet3_force_close(struct vmxnet3_adapter * adapter)3088 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3089 {
3090 int i;
3091
3092 /*
3093 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3094 * vmxnet3_close() will deadlock.
3095 */
3096 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3097
3098 /* we need to enable NAPI, otherwise dev_close will deadlock */
3099 for (i = 0; i < adapter->num_rx_queues; i++)
3100 napi_enable(&adapter->rx_queue[i].napi);
3101 /*
3102 * Need to clear the quiesce bit to ensure that vmxnet3_close
3103 * can quiesce the device properly
3104 */
3105 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3106 dev_close(adapter->netdev);
3107 }
3108
3109
3110 static int
vmxnet3_change_mtu(struct net_device * netdev,int new_mtu)3111 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3112 {
3113 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3114 int err = 0;
3115
3116 netdev->mtu = new_mtu;
3117
3118 /*
3119 * Reset_work may be in the middle of resetting the device, wait for its
3120 * completion.
3121 */
3122 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3123 usleep_range(1000, 2000);
3124
3125 if (netif_running(netdev)) {
3126 vmxnet3_quiesce_dev(adapter);
3127 vmxnet3_reset_dev(adapter);
3128
3129 /* we need to re-create the rx queue based on the new mtu */
3130 vmxnet3_rq_destroy_all(adapter);
3131 vmxnet3_adjust_rx_ring_size(adapter);
3132 err = vmxnet3_rq_create_all(adapter);
3133 if (err) {
3134 netdev_err(netdev,
3135 "failed to re-create rx queues, "
3136 " error %d. Closing it.\n", err);
3137 goto out;
3138 }
3139
3140 err = vmxnet3_activate_dev(adapter);
3141 if (err) {
3142 netdev_err(netdev,
3143 "failed to re-activate, error %d. "
3144 "Closing it\n", err);
3145 goto out;
3146 }
3147 }
3148
3149 out:
3150 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3151 if (err)
3152 vmxnet3_force_close(adapter);
3153
3154 return err;
3155 }
3156
3157
3158 static void
vmxnet3_declare_features(struct vmxnet3_adapter * adapter,bool dma64)3159 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3160 {
3161 struct net_device *netdev = adapter->netdev;
3162
3163 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3164 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3165 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3166 NETIF_F_LRO;
3167
3168 if (VMXNET3_VERSION_GE_4(adapter)) {
3169 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3170 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3171
3172 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3173 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3174 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3175 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3176 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3177 }
3178
3179 if (dma64)
3180 netdev->hw_features |= NETIF_F_HIGHDMA;
3181 netdev->vlan_features = netdev->hw_features &
3182 ~(NETIF_F_HW_VLAN_CTAG_TX |
3183 NETIF_F_HW_VLAN_CTAG_RX);
3184 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3185 }
3186
3187
3188 static void
vmxnet3_read_mac_addr(struct vmxnet3_adapter * adapter,u8 * mac)3189 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3190 {
3191 u32 tmp;
3192
3193 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3194 *(u32 *)mac = tmp;
3195
3196 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3197 mac[4] = tmp & 0xff;
3198 mac[5] = (tmp >> 8) & 0xff;
3199 }
3200
3201 #ifdef CONFIG_PCI_MSI
3202
3203 /*
3204 * Enable MSIx vectors.
3205 * Returns :
3206 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3207 * were enabled.
3208 * number of vectors which were enabled otherwise (this number is greater
3209 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3210 */
3211
3212 static int
vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter * adapter,int nvec)3213 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3214 {
3215 int ret = pci_enable_msix_range(adapter->pdev,
3216 adapter->intr.msix_entries, nvec, nvec);
3217
3218 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3219 dev_err(&adapter->netdev->dev,
3220 "Failed to enable %d MSI-X, trying %d\n",
3221 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3222
3223 ret = pci_enable_msix_range(adapter->pdev,
3224 adapter->intr.msix_entries,
3225 VMXNET3_LINUX_MIN_MSIX_VECT,
3226 VMXNET3_LINUX_MIN_MSIX_VECT);
3227 }
3228
3229 if (ret < 0) {
3230 dev_err(&adapter->netdev->dev,
3231 "Failed to enable MSI-X, error: %d\n", ret);
3232 }
3233
3234 return ret;
3235 }
3236
3237
3238 #endif /* CONFIG_PCI_MSI */
3239
3240 static void
vmxnet3_alloc_intr_resources(struct vmxnet3_adapter * adapter)3241 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3242 {
3243 u32 cfg;
3244 unsigned long flags;
3245
3246 /* intr settings */
3247 spin_lock_irqsave(&adapter->cmd_lock, flags);
3248 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3249 VMXNET3_CMD_GET_CONF_INTR);
3250 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3251 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3252 adapter->intr.type = cfg & 0x3;
3253 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3254
3255 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3256 adapter->intr.type = VMXNET3_IT_MSIX;
3257 }
3258
3259 #ifdef CONFIG_PCI_MSI
3260 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3261 int i, nvec;
3262
3263 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3264 1 : adapter->num_tx_queues;
3265 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3266 0 : adapter->num_rx_queues;
3267 nvec += 1; /* for link event */
3268 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3269 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3270
3271 for (i = 0; i < nvec; i++)
3272 adapter->intr.msix_entries[i].entry = i;
3273
3274 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3275 if (nvec < 0)
3276 goto msix_err;
3277
3278 /* If we cannot allocate one MSIx vector per queue
3279 * then limit the number of rx queues to 1
3280 */
3281 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
3282 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3283 || adapter->num_rx_queues != 1) {
3284 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3285 netdev_err(adapter->netdev,
3286 "Number of rx queues : 1\n");
3287 adapter->num_rx_queues = 1;
3288 }
3289 }
3290
3291 adapter->intr.num_intrs = nvec;
3292 return;
3293
3294 msix_err:
3295 /* If we cannot allocate MSIx vectors use only one rx queue */
3296 dev_info(&adapter->pdev->dev,
3297 "Failed to enable MSI-X, error %d. "
3298 "Limiting #rx queues to 1, try MSI.\n", nvec);
3299
3300 adapter->intr.type = VMXNET3_IT_MSI;
3301 }
3302
3303 if (adapter->intr.type == VMXNET3_IT_MSI) {
3304 if (!pci_enable_msi(adapter->pdev)) {
3305 adapter->num_rx_queues = 1;
3306 adapter->intr.num_intrs = 1;
3307 return;
3308 }
3309 }
3310 #endif /* CONFIG_PCI_MSI */
3311
3312 adapter->num_rx_queues = 1;
3313 dev_info(&adapter->netdev->dev,
3314 "Using INTx interrupt, #Rx queues: 1.\n");
3315 adapter->intr.type = VMXNET3_IT_INTX;
3316
3317 /* INT-X related setting */
3318 adapter->intr.num_intrs = 1;
3319 }
3320
3321
3322 static void
vmxnet3_free_intr_resources(struct vmxnet3_adapter * adapter)3323 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3324 {
3325 if (adapter->intr.type == VMXNET3_IT_MSIX)
3326 pci_disable_msix(adapter->pdev);
3327 else if (adapter->intr.type == VMXNET3_IT_MSI)
3328 pci_disable_msi(adapter->pdev);
3329 else
3330 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3331 }
3332
3333
3334 static void
vmxnet3_tx_timeout(struct net_device * netdev,unsigned int txqueue)3335 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3336 {
3337 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3338 adapter->tx_timeout_count++;
3339
3340 netdev_err(adapter->netdev, "tx hang\n");
3341 schedule_work(&adapter->work);
3342 }
3343
3344
3345 static void
vmxnet3_reset_work(struct work_struct * data)3346 vmxnet3_reset_work(struct work_struct *data)
3347 {
3348 struct vmxnet3_adapter *adapter;
3349
3350 adapter = container_of(data, struct vmxnet3_adapter, work);
3351
3352 /* if another thread is resetting the device, no need to proceed */
3353 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3354 return;
3355
3356 /* if the device is closed, we must leave it alone */
3357 rtnl_lock();
3358 if (netif_running(adapter->netdev)) {
3359 netdev_notice(adapter->netdev, "resetting\n");
3360 vmxnet3_quiesce_dev(adapter);
3361 vmxnet3_reset_dev(adapter);
3362 vmxnet3_activate_dev(adapter);
3363 } else {
3364 netdev_info(adapter->netdev, "already closed\n");
3365 }
3366 rtnl_unlock();
3367
3368 netif_wake_queue(adapter->netdev);
3369 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3370 }
3371
3372
3373 static int
vmxnet3_probe_device(struct pci_dev * pdev,const struct pci_device_id * id)3374 vmxnet3_probe_device(struct pci_dev *pdev,
3375 const struct pci_device_id *id)
3376 {
3377 static const struct net_device_ops vmxnet3_netdev_ops = {
3378 .ndo_open = vmxnet3_open,
3379 .ndo_stop = vmxnet3_close,
3380 .ndo_start_xmit = vmxnet3_xmit_frame,
3381 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3382 .ndo_change_mtu = vmxnet3_change_mtu,
3383 .ndo_fix_features = vmxnet3_fix_features,
3384 .ndo_set_features = vmxnet3_set_features,
3385 .ndo_features_check = vmxnet3_features_check,
3386 .ndo_get_stats64 = vmxnet3_get_stats64,
3387 .ndo_tx_timeout = vmxnet3_tx_timeout,
3388 .ndo_set_rx_mode = vmxnet3_set_mc,
3389 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3390 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3391 #ifdef CONFIG_NET_POLL_CONTROLLER
3392 .ndo_poll_controller = vmxnet3_netpoll,
3393 #endif
3394 };
3395 int err;
3396 bool dma64;
3397 u32 ver;
3398 struct net_device *netdev;
3399 struct vmxnet3_adapter *adapter;
3400 u8 mac[ETH_ALEN];
3401 int size;
3402 int num_tx_queues;
3403 int num_rx_queues;
3404
3405 if (!pci_msi_enabled())
3406 enable_mq = 0;
3407
3408 #ifdef VMXNET3_RSS
3409 if (enable_mq)
3410 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3411 (int)num_online_cpus());
3412 else
3413 #endif
3414 num_rx_queues = 1;
3415 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3416
3417 if (enable_mq)
3418 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3419 (int)num_online_cpus());
3420 else
3421 num_tx_queues = 1;
3422
3423 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3424 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3425 max(num_tx_queues, num_rx_queues));
3426 dev_info(&pdev->dev,
3427 "# of Tx queues : %d, # of Rx queues : %d\n",
3428 num_tx_queues, num_rx_queues);
3429
3430 if (!netdev)
3431 return -ENOMEM;
3432
3433 pci_set_drvdata(pdev, netdev);
3434 adapter = netdev_priv(netdev);
3435 adapter->netdev = netdev;
3436 adapter->pdev = pdev;
3437
3438 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3439 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3440 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3441
3442 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
3443 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
3444 dev_err(&pdev->dev,
3445 "pci_set_consistent_dma_mask failed\n");
3446 err = -EIO;
3447 goto err_set_mask;
3448 }
3449 dma64 = true;
3450 } else {
3451 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
3452 dev_err(&pdev->dev,
3453 "pci_set_dma_mask failed\n");
3454 err = -EIO;
3455 goto err_set_mask;
3456 }
3457 dma64 = false;
3458 }
3459
3460 spin_lock_init(&adapter->cmd_lock);
3461 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3462 sizeof(struct vmxnet3_adapter),
3463 PCI_DMA_TODEVICE);
3464 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3465 dev_err(&pdev->dev, "Failed to map dma\n");
3466 err = -EFAULT;
3467 goto err_set_mask;
3468 }
3469 adapter->shared = dma_alloc_coherent(
3470 &adapter->pdev->dev,
3471 sizeof(struct Vmxnet3_DriverShared),
3472 &adapter->shared_pa, GFP_KERNEL);
3473 if (!adapter->shared) {
3474 dev_err(&pdev->dev, "Failed to allocate memory\n");
3475 err = -ENOMEM;
3476 goto err_alloc_shared;
3477 }
3478
3479 adapter->num_rx_queues = num_rx_queues;
3480 adapter->num_tx_queues = num_tx_queues;
3481 adapter->rx_buf_per_pkt = 1;
3482
3483 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3484 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3485 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3486 &adapter->queue_desc_pa,
3487 GFP_KERNEL);
3488
3489 if (!adapter->tqd_start) {
3490 dev_err(&pdev->dev, "Failed to allocate memory\n");
3491 err = -ENOMEM;
3492 goto err_alloc_queue_desc;
3493 }
3494 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3495 adapter->num_tx_queues);
3496
3497 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3498 sizeof(struct Vmxnet3_PMConf),
3499 &adapter->pm_conf_pa,
3500 GFP_KERNEL);
3501 if (adapter->pm_conf == NULL) {
3502 err = -ENOMEM;
3503 goto err_alloc_pm;
3504 }
3505
3506 #ifdef VMXNET3_RSS
3507
3508 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3509 sizeof(struct UPT1_RSSConf),
3510 &adapter->rss_conf_pa,
3511 GFP_KERNEL);
3512 if (adapter->rss_conf == NULL) {
3513 err = -ENOMEM;
3514 goto err_alloc_rss;
3515 }
3516 #endif /* VMXNET3_RSS */
3517
3518 err = vmxnet3_alloc_pci_resources(adapter);
3519 if (err < 0)
3520 goto err_alloc_pci;
3521
3522 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3523 if (ver & (1 << VMXNET3_REV_4)) {
3524 VMXNET3_WRITE_BAR1_REG(adapter,
3525 VMXNET3_REG_VRRS,
3526 1 << VMXNET3_REV_4);
3527 adapter->version = VMXNET3_REV_4 + 1;
3528 } else if (ver & (1 << VMXNET3_REV_3)) {
3529 VMXNET3_WRITE_BAR1_REG(adapter,
3530 VMXNET3_REG_VRRS,
3531 1 << VMXNET3_REV_3);
3532 adapter->version = VMXNET3_REV_3 + 1;
3533 } else if (ver & (1 << VMXNET3_REV_2)) {
3534 VMXNET3_WRITE_BAR1_REG(adapter,
3535 VMXNET3_REG_VRRS,
3536 1 << VMXNET3_REV_2);
3537 adapter->version = VMXNET3_REV_2 + 1;
3538 } else if (ver & (1 << VMXNET3_REV_1)) {
3539 VMXNET3_WRITE_BAR1_REG(adapter,
3540 VMXNET3_REG_VRRS,
3541 1 << VMXNET3_REV_1);
3542 adapter->version = VMXNET3_REV_1 + 1;
3543 } else {
3544 dev_err(&pdev->dev,
3545 "Incompatible h/w version (0x%x) for adapter\n", ver);
3546 err = -EBUSY;
3547 goto err_ver;
3548 }
3549 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3550
3551 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3552 if (ver & 1) {
3553 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3554 } else {
3555 dev_err(&pdev->dev,
3556 "Incompatible upt version (0x%x) for adapter\n", ver);
3557 err = -EBUSY;
3558 goto err_ver;
3559 }
3560
3561 if (VMXNET3_VERSION_GE_3(adapter)) {
3562 adapter->coal_conf =
3563 dma_alloc_coherent(&adapter->pdev->dev,
3564 sizeof(struct Vmxnet3_CoalesceScheme)
3565 ,
3566 &adapter->coal_conf_pa,
3567 GFP_KERNEL);
3568 if (!adapter->coal_conf) {
3569 err = -ENOMEM;
3570 goto err_ver;
3571 }
3572 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3573 adapter->default_coal_mode = true;
3574 }
3575
3576 if (VMXNET3_VERSION_GE_4(adapter)) {
3577 adapter->default_rss_fields = true;
3578 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3579 }
3580
3581 SET_NETDEV_DEV(netdev, &pdev->dev);
3582 vmxnet3_declare_features(adapter, dma64);
3583
3584 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3585 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3586
3587 if (adapter->num_tx_queues == adapter->num_rx_queues)
3588 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3589 else
3590 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3591
3592 vmxnet3_alloc_intr_resources(adapter);
3593
3594 #ifdef VMXNET3_RSS
3595 if (adapter->num_rx_queues > 1 &&
3596 adapter->intr.type == VMXNET3_IT_MSIX) {
3597 adapter->rss = true;
3598 netdev->hw_features |= NETIF_F_RXHASH;
3599 netdev->features |= NETIF_F_RXHASH;
3600 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3601 } else {
3602 adapter->rss = false;
3603 }
3604 #endif
3605
3606 vmxnet3_read_mac_addr(adapter, mac);
3607 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3608
3609 netdev->netdev_ops = &vmxnet3_netdev_ops;
3610 vmxnet3_set_ethtool_ops(netdev);
3611 netdev->watchdog_timeo = 5 * HZ;
3612
3613 /* MTU range: 60 - 9000 */
3614 netdev->min_mtu = VMXNET3_MIN_MTU;
3615 netdev->max_mtu = VMXNET3_MAX_MTU;
3616
3617 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3618 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3619
3620 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3621 int i;
3622 for (i = 0; i < adapter->num_rx_queues; i++) {
3623 netif_napi_add(adapter->netdev,
3624 &adapter->rx_queue[i].napi,
3625 vmxnet3_poll_rx_only, 64);
3626 }
3627 } else {
3628 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3629 vmxnet3_poll, 64);
3630 }
3631
3632 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3633 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3634
3635 netif_carrier_off(netdev);
3636 err = register_netdev(netdev);
3637
3638 if (err) {
3639 dev_err(&pdev->dev, "Failed to register adapter\n");
3640 goto err_register;
3641 }
3642
3643 vmxnet3_check_link(adapter, false);
3644 return 0;
3645
3646 err_register:
3647 if (VMXNET3_VERSION_GE_3(adapter)) {
3648 dma_free_coherent(&adapter->pdev->dev,
3649 sizeof(struct Vmxnet3_CoalesceScheme),
3650 adapter->coal_conf, adapter->coal_conf_pa);
3651 }
3652 vmxnet3_free_intr_resources(adapter);
3653 err_ver:
3654 vmxnet3_free_pci_resources(adapter);
3655 err_alloc_pci:
3656 #ifdef VMXNET3_RSS
3657 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3658 adapter->rss_conf, adapter->rss_conf_pa);
3659 err_alloc_rss:
3660 #endif
3661 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3662 adapter->pm_conf, adapter->pm_conf_pa);
3663 err_alloc_pm:
3664 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3665 adapter->queue_desc_pa);
3666 err_alloc_queue_desc:
3667 dma_free_coherent(&adapter->pdev->dev,
3668 sizeof(struct Vmxnet3_DriverShared),
3669 adapter->shared, adapter->shared_pa);
3670 err_alloc_shared:
3671 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3672 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3673 err_set_mask:
3674 free_netdev(netdev);
3675 return err;
3676 }
3677
3678
3679 static void
vmxnet3_remove_device(struct pci_dev * pdev)3680 vmxnet3_remove_device(struct pci_dev *pdev)
3681 {
3682 struct net_device *netdev = pci_get_drvdata(pdev);
3683 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3684 int size = 0;
3685 int num_rx_queues;
3686
3687 #ifdef VMXNET3_RSS
3688 if (enable_mq)
3689 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3690 (int)num_online_cpus());
3691 else
3692 #endif
3693 num_rx_queues = 1;
3694 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3695
3696 cancel_work_sync(&adapter->work);
3697
3698 unregister_netdev(netdev);
3699
3700 vmxnet3_free_intr_resources(adapter);
3701 vmxnet3_free_pci_resources(adapter);
3702 if (VMXNET3_VERSION_GE_3(adapter)) {
3703 dma_free_coherent(&adapter->pdev->dev,
3704 sizeof(struct Vmxnet3_CoalesceScheme),
3705 adapter->coal_conf, adapter->coal_conf_pa);
3706 }
3707 #ifdef VMXNET3_RSS
3708 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3709 adapter->rss_conf, adapter->rss_conf_pa);
3710 #endif
3711 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3712 adapter->pm_conf, adapter->pm_conf_pa);
3713
3714 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3715 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3716 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3717 adapter->queue_desc_pa);
3718 dma_free_coherent(&adapter->pdev->dev,
3719 sizeof(struct Vmxnet3_DriverShared),
3720 adapter->shared, adapter->shared_pa);
3721 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3722 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
3723 free_netdev(netdev);
3724 }
3725
vmxnet3_shutdown_device(struct pci_dev * pdev)3726 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3727 {
3728 struct net_device *netdev = pci_get_drvdata(pdev);
3729 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3730 unsigned long flags;
3731
3732 /* Reset_work may be in the middle of resetting the device, wait for its
3733 * completion.
3734 */
3735 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3736 usleep_range(1000, 2000);
3737
3738 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3739 &adapter->state)) {
3740 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3741 return;
3742 }
3743 spin_lock_irqsave(&adapter->cmd_lock, flags);
3744 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3745 VMXNET3_CMD_QUIESCE_DEV);
3746 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3747 vmxnet3_disable_all_intrs(adapter);
3748
3749 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3750 }
3751
3752
3753 #ifdef CONFIG_PM
3754
3755 static int
vmxnet3_suspend(struct device * device)3756 vmxnet3_suspend(struct device *device)
3757 {
3758 struct pci_dev *pdev = to_pci_dev(device);
3759 struct net_device *netdev = pci_get_drvdata(pdev);
3760 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3761 struct Vmxnet3_PMConf *pmConf;
3762 struct ethhdr *ehdr;
3763 struct arphdr *ahdr;
3764 u8 *arpreq;
3765 struct in_device *in_dev;
3766 struct in_ifaddr *ifa;
3767 unsigned long flags;
3768 int i = 0;
3769
3770 if (!netif_running(netdev))
3771 return 0;
3772
3773 for (i = 0; i < adapter->num_rx_queues; i++)
3774 napi_disable(&adapter->rx_queue[i].napi);
3775
3776 vmxnet3_disable_all_intrs(adapter);
3777 vmxnet3_free_irqs(adapter);
3778 vmxnet3_free_intr_resources(adapter);
3779
3780 netif_device_detach(netdev);
3781
3782 /* Create wake-up filters. */
3783 pmConf = adapter->pm_conf;
3784 memset(pmConf, 0, sizeof(*pmConf));
3785
3786 if (adapter->wol & WAKE_UCAST) {
3787 pmConf->filters[i].patternSize = ETH_ALEN;
3788 pmConf->filters[i].maskSize = 1;
3789 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3790 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3791
3792 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3793 i++;
3794 }
3795
3796 if (adapter->wol & WAKE_ARP) {
3797 rcu_read_lock();
3798
3799 in_dev = __in_dev_get_rcu(netdev);
3800 if (!in_dev) {
3801 rcu_read_unlock();
3802 goto skip_arp;
3803 }
3804
3805 ifa = rcu_dereference(in_dev->ifa_list);
3806 if (!ifa) {
3807 rcu_read_unlock();
3808 goto skip_arp;
3809 }
3810
3811 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3812 sizeof(struct arphdr) + /* ARP header */
3813 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3814 2 * sizeof(u32); /*2 IPv4 addresses */
3815 pmConf->filters[i].maskSize =
3816 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3817
3818 /* ETH_P_ARP in Ethernet header. */
3819 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3820 ehdr->h_proto = htons(ETH_P_ARP);
3821
3822 /* ARPOP_REQUEST in ARP header. */
3823 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3824 ahdr->ar_op = htons(ARPOP_REQUEST);
3825 arpreq = (u8 *)(ahdr + 1);
3826
3827 /* The Unicast IPv4 address in 'tip' field. */
3828 arpreq += 2 * ETH_ALEN + sizeof(u32);
3829 *(__be32 *)arpreq = ifa->ifa_address;
3830
3831 rcu_read_unlock();
3832
3833 /* The mask for the relevant bits. */
3834 pmConf->filters[i].mask[0] = 0x00;
3835 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3836 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3837 pmConf->filters[i].mask[3] = 0x00;
3838 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3839 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3840
3841 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3842 i++;
3843 }
3844
3845 skip_arp:
3846 if (adapter->wol & WAKE_MAGIC)
3847 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3848
3849 pmConf->numFilters = i;
3850
3851 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3852 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3853 *pmConf));
3854 adapter->shared->devRead.pmConfDesc.confPA =
3855 cpu_to_le64(adapter->pm_conf_pa);
3856
3857 spin_lock_irqsave(&adapter->cmd_lock, flags);
3858 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3859 VMXNET3_CMD_UPDATE_PMCFG);
3860 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3861
3862 pci_save_state(pdev);
3863 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3864 adapter->wol);
3865 pci_disable_device(pdev);
3866 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3867
3868 return 0;
3869 }
3870
3871
3872 static int
vmxnet3_resume(struct device * device)3873 vmxnet3_resume(struct device *device)
3874 {
3875 int err;
3876 unsigned long flags;
3877 struct pci_dev *pdev = to_pci_dev(device);
3878 struct net_device *netdev = pci_get_drvdata(pdev);
3879 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3880
3881 if (!netif_running(netdev))
3882 return 0;
3883
3884 pci_set_power_state(pdev, PCI_D0);
3885 pci_restore_state(pdev);
3886 err = pci_enable_device_mem(pdev);
3887 if (err != 0)
3888 return err;
3889
3890 pci_enable_wake(pdev, PCI_D0, 0);
3891
3892 vmxnet3_alloc_intr_resources(adapter);
3893
3894 /* During hibernate and suspend, device has to be reinitialized as the
3895 * device state need not be preserved.
3896 */
3897
3898 /* Need not check adapter state as other reset tasks cannot run during
3899 * device resume.
3900 */
3901 spin_lock_irqsave(&adapter->cmd_lock, flags);
3902 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3903 VMXNET3_CMD_QUIESCE_DEV);
3904 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3905 vmxnet3_tq_cleanup_all(adapter);
3906 vmxnet3_rq_cleanup_all(adapter);
3907
3908 vmxnet3_reset_dev(adapter);
3909 err = vmxnet3_activate_dev(adapter);
3910 if (err != 0) {
3911 netdev_err(netdev,
3912 "failed to re-activate on resume, error: %d", err);
3913 vmxnet3_force_close(adapter);
3914 return err;
3915 }
3916 netif_device_attach(netdev);
3917
3918 return 0;
3919 }
3920
3921 static const struct dev_pm_ops vmxnet3_pm_ops = {
3922 .suspend = vmxnet3_suspend,
3923 .resume = vmxnet3_resume,
3924 .freeze = vmxnet3_suspend,
3925 .restore = vmxnet3_resume,
3926 };
3927 #endif
3928
3929 static struct pci_driver vmxnet3_driver = {
3930 .name = vmxnet3_driver_name,
3931 .id_table = vmxnet3_pciid_table,
3932 .probe = vmxnet3_probe_device,
3933 .remove = vmxnet3_remove_device,
3934 .shutdown = vmxnet3_shutdown_device,
3935 #ifdef CONFIG_PM
3936 .driver.pm = &vmxnet3_pm_ops,
3937 #endif
3938 };
3939
3940
3941 static int __init
vmxnet3_init_module(void)3942 vmxnet3_init_module(void)
3943 {
3944 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
3945 VMXNET3_DRIVER_VERSION_REPORT);
3946 return pci_register_driver(&vmxnet3_driver);
3947 }
3948
3949 module_init(vmxnet3_init_module);
3950
3951
3952 static void
vmxnet3_exit_module(void)3953 vmxnet3_exit_module(void)
3954 {
3955 pci_unregister_driver(&vmxnet3_driver);
3956 }
3957
3958 module_exit(vmxnet3_exit_module);
3959
3960 MODULE_AUTHOR("VMware, Inc.");
3961 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3962 MODULE_LICENSE("GPL v2");
3963 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
3964