1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10 #include <linux/bitops.h>
11 #include <linux/phy.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14
15 #define RTL821x_PHYSR 0x11
16 #define RTL821x_PHYSR_DUPLEX BIT(13)
17 #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
18
19 #define RTL821x_INER 0x12
20 #define RTL8211B_INER_INIT 0x6400
21 #define RTL8211E_INER_LINK_STATUS BIT(10)
22 #define RTL8211F_INER_LINK_STATUS BIT(4)
23
24 #define RTL821x_INSR 0x13
25
26 #define RTL821x_EXT_PAGE_SELECT 0x1e
27 #define RTL821x_PAGE_SELECT 0x1f
28
29 #define RTL8211F_PHYCR1 0x18
30 #define RTL8211F_INSR 0x1d
31
32 #define RTL8211F_TX_DELAY BIT(8)
33 #define RTL8211F_RX_DELAY BIT(3)
34
35 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
36 #define RTL8211F_ALDPS_ENABLE BIT(2)
37 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
38
39 #define RTL8211E_CTRL_DELAY BIT(13)
40 #define RTL8211E_TX_DELAY BIT(12)
41 #define RTL8211E_RX_DELAY BIT(11)
42
43 #define RTL8201F_ISR 0x1e
44 #define RTL8201F_IER 0x13
45
46 #define RTL8366RB_POWER_SAVE 0x15
47 #define RTL8366RB_POWER_SAVE_ON BIT(12)
48
49 #define RTL_SUPPORTS_5000FULL BIT(14)
50 #define RTL_SUPPORTS_2500FULL BIT(13)
51 #define RTL_SUPPORTS_10000FULL BIT(0)
52 #define RTL_ADV_2500FULL BIT(7)
53 #define RTL_LPADV_10000FULL BIT(11)
54 #define RTL_LPADV_5000FULL BIT(6)
55 #define RTL_LPADV_2500FULL BIT(5)
56
57 #define RTLGEN_SPEED_MASK 0x0630
58
59 #define RTL_GENERIC_PHYID 0x001cc800
60
61 MODULE_DESCRIPTION("Realtek PHY driver");
62 MODULE_AUTHOR("Johnson Leung");
63 MODULE_LICENSE("GPL");
64
rtl821x_read_page(struct phy_device * phydev)65 static int rtl821x_read_page(struct phy_device *phydev)
66 {
67 return __phy_read(phydev, RTL821x_PAGE_SELECT);
68 }
69
rtl821x_write_page(struct phy_device * phydev,int page)70 static int rtl821x_write_page(struct phy_device *phydev, int page)
71 {
72 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
73 }
74
rtl8201_ack_interrupt(struct phy_device * phydev)75 static int rtl8201_ack_interrupt(struct phy_device *phydev)
76 {
77 int err;
78
79 err = phy_read(phydev, RTL8201F_ISR);
80
81 return (err < 0) ? err : 0;
82 }
83
rtl821x_ack_interrupt(struct phy_device * phydev)84 static int rtl821x_ack_interrupt(struct phy_device *phydev)
85 {
86 int err;
87
88 err = phy_read(phydev, RTL821x_INSR);
89
90 return (err < 0) ? err : 0;
91 }
92
rtl8211f_ack_interrupt(struct phy_device * phydev)93 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
94 {
95 int err;
96
97 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
98
99 return (err < 0) ? err : 0;
100 }
101
rtl8201_config_intr(struct phy_device * phydev)102 static int rtl8201_config_intr(struct phy_device *phydev)
103 {
104 u16 val;
105
106 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
107 val = BIT(13) | BIT(12) | BIT(11);
108 else
109 val = 0;
110
111 return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
112 }
113
rtl8211b_config_intr(struct phy_device * phydev)114 static int rtl8211b_config_intr(struct phy_device *phydev)
115 {
116 int err;
117
118 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
119 err = phy_write(phydev, RTL821x_INER,
120 RTL8211B_INER_INIT);
121 else
122 err = phy_write(phydev, RTL821x_INER, 0);
123
124 return err;
125 }
126
rtl8211e_config_intr(struct phy_device * phydev)127 static int rtl8211e_config_intr(struct phy_device *phydev)
128 {
129 int err;
130
131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
132 err = phy_write(phydev, RTL821x_INER,
133 RTL8211E_INER_LINK_STATUS);
134 else
135 err = phy_write(phydev, RTL821x_INER, 0);
136
137 return err;
138 }
139
rtl8211f_config_intr(struct phy_device * phydev)140 static int rtl8211f_config_intr(struct phy_device *phydev)
141 {
142 u16 val;
143
144 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
145 val = RTL8211F_INER_LINK_STATUS;
146 else
147 val = 0;
148
149 return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
150 }
151
rtl8211_config_aneg(struct phy_device * phydev)152 static int rtl8211_config_aneg(struct phy_device *phydev)
153 {
154 int ret;
155
156 ret = genphy_config_aneg(phydev);
157 if (ret < 0)
158 return ret;
159
160 /* Quirk was copied from vendor driver. Unfortunately it includes no
161 * description of the magic numbers.
162 */
163 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
164 phy_write(phydev, 0x17, 0x2138);
165 phy_write(phydev, 0x0e, 0x0260);
166 } else {
167 phy_write(phydev, 0x17, 0x2108);
168 phy_write(phydev, 0x0e, 0x0000);
169 }
170
171 return 0;
172 }
173
rtl8211c_config_init(struct phy_device * phydev)174 static int rtl8211c_config_init(struct phy_device *phydev)
175 {
176 /* RTL8211C has an issue when operating in Gigabit slave mode */
177 return phy_set_bits(phydev, MII_CTRL1000,
178 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
179 }
180
rtl8211f_config_init(struct phy_device * phydev)181 static int rtl8211f_config_init(struct phy_device *phydev)
182 {
183 struct device *dev = &phydev->mdio.dev;
184 u16 val_txdly, val_rxdly;
185 u16 val;
186 int ret;
187
188 val = RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_XTAL_OFF;
189
190 phy_write(phydev, 0x1f, 0xd04);
191 phy_write(phydev, 0x10, 0x6d68);
192 phy_write(phydev, 0x11, 0x600b);
193 phy_write(phydev, 0x1f, 0xa42);
194
195 phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val);
196
197 switch (phydev->interface) {
198 case PHY_INTERFACE_MODE_RGMII:
199 val_txdly = 0;
200 val_rxdly = 0;
201 break;
202
203 case PHY_INTERFACE_MODE_RGMII_RXID:
204 val_txdly = 0;
205 val_rxdly = RTL8211F_RX_DELAY;
206 break;
207
208 case PHY_INTERFACE_MODE_RGMII_TXID:
209 val_txdly = RTL8211F_TX_DELAY;
210 val_rxdly = 0;
211 break;
212
213 case PHY_INTERFACE_MODE_RGMII_ID:
214 val_txdly = RTL8211F_TX_DELAY;
215 val_rxdly = RTL8211F_RX_DELAY;
216 break;
217
218 default: /* the rest of the modes imply leaving delay as is. */
219 return 0;
220 }
221
222 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
223 val_txdly);
224 if (ret < 0) {
225 dev_err(dev, "Failed to update the TX delay register\n");
226 return ret;
227 } else if (ret) {
228 dev_dbg(dev,
229 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
230 val_txdly ? "Enabling" : "Disabling");
231 } else {
232 dev_dbg(dev,
233 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
234 val_txdly ? "enabled" : "disabled");
235 }
236
237 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
238 val_rxdly);
239 if (ret < 0) {
240 dev_err(dev, "Failed to update the RX delay register\n");
241 return ret;
242 } else if (ret) {
243 dev_dbg(dev,
244 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
245 val_rxdly ? "Enabling" : "Disabling");
246 } else {
247 dev_dbg(dev,
248 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
249 val_rxdly ? "enabled" : "disabled");
250 }
251
252 return 0;
253 }
254
rtl821x_resume(struct phy_device * phydev)255 static int rtl821x_resume(struct phy_device *phydev)
256 {
257 int ret;
258
259 ret = genphy_resume(phydev);
260 if (ret < 0)
261 return ret;
262
263 msleep(20);
264
265 return 0;
266 }
267
rtl8211e_config_init(struct phy_device * phydev)268 static int rtl8211e_config_init(struct phy_device *phydev)
269 {
270 int ret = 0, oldpage;
271 u16 val;
272
273 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
274 switch (phydev->interface) {
275 case PHY_INTERFACE_MODE_RGMII:
276 val = RTL8211E_CTRL_DELAY | 0;
277 break;
278 case PHY_INTERFACE_MODE_RGMII_ID:
279 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
280 break;
281 case PHY_INTERFACE_MODE_RGMII_RXID:
282 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
283 break;
284 case PHY_INTERFACE_MODE_RGMII_TXID:
285 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
286 break;
287 default: /* the rest of the modes imply leaving delays as is. */
288 return 0;
289 }
290
291 /* According to a sample driver there is a 0x1c config register on the
292 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
293 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
294 * The configuration register definition:
295 * 14 = reserved
296 * 13 = Force Tx RX Delay controlled by bit12 bit11,
297 * 12 = RX Delay, 11 = TX Delay
298 * 10:0 = Test && debug settings reserved by realtek
299 */
300 oldpage = phy_select_page(phydev, 0x7);
301 if (oldpage < 0)
302 goto err_restore_page;
303
304 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
305 if (ret)
306 goto err_restore_page;
307
308 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
309 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
310 val);
311
312 err_restore_page:
313 return phy_restore_page(phydev, oldpage, ret);
314 }
315
rtl8211b_suspend(struct phy_device * phydev)316 static int rtl8211b_suspend(struct phy_device *phydev)
317 {
318 phy_write(phydev, MII_MMD_DATA, BIT(9));
319
320 return genphy_suspend(phydev);
321 }
322
rtl8211b_resume(struct phy_device * phydev)323 static int rtl8211b_resume(struct phy_device *phydev)
324 {
325 phy_write(phydev, MII_MMD_DATA, 0);
326
327 return genphy_resume(phydev);
328 }
329
rtl8366rb_config_init(struct phy_device * phydev)330 static int rtl8366rb_config_init(struct phy_device *phydev)
331 {
332 int ret;
333
334 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
335 RTL8366RB_POWER_SAVE_ON);
336 if (ret) {
337 dev_err(&phydev->mdio.dev,
338 "error enabling power management\n");
339 }
340
341 return ret;
342 }
343
344 /* get actual speed to cover the downshift case */
rtlgen_get_speed(struct phy_device * phydev)345 static int rtlgen_get_speed(struct phy_device *phydev)
346 {
347 int val;
348
349 if (!phydev->link)
350 return 0;
351
352 val = phy_read_paged(phydev, 0xa43, 0x12);
353 if (val < 0)
354 return val;
355
356 switch (val & RTLGEN_SPEED_MASK) {
357 case 0x0000:
358 phydev->speed = SPEED_10;
359 break;
360 case 0x0010:
361 phydev->speed = SPEED_100;
362 break;
363 case 0x0020:
364 phydev->speed = SPEED_1000;
365 break;
366 case 0x0200:
367 phydev->speed = SPEED_10000;
368 break;
369 case 0x0210:
370 phydev->speed = SPEED_2500;
371 break;
372 case 0x0220:
373 phydev->speed = SPEED_5000;
374 break;
375 default:
376 break;
377 }
378
379 return 0;
380 }
381
rtlgen_read_status(struct phy_device * phydev)382 static int rtlgen_read_status(struct phy_device *phydev)
383 {
384 int ret;
385
386 ret = genphy_read_status(phydev);
387 if (ret < 0)
388 return ret;
389
390 return rtlgen_get_speed(phydev);
391 }
392
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)393 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
394 {
395 int ret;
396
397 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
398 rtl821x_write_page(phydev, 0xa5c);
399 ret = __phy_read(phydev, 0x12);
400 rtl821x_write_page(phydev, 0);
401 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
402 rtl821x_write_page(phydev, 0xa5d);
403 ret = __phy_read(phydev, 0x10);
404 rtl821x_write_page(phydev, 0);
405 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
406 rtl821x_write_page(phydev, 0xa5d);
407 ret = __phy_read(phydev, 0x11);
408 rtl821x_write_page(phydev, 0);
409 } else {
410 ret = -EOPNOTSUPP;
411 }
412
413 return ret;
414 }
415
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)416 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
417 u16 val)
418 {
419 int ret;
420
421 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
422 rtl821x_write_page(phydev, 0xa5d);
423 ret = __phy_write(phydev, 0x10, val);
424 rtl821x_write_page(phydev, 0);
425 } else {
426 ret = -EOPNOTSUPP;
427 }
428
429 return ret;
430 }
431
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)432 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
433 {
434 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
435
436 if (ret != -EOPNOTSUPP)
437 return ret;
438
439 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
440 rtl821x_write_page(phydev, 0xa6e);
441 ret = __phy_read(phydev, 0x16);
442 rtl821x_write_page(phydev, 0);
443 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
444 rtl821x_write_page(phydev, 0xa6d);
445 ret = __phy_read(phydev, 0x12);
446 rtl821x_write_page(phydev, 0);
447 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
448 rtl821x_write_page(phydev, 0xa6d);
449 ret = __phy_read(phydev, 0x10);
450 rtl821x_write_page(phydev, 0);
451 }
452
453 return ret;
454 }
455
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)456 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
457 u16 val)
458 {
459 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
460
461 if (ret != -EOPNOTSUPP)
462 return ret;
463
464 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
465 rtl821x_write_page(phydev, 0xa6d);
466 ret = __phy_write(phydev, 0x12, val);
467 rtl821x_write_page(phydev, 0);
468 }
469
470 return ret;
471 }
472
rtl822x_get_features(struct phy_device * phydev)473 static int rtl822x_get_features(struct phy_device *phydev)
474 {
475 int val;
476
477 val = phy_read_paged(phydev, 0xa61, 0x13);
478 if (val < 0)
479 return val;
480
481 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
482 phydev->supported, val & RTL_SUPPORTS_2500FULL);
483 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
484 phydev->supported, val & RTL_SUPPORTS_5000FULL);
485 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
486 phydev->supported, val & RTL_SUPPORTS_10000FULL);
487
488 return genphy_read_abilities(phydev);
489 }
490
rtl822x_config_aneg(struct phy_device * phydev)491 static int rtl822x_config_aneg(struct phy_device *phydev)
492 {
493 int ret = 0;
494
495 if (phydev->autoneg == AUTONEG_ENABLE) {
496 u16 adv2500 = 0;
497
498 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
499 phydev->advertising))
500 adv2500 = RTL_ADV_2500FULL;
501
502 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
503 RTL_ADV_2500FULL, adv2500);
504 if (ret < 0)
505 return ret;
506 }
507
508 return __genphy_config_aneg(phydev, ret);
509 }
510
rtl822x_read_status(struct phy_device * phydev)511 static int rtl822x_read_status(struct phy_device *phydev)
512 {
513 int ret;
514
515 if (phydev->autoneg == AUTONEG_ENABLE) {
516 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
517
518 if (lpadv < 0)
519 return lpadv;
520
521 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
522 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
523 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
524 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
525 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
526 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
527 }
528
529 ret = genphy_read_status(phydev);
530 if (ret < 0)
531 return ret;
532
533 return rtlgen_get_speed(phydev);
534 }
535
rtlgen_supports_2_5gbps(struct phy_device * phydev)536 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
537 {
538 int val;
539
540 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
541 val = phy_read(phydev, 0x13);
542 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
543
544 return val >= 0 && val & RTL_SUPPORTS_2500FULL;
545 }
546
rtlgen_match_phy_device(struct phy_device * phydev)547 static int rtlgen_match_phy_device(struct phy_device *phydev)
548 {
549 return phydev->phy_id == RTL_GENERIC_PHYID &&
550 !rtlgen_supports_2_5gbps(phydev);
551 }
552
rtl8226_match_phy_device(struct phy_device * phydev)553 static int rtl8226_match_phy_device(struct phy_device *phydev)
554 {
555 return phydev->phy_id == RTL_GENERIC_PHYID &&
556 rtlgen_supports_2_5gbps(phydev);
557 }
558
rtlgen_resume(struct phy_device * phydev)559 static int rtlgen_resume(struct phy_device *phydev)
560 {
561 int ret = genphy_resume(phydev);
562
563 /* Internal PHY's from RTL8168h up may not be instantly ready */
564 msleep(20);
565
566 return ret;
567 }
568
rtl9010a_config_init(struct phy_device * phydev)569 static int rtl9010a_config_init(struct phy_device *phydev)
570 {
571 phydev->autoneg = AUTONEG_DISABLE;
572 phydev->speed = SPEED_1000;
573 phydev->duplex = DUPLEX_FULL;
574
575 return 0;
576 }
577
rtl9010a_config_aneg(struct phy_device * phydev)578 static int rtl9010a_config_aneg(struct phy_device *phydev)
579 {
580 return 0;
581 }
582
rtl9010a_get_features(struct phy_device * phydev)583 static int rtl9010a_get_features(struct phy_device *phydev)
584 {
585 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
586 phydev->supported);
587 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,
588 phydev->supported);
589
590 return 0;
591 }
592
rtl9010a_read_status(struct phy_device * phydev)593 static int rtl9010a_read_status(struct phy_device *phydev)
594 {
595 int ret;
596 u16 val;
597 int link_status, local_status, remote_status;
598
599 ret = genphy_read_status(phydev);
600 if (ret < 0)
601 return ret;
602
603 val = phy_read(phydev, 0x01);
604 val = phy_read(phydev, 0x01);
605 link_status = val & 0x0004 ? 1 : 0;
606
607 if (phydev->speed == SPEED_1000) {
608 val = phy_read(phydev, 0x0a);
609 local_status = val & 0x2000 ? 1 : 0;
610 remote_status = val & 0x1000 ? 1 : 0;
611 } else {
612 phy_write(phydev, 0x1f, 0xa64);
613 val = phy_read(phydev, 0x17);
614 local_status = val & 0x0004 ? 1 : 0;
615 remote_status = val & 0x0400 ? 1 : 0;
616 }
617
618 if (link_status && local_status && remote_status)
619 phydev->link = 1;
620 else
621 phydev->link = 0;
622
623 return 0;
624 }
625
626 static struct phy_driver realtek_drvs[] = {
627 {
628 PHY_ID_MATCH_EXACT(0x00008201),
629 .name = "RTL8201CP Ethernet",
630 .read_page = rtl821x_read_page,
631 .write_page = rtl821x_write_page,
632 }, {
633 PHY_ID_MATCH_EXACT(0x001cc816),
634 .name = "RTL8201F Fast Ethernet",
635 .ack_interrupt = &rtl8201_ack_interrupt,
636 .config_intr = &rtl8201_config_intr,
637 .suspend = genphy_suspend,
638 .resume = genphy_resume,
639 .read_page = rtl821x_read_page,
640 .write_page = rtl821x_write_page,
641 }, {
642 PHY_ID_MATCH_MODEL(0x001cc880),
643 .name = "RTL8208 Fast Ethernet",
644 .read_mmd = genphy_read_mmd_unsupported,
645 .write_mmd = genphy_write_mmd_unsupported,
646 .suspend = genphy_suspend,
647 .resume = genphy_resume,
648 .read_page = rtl821x_read_page,
649 .write_page = rtl821x_write_page,
650 }, {
651 PHY_ID_MATCH_EXACT(0x001cc910),
652 .name = "RTL8211 Gigabit Ethernet",
653 .config_aneg = rtl8211_config_aneg,
654 .read_mmd = &genphy_read_mmd_unsupported,
655 .write_mmd = &genphy_write_mmd_unsupported,
656 .read_page = rtl821x_read_page,
657 .write_page = rtl821x_write_page,
658 }, {
659 PHY_ID_MATCH_EXACT(0x001cc912),
660 .name = "RTL8211B Gigabit Ethernet",
661 .ack_interrupt = &rtl821x_ack_interrupt,
662 .config_intr = &rtl8211b_config_intr,
663 .read_mmd = &genphy_read_mmd_unsupported,
664 .write_mmd = &genphy_write_mmd_unsupported,
665 .suspend = rtl8211b_suspend,
666 .resume = rtl8211b_resume,
667 .read_page = rtl821x_read_page,
668 .write_page = rtl821x_write_page,
669 }, {
670 PHY_ID_MATCH_EXACT(0x001cc913),
671 .name = "RTL8211C Gigabit Ethernet",
672 .config_init = rtl8211c_config_init,
673 .read_mmd = &genphy_read_mmd_unsupported,
674 .write_mmd = &genphy_write_mmd_unsupported,
675 .read_page = rtl821x_read_page,
676 .write_page = rtl821x_write_page,
677 }, {
678 PHY_ID_MATCH_EXACT(0x001cc914),
679 .name = "RTL8211DN Gigabit Ethernet",
680 .ack_interrupt = rtl821x_ack_interrupt,
681 .config_intr = rtl8211e_config_intr,
682 .suspend = genphy_suspend,
683 .resume = genphy_resume,
684 .read_page = rtl821x_read_page,
685 .write_page = rtl821x_write_page,
686 }, {
687 PHY_ID_MATCH_EXACT(0x001cc915),
688 .name = "RTL8211E Gigabit Ethernet",
689 .config_init = &rtl8211e_config_init,
690 .ack_interrupt = &rtl821x_ack_interrupt,
691 .config_intr = &rtl8211e_config_intr,
692 .suspend = genphy_suspend,
693 .resume = genphy_resume,
694 .read_page = rtl821x_read_page,
695 .write_page = rtl821x_write_page,
696 }, {
697 PHY_ID_MATCH_EXACT(0x001cc916),
698 .name = "RTL8211F Gigabit Ethernet",
699 .config_init = &rtl8211f_config_init,
700 .read_status = rtlgen_read_status,
701 .ack_interrupt = &rtl8211f_ack_interrupt,
702 .config_intr = &rtl8211f_config_intr,
703 .suspend = genphy_suspend,
704 .resume = rtl821x_resume,
705 .read_page = rtl821x_read_page,
706 .write_page = rtl821x_write_page,
707 }, {
708 .name = "Generic FE-GE Realtek PHY",
709 .match_phy_device = rtlgen_match_phy_device,
710 .read_status = rtlgen_read_status,
711 .suspend = genphy_suspend,
712 .resume = rtlgen_resume,
713 .read_page = rtl821x_read_page,
714 .write_page = rtl821x_write_page,
715 .read_mmd = rtlgen_read_mmd,
716 .write_mmd = rtlgen_write_mmd,
717 }, {
718 .name = "RTL8226 2.5Gbps PHY",
719 .match_phy_device = rtl8226_match_phy_device,
720 .get_features = rtl822x_get_features,
721 .config_aneg = rtl822x_config_aneg,
722 .read_status = rtl822x_read_status,
723 .suspend = genphy_suspend,
724 .resume = rtlgen_resume,
725 .read_page = rtl821x_read_page,
726 .write_page = rtl821x_write_page,
727 .read_mmd = rtl822x_read_mmd,
728 .write_mmd = rtl822x_write_mmd,
729 }, {
730 PHY_ID_MATCH_EXACT(0x001cc840),
731 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
732 .get_features = rtl822x_get_features,
733 .config_aneg = rtl822x_config_aneg,
734 .read_status = rtl822x_read_status,
735 .suspend = genphy_suspend,
736 .resume = rtlgen_resume,
737 .read_page = rtl821x_read_page,
738 .write_page = rtl821x_write_page,
739 .read_mmd = rtl822x_read_mmd,
740 .write_mmd = rtl822x_write_mmd,
741 }, {
742 PHY_ID_MATCH_EXACT(0x001cc961),
743 .name = "RTL8366RB Gigabit Ethernet",
744 .config_init = &rtl8366rb_config_init,
745 /* These interrupts are handled by the irq controller
746 * embedded inside the RTL8366RB, they get unmasked when the
747 * irq is requested and ACKed by reading the status register,
748 * which is done by the irqchip code.
749 */
750 .ack_interrupt = genphy_no_ack_interrupt,
751 .config_intr = genphy_no_config_intr,
752 .suspend = genphy_suspend,
753 .resume = genphy_resume,
754 }, {
755 PHY_ID_MATCH_EXACT(0x001ccb30),
756 .name = "RTL9010AA_RTL9010AR_RTL9010AS Ethernet",
757 .config_init = rtl9010a_config_init,
758 .config_aneg = rtl9010a_config_aneg,
759 .read_status = rtl9010a_read_status,
760 .get_features = rtl9010a_get_features,
761 .suspend = genphy_suspend,
762 .resume = genphy_resume,
763 .read_page = rtl821x_read_page,
764 .write_page = rtl821x_write_page,
765 },
766 };
767
768 module_phy_driver(realtek_drvs);
769
770 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
771 { PHY_ID_MATCH_VENDOR(0x001cc800) },
772 { PHY_ID_MATCH_VENDOR(0x001ccb30) },
773 { }
774 };
775
776 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
777